1 /* ---------------------------------------------------------------------------- */
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2 /* Atmel Microcontroller Software Support */
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3 /* SAM Software Package License */
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4 /* ---------------------------------------------------------------------------- */
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5 /* Copyright (c) 2014, Atmel Corporation */
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7 /* All rights reserved. */
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9 /* Redistribution and use in source and binary forms, with or without */
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10 /* modification, are permitted provided that the following condition is met: */
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12 /* - Redistributions of source code must retain the above copyright notice, */
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13 /* this list of conditions and the disclaimer below. */
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15 /* Atmel's name may not be used to endorse or promote products derived from */
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16 /* this software without specific prior written permission. */
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18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
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20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
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21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
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22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
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23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
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24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
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26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
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27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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28 /* ---------------------------------------------------------------------------- */
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30 #ifndef _SAM_SSC_COMPONENT_
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31 #define _SAM_SSC_COMPONENT_
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33 /* ============================================================================= */
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34 /** SOFTWARE API DEFINITION FOR Synchronous Serial Controller */
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35 /* ============================================================================= */
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36 /** \addtogroup SAM_SSC Synchronous Serial Controller */
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39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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40 /** \brief Ssc hardware registers */
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42 __O uint32_t SSC_CR; /**< \brief (Ssc Offset: 0x0) Control Register */
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43 __IO uint32_t SSC_CMR; /**< \brief (Ssc Offset: 0x4) Clock Mode Register */
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44 __I uint32_t Reserved1[2];
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45 __IO uint32_t SSC_RCMR; /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */
\r
46 __IO uint32_t SSC_RFMR; /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */
\r
47 __IO uint32_t SSC_TCMR; /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */
\r
48 __IO uint32_t SSC_TFMR; /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */
\r
49 __I uint32_t SSC_RHR; /**< \brief (Ssc Offset: 0x20) Receive Holding Register */
\r
50 __O uint32_t SSC_THR; /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */
\r
51 __I uint32_t Reserved2[2];
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52 __I uint32_t SSC_RSHR; /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */
\r
53 __IO uint32_t SSC_TSHR; /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */
\r
54 __IO uint32_t SSC_RC0R; /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */
\r
55 __IO uint32_t SSC_RC1R; /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */
\r
56 __I uint32_t SSC_SR; /**< \brief (Ssc Offset: 0x40) Status Register */
\r
57 __O uint32_t SSC_IER; /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */
\r
58 __O uint32_t SSC_IDR; /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */
\r
59 __I uint32_t SSC_IMR; /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */
\r
60 __I uint32_t Reserved3[37];
\r
61 __IO uint32_t SSC_WPMR; /**< \brief (Ssc Offset: 0xE4) Write Protect Mode Register */
\r
62 __I uint32_t SSC_WPSR; /**< \brief (Ssc Offset: 0xE8) Write Protect Status Register */
\r
63 __I uint32_t Reserved4[4];
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64 __I uint32_t SSC_VERSION; /**< \brief (Ssc Offset: 0xFC) Version Register */
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66 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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67 /* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */
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68 #define SSC_CR_RXEN (0x1u << 0) /**< \brief (SSC_CR) Receive Enable */
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69 #define SSC_CR_RXDIS (0x1u << 1) /**< \brief (SSC_CR) Receive Disable */
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70 #define SSC_CR_TXEN (0x1u << 8) /**< \brief (SSC_CR) Transmit Enable */
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71 #define SSC_CR_TXDIS (0x1u << 9) /**< \brief (SSC_CR) Transmit Disable */
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72 #define SSC_CR_SWRST (0x1u << 15) /**< \brief (SSC_CR) Software Reset */
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73 /* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */
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74 #define SSC_CMR_DIV_Pos 0
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75 #define SSC_CMR_DIV_Msk (0xfffu << SSC_CMR_DIV_Pos) /**< \brief (SSC_CMR) Clock Divider */
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76 #define SSC_CMR_DIV(value) ((SSC_CMR_DIV_Msk & ((value) << SSC_CMR_DIV_Pos)))
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77 /* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */
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78 #define SSC_RCMR_CKS_Pos 0
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79 #define SSC_RCMR_CKS_Msk (0x3u << SSC_RCMR_CKS_Pos) /**< \brief (SSC_RCMR) Receive Clock Selection */
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80 #define SSC_RCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_RCMR) Divided Clock */
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81 #define SSC_RCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_RCMR) TK Clock signal */
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82 #define SSC_RCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_RCMR) RK pin */
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83 #define SSC_RCMR_CKO_Pos 2
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84 #define SSC_RCMR_CKO_Msk (0x7u << SSC_RCMR_CKO_Pos) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */
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85 #define SSC_RCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_RCMR) None, RK pin is an input */
\r
86 #define SSC_RCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_RCMR) Continuous Receive Clock, RK pin is an output */
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87 #define SSC_RCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_RCMR) Receive Clock only during data transfers, RK pin is an output */
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88 #define SSC_RCMR_CKI (0x1u << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */
\r
89 #define SSC_RCMR_CKG_Pos 6
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90 #define SSC_RCMR_CKG_Msk (0x3u << SSC_RCMR_CKG_Pos) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */
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91 #define SSC_RCMR_CKG_CONTINUOUS (0x0u << 6) /**< \brief (SSC_RCMR) None */
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92 #define SSC_RCMR_CKG_EN_RF_LOW (0x1u << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF Low */
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93 #define SSC_RCMR_CKG_EN_RF_HIGH (0x2u << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF High */
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94 #define SSC_RCMR_START_Pos 8
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95 #define SSC_RCMR_START_Msk (0xfu << SSC_RCMR_START_Pos) /**< \brief (SSC_RCMR) Receive Start Selection */
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96 #define SSC_RCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */
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97 #define SSC_RCMR_START_TRANSMIT (0x1u << 8) /**< \brief (SSC_RCMR) Transmit start */
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98 #define SSC_RCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_RCMR) Detection of a low level on RF signal */
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99 #define SSC_RCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_RCMR) Detection of a high level on RF signal */
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100 #define SSC_RCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_RCMR) Detection of a falling edge on RF signal */
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101 #define SSC_RCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_RCMR) Detection of a rising edge on RF signal */
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102 #define SSC_RCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_RCMR) Detection of any level change on RF signal */
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103 #define SSC_RCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_RCMR) Detection of any edge on RF signal */
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104 #define SSC_RCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_RCMR) Compare 0 */
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105 #define SSC_RCMR_STOP (0x1u << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */
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106 #define SSC_RCMR_STTDLY_Pos 16
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107 #define SSC_RCMR_STTDLY_Msk (0xffu << SSC_RCMR_STTDLY_Pos) /**< \brief (SSC_RCMR) Receive Start Delay */
\r
108 #define SSC_RCMR_STTDLY(value) ((SSC_RCMR_STTDLY_Msk & ((value) << SSC_RCMR_STTDLY_Pos)))
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109 #define SSC_RCMR_PERIOD_Pos 24
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110 #define SSC_RCMR_PERIOD_Msk (0xffu << SSC_RCMR_PERIOD_Pos) /**< \brief (SSC_RCMR) Receive Period Divider Selection */
\r
111 #define SSC_RCMR_PERIOD(value) ((SSC_RCMR_PERIOD_Msk & ((value) << SSC_RCMR_PERIOD_Pos)))
\r
112 /* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */
\r
113 #define SSC_RFMR_DATLEN_Pos 0
\r
114 #define SSC_RFMR_DATLEN_Msk (0x1fu << SSC_RFMR_DATLEN_Pos) /**< \brief (SSC_RFMR) Data Length */
\r
115 #define SSC_RFMR_DATLEN(value) ((SSC_RFMR_DATLEN_Msk & ((value) << SSC_RFMR_DATLEN_Pos)))
\r
116 #define SSC_RFMR_LOOP (0x1u << 5) /**< \brief (SSC_RFMR) Loop Mode */
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117 #define SSC_RFMR_MSBF (0x1u << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */
\r
118 #define SSC_RFMR_DATNB_Pos 8
\r
119 #define SSC_RFMR_DATNB_Msk (0xfu << SSC_RFMR_DATNB_Pos) /**< \brief (SSC_RFMR) Data Number per Frame */
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120 #define SSC_RFMR_DATNB(value) ((SSC_RFMR_DATNB_Msk & ((value) << SSC_RFMR_DATNB_Pos)))
\r
121 #define SSC_RFMR_FSLEN_Pos 16
\r
122 #define SSC_RFMR_FSLEN_Msk (0xfu << SSC_RFMR_FSLEN_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Length */
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123 #define SSC_RFMR_FSLEN(value) ((SSC_RFMR_FSLEN_Msk & ((value) << SSC_RFMR_FSLEN_Pos)))
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124 #define SSC_RFMR_FSOS_Pos 20
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125 #define SSC_RFMR_FSOS_Msk (0x7u << SSC_RFMR_FSOS_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */
\r
126 #define SSC_RFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_RFMR) None, RF pin is an input */
\r
127 #define SSC_RFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_RFMR) Negative Pulse, RF pin is an output */
\r
128 #define SSC_RFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_RFMR) Positive Pulse, RF pin is an output */
\r
129 #define SSC_RFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_RFMR) Driven Low during data transfer, RF pin is an output */
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130 #define SSC_RFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_RFMR) Driven High during data transfer, RF pin is an output */
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131 #define SSC_RFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_RFMR) Toggling at each start of data transfer, RF pin is an output */
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132 #define SSC_RFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */
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133 #define SSC_RFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_RFMR) Positive Edge Detection */
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134 #define SSC_RFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_RFMR) Negative Edge Detection */
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135 #define SSC_RFMR_FSLEN_EXT_Pos 28
\r
136 #define SSC_RFMR_FSLEN_EXT_Msk (0xfu << SSC_RFMR_FSLEN_EXT_Pos) /**< \brief (SSC_RFMR) FSLEN Field Extension */
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137 #define SSC_RFMR_FSLEN_EXT(value) ((SSC_RFMR_FSLEN_EXT_Msk & ((value) << SSC_RFMR_FSLEN_EXT_Pos)))
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138 /* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */
\r
139 #define SSC_TCMR_CKS_Pos 0
\r
140 #define SSC_TCMR_CKS_Msk (0x3u << SSC_TCMR_CKS_Pos) /**< \brief (SSC_TCMR) Transmit Clock Selection */
\r
141 #define SSC_TCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_TCMR) Divided Clock */
\r
142 #define SSC_TCMR_CKS_RK (0x1u << 0) /**< \brief (SSC_TCMR) RK Clock signal */
\r
143 #define SSC_TCMR_CKS_TK (0x2u << 0) /**< \brief (SSC_TCMR) TK pin */
\r
144 #define SSC_TCMR_CKO_Pos 2
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145 #define SSC_TCMR_CKO_Msk (0x7u << SSC_TCMR_CKO_Pos) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */
\r
146 #define SSC_TCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_TCMR) None, TK pin is an input */
\r
147 #define SSC_TCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_TCMR) Continuous Transmit Clock, TK pin is an output */
\r
148 #define SSC_TCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_TCMR) Transmit Clock only during data transfers, TK pin is an output */
\r
149 #define SSC_TCMR_CKI (0x1u << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */
\r
150 #define SSC_TCMR_CKG_Pos 6
\r
151 #define SSC_TCMR_CKG_Msk (0x3u << SSC_TCMR_CKG_Pos) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */
\r
152 #define SSC_TCMR_CKG_CONTINUOUS (0x0u << 6) /**< \brief (SSC_TCMR) None */
\r
153 #define SSC_TCMR_CKG_EN_TF_LOW (0x1u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF Low */
\r
154 #define SSC_TCMR_CKG_EN_TF_HIGH (0x2u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF High */
\r
155 #define SSC_TCMR_START_Pos 8
\r
156 #define SSC_TCMR_START_Msk (0xfu << SSC_TCMR_START_Pos) /**< \brief (SSC_TCMR) Transmit Start Selection */
\r
157 #define SSC_TCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data */
\r
158 #define SSC_TCMR_START_RECEIVE (0x1u << 8) /**< \brief (SSC_TCMR) Receive start */
\r
159 #define SSC_TCMR_START_TF_LOW (0x2u << 8) /**< \brief (SSC_TCMR) Detection of a low level on TF signal */
\r
160 #define SSC_TCMR_START_TF_HIGH (0x3u << 8) /**< \brief (SSC_TCMR) Detection of a high level on TF signal */
\r
161 #define SSC_TCMR_START_TF_FALLING (0x4u << 8) /**< \brief (SSC_TCMR) Detection of a falling edge on TF signal */
\r
162 #define SSC_TCMR_START_TF_RISING (0x5u << 8) /**< \brief (SSC_TCMR) Detection of a rising edge on TF signal */
\r
163 #define SSC_TCMR_START_TF_LEVEL (0x6u << 8) /**< \brief (SSC_TCMR) Detection of any level change on TF signal */
\r
164 #define SSC_TCMR_START_TF_EDGE (0x7u << 8) /**< \brief (SSC_TCMR) Detection of any edge on TF signal */
\r
165 #define SSC_TCMR_STTDLY_Pos 16
\r
166 #define SSC_TCMR_STTDLY_Msk (0xffu << SSC_TCMR_STTDLY_Pos) /**< \brief (SSC_TCMR) Transmit Start Delay */
\r
167 #define SSC_TCMR_STTDLY(value) ((SSC_TCMR_STTDLY_Msk & ((value) << SSC_TCMR_STTDLY_Pos)))
\r
168 #define SSC_TCMR_PERIOD_Pos 24
\r
169 #define SSC_TCMR_PERIOD_Msk (0xffu << SSC_TCMR_PERIOD_Pos) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */
\r
170 #define SSC_TCMR_PERIOD(value) ((SSC_TCMR_PERIOD_Msk & ((value) << SSC_TCMR_PERIOD_Pos)))
\r
171 /* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */
\r
172 #define SSC_TFMR_DATLEN_Pos 0
\r
173 #define SSC_TFMR_DATLEN_Msk (0x1fu << SSC_TFMR_DATLEN_Pos) /**< \brief (SSC_TFMR) Data Length */
\r
174 #define SSC_TFMR_DATLEN(value) ((SSC_TFMR_DATLEN_Msk & ((value) << SSC_TFMR_DATLEN_Pos)))
\r
175 #define SSC_TFMR_DATDEF (0x1u << 5) /**< \brief (SSC_TFMR) Data Default Value */
\r
176 #define SSC_TFMR_MSBF (0x1u << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */
\r
177 #define SSC_TFMR_DATNB_Pos 8
\r
178 #define SSC_TFMR_DATNB_Msk (0xfu << SSC_TFMR_DATNB_Pos) /**< \brief (SSC_TFMR) Data Number per frame */
\r
179 #define SSC_TFMR_DATNB(value) ((SSC_TFMR_DATNB_Msk & ((value) << SSC_TFMR_DATNB_Pos)))
\r
180 #define SSC_TFMR_FSLEN_Pos 16
\r
181 #define SSC_TFMR_FSLEN_Msk (0xfu << SSC_TFMR_FSLEN_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Length */
\r
182 #define SSC_TFMR_FSLEN(value) ((SSC_TFMR_FSLEN_Msk & ((value) << SSC_TFMR_FSLEN_Pos)))
\r
183 #define SSC_TFMR_FSOS_Pos 20
\r
184 #define SSC_TFMR_FSOS_Msk (0x7u << SSC_TFMR_FSOS_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */
\r
185 #define SSC_TFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_TFMR) None, RF pin is an input */
\r
186 #define SSC_TFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_TFMR) Negative Pulse, RF pin is an output */
\r
187 #define SSC_TFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_TFMR) Positive Pulse, RF pin is an output */
\r
188 #define SSC_TFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_TFMR) Driven Low during data transfer */
\r
189 #define SSC_TFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_TFMR) Driven High during data transfer */
\r
190 #define SSC_TFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_TFMR) Toggling at each start of data transfer */
\r
191 #define SSC_TFMR_FSDEN (0x1u << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */
\r
192 #define SSC_TFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */
\r
193 #define SSC_TFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_TFMR) Positive Edge Detection */
\r
194 #define SSC_TFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_TFMR) Negative Edge Detection */
\r
195 #define SSC_TFMR_FSLEN_EXT_Pos 28
\r
196 #define SSC_TFMR_FSLEN_EXT_Msk (0xfu << SSC_TFMR_FSLEN_EXT_Pos) /**< \brief (SSC_TFMR) FSLEN Field Extension */
\r
197 #define SSC_TFMR_FSLEN_EXT(value) ((SSC_TFMR_FSLEN_EXT_Msk & ((value) << SSC_TFMR_FSLEN_EXT_Pos)))
\r
198 /* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */
\r
199 #define SSC_RHR_RDAT_Pos 0
\r
200 #define SSC_RHR_RDAT_Msk (0xffffffffu << SSC_RHR_RDAT_Pos) /**< \brief (SSC_RHR) Receive Data */
\r
201 /* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */
\r
202 #define SSC_THR_TDAT_Pos 0
\r
203 #define SSC_THR_TDAT_Msk (0xffffffffu << SSC_THR_TDAT_Pos) /**< \brief (SSC_THR) Transmit Data */
\r
204 #define SSC_THR_TDAT(value) ((SSC_THR_TDAT_Msk & ((value) << SSC_THR_TDAT_Pos)))
\r
205 /* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */
\r
206 #define SSC_RSHR_RSDAT_Pos 0
\r
207 #define SSC_RSHR_RSDAT_Msk (0xffffu << SSC_RSHR_RSDAT_Pos) /**< \brief (SSC_RSHR) Receive Synchronization Data */
\r
208 /* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */
\r
209 #define SSC_TSHR_TSDAT_Pos 0
\r
210 #define SSC_TSHR_TSDAT_Msk (0xffffu << SSC_TSHR_TSDAT_Pos) /**< \brief (SSC_TSHR) Transmit Synchronization Data */
\r
211 #define SSC_TSHR_TSDAT(value) ((SSC_TSHR_TSDAT_Msk & ((value) << SSC_TSHR_TSDAT_Pos)))
\r
212 /* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */
\r
213 #define SSC_RC0R_CP0_Pos 0
\r
214 #define SSC_RC0R_CP0_Msk (0xffffu << SSC_RC0R_CP0_Pos) /**< \brief (SSC_RC0R) Receive Compare Data 0 */
\r
215 #define SSC_RC0R_CP0(value) ((SSC_RC0R_CP0_Msk & ((value) << SSC_RC0R_CP0_Pos)))
\r
216 /* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */
\r
217 #define SSC_RC1R_CP1_Pos 0
\r
218 #define SSC_RC1R_CP1_Msk (0xffffu << SSC_RC1R_CP1_Pos) /**< \brief (SSC_RC1R) Receive Compare Data 1 */
\r
219 #define SSC_RC1R_CP1(value) ((SSC_RC1R_CP1_Msk & ((value) << SSC_RC1R_CP1_Pos)))
\r
220 /* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */
\r
221 #define SSC_SR_TXRDY (0x1u << 0) /**< \brief (SSC_SR) Transmit Ready */
\r
222 #define SSC_SR_TXEMPTY (0x1u << 1) /**< \brief (SSC_SR) Transmit Empty */
\r
223 #define SSC_SR_RXRDY (0x1u << 4) /**< \brief (SSC_SR) Receive Ready */
\r
224 #define SSC_SR_OVRUN (0x1u << 5) /**< \brief (SSC_SR) Receive Overrun */
\r
225 #define SSC_SR_CP0 (0x1u << 8) /**< \brief (SSC_SR) Compare 0 */
\r
226 #define SSC_SR_CP1 (0x1u << 9) /**< \brief (SSC_SR) Compare 1 */
\r
227 #define SSC_SR_TXSYN (0x1u << 10) /**< \brief (SSC_SR) Transmit Sync */
\r
228 #define SSC_SR_RXSYN (0x1u << 11) /**< \brief (SSC_SR) Receive Sync */
\r
229 #define SSC_SR_TXEN (0x1u << 16) /**< \brief (SSC_SR) Transmit Enable */
\r
230 #define SSC_SR_RXEN (0x1u << 17) /**< \brief (SSC_SR) Receive Enable */
\r
231 /* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */
\r
232 #define SSC_IER_TXRDY (0x1u << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */
\r
233 #define SSC_IER_TXEMPTY (0x1u << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */
\r
234 #define SSC_IER_RXRDY (0x1u << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */
\r
235 #define SSC_IER_OVRUN (0x1u << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */
\r
236 #define SSC_IER_CP0 (0x1u << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */
\r
237 #define SSC_IER_CP1 (0x1u << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */
\r
238 #define SSC_IER_TXSYN (0x1u << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */
\r
239 #define SSC_IER_RXSYN (0x1u << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */
\r
240 /* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */
\r
241 #define SSC_IDR_TXRDY (0x1u << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */
\r
242 #define SSC_IDR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */
\r
243 #define SSC_IDR_RXRDY (0x1u << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */
\r
244 #define SSC_IDR_OVRUN (0x1u << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */
\r
245 #define SSC_IDR_CP0 (0x1u << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */
\r
246 #define SSC_IDR_CP1 (0x1u << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */
\r
247 #define SSC_IDR_TXSYN (0x1u << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */
\r
248 #define SSC_IDR_RXSYN (0x1u << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */
\r
249 /* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */
\r
250 #define SSC_IMR_TXRDY (0x1u << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */
\r
251 #define SSC_IMR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */
\r
252 #define SSC_IMR_RXRDY (0x1u << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */
\r
253 #define SSC_IMR_OVRUN (0x1u << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */
\r
254 #define SSC_IMR_CP0 (0x1u << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */
\r
255 #define SSC_IMR_CP1 (0x1u << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */
\r
256 #define SSC_IMR_TXSYN (0x1u << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */
\r
257 #define SSC_IMR_RXSYN (0x1u << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */
\r
258 /* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protect Mode Register -------- */
\r
259 #define SSC_WPMR_WPEN (0x1u << 0) /**< \brief (SSC_WPMR) Write Protect Enable */
\r
260 #define SSC_WPMR_WPKEY_Pos 8
\r
261 #define SSC_WPMR_WPKEY_Msk (0xffffffu << SSC_WPMR_WPKEY_Pos) /**< \brief (SSC_WPMR) Write Protect KEY */
\r
262 #define SSC_WPMR_WPKEY_PASSWD (0x535343u << 8) /**< \brief (SSC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */
\r
263 /* -------- SSC_VERSION : (SSC Offset: 0xFC) Version Register -------- */
\r
264 #define SSC_VERSION_VERSION_Pos 0
\r
265 #define SSC_VERSION_VERSION_Msk (0xffffu << SSC_VERSION_VERSION_Pos) /**< \brief (SSC_VERSION) Version of the Hardware Module */
\r
266 #define SSC_VERSION_MFN_Pos 16
\r
267 #define SSC_VERSION_MFN_Msk (0x7u << SSC_VERSION_MFN_Pos) /**< \brief (SSC_VERSION) Metal Fix Number */
\r
272 #endif /* _SAM_SSC_COMPONENT_ */
\r