1 /* ---------------------------------------------------------------------------- */
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2 /* Atmel Microcontroller Software Support */
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3 /* SAM Software Package License */
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4 /* ---------------------------------------------------------------------------- */
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5 /* Copyright (c) 2014, Atmel Corporation */
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7 /* All rights reserved. */
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9 /* Redistribution and use in source and binary forms, with or without */
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10 /* modification, are permitted provided that the following condition is met: */
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12 /* - Redistributions of source code must retain the above copyright notice, */
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13 /* this list of conditions and the disclaimer below. */
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15 /* Atmel's name may not be used to endorse or promote products derived from */
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16 /* this software without specific prior written permission. */
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18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
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20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
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21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
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22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
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23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
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24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
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26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
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27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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28 /* ---------------------------------------------------------------------------- */
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30 #ifndef _SAM_USART_COMPONENT_
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31 #define _SAM_USART_COMPONENT_
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33 /* ============================================================================= */
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34 /** SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */
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35 /* ============================================================================= */
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36 /** \addtogroup SAM_USART Universal Synchronous Asynchronous Receiver Transmitter */
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39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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40 /** \brief Usart hardware registers */
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42 __O uint32_t US_CR; /**< \brief (Usart Offset: 0x0000) Control Register */
\r
43 __IO uint32_t US_MR; /**< \brief (Usart Offset: 0x0004) Mode Register */
\r
44 __O uint32_t US_IER; /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */
\r
45 __O uint32_t US_IDR; /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */
\r
46 __I uint32_t US_IMR; /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */
\r
47 __I uint32_t US_CSR; /**< \brief (Usart Offset: 0x0014) Channel Status Register */
\r
48 __I uint32_t US_RHR; /**< \brief (Usart Offset: 0x0018) Receive Holding Register */
\r
49 __O uint32_t US_THR; /**< \brief (Usart Offset: 0x001C) Transmit Holding Register */
\r
50 __IO uint32_t US_BRGR; /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */
\r
51 __IO uint32_t US_RTOR; /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */
\r
52 __IO uint32_t US_TTGR; /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */
\r
53 __I uint32_t Reserved1[5];
\r
54 __IO uint32_t US_FIDI; /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */
\r
55 __I uint32_t US_NER; /**< \brief (Usart Offset: 0x0044) Number of Errors Register */
\r
56 __I uint32_t Reserved2[1];
\r
57 __IO uint32_t US_IF; /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */
\r
58 __IO uint32_t US_MAN; /**< \brief (Usart Offset: 0x0050) Manchester Configuration Register */
\r
59 __IO uint32_t US_LINMR; /**< \brief (Usart Offset: 0x0054) LIN Mode Register */
\r
60 __IO uint32_t US_LINIR; /**< \brief (Usart Offset: 0x0058) LIN Identifier Register */
\r
61 __I uint32_t US_LINBRR; /**< \brief (Usart Offset: 0x005C) LIN Baud Rate Register */
\r
62 __IO uint32_t US_LONMR; /**< \brief (Usart Offset: 0x0060) LON Mode Register */
\r
63 __IO uint32_t US_LONPR; /**< \brief (Usart Offset: 0x0064) LON Preamble Register */
\r
64 __IO uint32_t US_LONDL; /**< \brief (Usart Offset: 0x0068) LON Data Length Register */
\r
65 __IO uint32_t US_LONL2HDR; /**< \brief (Usart Offset: 0x006C) LON L2HDR Register */
\r
66 __I uint32_t US_LONBL; /**< \brief (Usart Offset: 0x0070) LON Backlog Register */
\r
67 __IO uint32_t US_LONB1TX; /**< \brief (Usart Offset: 0x0074) LON Beta1 Tx Register */
\r
68 __IO uint32_t US_LONB1RX; /**< \brief (Usart Offset: 0x0078) LON Beta1 Rx Register */
\r
69 __IO uint32_t US_LONPRIO; /**< \brief (Usart Offset: 0x007C) LON Priority Register */
\r
70 __IO uint32_t US_IDTTX; /**< \brief (Usart Offset: 0x0080) LON IDT Tx Register */
\r
71 __IO uint32_t US_IDTRX; /**< \brief (Usart Offset: 0x0084) LON IDT Rx Register */
\r
72 __IO uint32_t US_ICDIFF; /**< \brief (Usart Offset: 0x0088) IC DIFF Register */
\r
73 __I uint32_t Reserved3[22];
\r
74 __IO uint32_t US_WPMR; /**< \brief (Usart Offset: 0x00E4) Write Protection Mode Register */
\r
75 __I uint32_t US_WPSR; /**< \brief (Usart Offset: 0x00E8) Write Protection Status Register */
\r
76 __I uint32_t Reserved4[4];
\r
77 __I uint32_t US_VERSION; /**< \brief (Usart Offset: 0x00FC) Version Register */
\r
79 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
\r
80 /* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */
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81 #define US_CR_RSTRX (0x1u << 2) /**< \brief (US_CR) Reset Receiver */
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82 #define US_CR_RSTTX (0x1u << 3) /**< \brief (US_CR) Reset Transmitter */
\r
83 #define US_CR_RXEN (0x1u << 4) /**< \brief (US_CR) Receiver Enable */
\r
84 #define US_CR_RXDIS (0x1u << 5) /**< \brief (US_CR) Receiver Disable */
\r
85 #define US_CR_TXEN (0x1u << 6) /**< \brief (US_CR) Transmitter Enable */
\r
86 #define US_CR_TXDIS (0x1u << 7) /**< \brief (US_CR) Transmitter Disable */
\r
87 #define US_CR_RSTSTA (0x1u << 8) /**< \brief (US_CR) Reset Status Bits */
\r
88 #define US_CR_STTBRK (0x1u << 9) /**< \brief (US_CR) Start Break */
\r
89 #define US_CR_STPBRK (0x1u << 10) /**< \brief (US_CR) Stop Break */
\r
90 #define US_CR_STTTO (0x1u << 11) /**< \brief (US_CR) Start Time-out */
\r
91 #define US_CR_SENDA (0x1u << 12) /**< \brief (US_CR) Send Address */
\r
92 #define US_CR_RSTIT (0x1u << 13) /**< \brief (US_CR) Reset Iterations */
\r
93 #define US_CR_RSTNACK (0x1u << 14) /**< \brief (US_CR) Reset Non Acknowledge */
\r
94 #define US_CR_RETTO (0x1u << 15) /**< \brief (US_CR) Rearm Time-out */
\r
95 #define US_CR_DTREN (0x1u << 16) /**< \brief (US_CR) Data Terminal Ready Enable */
\r
96 #define US_CR_DTRDIS (0x1u << 17) /**< \brief (US_CR) Data Terminal Ready Disable */
\r
97 #define US_CR_RTSEN (0x1u << 18) /**< \brief (US_CR) Request to Send Enable */
\r
98 #define US_CR_RTSDIS (0x1u << 19) /**< \brief (US_CR) Request to Send Disable */
\r
99 #define US_CR_LINABT (0x1u << 20) /**< \brief (US_CR) Abort LIN Transmission */
\r
100 #define US_CR_LINWKUP (0x1u << 21) /**< \brief (US_CR) Send LIN Wakeup Signal */
\r
101 #define US_CR_FCS (0x1u << 18) /**< \brief (US_CR) Force SPI Chip Select */
\r
102 #define US_CR_RCS (0x1u << 19) /**< \brief (US_CR) Release SPI Chip Select */
\r
103 /* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */
\r
104 #define US_MR_USART_MODE_Pos 0
\r
105 #define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) /**< \brief (US_MR) USART Mode of Operation */
\r
106 #define US_MR_USART_MODE_NORMAL (0x0u << 0) /**< \brief (US_MR) Normal mode */
\r
107 #define US_MR_USART_MODE_RS485 (0x1u << 0) /**< \brief (US_MR) RS485 */
\r
108 #define US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) /**< \brief (US_MR) Hardware Handshaking */
\r
109 #define US_MR_USART_MODE_MODEM (0x3u << 0) /**< \brief (US_MR) Modem */
\r
110 #define US_MR_USART_MODE_IS07816_T_0 (0x4u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 0 */
\r
111 #define US_MR_USART_MODE_IS07816_T_1 (0x6u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 1 */
\r
112 #define US_MR_USART_MODE_IRDA (0x8u << 0) /**< \brief (US_MR) IrDA */
\r
113 #define US_MR_USART_MODE_LON (0x9u << 0) /**< \brief (US_MR) LON */
\r
114 #define US_MR_USART_MODE_SPI_MASTER (0xEu << 0) /**< \brief (US_MR) SPI master */
\r
115 #define US_MR_USART_MODE_SPI_SLAVE (0xFu << 0) /**< \brief (US_MR) SPI Slave */
\r
116 #define US_MR_USCLKS_Pos 4
\r
117 #define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) /**< \brief (US_MR) Clock Selection */
\r
118 #define US_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_MR) master Clock MCK is selected */
\r
119 #define US_MR_USCLKS_DIV (0x1u << 4) /**< \brief (US_MR) Internal Clock Divided MCK/DIV (DIV=DIV=8) is selected */
\r
120 #define US_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_MR) Serial Clock SLK is selected */
\r
121 #define US_MR_CHRL_Pos 6
\r
122 #define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) /**< \brief (US_MR) Character Length */
\r
123 #define US_MR_CHRL_5_BIT (0x0u << 6) /**< \brief (US_MR) Character length is 5 bits */
\r
124 #define US_MR_CHRL_6_BIT (0x1u << 6) /**< \brief (US_MR) Character length is 6 bits */
\r
125 #define US_MR_CHRL_7_BIT (0x2u << 6) /**< \brief (US_MR) Character length is 7 bits */
\r
126 #define US_MR_CHRL_8_BIT (0x3u << 6) /**< \brief (US_MR) Character length is 8 bits */
\r
127 #define US_MR_SYNC (0x1u << 8) /**< \brief (US_MR) Synchronous Mode Select */
\r
128 #define US_MR_PAR_Pos 9
\r
129 #define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) /**< \brief (US_MR) Parity Type */
\r
130 #define US_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_MR) Even parity */
\r
131 #define US_MR_PAR_ODD (0x1u << 9) /**< \brief (US_MR) Odd parity */
\r
132 #define US_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_MR) Parity forced to 0 (Space) */
\r
133 #define US_MR_PAR_MARK (0x3u << 9) /**< \brief (US_MR) Parity forced to 1 (Mark) */
\r
134 #define US_MR_PAR_NO (0x4u << 9) /**< \brief (US_MR) No parity */
\r
135 #define US_MR_PAR_MULTIDROP (0x6u << 9) /**< \brief (US_MR) Multidrop mode */
\r
136 #define US_MR_NBSTOP_Pos 12
\r
137 #define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) /**< \brief (US_MR) Number of Stop Bits */
\r
138 #define US_MR_NBSTOP_1_BIT (0x0u << 12) /**< \brief (US_MR) 1 stop bit */
\r
139 #define US_MR_NBSTOP_1_5_BIT (0x1u << 12) /**< \brief (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) */
\r
140 #define US_MR_NBSTOP_2_BIT (0x2u << 12) /**< \brief (US_MR) 2 stop bits */
\r
141 #define US_MR_CHMODE_Pos 14
\r
142 #define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) /**< \brief (US_MR) Channel Mode */
\r
143 #define US_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_MR) Normal mode */
\r
144 #define US_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */
\r
145 #define US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */
\r
146 #define US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */
\r
147 #define US_MR_MSBF (0x1u << 16) /**< \brief (US_MR) Bit Order */
\r
148 #define US_MR_MODE9 (0x1u << 17) /**< \brief (US_MR) 9-bit Character Length */
\r
149 #define US_MR_CLKO (0x1u << 18) /**< \brief (US_MR) Clock Output Select */
\r
150 #define US_MR_OVER (0x1u << 19) /**< \brief (US_MR) Oversampling Mode */
\r
151 #define US_MR_INACK (0x1u << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */
\r
152 #define US_MR_DSNACK (0x1u << 21) /**< \brief (US_MR) Disable Successive NACK */
\r
153 #define US_MR_VAR_SYNC (0x1u << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */
\r
154 #define US_MR_MAX_ITERATION_Pos 24
\r
155 #define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos) /**< \brief (US_MR) Maximum Number of Automatic Iteration */
\r
156 #define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos)))
\r
157 #define US_MR_FILTER (0x1u << 28) /**< \brief (US_MR) Infrared Receive Line Filter */
\r
158 #define US_MR_MAN (0x1u << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */
\r
159 #define US_MR_MODSYNC (0x1u << 30) /**< \brief (US_MR) Manchester Synchronization Mode */
\r
160 #define US_MR_ONEBIT (0x1u << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */
\r
161 #define US_MR_CPHA (0x1u << 8) /**< \brief (US_MR) SPI Clock Phase */
\r
162 #define US_MR_CPOL (0x1u << 16) /**< \brief (US_MR) SPI Clock Polarity */
\r
163 #define US_MR_WRDBT (0x1u << 20) /**< \brief (US_MR) Wait Read Data Before Transfer */
\r
164 /* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */
\r
165 #define US_IER_RXRDY (0x1u << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */
\r
166 #define US_IER_TXRDY (0x1u << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */
\r
167 #define US_IER_RXBRK (0x1u << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */
\r
168 #define US_IER_OVRE (0x1u << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */
\r
169 #define US_IER_FRAME (0x1u << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */
\r
170 #define US_IER_PARE (0x1u << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */
\r
171 #define US_IER_TIMEOUT (0x1u << 8) /**< \brief (US_IER) Time-out Interrupt Enable */
\r
172 #define US_IER_TXEMPTY (0x1u << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */
\r
173 #define US_IER_ITER (0x1u << 10) /**< \brief (US_IER) Max number of Repetitions Reached Interrupt Enable */
\r
174 #define US_IER_NACK (0x1u << 13) /**< \brief (US_IER) Non Acknowledge Interrupt Enable */
\r
175 #define US_IER_RIIC (0x1u << 16) /**< \brief (US_IER) Ring Indicator Input Change Enable */
\r
176 #define US_IER_DSRIC (0x1u << 17) /**< \brief (US_IER) Data Set Ready Input Change Enable */
\r
177 #define US_IER_DCDIC (0x1u << 18) /**< \brief (US_IER) Data Carrier Detect Input Change Interrupt Enable */
\r
178 #define US_IER_CTSIC (0x1u << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */
\r
179 #define US_IER_MANE (0x1u << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */
\r
180 #define US_IER_UNRE (0x1u << 10) /**< \brief (US_IER) SPI Underrun Error Interrupt Enable */
\r
181 #define US_IER_LINBK (0x1u << 13) /**< \brief (US_IER) LIN Break Sent or LIN Break Received Interrupt Enable */
\r
182 #define US_IER_LINID (0x1u << 14) /**< \brief (US_IER) LIN Identifier Sent or LIN Identifier Received Interrupt Enable */
\r
183 #define US_IER_LINTC (0x1u << 15) /**< \brief (US_IER) LIN Transfer Completed Interrupt Enable */
\r
184 #define US_IER_LINBE (0x1u << 25) /**< \brief (US_IER) LIN Bus Error Interrupt Enable */
\r
185 #define US_IER_LINISFE (0x1u << 26) /**< \brief (US_IER) LIN Inconsistent Synch Field Error Interrupt Enable */
\r
186 #define US_IER_LINIPE (0x1u << 27) /**< \brief (US_IER) LIN Identifier Parity Interrupt Enable */
\r
187 #define US_IER_LINCE (0x1u << 28) /**< \brief (US_IER) LIN Checksum Error Interrupt Enable */
\r
188 #define US_IER_LINSNRE (0x1u << 29) /**< \brief (US_IER) LIN Slave Not Responding Error Interrupt Enable */
\r
189 #define US_IER_LINSTE (0x1u << 30) /**< \brief (US_IER) LIN Synch Tolerance Error Interrupt Enable */
\r
190 #define US_IER_LINHTE (0x1u << 31) /**< \brief (US_IER) LIN Header Timeout Error Interrupt Enable */
\r
191 #define US_IER_LSFE (0x1u << 6) /**< \brief (US_IER) LON Short Frame Error Interrupt Enable */
\r
192 #define US_IER_LCRCE (0x1u << 7) /**< \brief (US_IER) LON CRC Error Interrupt Enable */
\r
193 #define US_IER_LTXD (0x1u << 24) /**< \brief (US_IER) LON Transmission Done Interrupt Enable */
\r
194 #define US_IER_LCOL (0x1u << 25) /**< \brief (US_IER) LON Collision Interrupt Enable */
\r
195 #define US_IER_LFET (0x1u << 26) /**< \brief (US_IER) LON Frame Early Termination Interrupt Enable */
\r
196 #define US_IER_LRXD (0x1u << 27) /**< \brief (US_IER) LON Reception Done Interrupt Enable */
\r
197 #define US_IER_LBLOVFE (0x1u << 28) /**< \brief (US_IER) LON Backlog Overflow Error Interrupt Enable */
\r
198 /* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */
\r
199 #define US_IDR_RXRDY (0x1u << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */
\r
200 #define US_IDR_TXRDY (0x1u << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */
\r
201 #define US_IDR_RXBRK (0x1u << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */
\r
202 #define US_IDR_OVRE (0x1u << 5) /**< \brief (US_IDR) Overrun Error Interrupt Enable */
\r
203 #define US_IDR_FRAME (0x1u << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */
\r
204 #define US_IDR_PARE (0x1u << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */
\r
205 #define US_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */
\r
206 #define US_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */
\r
207 #define US_IDR_ITER (0x1u << 10) /**< \brief (US_IDR) Max Number of Repetitions Reached Interrupt Disable */
\r
208 #define US_IDR_NACK (0x1u << 13) /**< \brief (US_IDR) Non Acknowledge Interrupt Disable */
\r
209 #define US_IDR_RIIC (0x1u << 16) /**< \brief (US_IDR) Ring Indicator Input Change Disable */
\r
210 #define US_IDR_DSRIC (0x1u << 17) /**< \brief (US_IDR) Data Set Ready Input Change Disable */
\r
211 #define US_IDR_DCDIC (0x1u << 18) /**< \brief (US_IDR) Data Carrier Detect Input Change Interrupt Disable */
\r
212 #define US_IDR_CTSIC (0x1u << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */
\r
213 #define US_IDR_MANE (0x1u << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */
\r
214 #define US_IDR_UNRE (0x1u << 10) /**< \brief (US_IDR) SPI Underrun Error Interrupt Disable */
\r
215 #define US_IDR_LINBK (0x1u << 13) /**< \brief (US_IDR) LIN Break Sent or LIN Break Received Interrupt Disable */
\r
216 #define US_IDR_LINID (0x1u << 14) /**< \brief (US_IDR) LIN Identifier Sent or LIN Identifier Received Interrupt Disable */
\r
217 #define US_IDR_LINTC (0x1u << 15) /**< \brief (US_IDR) LIN Transfer Completed Interrupt Disable */
\r
218 #define US_IDR_LINBE (0x1u << 25) /**< \brief (US_IDR) LIN Bus Error Interrupt Disable */
\r
219 #define US_IDR_LINISFE (0x1u << 26) /**< \brief (US_IDR) LIN Inconsistent Synch Field Error Interrupt Disable */
\r
220 #define US_IDR_LINIPE (0x1u << 27) /**< \brief (US_IDR) LIN Identifier Parity Interrupt Disable */
\r
221 #define US_IDR_LINCE (0x1u << 28) /**< \brief (US_IDR) LIN Checksum Error Interrupt Disable */
\r
222 #define US_IDR_LINSNRE (0x1u << 29) /**< \brief (US_IDR) LIN Slave Not Responding Error Interrupt Disable */
\r
223 #define US_IDR_LINSTE (0x1u << 30) /**< \brief (US_IDR) LIN Synch Tolerance Error Interrupt Disable */
\r
224 #define US_IDR_LINHTE (0x1u << 31) /**< \brief (US_IDR) LIN Header Timeout Error Interrupt Disable */
\r
225 #define US_IDR_LSFE (0x1u << 6) /**< \brief (US_IDR) LON Short Frame Error Interrupt Disable */
\r
226 #define US_IDR_LCRCE (0x1u << 7) /**< \brief (US_IDR) LON CRC Error Interrupt Disable */
\r
227 #define US_IDR_LTXD (0x1u << 24) /**< \brief (US_IDR) LON Transmission Done Interrupt Disable */
\r
228 #define US_IDR_LCOL (0x1u << 25) /**< \brief (US_IDR) LON Collision Interrupt Disable */
\r
229 #define US_IDR_LFET (0x1u << 26) /**< \brief (US_IDR) LON Frame Early Termination Interrupt Disable */
\r
230 #define US_IDR_LRXD (0x1u << 27) /**< \brief (US_IDR) LON Reception Done Interrupt Disable */
\r
231 #define US_IDR_LBLOVFE (0x1u << 28) /**< \brief (US_IDR) LON Backlog Overflow Error Interrupt Disable */
\r
232 /* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */
\r
233 #define US_IMR_RXRDY (0x1u << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */
\r
234 #define US_IMR_TXRDY (0x1u << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */
\r
235 #define US_IMR_RXBRK (0x1u << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */
\r
236 #define US_IMR_OVRE (0x1u << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */
\r
237 #define US_IMR_FRAME (0x1u << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */
\r
238 #define US_IMR_PARE (0x1u << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */
\r
239 #define US_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */
\r
240 #define US_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */
\r
241 #define US_IMR_ITER (0x1u << 10) /**< \brief (US_IMR) Max Number of Repetitions Reached Interrupt Mask */
\r
242 #define US_IMR_NACK (0x1u << 13) /**< \brief (US_IMR) Non Acknowledge Interrupt Mask */
\r
243 #define US_IMR_RIIC (0x1u << 16) /**< \brief (US_IMR) Ring Indicator Input Change Mask */
\r
244 #define US_IMR_DSRIC (0x1u << 17) /**< \brief (US_IMR) Data Set Ready Input Change Mask */
\r
245 #define US_IMR_DCDIC (0x1u << 18) /**< \brief (US_IMR) Data Carrier Detect Input Change Interrupt Mask */
\r
246 #define US_IMR_CTSIC (0x1u << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */
\r
247 #define US_IMR_MANE (0x1u << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */
\r
248 #define US_IMR_UNRE (0x1u << 10) /**< \brief (US_IMR) SPI Underrun Error Interrupt Mask */
\r
249 #define US_IMR_LINBK (0x1u << 13) /**< \brief (US_IMR) LIN Break Sent or LIN Break Received Interrupt Mask */
\r
250 #define US_IMR_LINID (0x1u << 14) /**< \brief (US_IMR) LIN Identifier Sent or LIN Identifier Received Interrupt Mask */
\r
251 #define US_IMR_LINTC (0x1u << 15) /**< \brief (US_IMR) LIN Transfer Completed Interrupt Mask */
\r
252 #define US_IMR_LINBE (0x1u << 25) /**< \brief (US_IMR) LIN Bus Error Interrupt Mask */
\r
253 #define US_IMR_LINISFE (0x1u << 26) /**< \brief (US_IMR) LIN Inconsistent Synch Field Error Interrupt Mask */
\r
254 #define US_IMR_LINIPE (0x1u << 27) /**< \brief (US_IMR) LIN Identifier Parity Interrupt Mask */
\r
255 #define US_IMR_LINCE (0x1u << 28) /**< \brief (US_IMR) LIN Checksum Error Interrupt Mask */
\r
256 #define US_IMR_LINSNRE (0x1u << 29) /**< \brief (US_IMR) LIN Slave Not Responding Error Interrupt Mask */
\r
257 #define US_IMR_LINSTE (0x1u << 30) /**< \brief (US_IMR) LIN Synch Tolerance Error Interrupt Mask */
\r
258 #define US_IMR_LINHTE (0x1u << 31) /**< \brief (US_IMR) LIN Header Timeout Error Interrupt Mask */
\r
259 #define US_IMR_LSFE (0x1u << 6) /**< \brief (US_IMR) LON Short Frame Error Interrupt Mask */
\r
260 #define US_IMR_LCRCE (0x1u << 7) /**< \brief (US_IMR) LON CRC Error Interrupt Mask */
\r
261 #define US_IMR_LTXD (0x1u << 24) /**< \brief (US_IMR) LON Transmission Done Interrupt Mask */
\r
262 #define US_IMR_LCOL (0x1u << 25) /**< \brief (US_IMR) LON Collision Interrupt Mask */
\r
263 #define US_IMR_LFET (0x1u << 26) /**< \brief (US_IMR) LON Frame Early Termination Interrupt Mask */
\r
264 #define US_IMR_LRXD (0x1u << 27) /**< \brief (US_IMR) LON Reception Done Interrupt Mask */
\r
265 #define US_IMR_LBLOVFE (0x1u << 28) /**< \brief (US_IMR) LON Backlog Overflow Error Interrupt Mask */
\r
266 /* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */
\r
267 #define US_CSR_RXRDY (0x1u << 0) /**< \brief (US_CSR) Receiver Ready */
\r
268 #define US_CSR_TXRDY (0x1u << 1) /**< \brief (US_CSR) Transmitter Ready */
\r
269 #define US_CSR_RXBRK (0x1u << 2) /**< \brief (US_CSR) Break Received/End of Break */
\r
270 #define US_CSR_OVRE (0x1u << 5) /**< \brief (US_CSR) Overrun Error */
\r
271 #define US_CSR_FRAME (0x1u << 6) /**< \brief (US_CSR) Framing Error */
\r
272 #define US_CSR_PARE (0x1u << 7) /**< \brief (US_CSR) Parity Error */
\r
273 #define US_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_CSR) Receiver Time-out */
\r
274 #define US_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_CSR) Transmitter Empty */
\r
275 #define US_CSR_ITER (0x1u << 10) /**< \brief (US_CSR) Max Number of Repetitions Reached */
\r
276 #define US_CSR_NACK (0x1u << 13) /**< \brief (US_CSR) Non Acknowledge Interrupt */
\r
277 #define US_CSR_RIIC (0x1u << 16) /**< \brief (US_CSR) Ring Indicator Input Change Flag */
\r
278 #define US_CSR_DSRIC (0x1u << 17) /**< \brief (US_CSR) Data Set Ready Input Change Flag */
\r
279 #define US_CSR_DCDIC (0x1u << 18) /**< \brief (US_CSR) Data Carrier Detect Input Change Flag */
\r
280 #define US_CSR_CTSIC (0x1u << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag */
\r
281 #define US_CSR_RI (0x1u << 20) /**< \brief (US_CSR) Image of RI Input */
\r
282 #define US_CSR_DSR (0x1u << 21) /**< \brief (US_CSR) Image of DSR Input */
\r
283 #define US_CSR_DCD (0x1u << 22) /**< \brief (US_CSR) Image of DCD Input */
\r
284 #define US_CSR_CTS (0x1u << 23) /**< \brief (US_CSR) Image of CTS Input */
\r
285 #define US_CSR_MANERR (0x1u << 24) /**< \brief (US_CSR) Manchester Error */
\r
286 #define US_CSR_UNRE (0x1u << 10) /**< \brief (US_CSR) Underrun Error */
\r
287 #define US_CSR_LINBK (0x1u << 13) /**< \brief (US_CSR) LIN Break Sent or LIN Break Received */
\r
288 #define US_CSR_LINID (0x1u << 14) /**< \brief (US_CSR) LIN Identifier Sent or LIN Identifier Received */
\r
289 #define US_CSR_LINTC (0x1u << 15) /**< \brief (US_CSR) LIN Transfer Completed */
\r
290 #define US_CSR_LINBLS (0x1u << 23) /**< \brief (US_CSR) LIN Bus Line Status */
\r
291 #define US_CSR_LINBE (0x1u << 25) /**< \brief (US_CSR) LIN Bit Error */
\r
292 #define US_CSR_LINISFE (0x1u << 26) /**< \brief (US_CSR) LIN Inconsistent Synch Field Error */
\r
293 #define US_CSR_LINIPE (0x1u << 27) /**< \brief (US_CSR) LIN Identifier Parity Error */
\r
294 #define US_CSR_LINCE (0x1u << 28) /**< \brief (US_CSR) LIN Checksum Error */
\r
295 #define US_CSR_LINSNRE (0x1u << 29) /**< \brief (US_CSR) LIN Slave Not Responding Error */
\r
296 #define US_CSR_LINSTE (0x1u << 30) /**< \brief (US_CSR) LIN Synch Tolerance Error */
\r
297 #define US_CSR_LINHTE (0x1u << 31) /**< \brief (US_CSR) LIN Header Timeout Error */
\r
298 #define US_CSR_LSFE (0x1u << 6) /**< \brief (US_CSR) LON Short Frame Error */
\r
299 #define US_CSR_LCRCE (0x1u << 7) /**< \brief (US_CSR) LON CRC Error */
\r
300 #define US_CSR_LTXD (0x1u << 24) /**< \brief (US_CSR) LON Transmission End Flag */
\r
301 #define US_CSR_LCOL (0x1u << 25) /**< \brief (US_CSR) LON Collision Detected Flag */
\r
302 #define US_CSR_LFET (0x1u << 26) /**< \brief (US_CSR) LON Frame Early Termination */
\r
303 #define US_CSR_LRXD (0x1u << 27) /**< \brief (US_CSR) LON Reception End Flag */
\r
304 #define US_CSR_LBLOVFE (0x1u << 28) /**< \brief (US_CSR) LON Backlog Overflow Error */
\r
305 /* -------- US_RHR : (USART Offset: 0x0018) Receive Holding Register -------- */
\r
306 #define US_RHR_RXCHR_Pos 0
\r
307 #define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) /**< \brief (US_RHR) Received Character */
\r
308 #define US_RHR_RXSYNH (0x1u << 15) /**< \brief (US_RHR) Received Sync */
\r
309 /* -------- US_THR : (USART Offset: 0x001C) Transmit Holding Register -------- */
\r
310 #define US_THR_TXCHR_Pos 0
\r
311 #define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) /**< \brief (US_THR) Character to be Transmitted */
\r
312 #define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos)))
\r
313 #define US_THR_TXSYNH (0x1u << 15) /**< \brief (US_THR) Sync Field to be Transmitted */
\r
314 /* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */
\r
315 #define US_BRGR_CD_Pos 0
\r
316 #define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) /**< \brief (US_BRGR) Clock Divider */
\r
317 #define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos)))
\r
318 #define US_BRGR_FP_Pos 16
\r
319 #define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) /**< \brief (US_BRGR) Fractional Part */
\r
320 #define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos)))
\r
321 /* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */
\r
322 #define US_RTOR_TO_Pos 0
\r
323 #define US_RTOR_TO_Msk (0x1ffffu << US_RTOR_TO_Pos) /**< \brief (US_RTOR) Time-out Value */
\r
324 #define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos)))
\r
325 /* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */
\r
326 #define US_TTGR_TG_Pos 0
\r
327 #define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) /**< \brief (US_TTGR) Timeguard Value */
\r
328 #define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos)))
\r
329 #define US_TTGR_PCYCLE_Pos 0
\r
330 #define US_TTGR_PCYCLE_Msk (0xffffffu << US_TTGR_PCYCLE_Pos) /**< \brief (US_TTGR) LON PCYCLE Length */
\r
331 #define US_TTGR_PCYCLE(value) ((US_TTGR_PCYCLE_Msk & ((value) << US_TTGR_PCYCLE_Pos)))
\r
332 /* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */
\r
333 #define US_FIDI_FI_DI_RATIO_Pos 0
\r
334 #define US_FIDI_FI_DI_RATIO_Msk (0xffffu << US_FIDI_FI_DI_RATIO_Pos) /**< \brief (US_FIDI) FI Over DI Ratio Value */
\r
335 #define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos)))
\r
336 #define US_FIDI_BETA2_Pos 0
\r
337 #define US_FIDI_BETA2_Msk (0xffffffu << US_FIDI_BETA2_Pos) /**< \brief (US_FIDI) LON BETA2 Length */
\r
338 #define US_FIDI_BETA2(value) ((US_FIDI_BETA2_Msk & ((value) << US_FIDI_BETA2_Pos)))
\r
339 /* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */
\r
340 #define US_NER_NB_ERRORS_Pos 0
\r
341 #define US_NER_NB_ERRORS_Msk (0xffu << US_NER_NB_ERRORS_Pos) /**< \brief (US_NER) Number of Errors */
\r
342 /* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */
\r
343 #define US_IF_IRDA_FILTER_Pos 0
\r
344 #define US_IF_IRDA_FILTER_Msk (0xffu << US_IF_IRDA_FILTER_Pos) /**< \brief (US_IF) IrDA Filter */
\r
345 #define US_IF_IRDA_FILTER(value) ((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos)))
\r
346 /* -------- US_MAN : (USART Offset: 0x0050) Manchester Configuration Register -------- */
\r
347 #define US_MAN_TX_PL_Pos 0
\r
348 #define US_MAN_TX_PL_Msk (0xfu << US_MAN_TX_PL_Pos) /**< \brief (US_MAN) Transmitter Preamble Length */
\r
349 #define US_MAN_TX_PL(value) ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos)))
\r
350 #define US_MAN_TX_PP_Pos 8
\r
351 #define US_MAN_TX_PP_Msk (0x3u << US_MAN_TX_PP_Pos) /**< \brief (US_MAN) Transmitter Preamble Pattern */
\r
352 #define US_MAN_TX_PP_ALL_ONE (0x0u << 8) /**< \brief (US_MAN) The preamble is composed of '1's */
\r
353 #define US_MAN_TX_PP_ALL_ZERO (0x1u << 8) /**< \brief (US_MAN) The preamble is composed of '0's */
\r
354 #define US_MAN_TX_PP_ZERO_ONE (0x2u << 8) /**< \brief (US_MAN) The preamble is composed of '01's */
\r
355 #define US_MAN_TX_PP_ONE_ZERO (0x3u << 8) /**< \brief (US_MAN) The preamble is composed of '10's */
\r
356 #define US_MAN_TX_MPOL (0x1u << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */
\r
357 #define US_MAN_RX_PL_Pos 16
\r
358 #define US_MAN_RX_PL_Msk (0xfu << US_MAN_RX_PL_Pos) /**< \brief (US_MAN) Receiver Preamble Length */
\r
359 #define US_MAN_RX_PL(value) ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos)))
\r
360 #define US_MAN_RX_PP_Pos 24
\r
361 #define US_MAN_RX_PP_Msk (0x3u << US_MAN_RX_PP_Pos) /**< \brief (US_MAN) Receiver Preamble Pattern detected */
\r
362 #define US_MAN_RX_PP_ALL_ONE (0x0u << 24) /**< \brief (US_MAN) The preamble is composed of '1's */
\r
363 #define US_MAN_RX_PP_ALL_ZERO (0x1u << 24) /**< \brief (US_MAN) The preamble is composed of '0's */
\r
364 #define US_MAN_RX_PP_ZERO_ONE (0x2u << 24) /**< \brief (US_MAN) The preamble is composed of '01's */
\r
365 #define US_MAN_RX_PP_ONE_ZERO (0x3u << 24) /**< \brief (US_MAN) The preamble is composed of '10's */
\r
366 #define US_MAN_RX_MPOL (0x1u << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */
\r
367 #define US_MAN_ONE (0x1u << 29) /**< \brief (US_MAN) Must Be Set to 1 */
\r
368 #define US_MAN_DRIFT (0x1u << 30) /**< \brief (US_MAN) Drift Compensation */
\r
369 #define US_MAN_RXIDLEV (0x1u << 31) /**< \brief (US_MAN) Receiver Idle Value */
\r
370 /* -------- US_LINMR : (USART Offset: 0x0054) LIN Mode Register -------- */
\r
371 #define US_LINMR_NACT_Pos 0
\r
372 #define US_LINMR_NACT_Msk (0x3u << US_LINMR_NACT_Pos) /**< \brief (US_LINMR) LIN Node Action */
\r
373 #define US_LINMR_NACT_PUBLISH (0x0u << 0) /**< \brief (US_LINMR) The USART transmits the response. */
\r
374 #define US_LINMR_NACT_SUBSCRIBE (0x1u << 0) /**< \brief (US_LINMR) The USART receives the response. */
\r
375 #define US_LINMR_NACT_IGNORE (0x2u << 0) /**< \brief (US_LINMR) The USART does not transmit and does not receive the response. */
\r
376 #define US_LINMR_PARDIS (0x1u << 2) /**< \brief (US_LINMR) Parity Disable */
\r
377 #define US_LINMR_CHKDIS (0x1u << 3) /**< \brief (US_LINMR) Checksum Disable */
\r
378 #define US_LINMR_CHKTYP (0x1u << 4) /**< \brief (US_LINMR) Checksum Type */
\r
379 #define US_LINMR_DLM (0x1u << 5) /**< \brief (US_LINMR) Data Length Mode */
\r
380 #define US_LINMR_FSDIS (0x1u << 6) /**< \brief (US_LINMR) Frame Slot Mode Disable */
\r
381 #define US_LINMR_WKUPTYP (0x1u << 7) /**< \brief (US_LINMR) Wakeup Signal Type */
\r
382 #define US_LINMR_DLC_Pos 8
\r
383 #define US_LINMR_DLC_Msk (0xffu << US_LINMR_DLC_Pos) /**< \brief (US_LINMR) Data Length Control */
\r
384 #define US_LINMR_DLC(value) ((US_LINMR_DLC_Msk & ((value) << US_LINMR_DLC_Pos)))
\r
385 #define US_LINMR_PDCM (0x1u << 16) /**< \brief (US_LINMR) DMAC Mode */
\r
386 #define US_LINMR_SYNCDIS (0x1u << 17) /**< \brief (US_LINMR) Synchronization Disable */
\r
387 /* -------- US_LINIR : (USART Offset: 0x0058) LIN Identifier Register -------- */
\r
388 #define US_LINIR_IDCHR_Pos 0
\r
389 #define US_LINIR_IDCHR_Msk (0xffu << US_LINIR_IDCHR_Pos) /**< \brief (US_LINIR) Identifier Character */
\r
390 #define US_LINIR_IDCHR(value) ((US_LINIR_IDCHR_Msk & ((value) << US_LINIR_IDCHR_Pos)))
\r
391 /* -------- US_LINBRR : (USART Offset: 0x005C) LIN Baud Rate Register -------- */
\r
392 #define US_LINBRR_LINCD_Pos 0
\r
393 #define US_LINBRR_LINCD_Msk (0xffffu << US_LINBRR_LINCD_Pos) /**< \brief (US_LINBRR) Clock Divider after Synchronization */
\r
394 #define US_LINBRR_LINFP_Pos 16
\r
395 #define US_LINBRR_LINFP_Msk (0x7u << US_LINBRR_LINFP_Pos) /**< \brief (US_LINBRR) Fractional Part after Synchronization */
\r
396 /* -------- US_LONMR : (USART Offset: 0x0060) LON Mode Register -------- */
\r
397 #define US_LONMR_COMMT (0x1u << 0) /**< \brief (US_LONMR) LON comm_type Parameter Value */
\r
398 #define US_LONMR_COLDET (0x1u << 1) /**< \brief (US_LONMR) LON Collision Detection Feature */
\r
399 #define US_LONMR_TCOL (0x1u << 2) /**< \brief (US_LONMR) Terminate Frame upon Collision Notification */
\r
400 #define US_LONMR_CDTAIL (0x1u << 3) /**< \brief (US_LONMR) LON Collision Detection on Frame Tail */
\r
401 #define US_LONMR_DMAM (0x1u << 4) /**< \brief (US_LONMR) LON DMA Mode */
\r
402 #define US_LONMR_LCDS (0x1u << 5) /**< \brief (US_LONMR) LON Collision Detection Source */
\r
403 #define US_LONMR_EOFS_Pos 16
\r
404 #define US_LONMR_EOFS_Msk (0xffu << US_LONMR_EOFS_Pos) /**< \brief (US_LONMR) End of Frame Condition Size */
\r
405 #define US_LONMR_EOFS(value) ((US_LONMR_EOFS_Msk & ((value) << US_LONMR_EOFS_Pos)))
\r
406 /* -------- US_LONPR : (USART Offset: 0x0064) LON Preamble Register -------- */
\r
407 #define US_LONPR_LONPL_Pos 0
\r
408 #define US_LONPR_LONPL_Msk (0x3fffu << US_LONPR_LONPL_Pos) /**< \brief (US_LONPR) LON Preamble Length */
\r
409 #define US_LONPR_LONPL(value) ((US_LONPR_LONPL_Msk & ((value) << US_LONPR_LONPL_Pos)))
\r
410 /* -------- US_LONDL : (USART Offset: 0x0068) LON Data Length Register -------- */
\r
411 #define US_LONDL_LONDL_Pos 0
\r
412 #define US_LONDL_LONDL_Msk (0xffu << US_LONDL_LONDL_Pos) /**< \brief (US_LONDL) LON Data Length */
\r
413 #define US_LONDL_LONDL(value) ((US_LONDL_LONDL_Msk & ((value) << US_LONDL_LONDL_Pos)))
\r
414 /* -------- US_LONL2HDR : (USART Offset: 0x006C) LON L2HDR Register -------- */
\r
415 #define US_LONL2HDR_BLI_Pos 0
\r
416 #define US_LONL2HDR_BLI_Msk (0x3fu << US_LONL2HDR_BLI_Pos) /**< \brief (US_LONL2HDR) LON Backlog Increment */
\r
417 #define US_LONL2HDR_BLI(value) ((US_LONL2HDR_BLI_Msk & ((value) << US_LONL2HDR_BLI_Pos)))
\r
418 #define US_LONL2HDR_ALTP (0x1u << 6) /**< \brief (US_LONL2HDR) LON Alternate Path Bit */
\r
419 #define US_LONL2HDR_PB (0x1u << 7) /**< \brief (US_LONL2HDR) LON Priority Bit */
\r
420 /* -------- US_LONBL : (USART Offset: 0x0070) LON Backlog Register -------- */
\r
421 #define US_LONBL_LONBL_Pos 0
\r
422 #define US_LONBL_LONBL_Msk (0x3fu << US_LONBL_LONBL_Pos) /**< \brief (US_LONBL) LON Node Backlog Value */
\r
423 /* -------- US_LONB1TX : (USART Offset: 0x0074) LON Beta1 Tx Register -------- */
\r
424 #define US_LONB1TX_BETA1TX_Pos 0
\r
425 #define US_LONB1TX_BETA1TX_Msk (0xffffffu << US_LONB1TX_BETA1TX_Pos) /**< \brief (US_LONB1TX) LON Beta1 Length after Transmission */
\r
426 #define US_LONB1TX_BETA1TX(value) ((US_LONB1TX_BETA1TX_Msk & ((value) << US_LONB1TX_BETA1TX_Pos)))
\r
427 /* -------- US_LONB1RX : (USART Offset: 0x0078) LON Beta1 Rx Register -------- */
\r
428 #define US_LONB1RX_BETA1RX_Pos 0
\r
429 #define US_LONB1RX_BETA1RX_Msk (0xffffffu << US_LONB1RX_BETA1RX_Pos) /**< \brief (US_LONB1RX) LON Beta1 Length after Reception */
\r
430 #define US_LONB1RX_BETA1RX(value) ((US_LONB1RX_BETA1RX_Msk & ((value) << US_LONB1RX_BETA1RX_Pos)))
\r
431 /* -------- US_LONPRIO : (USART Offset: 0x007C) LON Priority Register -------- */
\r
432 #define US_LONPRIO_PSNB_Pos 0
\r
433 #define US_LONPRIO_PSNB_Msk (0x7fu << US_LONPRIO_PSNB_Pos) /**< \brief (US_LONPRIO) LON Priority Slot Number */
\r
434 #define US_LONPRIO_PSNB(value) ((US_LONPRIO_PSNB_Msk & ((value) << US_LONPRIO_PSNB_Pos)))
\r
435 #define US_LONPRIO_NPS_Pos 8
\r
436 #define US_LONPRIO_NPS_Msk (0x7fu << US_LONPRIO_NPS_Pos) /**< \brief (US_LONPRIO) LON Node Priority Slot */
\r
437 #define US_LONPRIO_NPS(value) ((US_LONPRIO_NPS_Msk & ((value) << US_LONPRIO_NPS_Pos)))
\r
438 /* -------- US_IDTTX : (USART Offset: 0x0080) LON IDT Tx Register -------- */
\r
439 #define US_IDTTX_IDTTX_Pos 0
\r
440 #define US_IDTTX_IDTTX_Msk (0xffffffu << US_IDTTX_IDTTX_Pos) /**< \brief (US_IDTTX) LON Indeterminate Time after Transmission (comm_type = 1 mode only) */
\r
441 #define US_IDTTX_IDTTX(value) ((US_IDTTX_IDTTX_Msk & ((value) << US_IDTTX_IDTTX_Pos)))
\r
442 /* -------- US_IDTRX : (USART Offset: 0x0084) LON IDT Rx Register -------- */
\r
443 #define US_IDTRX_IDTRX_Pos 0
\r
444 #define US_IDTRX_IDTRX_Msk (0xffffffu << US_IDTRX_IDTRX_Pos) /**< \brief (US_IDTRX) LON Indeterminate Time after Reception (comm_type = 1 mode only) */
\r
445 #define US_IDTRX_IDTRX(value) ((US_IDTRX_IDTRX_Msk & ((value) << US_IDTRX_IDTRX_Pos)))
\r
446 /* -------- US_ICDIFF : (USART Offset: 0x0088) IC DIFF Register -------- */
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447 #define US_ICDIFF_ICDIFF_Pos 0
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448 #define US_ICDIFF_ICDIFF_Msk (0xfu << US_ICDIFF_ICDIFF_Pos) /**< \brief (US_ICDIFF) IC Differentiator Number */
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449 #define US_ICDIFF_ICDIFF(value) ((US_ICDIFF_ICDIFF_Msk & ((value) << US_ICDIFF_ICDIFF_Pos)))
\r
450 /* -------- US_WPMR : (USART Offset: 0x00E4) Write Protection Mode Register -------- */
\r
451 #define US_WPMR_WPEN (0x1u << 0) /**< \brief (US_WPMR) Write Protection Enable */
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452 #define US_WPMR_WPKEY_Pos 8
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453 #define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) /**< \brief (US_WPMR) Write Protection Key */
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454 #define US_WPMR_WPKEY_PASSWD (0x555341u << 8) /**< \brief (US_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */
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455 /* -------- US_WPSR : (USART Offset: 0x00E8) Write Protection Status Register -------- */
\r
456 #define US_WPSR_WPVS (0x1u << 0) /**< \brief (US_WPSR) Write Protection Violation Status */
\r
457 #define US_WPSR_WPVSRC_Pos 8
\r
458 #define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) /**< \brief (US_WPSR) Write Protection Violation Source */
\r
459 /* -------- US_VERSION : (USART Offset: 0x00FC) Version Register -------- */
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460 #define US_VERSION_VERSION_Pos 0
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461 #define US_VERSION_VERSION_Msk (0xfffu << US_VERSION_VERSION_Pos) /**< \brief (US_VERSION) Hardware Module Version */
\r
462 #define US_VERSION_MFN_Pos 16
\r
463 #define US_VERSION_MFN_Msk (0x7u << US_VERSION_MFN_Pos) /**< \brief (US_VERSION) Metal Fix Number */
\r
468 #endif /* _SAM_USART_COMPONENT_ */
\r
projects / freertos / blob