1 /* ---------------------------------------------------------------------------- */
\r
2 /* Atmel Microcontroller Software Support */
\r
3 /* SAM Software Package License */
\r
4 /* ---------------------------------------------------------------------------- */
\r
5 /* Copyright (c) 2014, Atmel Corporation */
\r
7 /* All rights reserved. */
\r
9 /* Redistribution and use in source and binary forms, with or without */
\r
10 /* modification, are permitted provided that the following condition is met: */
\r
12 /* - Redistributions of source code must retain the above copyright notice, */
\r
13 /* this list of conditions and the disclaimer below. */
\r
15 /* Atmel's name may not be used to endorse or promote products derived from */
\r
16 /* this software without specific prior written permission. */
\r
18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
\r
19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
\r
20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
\r
21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
\r
22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
\r
23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
\r
24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
\r
25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
\r
26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
\r
27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
\r
28 /* ---------------------------------------------------------------------------- */
\r
30 #ifndef _SAM_DACC_INSTANCE_
\r
31 #define _SAM_DACC_INSTANCE_
\r
33 /* ========== Register definition for DACC peripheral ========== */
\r
34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
\r
35 #define REG_DACC_CR (0x40040000U) /**< \brief (DACC) Control Register */
\r
36 #define REG_DACC_MR (0x40040004U) /**< \brief (DACC) Mode Register */
\r
37 #define REG_DACC_TRIGR (0x40040008U) /**< \brief (DACC) Trigger Register */
\r
38 #define REG_DACC_CHER (0x40040010U) /**< \brief (DACC) Channel Enable Register */
\r
39 #define REG_DACC_CHDR (0x40040014U) /**< \brief (DACC) Channel Disable Register */
\r
40 #define REG_DACC_CHSR (0x40040018U) /**< \brief (DACC) Channel Status Register */
\r
41 #define REG_DACC_CDR (0x4004001CU) /**< \brief (DACC) Conversion Data Register */
\r
42 #define REG_DACC_IER (0x40040024U) /**< \brief (DACC) Interrupt Enable Register */
\r
43 #define REG_DACC_IDR (0x40040028U) /**< \brief (DACC) Interrupt Disable Register */
\r
44 #define REG_DACC_IMR (0x4004002CU) /**< \brief (DACC) Interrupt Mask Register */
\r
45 #define REG_DACC_ISR (0x40040030U) /**< \brief (DACC) Interrupt Status Register */
\r
46 #define REG_DACC_ACR (0x40040094U) /**< \brief (DACC) Analog Current Register */
\r
47 #define REG_DACC_WPMR (0x400400E4U) /**< \brief (DACC) Write Protection Mode register */
\r
48 #define REG_DACC_WPSR (0x400400E8U) /**< \brief (DACC) Write Protection Status register */
\r
50 #define REG_DACC_CR (*(__O uint32_t*)0x40040000U) /**< \brief (DACC) Control Register */
\r
51 #define REG_DACC_MR (*(__IO uint32_t*)0x40040004U) /**< \brief (DACC) Mode Register */
\r
52 #define REG_DACC_TRIGR (*(__IO uint32_t*)0x40040008U) /**< \brief (DACC) Trigger Register */
\r
53 #define REG_DACC_CHER (*(__O uint32_t*)0x40040010U) /**< \brief (DACC) Channel Enable Register */
\r
54 #define REG_DACC_CHDR (*(__O uint32_t*)0x40040014U) /**< \brief (DACC) Channel Disable Register */
\r
55 #define REG_DACC_CHSR (*(__I uint32_t*)0x40040018U) /**< \brief (DACC) Channel Status Register */
\r
56 #define REG_DACC_CDR (*(__O uint32_t*)0x4004001CU) /**< \brief (DACC) Conversion Data Register */
\r
57 #define REG_DACC_IER (*(__O uint32_t*)0x40040024U) /**< \brief (DACC) Interrupt Enable Register */
\r
58 #define REG_DACC_IDR (*(__O uint32_t*)0x40040028U) /**< \brief (DACC) Interrupt Disable Register */
\r
59 #define REG_DACC_IMR (*(__I uint32_t*)0x4004002CU) /**< \brief (DACC) Interrupt Mask Register */
\r
60 #define REG_DACC_ISR (*(__I uint32_t*)0x40040030U) /**< \brief (DACC) Interrupt Status Register */
\r
61 #define REG_DACC_ACR (*(__IO uint32_t*)0x40040094U) /**< \brief (DACC) Analog Current Register */
\r
62 #define REG_DACC_WPMR (*(__IO uint32_t*)0x400400E4U) /**< \brief (DACC) Write Protection Mode register */
\r
63 #define REG_DACC_WPSR (*(__I uint32_t*)0x400400E8U) /**< \brief (DACC) Write Protection Status register */
\r
64 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
\r
66 #endif /* _SAM_DACC_INSTANCE_ */
\r