1 /* ---------------------------------------------------------------------------- */
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2 /* Atmel Microcontroller Software Support */
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3 /* SAM Software Package License */
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4 /* ---------------------------------------------------------------------------- */
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5 /* Copyright (c) 2014, Atmel Corporation */
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7 /* All rights reserved. */
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9 /* Redistribution and use in source and binary forms, with or without */
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10 /* modification, are permitted provided that the following condition is met: */
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12 /* - Redistributions of source code must retain the above copyright notice, */
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13 /* this list of conditions and the disclaimer below. */
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15 /* Atmel's name may not be used to endorse or promote products derived from */
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16 /* this software without specific prior written permission. */
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18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
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20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
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21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
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22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
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23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
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24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
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26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
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27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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28 /* ---------------------------------------------------------------------------- */
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30 #ifndef _SAM_USART1_INSTANCE_
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31 #define _SAM_USART1_INSTANCE_
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33 /* ========== Register definition for USART1 peripheral ========== */
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34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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35 #define REG_USART1_CR (0x40028000U) /**< \brief (USART1) Control Register */
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36 #define REG_USART1_MR (0x40028004U) /**< \brief (USART1) Mode Register */
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37 #define REG_USART1_IER (0x40028008U) /**< \brief (USART1) Interrupt Enable Register */
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38 #define REG_USART1_IDR (0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */
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39 #define REG_USART1_IMR (0x40028010U) /**< \brief (USART1) Interrupt Mask Register */
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40 #define REG_USART1_CSR (0x40028014U) /**< \brief (USART1) Channel Status Register */
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41 #define REG_USART1_RHR (0x40028018U) /**< \brief (USART1) Receive Holding Register */
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42 #define REG_USART1_THR (0x4002801CU) /**< \brief (USART1) Transmit Holding Register */
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43 #define REG_USART1_BRGR (0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */
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44 #define REG_USART1_RTOR (0x40028024U) /**< \brief (USART1) Receiver Time-out Register */
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45 #define REG_USART1_TTGR (0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */
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46 #define REG_USART1_FIDI (0x40028040U) /**< \brief (USART1) FI DI Ratio Register */
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47 #define REG_USART1_NER (0x40028044U) /**< \brief (USART1) Number of Errors Register */
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48 #define REG_USART1_IF (0x4002804CU) /**< \brief (USART1) IrDA Filter Register */
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49 #define REG_USART1_MAN (0x40028050U) /**< \brief (USART1) Manchester Configuration Register */
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50 #define REG_USART1_LINMR (0x40028054U) /**< \brief (USART1) LIN Mode Register */
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51 #define REG_USART1_LINIR (0x40028058U) /**< \brief (USART1) LIN Identifier Register */
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52 #define REG_USART1_LINBRR (0x4002805CU) /**< \brief (USART1) LIN Baud Rate Register */
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53 #define REG_USART1_LONMR (0x40028060U) /**< \brief (USART1) LON Mode Register */
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54 #define REG_USART1_LONPR (0x40028064U) /**< \brief (USART1) LON Preamble Register */
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55 #define REG_USART1_LONDL (0x40028068U) /**< \brief (USART1) LON Data Length Register */
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56 #define REG_USART1_LONL2HDR (0x4002806CU) /**< \brief (USART1) LON L2HDR Register */
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57 #define REG_USART1_LONBL (0x40028070U) /**< \brief (USART1) LON Backlog Register */
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58 #define REG_USART1_LONB1TX (0x40028074U) /**< \brief (USART1) LON Beta1 Tx Register */
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59 #define REG_USART1_LONB1RX (0x40028078U) /**< \brief (USART1) LON Beta1 Rx Register */
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60 #define REG_USART1_LONPRIO (0x4002807CU) /**< \brief (USART1) LON Priority Register */
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61 #define REG_USART1_IDTTX (0x40028080U) /**< \brief (USART1) LON IDT Tx Register */
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62 #define REG_USART1_IDTRX (0x40028084U) /**< \brief (USART1) LON IDT Rx Register */
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63 #define REG_USART1_ICDIFF (0x40028088U) /**< \brief (USART1) IC DIFF Register */
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64 #define REG_USART1_WPMR (0x400280E4U) /**< \brief (USART1) Write Protection Mode Register */
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65 #define REG_USART1_WPSR (0x400280E8U) /**< \brief (USART1) Write Protection Status Register */
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66 #define REG_USART1_VERSION (0x400280FCU) /**< \brief (USART1) Version Register */
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68 #define REG_USART1_CR (*(__O uint32_t*)0x40028000U) /**< \brief (USART1) Control Register */
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69 #define REG_USART1_MR (*(__IO uint32_t*)0x40028004U) /**< \brief (USART1) Mode Register */
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70 #define REG_USART1_IER (*(__O uint32_t*)0x40028008U) /**< \brief (USART1) Interrupt Enable Register */
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71 #define REG_USART1_IDR (*(__O uint32_t*)0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */
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72 #define REG_USART1_IMR (*(__I uint32_t*)0x40028010U) /**< \brief (USART1) Interrupt Mask Register */
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73 #define REG_USART1_CSR (*(__I uint32_t*)0x40028014U) /**< \brief (USART1) Channel Status Register */
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74 #define REG_USART1_RHR (*(__I uint32_t*)0x40028018U) /**< \brief (USART1) Receive Holding Register */
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75 #define REG_USART1_THR (*(__O uint32_t*)0x4002801CU) /**< \brief (USART1) Transmit Holding Register */
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76 #define REG_USART1_BRGR (*(__IO uint32_t*)0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */
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77 #define REG_USART1_RTOR (*(__IO uint32_t*)0x40028024U) /**< \brief (USART1) Receiver Time-out Register */
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78 #define REG_USART1_TTGR (*(__IO uint32_t*)0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */
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79 #define REG_USART1_FIDI (*(__IO uint32_t*)0x40028040U) /**< \brief (USART1) FI DI Ratio Register */
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80 #define REG_USART1_NER (*(__I uint32_t*)0x40028044U) /**< \brief (USART1) Number of Errors Register */
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81 #define REG_USART1_IF (*(__IO uint32_t*)0x4002804CU) /**< \brief (USART1) IrDA Filter Register */
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82 #define REG_USART1_MAN (*(__IO uint32_t*)0x40028050U) /**< \brief (USART1) Manchester Configuration Register */
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83 #define REG_USART1_LINMR (*(__IO uint32_t*)0x40028054U) /**< \brief (USART1) LIN Mode Register */
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84 #define REG_USART1_LINIR (*(__IO uint32_t*)0x40028058U) /**< \brief (USART1) LIN Identifier Register */
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85 #define REG_USART1_LINBRR (*(__I uint32_t*)0x4002805CU) /**< \brief (USART1) LIN Baud Rate Register */
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86 #define REG_USART1_LONMR (*(__IO uint32_t*)0x40028060U) /**< \brief (USART1) LON Mode Register */
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87 #define REG_USART1_LONPR (*(__IO uint32_t*)0x40028064U) /**< \brief (USART1) LON Preamble Register */
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88 #define REG_USART1_LONDL (*(__IO uint32_t*)0x40028068U) /**< \brief (USART1) LON Data Length Register */
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89 #define REG_USART1_LONL2HDR (*(__IO uint32_t*)0x4002806CU) /**< \brief (USART1) LON L2HDR Register */
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90 #define REG_USART1_LONBL (*(__I uint32_t*)0x40028070U) /**< \brief (USART1) LON Backlog Register */
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91 #define REG_USART1_LONB1TX (*(__IO uint32_t*)0x40028074U) /**< \brief (USART1) LON Beta1 Tx Register */
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92 #define REG_USART1_LONB1RX (*(__IO uint32_t*)0x40028078U) /**< \brief (USART1) LON Beta1 Rx Register */
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93 #define REG_USART1_LONPRIO (*(__IO uint32_t*)0x4002807CU) /**< \brief (USART1) LON Priority Register */
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94 #define REG_USART1_IDTTX (*(__IO uint32_t*)0x40028080U) /**< \brief (USART1) LON IDT Tx Register */
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95 #define REG_USART1_IDTRX (*(__IO uint32_t*)0x40028084U) /**< \brief (USART1) LON IDT Rx Register */
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96 #define REG_USART1_ICDIFF (*(__IO uint32_t*)0x40028088U) /**< \brief (USART1) IC DIFF Register */
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97 #define REG_USART1_WPMR (*(__IO uint32_t*)0x400280E4U) /**< \brief (USART1) Write Protection Mode Register */
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98 #define REG_USART1_WPSR (*(__I uint32_t*)0x400280E8U) /**< \brief (USART1) Write Protection Status Register */
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99 #define REG_USART1_VERSION (*(__I uint32_t*)0x400280FCU) /**< \brief (USART1) Version Register */
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100 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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102 #endif /* _SAM_USART1_INSTANCE_ */
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