1 /* ---------------------------------------------------------------------------- */
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2 /* Atmel Microcontroller Software Support */
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3 /* SAM Software Package License */
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4 /* ---------------------------------------------------------------------------- */
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5 /* Copyright (c) 2014, Atmel Corporation */
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7 /* All rights reserved. */
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9 /* Redistribution and use in source and binary forms, with or without */
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10 /* modification, are permitted provided that the following condition is met: */
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12 /* - Redistributions of source code must retain the above copyright notice, */
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13 /* this list of conditions and the disclaimer below. */
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15 /* Atmel's name may not be used to endorse or promote products derived from */
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16 /* this software without specific prior written permission. */
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18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
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20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
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21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
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22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
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23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
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24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
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26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
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27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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28 /* ---------------------------------------------------------------------------- */
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30 #ifndef _SAM_XDMAC_INSTANCE_
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31 #define _SAM_XDMAC_INSTANCE_
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33 /* ========== Register definition for XDMAC peripheral ========== */
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34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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35 #define REG_XDMAC_GTYPE (0x40078000U) /**< \brief (XDMAC) Global Type Register */
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36 #define REG_XDMAC_GCFG (0x40078004U) /**< \brief (XDMAC) Global Configuration Register */
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37 #define REG_XDMAC_GWAC (0x40078008U) /**< \brief (XDMAC) Global Weighted Arbiter Configuration Register */
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38 #define REG_XDMAC_GIE (0x4007800CU) /**< \brief (XDMAC) Global Interrupt Enable Register */
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39 #define REG_XDMAC_GID (0x40078010U) /**< \brief (XDMAC) Global Interrupt Disable Register */
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40 #define REG_XDMAC_GIM (0x40078014U) /**< \brief (XDMAC) Global Interrupt Mask Register */
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41 #define REG_XDMAC_GIS (0x40078018U) /**< \brief (XDMAC) Global Interrupt Status Register */
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42 #define REG_XDMAC_GE (0x4007801CU) /**< \brief (XDMAC) Global Channel Enable Register */
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43 #define REG_XDMAC_GD (0x40078020U) /**< \brief (XDMAC) Global Channel Disable Register */
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44 #define REG_XDMAC_GS (0x40078024U) /**< \brief (XDMAC) Global Channel Status Register */
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45 #define REG_XDMAC_GRS (0x40078028U) /**< \brief (XDMAC) Global Channel Read Suspend Register */
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46 #define REG_XDMAC_GWS (0x4007802CU) /**< \brief (XDMAC) Global Channel Write Suspend Register */
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47 #define REG_XDMAC_GRWS (0x40078030U) /**< \brief (XDMAC) Global Channel Read Write Suspend Register */
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48 #define REG_XDMAC_GRWR (0x40078034U) /**< \brief (XDMAC) Global Channel Read Write Resume Register */
\r
49 #define REG_XDMAC_GSWR (0x40078038U) /**< \brief (XDMAC) Global Channel Software Request Register */
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50 #define REG_XDMAC_GSWS (0x4007803CU) /**< \brief (XDMAC) Global Channel Software Request Status Register */
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51 #define REG_XDMAC_GSWF (0x40078040U) /**< \brief (XDMAC) Global Channel Software Flush Request Register */
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52 #define REG_XDMAC_CIE0 (0x40078050U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 0) */
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53 #define REG_XDMAC_CID0 (0x40078054U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 0) */
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54 #define REG_XDMAC_CIM0 (0x40078058U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 0) */
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55 #define REG_XDMAC_CIS0 (0x4007805CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 0) */
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56 #define REG_XDMAC_CSA0 (0x40078060U) /**< \brief (XDMAC) Channel Source Address Register (chid = 0) */
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57 #define REG_XDMAC_CDA0 (0x40078064U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 0) */
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58 #define REG_XDMAC_CNDA0 (0x40078068U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 0) */
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59 #define REG_XDMAC_CNDC0 (0x4007806CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 0) */
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60 #define REG_XDMAC_CUBC0 (0x40078070U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 0) */
\r
61 #define REG_XDMAC_CBC0 (0x40078074U) /**< \brief (XDMAC) Channel Block Control Register (chid = 0) */
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62 #define REG_XDMAC_CC0 (0x40078078U) /**< \brief (XDMAC) Channel Configuration Register (chid = 0) */
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63 #define REG_XDMAC_CDS_MSP0 (0x4007807CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) */
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64 #define REG_XDMAC_CSUS0 (0x40078080U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 0) */
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65 #define REG_XDMAC_CDUS0 (0x40078084U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 0) */
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66 #define REG_XDMAC_CIE1 (0x40078090U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 1) */
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67 #define REG_XDMAC_CID1 (0x40078094U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 1) */
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68 #define REG_XDMAC_CIM1 (0x40078098U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 1) */
\r
69 #define REG_XDMAC_CIS1 (0x4007809CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 1) */
\r
70 #define REG_XDMAC_CSA1 (0x400780A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 1) */
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71 #define REG_XDMAC_CDA1 (0x400780A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 1) */
\r
72 #define REG_XDMAC_CNDA1 (0x400780A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 1) */
\r
73 #define REG_XDMAC_CNDC1 (0x400780ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 1) */
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74 #define REG_XDMAC_CUBC1 (0x400780B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 1) */
\r
75 #define REG_XDMAC_CBC1 (0x400780B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 1) */
\r
76 #define REG_XDMAC_CC1 (0x400780B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 1) */
\r
77 #define REG_XDMAC_CDS_MSP1 (0x400780BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 1) */
\r
78 #define REG_XDMAC_CSUS1 (0x400780C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 1) */
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79 #define REG_XDMAC_CDUS1 (0x400780C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 1) */
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80 #define REG_XDMAC_CIE2 (0x400780D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 2) */
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81 #define REG_XDMAC_CID2 (0x400780D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 2) */
\r
82 #define REG_XDMAC_CIM2 (0x400780D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 2) */
\r
83 #define REG_XDMAC_CIS2 (0x400780DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 2) */
\r
84 #define REG_XDMAC_CSA2 (0x400780E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 2) */
\r
85 #define REG_XDMAC_CDA2 (0x400780E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 2) */
\r
86 #define REG_XDMAC_CNDA2 (0x400780E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 2) */
\r
87 #define REG_XDMAC_CNDC2 (0x400780ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 2) */
\r
88 #define REG_XDMAC_CUBC2 (0x400780F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 2) */
\r
89 #define REG_XDMAC_CBC2 (0x400780F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 2) */
\r
90 #define REG_XDMAC_CC2 (0x400780F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 2) */
\r
91 #define REG_XDMAC_CDS_MSP2 (0x400780FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 2) */
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92 #define REG_XDMAC_CSUS2 (0x40078100U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 2) */
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93 #define REG_XDMAC_CDUS2 (0x40078104U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 2) */
\r
94 #define REG_XDMAC_CIE3 (0x40078110U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 3) */
\r
95 #define REG_XDMAC_CID3 (0x40078114U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 3) */
\r
96 #define REG_XDMAC_CIM3 (0x40078118U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 3) */
\r
97 #define REG_XDMAC_CIS3 (0x4007811CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 3) */
\r
98 #define REG_XDMAC_CSA3 (0x40078120U) /**< \brief (XDMAC) Channel Source Address Register (chid = 3) */
\r
99 #define REG_XDMAC_CDA3 (0x40078124U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 3) */
\r
100 #define REG_XDMAC_CNDA3 (0x40078128U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 3) */
\r
101 #define REG_XDMAC_CNDC3 (0x4007812CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 3) */
\r
102 #define REG_XDMAC_CUBC3 (0x40078130U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 3) */
\r
103 #define REG_XDMAC_CBC3 (0x40078134U) /**< \brief (XDMAC) Channel Block Control Register (chid = 3) */
\r
104 #define REG_XDMAC_CC3 (0x40078138U) /**< \brief (XDMAC) Channel Configuration Register (chid = 3) */
\r
105 #define REG_XDMAC_CDS_MSP3 (0x4007813CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 3) */
\r
106 #define REG_XDMAC_CSUS3 (0x40078140U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 3) */
\r
107 #define REG_XDMAC_CDUS3 (0x40078144U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 3) */
\r
108 #define REG_XDMAC_CIE4 (0x40078150U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 4) */
\r
109 #define REG_XDMAC_CID4 (0x40078154U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 4) */
\r
110 #define REG_XDMAC_CIM4 (0x40078158U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 4) */
\r
111 #define REG_XDMAC_CIS4 (0x4007815CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 4) */
\r
112 #define REG_XDMAC_CSA4 (0x40078160U) /**< \brief (XDMAC) Channel Source Address Register (chid = 4) */
\r
113 #define REG_XDMAC_CDA4 (0x40078164U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 4) */
\r
114 #define REG_XDMAC_CNDA4 (0x40078168U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 4) */
\r
115 #define REG_XDMAC_CNDC4 (0x4007816CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 4) */
\r
116 #define REG_XDMAC_CUBC4 (0x40078170U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 4) */
\r
117 #define REG_XDMAC_CBC4 (0x40078174U) /**< \brief (XDMAC) Channel Block Control Register (chid = 4) */
\r
118 #define REG_XDMAC_CC4 (0x40078178U) /**< \brief (XDMAC) Channel Configuration Register (chid = 4) */
\r
119 #define REG_XDMAC_CDS_MSP4 (0x4007817CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 4) */
\r
120 #define REG_XDMAC_CSUS4 (0x40078180U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 4) */
\r
121 #define REG_XDMAC_CDUS4 (0x40078184U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 4) */
\r
122 #define REG_XDMAC_CIE5 (0x40078190U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 5) */
\r
123 #define REG_XDMAC_CID5 (0x40078194U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 5) */
\r
124 #define REG_XDMAC_CIM5 (0x40078198U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 5) */
\r
125 #define REG_XDMAC_CIS5 (0x4007819CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 5) */
\r
126 #define REG_XDMAC_CSA5 (0x400781A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 5) */
\r
127 #define REG_XDMAC_CDA5 (0x400781A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 5) */
\r
128 #define REG_XDMAC_CNDA5 (0x400781A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 5) */
\r
129 #define REG_XDMAC_CNDC5 (0x400781ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 5) */
\r
130 #define REG_XDMAC_CUBC5 (0x400781B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 5) */
\r
131 #define REG_XDMAC_CBC5 (0x400781B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 5) */
\r
132 #define REG_XDMAC_CC5 (0x400781B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 5) */
\r
133 #define REG_XDMAC_CDS_MSP5 (0x400781BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 5) */
\r
134 #define REG_XDMAC_CSUS5 (0x400781C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 5) */
\r
135 #define REG_XDMAC_CDUS5 (0x400781C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 5) */
\r
136 #define REG_XDMAC_CIE6 (0x400781D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 6) */
\r
137 #define REG_XDMAC_CID6 (0x400781D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 6) */
\r
138 #define REG_XDMAC_CIM6 (0x400781D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 6) */
\r
139 #define REG_XDMAC_CIS6 (0x400781DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 6) */
\r
140 #define REG_XDMAC_CSA6 (0x400781E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 6) */
\r
141 #define REG_XDMAC_CDA6 (0x400781E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 6) */
\r
142 #define REG_XDMAC_CNDA6 (0x400781E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 6) */
\r
143 #define REG_XDMAC_CNDC6 (0x400781ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 6) */
\r
144 #define REG_XDMAC_CUBC6 (0x400781F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 6) */
\r
145 #define REG_XDMAC_CBC6 (0x400781F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 6) */
\r
146 #define REG_XDMAC_CC6 (0x400781F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 6) */
\r
147 #define REG_XDMAC_CDS_MSP6 (0x400781FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 6) */
\r
148 #define REG_XDMAC_CSUS6 (0x40078200U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 6) */
\r
149 #define REG_XDMAC_CDUS6 (0x40078204U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 6) */
\r
150 #define REG_XDMAC_CIE7 (0x40078210U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 7) */
\r
151 #define REG_XDMAC_CID7 (0x40078214U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 7) */
\r
152 #define REG_XDMAC_CIM7 (0x40078218U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 7) */
\r
153 #define REG_XDMAC_CIS7 (0x4007821CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 7) */
\r
154 #define REG_XDMAC_CSA7 (0x40078220U) /**< \brief (XDMAC) Channel Source Address Register (chid = 7) */
\r
155 #define REG_XDMAC_CDA7 (0x40078224U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 7) */
\r
156 #define REG_XDMAC_CNDA7 (0x40078228U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 7) */
\r
157 #define REG_XDMAC_CNDC7 (0x4007822CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 7) */
\r
158 #define REG_XDMAC_CUBC7 (0x40078230U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 7) */
\r
159 #define REG_XDMAC_CBC7 (0x40078234U) /**< \brief (XDMAC) Channel Block Control Register (chid = 7) */
\r
160 #define REG_XDMAC_CC7 (0x40078238U) /**< \brief (XDMAC) Channel Configuration Register (chid = 7) */
\r
161 #define REG_XDMAC_CDS_MSP7 (0x4007823CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 7) */
\r
162 #define REG_XDMAC_CSUS7 (0x40078240U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 7) */
\r
163 #define REG_XDMAC_CDUS7 (0x40078244U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 7) */
\r
164 #define REG_XDMAC_CIE8 (0x40078250U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 8) */
\r
165 #define REG_XDMAC_CID8 (0x40078254U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 8) */
\r
166 #define REG_XDMAC_CIM8 (0x40078258U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 8) */
\r
167 #define REG_XDMAC_CIS8 (0x4007825CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 8) */
\r
168 #define REG_XDMAC_CSA8 (0x40078260U) /**< \brief (XDMAC) Channel Source Address Register (chid = 8) */
\r
169 #define REG_XDMAC_CDA8 (0x40078264U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 8) */
\r
170 #define REG_XDMAC_CNDA8 (0x40078268U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 8) */
\r
171 #define REG_XDMAC_CNDC8 (0x4007826CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 8) */
\r
172 #define REG_XDMAC_CUBC8 (0x40078270U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 8) */
\r
173 #define REG_XDMAC_CBC8 (0x40078274U) /**< \brief (XDMAC) Channel Block Control Register (chid = 8) */
\r
174 #define REG_XDMAC_CC8 (0x40078278U) /**< \brief (XDMAC) Channel Configuration Register (chid = 8) */
\r
175 #define REG_XDMAC_CDS_MSP8 (0x4007827CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 8) */
\r
176 #define REG_XDMAC_CSUS8 (0x40078280U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 8) */
\r
177 #define REG_XDMAC_CDUS8 (0x40078284U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 8) */
\r
178 #define REG_XDMAC_CIE9 (0x40078290U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 9) */
\r
179 #define REG_XDMAC_CID9 (0x40078294U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 9) */
\r
180 #define REG_XDMAC_CIM9 (0x40078298U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 9) */
\r
181 #define REG_XDMAC_CIS9 (0x4007829CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 9) */
\r
182 #define REG_XDMAC_CSA9 (0x400782A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 9) */
\r
183 #define REG_XDMAC_CDA9 (0x400782A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 9) */
\r
184 #define REG_XDMAC_CNDA9 (0x400782A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 9) */
\r
185 #define REG_XDMAC_CNDC9 (0x400782ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 9) */
\r
186 #define REG_XDMAC_CUBC9 (0x400782B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 9) */
\r
187 #define REG_XDMAC_CBC9 (0x400782B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 9) */
\r
188 #define REG_XDMAC_CC9 (0x400782B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 9) */
\r
189 #define REG_XDMAC_CDS_MSP9 (0x400782BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 9) */
\r
190 #define REG_XDMAC_CSUS9 (0x400782C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 9) */
\r
191 #define REG_XDMAC_CDUS9 (0x400782C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 9) */
\r
192 #define REG_XDMAC_CIE10 (0x400782D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 10) */
\r
193 #define REG_XDMAC_CID10 (0x400782D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 10) */
\r
194 #define REG_XDMAC_CIM10 (0x400782D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 10) */
\r
195 #define REG_XDMAC_CIS10 (0x400782DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 10) */
\r
196 #define REG_XDMAC_CSA10 (0x400782E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 10) */
\r
197 #define REG_XDMAC_CDA10 (0x400782E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 10) */
\r
198 #define REG_XDMAC_CNDA10 (0x400782E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 10) */
\r
199 #define REG_XDMAC_CNDC10 (0x400782ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 10) */
\r
200 #define REG_XDMAC_CUBC10 (0x400782F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 10) */
\r
201 #define REG_XDMAC_CBC10 (0x400782F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 10) */
\r
202 #define REG_XDMAC_CC10 (0x400782F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 10) */
\r
203 #define REG_XDMAC_CDS_MSP10 (0x400782FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 10) */
\r
204 #define REG_XDMAC_CSUS10 (0x40078300U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 10) */
\r
205 #define REG_XDMAC_CDUS10 (0x40078304U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 10) */
\r
206 #define REG_XDMAC_CIE11 (0x40078310U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 11) */
\r
207 #define REG_XDMAC_CID11 (0x40078314U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 11) */
\r
208 #define REG_XDMAC_CIM11 (0x40078318U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 11) */
\r
209 #define REG_XDMAC_CIS11 (0x4007831CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 11) */
\r
210 #define REG_XDMAC_CSA11 (0x40078320U) /**< \brief (XDMAC) Channel Source Address Register (chid = 11) */
\r
211 #define REG_XDMAC_CDA11 (0x40078324U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 11) */
\r
212 #define REG_XDMAC_CNDA11 (0x40078328U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 11) */
\r
213 #define REG_XDMAC_CNDC11 (0x4007832CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 11) */
\r
214 #define REG_XDMAC_CUBC11 (0x40078330U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 11) */
\r
215 #define REG_XDMAC_CBC11 (0x40078334U) /**< \brief (XDMAC) Channel Block Control Register (chid = 11) */
\r
216 #define REG_XDMAC_CC11 (0x40078338U) /**< \brief (XDMAC) Channel Configuration Register (chid = 11) */
\r
217 #define REG_XDMAC_CDS_MSP11 (0x4007833CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 11) */
\r
218 #define REG_XDMAC_CSUS11 (0x40078340U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 11) */
\r
219 #define REG_XDMAC_CDUS11 (0x40078344U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 11) */
\r
220 #define REG_XDMAC_CIE12 (0x40078350U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 12) */
\r
221 #define REG_XDMAC_CID12 (0x40078354U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 12) */
\r
222 #define REG_XDMAC_CIM12 (0x40078358U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 12) */
\r
223 #define REG_XDMAC_CIS12 (0x4007835CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 12) */
\r
224 #define REG_XDMAC_CSA12 (0x40078360U) /**< \brief (XDMAC) Channel Source Address Register (chid = 12) */
\r
225 #define REG_XDMAC_CDA12 (0x40078364U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 12) */
\r
226 #define REG_XDMAC_CNDA12 (0x40078368U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 12) */
\r
227 #define REG_XDMAC_CNDC12 (0x4007836CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 12) */
\r
228 #define REG_XDMAC_CUBC12 (0x40078370U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 12) */
\r
229 #define REG_XDMAC_CBC12 (0x40078374U) /**< \brief (XDMAC) Channel Block Control Register (chid = 12) */
\r
230 #define REG_XDMAC_CC12 (0x40078378U) /**< \brief (XDMAC) Channel Configuration Register (chid = 12) */
\r
231 #define REG_XDMAC_CDS_MSP12 (0x4007837CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 12) */
\r
232 #define REG_XDMAC_CSUS12 (0x40078380U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 12) */
\r
233 #define REG_XDMAC_CDUS12 (0x40078384U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 12) */
\r
234 #define REG_XDMAC_CIE13 (0x40078390U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 13) */
\r
235 #define REG_XDMAC_CID13 (0x40078394U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 13) */
\r
236 #define REG_XDMAC_CIM13 (0x40078398U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 13) */
\r
237 #define REG_XDMAC_CIS13 (0x4007839CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 13) */
\r
238 #define REG_XDMAC_CSA13 (0x400783A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 13) */
\r
239 #define REG_XDMAC_CDA13 (0x400783A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 13) */
\r
240 #define REG_XDMAC_CNDA13 (0x400783A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 13) */
\r
241 #define REG_XDMAC_CNDC13 (0x400783ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 13) */
\r
242 #define REG_XDMAC_CUBC13 (0x400783B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 13) */
\r
243 #define REG_XDMAC_CBC13 (0x400783B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 13) */
\r
244 #define REG_XDMAC_CC13 (0x400783B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 13) */
\r
245 #define REG_XDMAC_CDS_MSP13 (0x400783BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 13) */
\r
246 #define REG_XDMAC_CSUS13 (0x400783C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 13) */
\r
247 #define REG_XDMAC_CDUS13 (0x400783C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 13) */
\r
248 #define REG_XDMAC_CIE14 (0x400783D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 14) */
\r
249 #define REG_XDMAC_CID14 (0x400783D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 14) */
\r
250 #define REG_XDMAC_CIM14 (0x400783D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 14) */
\r
251 #define REG_XDMAC_CIS14 (0x400783DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 14) */
\r
252 #define REG_XDMAC_CSA14 (0x400783E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 14) */
\r
253 #define REG_XDMAC_CDA14 (0x400783E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 14) */
\r
254 #define REG_XDMAC_CNDA14 (0x400783E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 14) */
\r
255 #define REG_XDMAC_CNDC14 (0x400783ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 14) */
\r
256 #define REG_XDMAC_CUBC14 (0x400783F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 14) */
\r
257 #define REG_XDMAC_CBC14 (0x400783F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 14) */
\r
258 #define REG_XDMAC_CC14 (0x400783F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 14) */
\r
259 #define REG_XDMAC_CDS_MSP14 (0x400783FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 14) */
\r
260 #define REG_XDMAC_CSUS14 (0x40078400U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 14) */
\r
261 #define REG_XDMAC_CDUS14 (0x40078404U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 14) */
\r
262 #define REG_XDMAC_CIE15 (0x40078410U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 15) */
\r
263 #define REG_XDMAC_CID15 (0x40078414U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 15) */
\r
264 #define REG_XDMAC_CIM15 (0x40078418U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 15) */
\r
265 #define REG_XDMAC_CIS15 (0x4007841CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 15) */
\r
266 #define REG_XDMAC_CSA15 (0x40078420U) /**< \brief (XDMAC) Channel Source Address Register (chid = 15) */
\r
267 #define REG_XDMAC_CDA15 (0x40078424U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 15) */
\r
268 #define REG_XDMAC_CNDA15 (0x40078428U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 15) */
\r
269 #define REG_XDMAC_CNDC15 (0x4007842CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 15) */
\r
270 #define REG_XDMAC_CUBC15 (0x40078430U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 15) */
\r
271 #define REG_XDMAC_CBC15 (0x40078434U) /**< \brief (XDMAC) Channel Block Control Register (chid = 15) */
\r
272 #define REG_XDMAC_CC15 (0x40078438U) /**< \brief (XDMAC) Channel Configuration Register (chid = 15) */
\r
273 #define REG_XDMAC_CDS_MSP15 (0x4007843CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 15) */
\r
274 #define REG_XDMAC_CSUS15 (0x40078440U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 15) */
\r
275 #define REG_XDMAC_CDUS15 (0x40078444U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 15) */
\r
276 #define REG_XDMAC_CIE16 (0x40078450U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 16) */
\r
277 #define REG_XDMAC_CID16 (0x40078454U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 16) */
\r
278 #define REG_XDMAC_CIM16 (0x40078458U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 16) */
\r
279 #define REG_XDMAC_CIS16 (0x4007845CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 16) */
\r
280 #define REG_XDMAC_CSA16 (0x40078460U) /**< \brief (XDMAC) Channel Source Address Register (chid = 16) */
\r
281 #define REG_XDMAC_CDA16 (0x40078464U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 16) */
\r
282 #define REG_XDMAC_CNDA16 (0x40078468U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 16) */
\r
283 #define REG_XDMAC_CNDC16 (0x4007846CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 16) */
\r
284 #define REG_XDMAC_CUBC16 (0x40078470U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 16) */
\r
285 #define REG_XDMAC_CBC16 (0x40078474U) /**< \brief (XDMAC) Channel Block Control Register (chid = 16) */
\r
286 #define REG_XDMAC_CC16 (0x40078478U) /**< \brief (XDMAC) Channel Configuration Register (chid = 16) */
\r
287 #define REG_XDMAC_CDS_MSP16 (0x4007847CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 16) */
\r
288 #define REG_XDMAC_CSUS16 (0x40078480U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 16) */
\r
289 #define REG_XDMAC_CDUS16 (0x40078484U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 16) */
\r
290 #define REG_XDMAC_CIE17 (0x40078490U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 17) */
\r
291 #define REG_XDMAC_CID17 (0x40078494U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 17) */
\r
292 #define REG_XDMAC_CIM17 (0x40078498U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 17) */
\r
293 #define REG_XDMAC_CIS17 (0x4007849CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 17) */
\r
294 #define REG_XDMAC_CSA17 (0x400784A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 17) */
\r
295 #define REG_XDMAC_CDA17 (0x400784A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 17) */
\r
296 #define REG_XDMAC_CNDA17 (0x400784A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 17) */
\r
297 #define REG_XDMAC_CNDC17 (0x400784ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 17) */
\r
298 #define REG_XDMAC_CUBC17 (0x400784B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 17) */
\r
299 #define REG_XDMAC_CBC17 (0x400784B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 17) */
\r
300 #define REG_XDMAC_CC17 (0x400784B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 17) */
\r
301 #define REG_XDMAC_CDS_MSP17 (0x400784BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 17) */
\r
302 #define REG_XDMAC_CSUS17 (0x400784C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 17) */
\r
303 #define REG_XDMAC_CDUS17 (0x400784C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 17) */
\r
304 #define REG_XDMAC_CIE18 (0x400784D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 18) */
\r
305 #define REG_XDMAC_CID18 (0x400784D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 18) */
\r
306 #define REG_XDMAC_CIM18 (0x400784D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 18) */
\r
307 #define REG_XDMAC_CIS18 (0x400784DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 18) */
\r
308 #define REG_XDMAC_CSA18 (0x400784E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 18) */
\r
309 #define REG_XDMAC_CDA18 (0x400784E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 18) */
\r
310 #define REG_XDMAC_CNDA18 (0x400784E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 18) */
\r
311 #define REG_XDMAC_CNDC18 (0x400784ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 18) */
\r
312 #define REG_XDMAC_CUBC18 (0x400784F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 18) */
\r
313 #define REG_XDMAC_CBC18 (0x400784F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 18) */
\r
314 #define REG_XDMAC_CC18 (0x400784F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 18) */
\r
315 #define REG_XDMAC_CDS_MSP18 (0x400784FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 18) */
\r
316 #define REG_XDMAC_CSUS18 (0x40078500U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 18) */
\r
317 #define REG_XDMAC_CDUS18 (0x40078504U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 18) */
\r
318 #define REG_XDMAC_CIE19 (0x40078510U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 19) */
\r
319 #define REG_XDMAC_CID19 (0x40078514U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 19) */
\r
320 #define REG_XDMAC_CIM19 (0x40078518U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 19) */
\r
321 #define REG_XDMAC_CIS19 (0x4007851CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 19) */
\r
322 #define REG_XDMAC_CSA19 (0x40078520U) /**< \brief (XDMAC) Channel Source Address Register (chid = 19) */
\r
323 #define REG_XDMAC_CDA19 (0x40078524U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 19) */
\r
324 #define REG_XDMAC_CNDA19 (0x40078528U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 19) */
\r
325 #define REG_XDMAC_CNDC19 (0x4007852CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 19) */
\r
326 #define REG_XDMAC_CUBC19 (0x40078530U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 19) */
\r
327 #define REG_XDMAC_CBC19 (0x40078534U) /**< \brief (XDMAC) Channel Block Control Register (chid = 19) */
\r
328 #define REG_XDMAC_CC19 (0x40078538U) /**< \brief (XDMAC) Channel Configuration Register (chid = 19) */
\r
329 #define REG_XDMAC_CDS_MSP19 (0x4007853CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 19) */
\r
330 #define REG_XDMAC_CSUS19 (0x40078540U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 19) */
\r
331 #define REG_XDMAC_CDUS19 (0x40078544U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 19) */
\r
332 #define REG_XDMAC_CIE20 (0x40078550U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 20) */
\r
333 #define REG_XDMAC_CID20 (0x40078554U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 20) */
\r
334 #define REG_XDMAC_CIM20 (0x40078558U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 20) */
\r
335 #define REG_XDMAC_CIS20 (0x4007855CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 20) */
\r
336 #define REG_XDMAC_CSA20 (0x40078560U) /**< \brief (XDMAC) Channel Source Address Register (chid = 20) */
\r
337 #define REG_XDMAC_CDA20 (0x40078564U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 20) */
\r
338 #define REG_XDMAC_CNDA20 (0x40078568U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 20) */
\r
339 #define REG_XDMAC_CNDC20 (0x4007856CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 20) */
\r
340 #define REG_XDMAC_CUBC20 (0x40078570U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 20) */
\r
341 #define REG_XDMAC_CBC20 (0x40078574U) /**< \brief (XDMAC) Channel Block Control Register (chid = 20) */
\r
342 #define REG_XDMAC_CC20 (0x40078578U) /**< \brief (XDMAC) Channel Configuration Register (chid = 20) */
\r
343 #define REG_XDMAC_CDS_MSP20 (0x4007857CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 20) */
\r
344 #define REG_XDMAC_CSUS20 (0x40078580U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 20) */
\r
345 #define REG_XDMAC_CDUS20 (0x40078584U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 20) */
\r
346 #define REG_XDMAC_CIE21 (0x40078590U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 21) */
\r
347 #define REG_XDMAC_CID21 (0x40078594U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 21) */
\r
348 #define REG_XDMAC_CIM21 (0x40078598U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 21) */
\r
349 #define REG_XDMAC_CIS21 (0x4007859CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 21) */
\r
350 #define REG_XDMAC_CSA21 (0x400785A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 21) */
\r
351 #define REG_XDMAC_CDA21 (0x400785A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 21) */
\r
352 #define REG_XDMAC_CNDA21 (0x400785A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 21) */
\r
353 #define REG_XDMAC_CNDC21 (0x400785ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 21) */
\r
354 #define REG_XDMAC_CUBC21 (0x400785B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 21) */
\r
355 #define REG_XDMAC_CBC21 (0x400785B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 21) */
\r
356 #define REG_XDMAC_CC21 (0x400785B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 21) */
\r
357 #define REG_XDMAC_CDS_MSP21 (0x400785BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 21) */
\r
358 #define REG_XDMAC_CSUS21 (0x400785C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 21) */
\r
359 #define REG_XDMAC_CDUS21 (0x400785C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 21) */
\r
360 #define REG_XDMAC_CIE22 (0x400785D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 22) */
\r
361 #define REG_XDMAC_CID22 (0x400785D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 22) */
\r
362 #define REG_XDMAC_CIM22 (0x400785D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 22) */
\r
363 #define REG_XDMAC_CIS22 (0x400785DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 22) */
\r
364 #define REG_XDMAC_CSA22 (0x400785E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 22) */
\r
365 #define REG_XDMAC_CDA22 (0x400785E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 22) */
\r
366 #define REG_XDMAC_CNDA22 (0x400785E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 22) */
\r
367 #define REG_XDMAC_CNDC22 (0x400785ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 22) */
\r
368 #define REG_XDMAC_CUBC22 (0x400785F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 22) */
\r
369 #define REG_XDMAC_CBC22 (0x400785F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 22) */
\r
370 #define REG_XDMAC_CC22 (0x400785F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 22) */
\r
371 #define REG_XDMAC_CDS_MSP22 (0x400785FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 22) */
\r
372 #define REG_XDMAC_CSUS22 (0x40078600U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 22) */
\r
373 #define REG_XDMAC_CDUS22 (0x40078604U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 22) */
\r
374 #define REG_XDMAC_CIE23 (0x40078610U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 23) */
\r
375 #define REG_XDMAC_CID23 (0x40078614U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 23) */
\r
376 #define REG_XDMAC_CIM23 (0x40078618U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 23) */
\r
377 #define REG_XDMAC_CIS23 (0x4007861CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 23) */
\r
378 #define REG_XDMAC_CSA23 (0x40078620U) /**< \brief (XDMAC) Channel Source Address Register (chid = 23) */
\r
379 #define REG_XDMAC_CDA23 (0x40078624U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 23) */
\r
380 #define REG_XDMAC_CNDA23 (0x40078628U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 23) */
\r
381 #define REG_XDMAC_CNDC23 (0x4007862CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 23) */
\r
382 #define REG_XDMAC_CUBC23 (0x40078630U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 23) */
\r
383 #define REG_XDMAC_CBC23 (0x40078634U) /**< \brief (XDMAC) Channel Block Control Register (chid = 23) */
\r
384 #define REG_XDMAC_CC23 (0x40078638U) /**< \brief (XDMAC) Channel Configuration Register (chid = 23) */
\r
385 #define REG_XDMAC_CDS_MSP23 (0x4007863CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 23) */
\r
386 #define REG_XDMAC_CSUS23 (0x40078640U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 23) */
\r
387 #define REG_XDMAC_CDUS23 (0x40078644U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 23) */
\r
388 #define REG_XDMAC_VERSION (0x40078FFCU) /**< \brief (XDMAC) XDMAC Version Register */
\r
390 #define REG_XDMAC_GTYPE (*(__IO uint32_t*)0x40078000U) /**< \brief (XDMAC) Global Type Register */
\r
391 #define REG_XDMAC_GCFG (*(__I uint32_t*)0x40078004U) /**< \brief (XDMAC) Global Configuration Register */
\r
392 #define REG_XDMAC_GWAC (*(__IO uint32_t*)0x40078008U) /**< \brief (XDMAC) Global Weighted Arbiter Configuration Register */
\r
393 #define REG_XDMAC_GIE (*(__O uint32_t*)0x4007800CU) /**< \brief (XDMAC) Global Interrupt Enable Register */
\r
394 #define REG_XDMAC_GID (*(__O uint32_t*)0x40078010U) /**< \brief (XDMAC) Global Interrupt Disable Register */
\r
395 #define REG_XDMAC_GIM (*(__I uint32_t*)0x40078014U) /**< \brief (XDMAC) Global Interrupt Mask Register */
\r
396 #define REG_XDMAC_GIS (*(__I uint32_t*)0x40078018U) /**< \brief (XDMAC) Global Interrupt Status Register */
\r
397 #define REG_XDMAC_GE (*(__O uint32_t*)0x4007801CU) /**< \brief (XDMAC) Global Channel Enable Register */
\r
398 #define REG_XDMAC_GD (*(__O uint32_t*)0x40078020U) /**< \brief (XDMAC) Global Channel Disable Register */
\r
399 #define REG_XDMAC_GS (*(__I uint32_t*)0x40078024U) /**< \brief (XDMAC) Global Channel Status Register */
\r
400 #define REG_XDMAC_GRS (*(__IO uint32_t*)0x40078028U) /**< \brief (XDMAC) Global Channel Read Suspend Register */
\r
401 #define REG_XDMAC_GWS (*(__IO uint32_t*)0x4007802CU) /**< \brief (XDMAC) Global Channel Write Suspend Register */
\r
402 #define REG_XDMAC_GRWS (*(__O uint32_t*)0x40078030U) /**< \brief (XDMAC) Global Channel Read Write Suspend Register */
\r
403 #define REG_XDMAC_GRWR (*(__O uint32_t*)0x40078034U) /**< \brief (XDMAC) Global Channel Read Write Resume Register */
\r
404 #define REG_XDMAC_GSWR (*(__O uint32_t*)0x40078038U) /**< \brief (XDMAC) Global Channel Software Request Register */
\r
405 #define REG_XDMAC_GSWS (*(__I uint32_t*)0x4007803CU) /**< \brief (XDMAC) Global Channel Software Request Status Register */
\r
406 #define REG_XDMAC_GSWF (*(__O uint32_t*)0x40078040U) /**< \brief (XDMAC) Global Channel Software Flush Request Register */
\r
407 #define REG_XDMAC_CIE0 (*(__O uint32_t*)0x40078050U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 0) */
\r
408 #define REG_XDMAC_CID0 (*(__O uint32_t*)0x40078054U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 0) */
\r
409 #define REG_XDMAC_CIM0 (*(__O uint32_t*)0x40078058U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 0) */
\r
410 #define REG_XDMAC_CIS0 (*(__I uint32_t*)0x4007805CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 0) */
\r
411 #define REG_XDMAC_CSA0 (*(__IO uint32_t*)0x40078060U) /**< \brief (XDMAC) Channel Source Address Register (chid = 0) */
\r
412 #define REG_XDMAC_CDA0 (*(__IO uint32_t*)0x40078064U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 0) */
\r
413 #define REG_XDMAC_CNDA0 (*(__IO uint32_t*)0x40078068U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 0) */
\r
414 #define REG_XDMAC_CNDC0 (*(__IO uint32_t*)0x4007806CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 0) */
\r
415 #define REG_XDMAC_CUBC0 (*(__IO uint32_t*)0x40078070U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 0) */
\r
416 #define REG_XDMAC_CBC0 (*(__IO uint32_t*)0x40078074U) /**< \brief (XDMAC) Channel Block Control Register (chid = 0) */
\r
417 #define REG_XDMAC_CC0 (*(__IO uint32_t*)0x40078078U) /**< \brief (XDMAC) Channel Configuration Register (chid = 0) */
\r
418 #define REG_XDMAC_CDS_MSP0 (*(__IO uint32_t*)0x4007807CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) */
\r
419 #define REG_XDMAC_CSUS0 (*(__IO uint32_t*)0x40078080U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 0) */
\r
420 #define REG_XDMAC_CDUS0 (*(__IO uint32_t*)0x40078084U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 0) */
\r
421 #define REG_XDMAC_CIE1 (*(__O uint32_t*)0x40078090U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 1) */
\r
422 #define REG_XDMAC_CID1 (*(__O uint32_t*)0x40078094U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 1) */
\r
423 #define REG_XDMAC_CIM1 (*(__O uint32_t*)0x40078098U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 1) */
\r
424 #define REG_XDMAC_CIS1 (*(__I uint32_t*)0x4007809CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 1) */
\r
425 #define REG_XDMAC_CSA1 (*(__IO uint32_t*)0x400780A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 1) */
\r
426 #define REG_XDMAC_CDA1 (*(__IO uint32_t*)0x400780A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 1) */
\r
427 #define REG_XDMAC_CNDA1 (*(__IO uint32_t*)0x400780A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 1) */
\r
428 #define REG_XDMAC_CNDC1 (*(__IO uint32_t*)0x400780ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 1) */
\r
429 #define REG_XDMAC_CUBC1 (*(__IO uint32_t*)0x400780B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 1) */
\r
430 #define REG_XDMAC_CBC1 (*(__IO uint32_t*)0x400780B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 1) */
\r
431 #define REG_XDMAC_CC1 (*(__IO uint32_t*)0x400780B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 1) */
\r
432 #define REG_XDMAC_CDS_MSP1 (*(__IO uint32_t*)0x400780BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 1) */
\r
433 #define REG_XDMAC_CSUS1 (*(__IO uint32_t*)0x400780C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 1) */
\r
434 #define REG_XDMAC_CDUS1 (*(__IO uint32_t*)0x400780C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 1) */
\r
435 #define REG_XDMAC_CIE2 (*(__O uint32_t*)0x400780D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 2) */
\r
436 #define REG_XDMAC_CID2 (*(__O uint32_t*)0x400780D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 2) */
\r
437 #define REG_XDMAC_CIM2 (*(__O uint32_t*)0x400780D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 2) */
\r
438 #define REG_XDMAC_CIS2 (*(__I uint32_t*)0x400780DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 2) */
\r
439 #define REG_XDMAC_CSA2 (*(__IO uint32_t*)0x400780E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 2) */
\r
440 #define REG_XDMAC_CDA2 (*(__IO uint32_t*)0x400780E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 2) */
\r
441 #define REG_XDMAC_CNDA2 (*(__IO uint32_t*)0x400780E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 2) */
\r
442 #define REG_XDMAC_CNDC2 (*(__IO uint32_t*)0x400780ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 2) */
\r
443 #define REG_XDMAC_CUBC2 (*(__IO uint32_t*)0x400780F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 2) */
\r
444 #define REG_XDMAC_CBC2 (*(__IO uint32_t*)0x400780F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 2) */
\r
445 #define REG_XDMAC_CC2 (*(__IO uint32_t*)0x400780F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 2) */
\r
446 #define REG_XDMAC_CDS_MSP2 (*(__IO uint32_t*)0x400780FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 2) */
\r
447 #define REG_XDMAC_CSUS2 (*(__IO uint32_t*)0x40078100U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 2) */
\r
448 #define REG_XDMAC_CDUS2 (*(__IO uint32_t*)0x40078104U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 2) */
\r
449 #define REG_XDMAC_CIE3 (*(__O uint32_t*)0x40078110U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 3) */
\r
450 #define REG_XDMAC_CID3 (*(__O uint32_t*)0x40078114U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 3) */
\r
451 #define REG_XDMAC_CIM3 (*(__O uint32_t*)0x40078118U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 3) */
\r
452 #define REG_XDMAC_CIS3 (*(__I uint32_t*)0x4007811CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 3) */
\r
453 #define REG_XDMAC_CSA3 (*(__IO uint32_t*)0x40078120U) /**< \brief (XDMAC) Channel Source Address Register (chid = 3) */
\r
454 #define REG_XDMAC_CDA3 (*(__IO uint32_t*)0x40078124U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 3) */
\r
455 #define REG_XDMAC_CNDA3 (*(__IO uint32_t*)0x40078128U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 3) */
\r
456 #define REG_XDMAC_CNDC3 (*(__IO uint32_t*)0x4007812CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 3) */
\r
457 #define REG_XDMAC_CUBC3 (*(__IO uint32_t*)0x40078130U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 3) */
\r
458 #define REG_XDMAC_CBC3 (*(__IO uint32_t*)0x40078134U) /**< \brief (XDMAC) Channel Block Control Register (chid = 3) */
\r
459 #define REG_XDMAC_CC3 (*(__IO uint32_t*)0x40078138U) /**< \brief (XDMAC) Channel Configuration Register (chid = 3) */
\r
460 #define REG_XDMAC_CDS_MSP3 (*(__IO uint32_t*)0x4007813CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 3) */
\r
461 #define REG_XDMAC_CSUS3 (*(__IO uint32_t*)0x40078140U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 3) */
\r
462 #define REG_XDMAC_CDUS3 (*(__IO uint32_t*)0x40078144U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 3) */
\r
463 #define REG_XDMAC_CIE4 (*(__O uint32_t*)0x40078150U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 4) */
\r
464 #define REG_XDMAC_CID4 (*(__O uint32_t*)0x40078154U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 4) */
\r
465 #define REG_XDMAC_CIM4 (*(__O uint32_t*)0x40078158U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 4) */
\r
466 #define REG_XDMAC_CIS4 (*(__I uint32_t*)0x4007815CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 4) */
\r
467 #define REG_XDMAC_CSA4 (*(__IO uint32_t*)0x40078160U) /**< \brief (XDMAC) Channel Source Address Register (chid = 4) */
\r
468 #define REG_XDMAC_CDA4 (*(__IO uint32_t*)0x40078164U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 4) */
\r
469 #define REG_XDMAC_CNDA4 (*(__IO uint32_t*)0x40078168U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 4) */
\r
470 #define REG_XDMAC_CNDC4 (*(__IO uint32_t*)0x4007816CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 4) */
\r
471 #define REG_XDMAC_CUBC4 (*(__IO uint32_t*)0x40078170U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 4) */
\r
472 #define REG_XDMAC_CBC4 (*(__IO uint32_t*)0x40078174U) /**< \brief (XDMAC) Channel Block Control Register (chid = 4) */
\r
473 #define REG_XDMAC_CC4 (*(__IO uint32_t*)0x40078178U) /**< \brief (XDMAC) Channel Configuration Register (chid = 4) */
\r
474 #define REG_XDMAC_CDS_MSP4 (*(__IO uint32_t*)0x4007817CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 4) */
\r
475 #define REG_XDMAC_CSUS4 (*(__IO uint32_t*)0x40078180U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 4) */
\r
476 #define REG_XDMAC_CDUS4 (*(__IO uint32_t*)0x40078184U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 4) */
\r
477 #define REG_XDMAC_CIE5 (*(__O uint32_t*)0x40078190U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 5) */
\r
478 #define REG_XDMAC_CID5 (*(__O uint32_t*)0x40078194U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 5) */
\r
479 #define REG_XDMAC_CIM5 (*(__O uint32_t*)0x40078198U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 5) */
\r
480 #define REG_XDMAC_CIS5 (*(__I uint32_t*)0x4007819CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 5) */
\r
481 #define REG_XDMAC_CSA5 (*(__IO uint32_t*)0x400781A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 5) */
\r
482 #define REG_XDMAC_CDA5 (*(__IO uint32_t*)0x400781A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 5) */
\r
483 #define REG_XDMAC_CNDA5 (*(__IO uint32_t*)0x400781A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 5) */
\r
484 #define REG_XDMAC_CNDC5 (*(__IO uint32_t*)0x400781ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 5) */
\r
485 #define REG_XDMAC_CUBC5 (*(__IO uint32_t*)0x400781B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 5) */
\r
486 #define REG_XDMAC_CBC5 (*(__IO uint32_t*)0x400781B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 5) */
\r
487 #define REG_XDMAC_CC5 (*(__IO uint32_t*)0x400781B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 5) */
\r
488 #define REG_XDMAC_CDS_MSP5 (*(__IO uint32_t*)0x400781BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 5) */
\r
489 #define REG_XDMAC_CSUS5 (*(__IO uint32_t*)0x400781C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 5) */
\r
490 #define REG_XDMAC_CDUS5 (*(__IO uint32_t*)0x400781C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 5) */
\r
491 #define REG_XDMAC_CIE6 (*(__O uint32_t*)0x400781D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 6) */
\r
492 #define REG_XDMAC_CID6 (*(__O uint32_t*)0x400781D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 6) */
\r
493 #define REG_XDMAC_CIM6 (*(__O uint32_t*)0x400781D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 6) */
\r
494 #define REG_XDMAC_CIS6 (*(__I uint32_t*)0x400781DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 6) */
\r
495 #define REG_XDMAC_CSA6 (*(__IO uint32_t*)0x400781E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 6) */
\r
496 #define REG_XDMAC_CDA6 (*(__IO uint32_t*)0x400781E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 6) */
\r
497 #define REG_XDMAC_CNDA6 (*(__IO uint32_t*)0x400781E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 6) */
\r
498 #define REG_XDMAC_CNDC6 (*(__IO uint32_t*)0x400781ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 6) */
\r
499 #define REG_XDMAC_CUBC6 (*(__IO uint32_t*)0x400781F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 6) */
\r
500 #define REG_XDMAC_CBC6 (*(__IO uint32_t*)0x400781F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 6) */
\r
501 #define REG_XDMAC_CC6 (*(__IO uint32_t*)0x400781F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 6) */
\r
502 #define REG_XDMAC_CDS_MSP6 (*(__IO uint32_t*)0x400781FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 6) */
\r
503 #define REG_XDMAC_CSUS6 (*(__IO uint32_t*)0x40078200U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 6) */
\r
504 #define REG_XDMAC_CDUS6 (*(__IO uint32_t*)0x40078204U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 6) */
\r
505 #define REG_XDMAC_CIE7 (*(__O uint32_t*)0x40078210U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 7) */
\r
506 #define REG_XDMAC_CID7 (*(__O uint32_t*)0x40078214U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 7) */
\r
507 #define REG_XDMAC_CIM7 (*(__O uint32_t*)0x40078218U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 7) */
\r
508 #define REG_XDMAC_CIS7 (*(__I uint32_t*)0x4007821CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 7) */
\r
509 #define REG_XDMAC_CSA7 (*(__IO uint32_t*)0x40078220U) /**< \brief (XDMAC) Channel Source Address Register (chid = 7) */
\r
510 #define REG_XDMAC_CDA7 (*(__IO uint32_t*)0x40078224U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 7) */
\r
511 #define REG_XDMAC_CNDA7 (*(__IO uint32_t*)0x40078228U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 7) */
\r
512 #define REG_XDMAC_CNDC7 (*(__IO uint32_t*)0x4007822CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 7) */
\r
513 #define REG_XDMAC_CUBC7 (*(__IO uint32_t*)0x40078230U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 7) */
\r
514 #define REG_XDMAC_CBC7 (*(__IO uint32_t*)0x40078234U) /**< \brief (XDMAC) Channel Block Control Register (chid = 7) */
\r
515 #define REG_XDMAC_CC7 (*(__IO uint32_t*)0x40078238U) /**< \brief (XDMAC) Channel Configuration Register (chid = 7) */
\r
516 #define REG_XDMAC_CDS_MSP7 (*(__IO uint32_t*)0x4007823CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 7) */
\r
517 #define REG_XDMAC_CSUS7 (*(__IO uint32_t*)0x40078240U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 7) */
\r
518 #define REG_XDMAC_CDUS7 (*(__IO uint32_t*)0x40078244U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 7) */
\r
519 #define REG_XDMAC_CIE8 (*(__O uint32_t*)0x40078250U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 8) */
\r
520 #define REG_XDMAC_CID8 (*(__O uint32_t*)0x40078254U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 8) */
\r
521 #define REG_XDMAC_CIM8 (*(__O uint32_t*)0x40078258U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 8) */
\r
522 #define REG_XDMAC_CIS8 (*(__I uint32_t*)0x4007825CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 8) */
\r
523 #define REG_XDMAC_CSA8 (*(__IO uint32_t*)0x40078260U) /**< \brief (XDMAC) Channel Source Address Register (chid = 8) */
\r
524 #define REG_XDMAC_CDA8 (*(__IO uint32_t*)0x40078264U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 8) */
\r
525 #define REG_XDMAC_CNDA8 (*(__IO uint32_t*)0x40078268U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 8) */
\r
526 #define REG_XDMAC_CNDC8 (*(__IO uint32_t*)0x4007826CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 8) */
\r
527 #define REG_XDMAC_CUBC8 (*(__IO uint32_t*)0x40078270U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 8) */
\r
528 #define REG_XDMAC_CBC8 (*(__IO uint32_t*)0x40078274U) /**< \brief (XDMAC) Channel Block Control Register (chid = 8) */
\r
529 #define REG_XDMAC_CC8 (*(__IO uint32_t*)0x40078278U) /**< \brief (XDMAC) Channel Configuration Register (chid = 8) */
\r
530 #define REG_XDMAC_CDS_MSP8 (*(__IO uint32_t*)0x4007827CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 8) */
\r
531 #define REG_XDMAC_CSUS8 (*(__IO uint32_t*)0x40078280U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 8) */
\r
532 #define REG_XDMAC_CDUS8 (*(__IO uint32_t*)0x40078284U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 8) */
\r
533 #define REG_XDMAC_CIE9 (*(__O uint32_t*)0x40078290U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 9) */
\r
534 #define REG_XDMAC_CID9 (*(__O uint32_t*)0x40078294U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 9) */
\r
535 #define REG_XDMAC_CIM9 (*(__O uint32_t*)0x40078298U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 9) */
\r
536 #define REG_XDMAC_CIS9 (*(__I uint32_t*)0x4007829CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 9) */
\r
537 #define REG_XDMAC_CSA9 (*(__IO uint32_t*)0x400782A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 9) */
\r
538 #define REG_XDMAC_CDA9 (*(__IO uint32_t*)0x400782A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 9) */
\r
539 #define REG_XDMAC_CNDA9 (*(__IO uint32_t*)0x400782A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 9) */
\r
540 #define REG_XDMAC_CNDC9 (*(__IO uint32_t*)0x400782ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 9) */
\r
541 #define REG_XDMAC_CUBC9 (*(__IO uint32_t*)0x400782B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 9) */
\r
542 #define REG_XDMAC_CBC9 (*(__IO uint32_t*)0x400782B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 9) */
\r
543 #define REG_XDMAC_CC9 (*(__IO uint32_t*)0x400782B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 9) */
\r
544 #define REG_XDMAC_CDS_MSP9 (*(__IO uint32_t*)0x400782BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 9) */
\r
545 #define REG_XDMAC_CSUS9 (*(__IO uint32_t*)0x400782C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 9) */
\r
546 #define REG_XDMAC_CDUS9 (*(__IO uint32_t*)0x400782C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 9) */
\r
547 #define REG_XDMAC_CIE10 (*(__O uint32_t*)0x400782D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 10) */
\r
548 #define REG_XDMAC_CID10 (*(__O uint32_t*)0x400782D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 10) */
\r
549 #define REG_XDMAC_CIM10 (*(__O uint32_t*)0x400782D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 10) */
\r
550 #define REG_XDMAC_CIS10 (*(__I uint32_t*)0x400782DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 10) */
\r
551 #define REG_XDMAC_CSA10 (*(__IO uint32_t*)0x400782E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 10) */
\r
552 #define REG_XDMAC_CDA10 (*(__IO uint32_t*)0x400782E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 10) */
\r
553 #define REG_XDMAC_CNDA10 (*(__IO uint32_t*)0x400782E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 10) */
\r
554 #define REG_XDMAC_CNDC10 (*(__IO uint32_t*)0x400782ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 10) */
\r
555 #define REG_XDMAC_CUBC10 (*(__IO uint32_t*)0x400782F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 10) */
\r
556 #define REG_XDMAC_CBC10 (*(__IO uint32_t*)0x400782F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 10) */
\r
557 #define REG_XDMAC_CC10 (*(__IO uint32_t*)0x400782F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 10) */
\r
558 #define REG_XDMAC_CDS_MSP10 (*(__IO uint32_t*)0x400782FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 10) */
\r
559 #define REG_XDMAC_CSUS10 (*(__IO uint32_t*)0x40078300U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 10) */
\r
560 #define REG_XDMAC_CDUS10 (*(__IO uint32_t*)0x40078304U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 10) */
\r
561 #define REG_XDMAC_CIE11 (*(__O uint32_t*)0x40078310U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 11) */
\r
562 #define REG_XDMAC_CID11 (*(__O uint32_t*)0x40078314U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 11) */
\r
563 #define REG_XDMAC_CIM11 (*(__O uint32_t*)0x40078318U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 11) */
\r
564 #define REG_XDMAC_CIS11 (*(__I uint32_t*)0x4007831CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 11) */
\r
565 #define REG_XDMAC_CSA11 (*(__IO uint32_t*)0x40078320U) /**< \brief (XDMAC) Channel Source Address Register (chid = 11) */
\r
566 #define REG_XDMAC_CDA11 (*(__IO uint32_t*)0x40078324U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 11) */
\r
567 #define REG_XDMAC_CNDA11 (*(__IO uint32_t*)0x40078328U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 11) */
\r
568 #define REG_XDMAC_CNDC11 (*(__IO uint32_t*)0x4007832CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 11) */
\r
569 #define REG_XDMAC_CUBC11 (*(__IO uint32_t*)0x40078330U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 11) */
\r
570 #define REG_XDMAC_CBC11 (*(__IO uint32_t*)0x40078334U) /**< \brief (XDMAC) Channel Block Control Register (chid = 11) */
\r
571 #define REG_XDMAC_CC11 (*(__IO uint32_t*)0x40078338U) /**< \brief (XDMAC) Channel Configuration Register (chid = 11) */
\r
572 #define REG_XDMAC_CDS_MSP11 (*(__IO uint32_t*)0x4007833CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 11) */
\r
573 #define REG_XDMAC_CSUS11 (*(__IO uint32_t*)0x40078340U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 11) */
\r
574 #define REG_XDMAC_CDUS11 (*(__IO uint32_t*)0x40078344U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 11) */
\r
575 #define REG_XDMAC_CIE12 (*(__O uint32_t*)0x40078350U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 12) */
\r
576 #define REG_XDMAC_CID12 (*(__O uint32_t*)0x40078354U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 12) */
\r
577 #define REG_XDMAC_CIM12 (*(__O uint32_t*)0x40078358U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 12) */
\r
578 #define REG_XDMAC_CIS12 (*(__I uint32_t*)0x4007835CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 12) */
\r
579 #define REG_XDMAC_CSA12 (*(__IO uint32_t*)0x40078360U) /**< \brief (XDMAC) Channel Source Address Register (chid = 12) */
\r
580 #define REG_XDMAC_CDA12 (*(__IO uint32_t*)0x40078364U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 12) */
\r
581 #define REG_XDMAC_CNDA12 (*(__IO uint32_t*)0x40078368U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 12) */
\r
582 #define REG_XDMAC_CNDC12 (*(__IO uint32_t*)0x4007836CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 12) */
\r
583 #define REG_XDMAC_CUBC12 (*(__IO uint32_t*)0x40078370U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 12) */
\r
584 #define REG_XDMAC_CBC12 (*(__IO uint32_t*)0x40078374U) /**< \brief (XDMAC) Channel Block Control Register (chid = 12) */
\r
585 #define REG_XDMAC_CC12 (*(__IO uint32_t*)0x40078378U) /**< \brief (XDMAC) Channel Configuration Register (chid = 12) */
\r
586 #define REG_XDMAC_CDS_MSP12 (*(__IO uint32_t*)0x4007837CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 12) */
\r
587 #define REG_XDMAC_CSUS12 (*(__IO uint32_t*)0x40078380U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 12) */
\r
588 #define REG_XDMAC_CDUS12 (*(__IO uint32_t*)0x40078384U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 12) */
\r
589 #define REG_XDMAC_CIE13 (*(__O uint32_t*)0x40078390U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 13) */
\r
590 #define REG_XDMAC_CID13 (*(__O uint32_t*)0x40078394U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 13) */
\r
591 #define REG_XDMAC_CIM13 (*(__O uint32_t*)0x40078398U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 13) */
\r
592 #define REG_XDMAC_CIS13 (*(__I uint32_t*)0x4007839CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 13) */
\r
593 #define REG_XDMAC_CSA13 (*(__IO uint32_t*)0x400783A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 13) */
\r
594 #define REG_XDMAC_CDA13 (*(__IO uint32_t*)0x400783A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 13) */
\r
595 #define REG_XDMAC_CNDA13 (*(__IO uint32_t*)0x400783A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 13) */
\r
596 #define REG_XDMAC_CNDC13 (*(__IO uint32_t*)0x400783ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 13) */
\r
597 #define REG_XDMAC_CUBC13 (*(__IO uint32_t*)0x400783B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 13) */
\r
598 #define REG_XDMAC_CBC13 (*(__IO uint32_t*)0x400783B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 13) */
\r
599 #define REG_XDMAC_CC13 (*(__IO uint32_t*)0x400783B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 13) */
\r
600 #define REG_XDMAC_CDS_MSP13 (*(__IO uint32_t*)0x400783BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 13) */
\r
601 #define REG_XDMAC_CSUS13 (*(__IO uint32_t*)0x400783C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 13) */
\r
602 #define REG_XDMAC_CDUS13 (*(__IO uint32_t*)0x400783C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 13) */
\r
603 #define REG_XDMAC_CIE14 (*(__O uint32_t*)0x400783D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 14) */
\r
604 #define REG_XDMAC_CID14 (*(__O uint32_t*)0x400783D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 14) */
\r
605 #define REG_XDMAC_CIM14 (*(__O uint32_t*)0x400783D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 14) */
\r
606 #define REG_XDMAC_CIS14 (*(__I uint32_t*)0x400783DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 14) */
\r
607 #define REG_XDMAC_CSA14 (*(__IO uint32_t*)0x400783E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 14) */
\r
608 #define REG_XDMAC_CDA14 (*(__IO uint32_t*)0x400783E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 14) */
\r
609 #define REG_XDMAC_CNDA14 (*(__IO uint32_t*)0x400783E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 14) */
\r
610 #define REG_XDMAC_CNDC14 (*(__IO uint32_t*)0x400783ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 14) */
\r
611 #define REG_XDMAC_CUBC14 (*(__IO uint32_t*)0x400783F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 14) */
\r
612 #define REG_XDMAC_CBC14 (*(__IO uint32_t*)0x400783F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 14) */
\r
613 #define REG_XDMAC_CC14 (*(__IO uint32_t*)0x400783F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 14) */
\r
614 #define REG_XDMAC_CDS_MSP14 (*(__IO uint32_t*)0x400783FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 14) */
\r
615 #define REG_XDMAC_CSUS14 (*(__IO uint32_t*)0x40078400U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 14) */
\r
616 #define REG_XDMAC_CDUS14 (*(__IO uint32_t*)0x40078404U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 14) */
\r
617 #define REG_XDMAC_CIE15 (*(__O uint32_t*)0x40078410U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 15) */
\r
618 #define REG_XDMAC_CID15 (*(__O uint32_t*)0x40078414U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 15) */
\r
619 #define REG_XDMAC_CIM15 (*(__O uint32_t*)0x40078418U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 15) */
\r
620 #define REG_XDMAC_CIS15 (*(__I uint32_t*)0x4007841CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 15) */
\r
621 #define REG_XDMAC_CSA15 (*(__IO uint32_t*)0x40078420U) /**< \brief (XDMAC) Channel Source Address Register (chid = 15) */
\r
622 #define REG_XDMAC_CDA15 (*(__IO uint32_t*)0x40078424U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 15) */
\r
623 #define REG_XDMAC_CNDA15 (*(__IO uint32_t*)0x40078428U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 15) */
\r
624 #define REG_XDMAC_CNDC15 (*(__IO uint32_t*)0x4007842CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 15) */
\r
625 #define REG_XDMAC_CUBC15 (*(__IO uint32_t*)0x40078430U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 15) */
\r
626 #define REG_XDMAC_CBC15 (*(__IO uint32_t*)0x40078434U) /**< \brief (XDMAC) Channel Block Control Register (chid = 15) */
\r
627 #define REG_XDMAC_CC15 (*(__IO uint32_t*)0x40078438U) /**< \brief (XDMAC) Channel Configuration Register (chid = 15) */
\r
628 #define REG_XDMAC_CDS_MSP15 (*(__IO uint32_t*)0x4007843CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 15) */
\r
629 #define REG_XDMAC_CSUS15 (*(__IO uint32_t*)0x40078440U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 15) */
\r
630 #define REG_XDMAC_CDUS15 (*(__IO uint32_t*)0x40078444U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 15) */
\r
631 #define REG_XDMAC_CIE16 (*(__O uint32_t*)0x40078450U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 16) */
\r
632 #define REG_XDMAC_CID16 (*(__O uint32_t*)0x40078454U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 16) */
\r
633 #define REG_XDMAC_CIM16 (*(__O uint32_t*)0x40078458U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 16) */
\r
634 #define REG_XDMAC_CIS16 (*(__I uint32_t*)0x4007845CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 16) */
\r
635 #define REG_XDMAC_CSA16 (*(__IO uint32_t*)0x40078460U) /**< \brief (XDMAC) Channel Source Address Register (chid = 16) */
\r
636 #define REG_XDMAC_CDA16 (*(__IO uint32_t*)0x40078464U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 16) */
\r
637 #define REG_XDMAC_CNDA16 (*(__IO uint32_t*)0x40078468U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 16) */
\r
638 #define REG_XDMAC_CNDC16 (*(__IO uint32_t*)0x4007846CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 16) */
\r
639 #define REG_XDMAC_CUBC16 (*(__IO uint32_t*)0x40078470U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 16) */
\r
640 #define REG_XDMAC_CBC16 (*(__IO uint32_t*)0x40078474U) /**< \brief (XDMAC) Channel Block Control Register (chid = 16) */
\r
641 #define REG_XDMAC_CC16 (*(__IO uint32_t*)0x40078478U) /**< \brief (XDMAC) Channel Configuration Register (chid = 16) */
\r
642 #define REG_XDMAC_CDS_MSP16 (*(__IO uint32_t*)0x4007847CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 16) */
\r
643 #define REG_XDMAC_CSUS16 (*(__IO uint32_t*)0x40078480U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 16) */
\r
644 #define REG_XDMAC_CDUS16 (*(__IO uint32_t*)0x40078484U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 16) */
\r
645 #define REG_XDMAC_CIE17 (*(__O uint32_t*)0x40078490U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 17) */
\r
646 #define REG_XDMAC_CID17 (*(__O uint32_t*)0x40078494U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 17) */
\r
647 #define REG_XDMAC_CIM17 (*(__O uint32_t*)0x40078498U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 17) */
\r
648 #define REG_XDMAC_CIS17 (*(__I uint32_t*)0x4007849CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 17) */
\r
649 #define REG_XDMAC_CSA17 (*(__IO uint32_t*)0x400784A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 17) */
\r
650 #define REG_XDMAC_CDA17 (*(__IO uint32_t*)0x400784A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 17) */
\r
651 #define REG_XDMAC_CNDA17 (*(__IO uint32_t*)0x400784A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 17) */
\r
652 #define REG_XDMAC_CNDC17 (*(__IO uint32_t*)0x400784ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 17) */
\r
653 #define REG_XDMAC_CUBC17 (*(__IO uint32_t*)0x400784B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 17) */
\r
654 #define REG_XDMAC_CBC17 (*(__IO uint32_t*)0x400784B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 17) */
\r
655 #define REG_XDMAC_CC17 (*(__IO uint32_t*)0x400784B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 17) */
\r
656 #define REG_XDMAC_CDS_MSP17 (*(__IO uint32_t*)0x400784BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 17) */
\r
657 #define REG_XDMAC_CSUS17 (*(__IO uint32_t*)0x400784C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 17) */
\r
658 #define REG_XDMAC_CDUS17 (*(__IO uint32_t*)0x400784C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 17) */
\r
659 #define REG_XDMAC_CIE18 (*(__O uint32_t*)0x400784D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 18) */
\r
660 #define REG_XDMAC_CID18 (*(__O uint32_t*)0x400784D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 18) */
\r
661 #define REG_XDMAC_CIM18 (*(__O uint32_t*)0x400784D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 18) */
\r
662 #define REG_XDMAC_CIS18 (*(__I uint32_t*)0x400784DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 18) */
\r
663 #define REG_XDMAC_CSA18 (*(__IO uint32_t*)0x400784E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 18) */
\r
664 #define REG_XDMAC_CDA18 (*(__IO uint32_t*)0x400784E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 18) */
\r
665 #define REG_XDMAC_CNDA18 (*(__IO uint32_t*)0x400784E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 18) */
\r
666 #define REG_XDMAC_CNDC18 (*(__IO uint32_t*)0x400784ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 18) */
\r
667 #define REG_XDMAC_CUBC18 (*(__IO uint32_t*)0x400784F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 18) */
\r
668 #define REG_XDMAC_CBC18 (*(__IO uint32_t*)0x400784F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 18) */
\r
669 #define REG_XDMAC_CC18 (*(__IO uint32_t*)0x400784F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 18) */
\r
670 #define REG_XDMAC_CDS_MSP18 (*(__IO uint32_t*)0x400784FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 18) */
\r
671 #define REG_XDMAC_CSUS18 (*(__IO uint32_t*)0x40078500U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 18) */
\r
672 #define REG_XDMAC_CDUS18 (*(__IO uint32_t*)0x40078504U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 18) */
\r
673 #define REG_XDMAC_CIE19 (*(__O uint32_t*)0x40078510U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 19) */
\r
674 #define REG_XDMAC_CID19 (*(__O uint32_t*)0x40078514U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 19) */
\r
675 #define REG_XDMAC_CIM19 (*(__O uint32_t*)0x40078518U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 19) */
\r
676 #define REG_XDMAC_CIS19 (*(__I uint32_t*)0x4007851CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 19) */
\r
677 #define REG_XDMAC_CSA19 (*(__IO uint32_t*)0x40078520U) /**< \brief (XDMAC) Channel Source Address Register (chid = 19) */
\r
678 #define REG_XDMAC_CDA19 (*(__IO uint32_t*)0x40078524U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 19) */
\r
679 #define REG_XDMAC_CNDA19 (*(__IO uint32_t*)0x40078528U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 19) */
\r
680 #define REG_XDMAC_CNDC19 (*(__IO uint32_t*)0x4007852CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 19) */
\r
681 #define REG_XDMAC_CUBC19 (*(__IO uint32_t*)0x40078530U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 19) */
\r
682 #define REG_XDMAC_CBC19 (*(__IO uint32_t*)0x40078534U) /**< \brief (XDMAC) Channel Block Control Register (chid = 19) */
\r
683 #define REG_XDMAC_CC19 (*(__IO uint32_t*)0x40078538U) /**< \brief (XDMAC) Channel Configuration Register (chid = 19) */
\r
684 #define REG_XDMAC_CDS_MSP19 (*(__IO uint32_t*)0x4007853CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 19) */
\r
685 #define REG_XDMAC_CSUS19 (*(__IO uint32_t*)0x40078540U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 19) */
\r
686 #define REG_XDMAC_CDUS19 (*(__IO uint32_t*)0x40078544U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 19) */
\r
687 #define REG_XDMAC_CIE20 (*(__O uint32_t*)0x40078550U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 20) */
\r
688 #define REG_XDMAC_CID20 (*(__O uint32_t*)0x40078554U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 20) */
\r
689 #define REG_XDMAC_CIM20 (*(__O uint32_t*)0x40078558U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 20) */
\r
690 #define REG_XDMAC_CIS20 (*(__I uint32_t*)0x4007855CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 20) */
\r
691 #define REG_XDMAC_CSA20 (*(__IO uint32_t*)0x40078560U) /**< \brief (XDMAC) Channel Source Address Register (chid = 20) */
\r
692 #define REG_XDMAC_CDA20 (*(__IO uint32_t*)0x40078564U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 20) */
\r
693 #define REG_XDMAC_CNDA20 (*(__IO uint32_t*)0x40078568U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 20) */
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694 #define REG_XDMAC_CNDC20 (*(__IO uint32_t*)0x4007856CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 20) */
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695 #define REG_XDMAC_CUBC20 (*(__IO uint32_t*)0x40078570U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 20) */
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696 #define REG_XDMAC_CBC20 (*(__IO uint32_t*)0x40078574U) /**< \brief (XDMAC) Channel Block Control Register (chid = 20) */
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697 #define REG_XDMAC_CC20 (*(__IO uint32_t*)0x40078578U) /**< \brief (XDMAC) Channel Configuration Register (chid = 20) */
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698 #define REG_XDMAC_CDS_MSP20 (*(__IO uint32_t*)0x4007857CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 20) */
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699 #define REG_XDMAC_CSUS20 (*(__IO uint32_t*)0x40078580U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 20) */
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700 #define REG_XDMAC_CDUS20 (*(__IO uint32_t*)0x40078584U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 20) */
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701 #define REG_XDMAC_CIE21 (*(__O uint32_t*)0x40078590U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 21) */
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702 #define REG_XDMAC_CID21 (*(__O uint32_t*)0x40078594U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 21) */
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703 #define REG_XDMAC_CIM21 (*(__O uint32_t*)0x40078598U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 21) */
\r
704 #define REG_XDMAC_CIS21 (*(__I uint32_t*)0x4007859CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 21) */
\r
705 #define REG_XDMAC_CSA21 (*(__IO uint32_t*)0x400785A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 21) */
\r
706 #define REG_XDMAC_CDA21 (*(__IO uint32_t*)0x400785A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 21) */
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707 #define REG_XDMAC_CNDA21 (*(__IO uint32_t*)0x400785A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 21) */
\r
708 #define REG_XDMAC_CNDC21 (*(__IO uint32_t*)0x400785ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 21) */
\r
709 #define REG_XDMAC_CUBC21 (*(__IO uint32_t*)0x400785B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 21) */
\r
710 #define REG_XDMAC_CBC21 (*(__IO uint32_t*)0x400785B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 21) */
\r
711 #define REG_XDMAC_CC21 (*(__IO uint32_t*)0x400785B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 21) */
\r
712 #define REG_XDMAC_CDS_MSP21 (*(__IO uint32_t*)0x400785BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 21) */
\r
713 #define REG_XDMAC_CSUS21 (*(__IO uint32_t*)0x400785C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 21) */
\r
714 #define REG_XDMAC_CDUS21 (*(__IO uint32_t*)0x400785C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 21) */
\r
715 #define REG_XDMAC_CIE22 (*(__O uint32_t*)0x400785D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 22) */
\r
716 #define REG_XDMAC_CID22 (*(__O uint32_t*)0x400785D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 22) */
\r
717 #define REG_XDMAC_CIM22 (*(__O uint32_t*)0x400785D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 22) */
\r
718 #define REG_XDMAC_CIS22 (*(__I uint32_t*)0x400785DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 22) */
\r
719 #define REG_XDMAC_CSA22 (*(__IO uint32_t*)0x400785E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 22) */
\r
720 #define REG_XDMAC_CDA22 (*(__IO uint32_t*)0x400785E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 22) */
\r
721 #define REG_XDMAC_CNDA22 (*(__IO uint32_t*)0x400785E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 22) */
\r
722 #define REG_XDMAC_CNDC22 (*(__IO uint32_t*)0x400785ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 22) */
\r
723 #define REG_XDMAC_CUBC22 (*(__IO uint32_t*)0x400785F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 22) */
\r
724 #define REG_XDMAC_CBC22 (*(__IO uint32_t*)0x400785F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 22) */
\r
725 #define REG_XDMAC_CC22 (*(__IO uint32_t*)0x400785F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 22) */
\r
726 #define REG_XDMAC_CDS_MSP22 (*(__IO uint32_t*)0x400785FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 22) */
\r
727 #define REG_XDMAC_CSUS22 (*(__IO uint32_t*)0x40078600U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 22) */
\r
728 #define REG_XDMAC_CDUS22 (*(__IO uint32_t*)0x40078604U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 22) */
\r
729 #define REG_XDMAC_CIE23 (*(__O uint32_t*)0x40078610U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 23) */
\r
730 #define REG_XDMAC_CID23 (*(__O uint32_t*)0x40078614U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 23) */
\r
731 #define REG_XDMAC_CIM23 (*(__O uint32_t*)0x40078618U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 23) */
\r
732 #define REG_XDMAC_CIS23 (*(__I uint32_t*)0x4007861CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 23) */
\r
733 #define REG_XDMAC_CSA23 (*(__IO uint32_t*)0x40078620U) /**< \brief (XDMAC) Channel Source Address Register (chid = 23) */
\r
734 #define REG_XDMAC_CDA23 (*(__IO uint32_t*)0x40078624U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 23) */
\r
735 #define REG_XDMAC_CNDA23 (*(__IO uint32_t*)0x40078628U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 23) */
\r
736 #define REG_XDMAC_CNDC23 (*(__IO uint32_t*)0x4007862CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 23) */
\r
737 #define REG_XDMAC_CUBC23 (*(__IO uint32_t*)0x40078630U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 23) */
\r
738 #define REG_XDMAC_CBC23 (*(__IO uint32_t*)0x40078634U) /**< \brief (XDMAC) Channel Block Control Register (chid = 23) */
\r
739 #define REG_XDMAC_CC23 (*(__IO uint32_t*)0x40078638U) /**< \brief (XDMAC) Channel Configuration Register (chid = 23) */
\r
740 #define REG_XDMAC_CDS_MSP23 (*(__IO uint32_t*)0x4007863CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 23) */
\r
741 #define REG_XDMAC_CSUS23 (*(__IO uint32_t*)0x40078640U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 23) */
\r
742 #define REG_XDMAC_CDUS23 (*(__IO uint32_t*)0x40078644U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 23) */
\r
743 #define REG_XDMAC_VERSION (*(__IO uint32_t*)0x40078FFCU) /**< \brief (XDMAC) XDMAC Version Register */
\r
744 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
\r
746 #endif /* _SAM_XDMAC_INSTANCE_ */
\r
projects / freertos / blob