2 ******************************************************************************
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3 * @file stm32f746xx.h
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4 * @author MCD Application Team
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6 * @date 06-March-2015
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7 * @brief CMSIS STM32F746xx Device Peripheral Access Layer Header File.
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9 * This file contains:
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10 * - Data structures and the address mapping for all peripherals
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11 * - Peripheral's registers declarations and bits definition
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12 * - Macros to access peripheral
\92s registers hardware
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14 ******************************************************************************
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17 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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19 * Redistribution and use in source and binary forms, with or without modification,
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20 * are permitted provided that the following conditions are met:
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21 * 1. Redistributions of source code must retain the above copyright notice,
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22 * this list of conditions and the following disclaimer.
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23 * 2. Redistributions in binary form must reproduce the above copyright notice,
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24 * this list of conditions and the following disclaimer in the documentation
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25 * and/or other materials provided with the distribution.
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26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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27 * may be used to endorse or promote products derived from this software
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28 * without specific prior written permission.
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30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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41 ******************************************************************************
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44 /** @addtogroup CMSIS_Device
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48 /** @addtogroup stm32f746xx
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52 #ifndef __STM32F746xx_H
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53 #define __STM32F746xx_H
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57 #endif /* __cplusplus */
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59 /** @addtogroup Configuration_section_for_CMSIS
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64 * @brief STM32F7xx Interrupt Number Definition, according to the selected device
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65 * in @ref Library_configuration_section
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69 /****** Cortex-M7 Processor Exceptions Numbers ****************************************************************/
\r
70 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
\r
71 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M7 Memory Management Interrupt */
\r
72 BusFault_IRQn = -11, /*!< 5 Cortex-M7 Bus Fault Interrupt */
\r
73 UsageFault_IRQn = -10, /*!< 6 Cortex-M7 Usage Fault Interrupt */
\r
74 SVCall_IRQn = -5, /*!< 11 Cortex-M7 SV Call Interrupt */
\r
75 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M7 Debug Monitor Interrupt */
\r
76 PendSV_IRQn = -2, /*!< 14 Cortex-M7 Pend SV Interrupt */
\r
77 SysTick_IRQn = -1, /*!< 15 Cortex-M7 System Tick Interrupt */
\r
78 /****** STM32 specific Interrupt Numbers **********************************************************************/
\r
79 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
\r
80 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
\r
81 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
\r
82 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
\r
83 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
\r
84 RCC_IRQn = 5, /*!< RCC global Interrupt */
\r
85 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
\r
86 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
\r
87 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
\r
88 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
\r
89 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
\r
90 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
\r
91 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
\r
92 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
\r
93 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
\r
94 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
\r
95 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
\r
96 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
\r
97 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
\r
98 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
\r
99 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
\r
100 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
\r
101 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
\r
102 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
\r
103 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
\r
104 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
\r
105 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
\r
106 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
\r
107 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
\r
108 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
\r
109 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
\r
110 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
\r
111 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
\r
112 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
\r
113 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
\r
114 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
\r
115 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
\r
116 USART1_IRQn = 37, /*!< USART1 global Interrupt */
\r
117 USART2_IRQn = 38, /*!< USART2 global Interrupt */
\r
118 USART3_IRQn = 39, /*!< USART3 global Interrupt */
\r
119 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
\r
120 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
\r
121 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
\r
122 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
\r
123 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
\r
124 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
\r
125 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
\r
126 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
\r
127 FMC_IRQn = 48, /*!< FMC global Interrupt */
\r
128 SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
\r
129 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
\r
130 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
\r
131 UART4_IRQn = 52, /*!< UART4 global Interrupt */
\r
132 UART5_IRQn = 53, /*!< UART5 global Interrupt */
\r
133 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
\r
134 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
\r
135 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
\r
136 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
\r
137 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
\r
138 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
\r
139 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
\r
140 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
\r
141 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
\r
142 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
\r
143 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
\r
144 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
\r
145 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
\r
146 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
\r
147 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
\r
148 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
\r
149 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
\r
150 USART6_IRQn = 71, /*!< USART6 global interrupt */
\r
151 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
\r
152 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
\r
153 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
\r
154 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
\r
155 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
\r
156 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
\r
157 DCMI_IRQn = 78, /*!< DCMI global interrupt */
\r
158 RNG_IRQn = 80, /*!< RNG global interrupt */
\r
159 FPU_IRQn = 81, /*!< FPU global interrupt */
\r
160 UART7_IRQn = 82, /*!< UART7 global interrupt */
\r
161 UART8_IRQn = 83, /*!< UART8 global interrupt */
\r
162 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
\r
163 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
\r
164 SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
\r
165 SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
\r
166 LTDC_IRQn = 88, /*!< LTDC global Interrupt */
\r
167 LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
\r
168 DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */
\r
169 SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
\r
170 QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */
\r
171 LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */
\r
172 CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */
\r
173 I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */
\r
174 I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */
\r
175 SPDIF_RX_IRQn = 97 /*!< SPDIF-RX global Interrupt */
\r
183 * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
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185 #define __CM7_REV 0x0000 /*!< Cortex-M7 revision r0p1 */
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186 #define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
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187 #define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
\r
188 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
\r
189 #define __FPU_PRESENT 1 /*!< FPU present */
\r
190 #define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
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191 #define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
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192 #include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
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195 #include "system_stm32f7xx.h"
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196 #include <stdint.h>
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198 /** @addtogroup Peripheral_registers_structures
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203 * @brief Analog to Digital Converter
\r
208 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
\r
209 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
\r
210 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
\r
211 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
\r
212 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
\r
213 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
\r
214 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
\r
215 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
\r
216 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
\r
217 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
\r
218 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
\r
219 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
\r
220 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
\r
221 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
\r
222 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
\r
223 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
\r
224 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
\r
225 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
\r
226 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
\r
227 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
\r
232 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
\r
233 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
\r
234 __IO uint32_t CDR; /*!< ADC common regular data register for dual
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235 AND triple modes, Address offset: ADC1 base address + 0x308 */
\r
236 } ADC_Common_TypeDef;
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240 * @brief Controller Area Network TxMailBox
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245 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
\r
246 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
\r
247 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
\r
248 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
\r
249 } CAN_TxMailBox_TypeDef;
\r
252 * @brief Controller Area Network FIFOMailBox
\r
257 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
\r
258 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
\r
259 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
\r
260 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
\r
261 } CAN_FIFOMailBox_TypeDef;
\r
264 * @brief Controller Area Network FilterRegister
\r
269 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
\r
270 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
\r
271 } CAN_FilterRegister_TypeDef;
\r
274 * @brief Controller Area Network
\r
279 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
\r
280 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
\r
281 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
\r
282 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
\r
283 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
\r
284 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
\r
285 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
\r
286 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
\r
287 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
\r
288 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
\r
289 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
\r
290 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
\r
291 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
\r
292 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
\r
293 uint32_t RESERVED2; /*!< Reserved, 0x208 */
\r
294 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
\r
295 uint32_t RESERVED3; /*!< Reserved, 0x210 */
\r
296 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
\r
297 uint32_t RESERVED4; /*!< Reserved, 0x218 */
\r
298 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
\r
299 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
\r
300 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
\r
309 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
\r
310 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
\r
311 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
\r
312 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
\r
313 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
\r
314 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
\r
319 * @brief CRC calculation unit
\r
324 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
\r
325 __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
\r
326 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
\r
327 uint32_t RESERVED0; /*!< Reserved, 0x0C */
\r
328 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
\r
329 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
\r
333 * @brief Digital to Analog Converter
\r
338 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
\r
339 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
\r
340 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
\r
341 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
\r
342 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
\r
343 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
\r
344 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
\r
345 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
\r
346 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
\r
347 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
\r
348 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
\r
349 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
\r
350 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
\r
351 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
\r
360 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
\r
361 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
\r
362 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
\r
363 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
\r
372 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
\r
373 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
\r
374 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
\r
375 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
\r
376 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
\r
377 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
\r
378 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
\r
379 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
\r
380 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
\r
381 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
\r
382 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
\r
386 * @brief DMA Controller
\r
391 __IO uint32_t CR; /*!< DMA stream x configuration register */
\r
392 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
\r
393 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
\r
394 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
\r
395 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
\r
396 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
\r
397 } DMA_Stream_TypeDef;
\r
401 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
\r
402 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
\r
403 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
\r
404 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
\r
409 * @brief DMA2D Controller
\r
414 __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
\r
415 __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
\r
416 __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
\r
417 __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
\r
418 __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
\r
419 __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
\r
420 __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
\r
421 __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
\r
422 __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
\r
423 __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
\r
424 __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
\r
425 __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
\r
426 __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
\r
427 __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
\r
428 __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
\r
429 __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
\r
430 __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
\r
431 __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
\r
432 __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
\r
433 __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
\r
434 uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
\r
435 __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
\r
436 __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
\r
441 * @brief Ethernet MAC
\r
446 __IO uint32_t MACCR;
\r
447 __IO uint32_t MACFFR;
\r
448 __IO uint32_t MACHTHR;
\r
449 __IO uint32_t MACHTLR;
\r
450 __IO uint32_t MACMIIAR;
\r
451 __IO uint32_t MACMIIDR;
\r
452 __IO uint32_t MACFCR;
\r
453 __IO uint32_t MACVLANTR; /* 8 */
\r
454 uint32_t RESERVED0[2];
\r
455 __IO uint32_t MACRWUFFR; /* 11 */
\r
456 __IO uint32_t MACPMTCSR;
\r
457 uint32_t RESERVED1[2];
\r
458 __IO uint32_t MACSR; /* 15 */
\r
459 __IO uint32_t MACIMR;
\r
460 __IO uint32_t MACA0HR;
\r
461 __IO uint32_t MACA0LR;
\r
462 __IO uint32_t MACA1HR;
\r
463 __IO uint32_t MACA1LR;
\r
464 __IO uint32_t MACA2HR;
\r
465 __IO uint32_t MACA2LR;
\r
466 __IO uint32_t MACA3HR;
\r
467 __IO uint32_t MACA3LR; /* 24 */
\r
468 uint32_t RESERVED2[40];
\r
469 __IO uint32_t MMCCR; /* 65 */
\r
470 __IO uint32_t MMCRIR;
\r
471 __IO uint32_t MMCTIR;
\r
472 __IO uint32_t MMCRIMR;
\r
473 __IO uint32_t MMCTIMR; /* 69 */
\r
474 uint32_t RESERVED3[14];
\r
475 __IO uint32_t MMCTGFSCCR; /* 84 */
\r
476 __IO uint32_t MMCTGFMSCCR;
\r
477 uint32_t RESERVED4[5];
\r
478 __IO uint32_t MMCTGFCR;
\r
479 uint32_t RESERVED5[10];
\r
480 __IO uint32_t MMCRFCECR;
\r
481 __IO uint32_t MMCRFAECR;
\r
482 uint32_t RESERVED6[10];
\r
483 __IO uint32_t MMCRGUFCR;
\r
484 uint32_t RESERVED7[334];
\r
485 __IO uint32_t PTPTSCR;
\r
486 __IO uint32_t PTPSSIR;
\r
487 __IO uint32_t PTPTSHR;
\r
488 __IO uint32_t PTPTSLR;
\r
489 __IO uint32_t PTPTSHUR;
\r
490 __IO uint32_t PTPTSLUR;
\r
491 __IO uint32_t PTPTSAR;
\r
492 __IO uint32_t PTPTTHR;
\r
493 __IO uint32_t PTPTTLR;
\r
494 __IO uint32_t RESERVED8;
\r
495 __IO uint32_t PTPTSSR;
\r
496 uint32_t RESERVED9[565];
\r
497 __IO uint32_t DMABMR;
\r
498 __IO uint32_t DMATPDR;
\r
499 __IO uint32_t DMARPDR;
\r
500 __IO uint32_t DMARDLAR;
\r
501 __IO uint32_t DMATDLAR;
\r
502 __IO uint32_t DMASR;
\r
503 __IO uint32_t DMAOMR;
\r
504 __IO uint32_t DMAIER;
\r
505 __IO uint32_t DMAMFBOCR;
\r
506 __IO uint32_t DMARSWTR;
\r
507 uint32_t RESERVED10[8];
\r
508 __IO uint32_t DMACHTDR;
\r
509 __IO uint32_t DMACHRDR;
\r
510 __IO uint32_t DMACHTBAR;
\r
511 __IO uint32_t DMACHRBAR;
\r
515 * @brief External Interrupt/Event Controller
\r
520 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
\r
521 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
\r
522 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
\r
523 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
\r
524 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
\r
525 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
\r
529 * @brief FLASH Registers
\r
534 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
\r
535 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
\r
536 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
\r
537 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
\r
538 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
\r
539 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
\r
540 __IO uint32_t OPTCR1; /*!< FLASH option control register 1 , Address offset: 0x18 */
\r
546 * @brief Flexible Memory Controller
\r
551 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
\r
552 } FMC_Bank1_TypeDef;
\r
555 * @brief Flexible Memory Controller Bank1E
\r
560 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
\r
561 } FMC_Bank1E_TypeDef;
\r
564 * @brief Flexible Memory Controller Bank3
\r
569 __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
\r
570 __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
\r
571 __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
\r
572 __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
\r
573 uint32_t RESERVED0; /*!< Reserved, 0x90 */
\r
574 __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
\r
575 } FMC_Bank3_TypeDef;
\r
578 * @brief Flexible Memory Controller Bank5_6
\r
583 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
\r
584 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
\r
585 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
\r
586 __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
\r
587 __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
\r
588 } FMC_Bank5_6_TypeDef;
\r
592 * @brief General Purpose I/O
\r
597 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
\r
598 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
\r
599 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
\r
600 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
\r
601 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
\r
602 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
\r
603 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
\r
604 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
\r
605 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
\r
609 * @brief System configuration controller
\r
614 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
\r
615 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
\r
616 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
\r
617 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
\r
618 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
\r
622 * @brief Inter-integrated Circuit Interface
\r
627 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
\r
628 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
\r
629 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
\r
630 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
\r
631 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
\r
632 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
\r
633 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
\r
634 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
\r
635 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
\r
636 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
\r
637 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
\r
641 * @brief Independent WATCHDOG
\r
646 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
\r
647 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
\r
648 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
\r
649 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
\r
650 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
\r
655 * @brief LCD-TFT Display Controller
\r
660 uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
\r
661 __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
\r
662 __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
\r
663 __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
\r
664 __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
\r
665 __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
\r
666 uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
\r
667 __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
\r
668 uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
\r
669 __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
\r
670 uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
\r
671 __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
\r
672 __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
\r
673 __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
\r
674 __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
\r
675 __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
\r
676 __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
\r
680 * @brief LCD-TFT Display layer x Controller
\r
685 __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
\r
686 __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
\r
687 __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
\r
688 __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
\r
689 __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
\r
690 __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
\r
691 __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
\r
692 __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
\r
693 uint32_t RESERVED0[2]; /*!< Reserved */
\r
694 __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
\r
695 __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
\r
696 __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
\r
697 uint32_t RESERVED1[3]; /*!< Reserved */
\r
698 __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
\r
700 } LTDC_Layer_TypeDef;
\r
704 * @brief Power Control
\r
709 __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
\r
710 __IO uint32_t CSR1; /*!< PWR power control/status register 2, Address offset: 0x04 */
\r
711 __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */
\r
712 __IO uint32_t CSR2; /*!< PWR power control/status register 2, Address offset: 0x0C */
\r
717 * @brief Reset and Clock Control
\r
722 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
\r
723 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
\r
724 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
\r
725 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
\r
726 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
\r
727 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
\r
728 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
\r
729 uint32_t RESERVED0; /*!< Reserved, 0x1C */
\r
730 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
\r
731 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
\r
732 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
\r
733 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
\r
734 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
\r
735 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
\r
736 uint32_t RESERVED2; /*!< Reserved, 0x3C */
\r
737 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
\r
738 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
\r
739 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
\r
740 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
\r
741 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
\r
742 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
\r
743 uint32_t RESERVED4; /*!< Reserved, 0x5C */
\r
744 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
\r
745 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
\r
746 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
\r
747 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
\r
748 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
\r
749 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
\r
750 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
\r
751 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
\r
752 __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
\r
753 __IO uint32_t DCKCFGR1; /*!< RCC Dedicated Clocks configuration register1, Address offset: 0x8C */
\r
754 __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x90 */
\r
759 * @brief Real-Time Clock
\r
764 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
\r
765 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
\r
766 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
\r
767 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
\r
768 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
\r
769 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
\r
770 uint32_t reserved; /*!< Reserved */
\r
771 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
\r
772 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
\r
773 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
\r
774 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
\r
775 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
\r
776 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
\r
777 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
\r
778 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
\r
779 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
\r
780 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
\r
781 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
\r
782 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
\r
783 __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
\r
784 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
\r
785 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
\r
786 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
\r
787 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
\r
788 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
\r
789 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
\r
790 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
\r
791 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
\r
792 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
\r
793 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
\r
794 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
\r
795 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
\r
796 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
\r
797 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
\r
798 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
\r
799 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
\r
800 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
\r
801 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
\r
802 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
\r
803 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
\r
804 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
\r
805 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
\r
806 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
\r
807 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
\r
808 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
\r
809 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
\r
810 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
\r
811 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
\r
812 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
\r
813 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
\r
814 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
\r
815 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
\r
820 * @brief Serial Audio Interface
\r
825 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
\r
830 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
\r
831 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
\r
832 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
\r
833 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
\r
834 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
\r
835 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
\r
836 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
\r
837 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
\r
838 } SAI_Block_TypeDef;
\r
841 * @brief SPDIF-RX Interface
\r
846 __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
\r
847 __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
\r
848 __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
\r
849 __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
\r
850 __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
\r
851 __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
\r
852 __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
\r
857 * @brief SD host Interface
\r
862 __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
\r
863 __IO uint32_t CLKCR; /*!< SDMMClock control register, Address offset: 0x04 */
\r
864 __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
\r
865 __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
\r
866 __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
\r
867 __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
\r
868 __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
\r
869 __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
\r
870 __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
\r
871 __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
\r
872 __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
\r
873 __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
\r
874 __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
\r
875 __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
\r
876 __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
\r
877 __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
\r
878 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
\r
879 __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */
\r
880 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
\r
881 __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
\r
885 * @brief Serial Peripheral Interface
\r
890 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
\r
891 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
\r
892 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
\r
893 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
\r
894 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
\r
895 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
\r
896 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
\r
897 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
\r
898 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
\r
902 * @brief QUAD Serial Peripheral Interface
\r
907 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
\r
908 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
\r
909 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
\r
910 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
\r
911 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
\r
912 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
\r
913 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
\r
914 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
\r
915 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
\r
916 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
\r
917 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
\r
918 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
\r
919 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
\r
928 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
\r
929 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
\r
930 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
\r
931 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
\r
932 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
\r
933 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
\r
934 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
\r
935 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
\r
936 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
\r
937 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
\r
938 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
\r
939 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
\r
940 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
\r
941 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
\r
942 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
\r
943 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
\r
944 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
\r
945 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
\r
946 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
\r
947 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
\r
948 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
\r
949 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
\r
950 __IO uint32_t CCR5; /*!< TIM capture/compare mode register5, Address offset: 0x58 */
\r
951 __IO uint32_t CCR6; /*!< TIM capture/compare mode register6, Address offset: 0x5C */
\r
960 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
\r
961 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
\r
962 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
\r
963 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
\r
964 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
\r
965 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
\r
966 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
\r
967 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
\r
968 __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
\r
973 * @brief Universal Synchronous Asynchronous Receiver Transmitter
\r
978 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
\r
979 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
\r
980 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
\r
981 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
\r
982 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
\r
983 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
\r
984 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
\r
985 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
\r
986 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
\r
987 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
\r
988 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
\r
993 * @brief Window WATCHDOG
\r
998 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
\r
999 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
\r
1000 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
\r
1009 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
\r
1010 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
\r
1011 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
\r
1019 * @brief USB_OTG_Core_Registers
\r
1023 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
\r
1024 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
\r
1025 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
\r
1026 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
\r
1027 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
\r
1028 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
\r
1029 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
\r
1030 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
\r
1031 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
\r
1032 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
\r
1033 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
\r
1034 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
\r
1035 uint32_t Reserved30[2]; /*!< Reserved 030h */
\r
1036 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
\r
1037 __IO uint32_t CID; /*!< User ID Register 03Ch */
\r
1038 uint32_t Reserved5[3]; /*!< Reserved 040h-048h */
\r
1039 __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
\r
1040 uint32_t Reserved6; /*!< Reserved 050h */
\r
1041 __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
\r
1042 __IO uint32_t GPWRDN; /*!< Power Down Register 058h */
\r
1043 __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
\r
1044 __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */
\r
1045 uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */
\r
1046 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
\r
1047 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
\r
1048 } USB_OTG_GlobalTypeDef;
\r
1052 * @brief USB_OTG_device_Registers
\r
1056 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
\r
1057 __IO uint32_t DCTL; /*!< dev Control Register 804h */
\r
1058 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
\r
1059 uint32_t Reserved0C; /*!< Reserved 80Ch */
\r
1060 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
\r
1061 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
\r
1062 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
\r
1063 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
\r
1064 uint32_t Reserved20; /*!< Reserved 820h */
\r
1065 uint32_t Reserved9; /*!< Reserved 824h */
\r
1066 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
\r
1067 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
\r
1068 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
\r
1069 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
\r
1070 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
\r
1071 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
\r
1072 uint32_t Reserved40; /*!< dedicated EP mask 840h */
\r
1073 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
\r
1074 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
\r
1075 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
\r
1076 } USB_OTG_DeviceTypeDef;
\r
1080 * @brief USB_OTG_IN_Endpoint-Specific_Register
\r
1084 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
\r
1085 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
\r
1086 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
\r
1087 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
\r
1088 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
\r
1089 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
\r
1090 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
\r
1091 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
\r
1092 } USB_OTG_INEndpointTypeDef;
\r
1096 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
\r
1100 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
\r
1101 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
\r
1102 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
\r
1103 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
\r
1104 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
\r
1105 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
\r
1106 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
\r
1107 } USB_OTG_OUTEndpointTypeDef;
\r
1111 * @brief USB_OTG_Host_Mode_Register_Structures
\r
1115 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
\r
1116 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
\r
1117 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
\r
1118 uint32_t Reserved40C; /*!< Reserved 40Ch */
\r
1119 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
\r
1120 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
\r
1121 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
\r
1122 } USB_OTG_HostTypeDef;
\r
1125 * @brief USB_OTG_Host_Channel_Specific_Registers
\r
1129 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
\r
1130 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
\r
1131 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
\r
1132 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
\r
1133 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
\r
1134 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
\r
1135 uint32_t Reserved[2]; /*!< Reserved */
\r
1136 } USB_OTG_HostChannelTypeDef;
\r
1142 /** @addtogroup Peripheral_memory_map
\r
1145 #define RAMITCM_BASE ((uint32_t)0x00000000) /*!< Base address of :16KB RAM reserved for CPU execution/instruction accessible over ITCM */
\r
1146 #define FLASHITCM_BASE ((uint32_t)0x00200000) /*!< Base address of :(up to 1 MB) embedded FLASH memory accessible over ITCM */
\r
1147 #define FLASHAXI_BASE ((uint32_t)0x08000000) /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI */
\r
1148 #define RAMDTCM_BASE ((uint32_t)0x20000000) /*!< Base address of : 64KB system data RAM accessible over DTCM */
\r
1149 #define SRAM1_BASE ((uint32_t)0x20010000) /*!< Base address of : 240KB RAM1 accessible over AXI/AHB */
\r
1150 #define SRAM2_BASE ((uint32_t)0x2004C000) /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */
\r
1151 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */
\r
1152 #define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Base address of : Backup SRAM(4 KB) */
\r
1153 #define QSPI_BASE ((uint32_t)0x90000000) /*!< Base address of : QSPI memories accessible over AXI */
\r
1154 #define FMC_R_BASE ((uint32_t)0xA0000000) /*!< Base address of : FMC Control registers */
\r
1155 #define QSPI_R_BASE ((uint32_t)0xA0001000) /*!< Base address of : QSPI Control registers */
\r
1156 #define FLASH_END ((uint32_t)0x080FFFFF) /*!< FLASH end address */
\r
1158 /* Legacy define */
\r
1159 #define FLASH_BASE FLASHAXI_BASE
\r
1161 /*!< Peripheral memory map */
\r
1162 #define APB1PERIPH_BASE PERIPH_BASE
\r
1163 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
\r
1164 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
\r
1165 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
\r
1167 /*!< APB1 peripherals */
\r
1168 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
\r
1169 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
\r
1170 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
\r
1171 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
\r
1172 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
\r
1173 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
\r
1174 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
\r
1175 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
\r
1176 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
\r
1177 #define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400)
\r
1178 #define RTC_BASE (APB1PERIPH_BASE + 0x2800)
\r
1179 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
\r
1180 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
\r
1181 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
\r
1182 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
\r
1183 #define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000)
\r
1184 #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
\r
1185 #define USART3_BASE (APB1PERIPH_BASE + 0x4800)
\r
1186 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
\r
1187 #define UART5_BASE (APB1PERIPH_BASE + 0x5000)
\r
1188 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
\r
1189 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
\r
1190 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
\r
1191 #define I2C4_BASE (APB1PERIPH_BASE + 0x6000)
\r
1192 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
\r
1193 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
\r
1194 #define CEC_BASE (APB1PERIPH_BASE + 0x6C00)
\r
1195 #define PWR_BASE (APB1PERIPH_BASE + 0x7000)
\r
1196 #define DAC_BASE (APB1PERIPH_BASE + 0x7400)
\r
1197 #define UART7_BASE (APB1PERIPH_BASE + 0x7800)
\r
1198 #define UART8_BASE (APB1PERIPH_BASE + 0x7C00)
\r
1200 /*!< APB2 peripherals */
\r
1201 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
\r
1202 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400)
\r
1203 #define USART1_BASE (APB2PERIPH_BASE + 0x1000)
\r
1204 #define USART6_BASE (APB2PERIPH_BASE + 0x1400)
\r
1205 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
\r
1206 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
\r
1207 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
\r
1208 #define ADC_BASE (APB2PERIPH_BASE + 0x2300)
\r
1209 #define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00)
\r
1210 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
\r
1211 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
\r
1212 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
\r
1213 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
\r
1214 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
\r
1215 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
\r
1216 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
\r
1217 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000)
\r
1218 #define SPI6_BASE (APB2PERIPH_BASE + 0x5400)
\r
1219 #define SAI1_BASE (APB2PERIPH_BASE + 0x5800)
\r
1220 #define SAI2_BASE (APB2PERIPH_BASE + 0x5C00)
\r
1221 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
\r
1222 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
\r
1223 #define SAI2_Block_A_BASE (SAI2_BASE + 0x004)
\r
1224 #define SAI2_Block_B_BASE (SAI2_BASE + 0x024)
\r
1225 #define LTDC_BASE (APB2PERIPH_BASE + 0x6800)
\r
1226 #define LTDC_Layer1_BASE (LTDC_BASE + 0x84)
\r
1227 #define LTDC_Layer2_BASE (LTDC_BASE + 0x104)
\r
1228 /*!< AHB1 peripherals */
\r
1229 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
\r
1230 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
\r
1231 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
\r
1232 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
\r
1233 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
\r
1234 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)
\r
1235 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)
\r
1236 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
\r
1237 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)
\r
1238 #define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400)
\r
1239 #define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800)
\r
1240 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
\r
1241 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
\r
1242 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
\r
1243 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
\r
1244 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
\r
1245 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
\r
1246 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
\r
1247 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
\r
1248 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
\r
1249 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
\r
1250 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
\r
1251 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
\r
1252 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
\r
1253 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
\r
1254 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
\r
1255 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
\r
1256 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
\r
1257 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
\r
1258 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
\r
1259 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
\r
1260 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
\r
1261 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000)
\r
1262 #define ETH_MAC_BASE (ETH_BASE)
\r
1263 #define ETH_MMC_BASE (ETH_BASE + 0x0100)
\r
1264 #define ETH_PTP_BASE (ETH_BASE + 0x0700)
\r
1265 #define ETH_DMA_BASE (ETH_BASE + 0x1000)
\r
1266 #define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000)
\r
1267 /*!< AHB2 peripherals */
\r
1268 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)
\r
1269 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800)
\r
1270 /*!< FMC Bankx registers base address */
\r
1271 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)
\r
1272 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)
\r
1273 #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080)
\r
1274 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140)
\r
1276 /* Debug MCU registers base address */
\r
1277 #define DBGMCU_BASE ((uint32_t )0xE0042000)
\r
1279 /*!< USB registers base address */
\r
1280 #define USB_OTG_HS_PERIPH_BASE ((uint32_t )0x40040000)
\r
1281 #define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000)
\r
1283 #define USB_OTG_GLOBAL_BASE ((uint32_t )0x000)
\r
1284 #define USB_OTG_DEVICE_BASE ((uint32_t )0x800)
\r
1285 #define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900)
\r
1286 #define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00)
\r
1287 #define USB_OTG_EP_REG_SIZE ((uint32_t )0x20)
\r
1288 #define USB_OTG_HOST_BASE ((uint32_t )0x400)
\r
1289 #define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440)
\r
1290 #define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500)
\r
1291 #define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20)
\r
1292 #define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00)
\r
1293 #define USB_OTG_FIFO_BASE ((uint32_t )0x1000)
\r
1294 #define USB_OTG_FIFO_SIZE ((uint32_t )0x1000)
\r
1300 /** @addtogroup Peripheral_declaration
\r
1303 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
\r
1304 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
\r
1305 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
\r
1306 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
\r
1307 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
\r
1308 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
\r
1309 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
\r
1310 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
\r
1311 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
\r
1312 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
\r
1313 #define RTC ((RTC_TypeDef *) RTC_BASE)
\r
1314 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
\r
1315 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
\r
1316 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
\r
1317 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
\r
1318 #define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
\r
1319 #define USART2 ((USART_TypeDef *) USART2_BASE)
\r
1320 #define USART3 ((USART_TypeDef *) USART3_BASE)
\r
1321 #define UART4 ((USART_TypeDef *) UART4_BASE)
\r
1322 #define UART5 ((USART_TypeDef *) UART5_BASE)
\r
1323 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
\r
1324 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
\r
1325 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
\r
1326 #define I2C4 ((I2C_TypeDef *) I2C4_BASE)
\r
1327 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
\r
1328 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
\r
1329 #define CEC ((CEC_TypeDef *) CEC_BASE)
\r
1330 #define PWR ((PWR_TypeDef *) PWR_BASE)
\r
1331 #define DAC ((DAC_TypeDef *) DAC_BASE)
\r
1332 #define UART7 ((USART_TypeDef *) UART7_BASE)
\r
1333 #define UART8 ((USART_TypeDef *) UART8_BASE)
\r
1334 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
\r
1335 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
\r
1336 #define USART1 ((USART_TypeDef *) USART1_BASE)
\r
1337 #define USART6 ((USART_TypeDef *) USART6_BASE)
\r
1338 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
\r
1339 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
\r
1340 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
\r
1341 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
\r
1342 #define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
\r
1343 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
\r
1344 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
\r
1345 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
\r
1346 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
\r
1347 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
\r
1348 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
\r
1349 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
\r
1350 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
\r
1351 #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
\r
1352 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
\r
1353 #define SAI2 ((SAI_TypeDef *) SAI2_BASE)
\r
1354 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
\r
1355 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
\r
1356 #define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
\r
1357 #define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
\r
1358 #define LTDC ((LTDC_TypeDef *)LTDC_BASE)
\r
1359 #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
\r
1360 #define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
\r
1361 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
\r
1362 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
\r
1363 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
\r
1364 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
\r
1365 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
\r
1366 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
\r
1367 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
\r
1368 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
\r
1369 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
\r
1370 #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
\r
1371 #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
\r
1372 #define CRC ((CRC_TypeDef *) CRC_BASE)
\r
1373 #define RCC ((RCC_TypeDef *) RCC_BASE)
\r
1374 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
\r
1375 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
\r
1376 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
\r
1377 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
\r
1378 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
\r
1379 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
\r
1380 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
\r
1381 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
\r
1382 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
\r
1383 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
\r
1384 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
\r
1385 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
\r
1386 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
\r
1387 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
\r
1388 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
\r
1389 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
\r
1390 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
\r
1391 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
\r
1392 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
\r
1393 #define ETH ((ETH_TypeDef *) ETH_BASE)
\r
1394 #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
\r
1395 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
\r
1396 #define RNG ((RNG_TypeDef *) RNG_BASE)
\r
1397 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
\r
1398 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
\r
1399 #define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
\r
1400 #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
\r
1401 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
\r
1402 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
\r
1403 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
\r
1404 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
\r
1410 /** @addtogroup Exported_constants
\r
1414 /** @addtogroup Peripheral_Registers_Bits_Definition
\r
1418 /******************************************************************************/
\r
1419 /* Peripheral Registers_Bits_Definition */
\r
1420 /******************************************************************************/
\r
1422 /******************************************************************************/
\r
1424 /* Analog to Digital Converter */
\r
1426 /******************************************************************************/
\r
1427 /******************** Bit definition for ADC_SR register ********************/
\r
1428 #define ADC_SR_AWD ((uint32_t)0x00000001) /*!<Analog watchdog flag */
\r
1429 #define ADC_SR_EOC ((uint32_t)0x00000002) /*!<End of conversion */
\r
1430 #define ADC_SR_JEOC ((uint32_t)0x00000004) /*!<Injected channel end of conversion */
\r
1431 #define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!<Injected channel Start flag */
\r
1432 #define ADC_SR_STRT ((uint32_t)0x00000010) /*!<Regular channel Start flag */
\r
1433 #define ADC_SR_OVR ((uint32_t)0x00000020) /*!<Overrun flag */
\r
1435 /******************* Bit definition for ADC_CR1 register ********************/
\r
1436 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
\r
1437 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
1438 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
1439 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
1440 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
1441 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
\r
1442 #define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
\r
1443 #define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
\r
1444 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
\r
1445 #define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
\r
1446 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
\r
1447 #define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
\r
1448 #define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
\r
1449 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
\r
1450 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
\r
1451 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
\r
1452 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
\r
1453 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
\r
1454 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
\r
1455 #define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
\r
1456 #define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */
\r
1457 #define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */
\r
1458 #define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */
\r
1459 #define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */
\r
1461 /******************* Bit definition for ADC_CR2 register ********************/
\r
1462 #define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
\r
1463 #define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
\r
1464 #define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
\r
1465 #define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */
\r
1466 #define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */
\r
1467 #define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
\r
1468 #define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */
\r
1469 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
\r
1470 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
\r
1471 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
\r
1472 #define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */
\r
1473 #define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
\r
1474 #define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */
\r
1475 #define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */
\r
1476 #define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */
\r
1477 #define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
\r
1478 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
\r
1479 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
\r
1480 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
\r
1481 #define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
\r
1482 #define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
\r
1483 #define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */
\r
1484 #define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */
\r
1485 #define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */
\r
1487 /****************** Bit definition for ADC_SMPR1 register *******************/
\r
1488 #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
\r
1489 #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
1490 #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
1491 #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
1492 #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
\r
1493 #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
\r
1494 #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
\r
1495 #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
\r
1496 #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
\r
1497 #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
\r
1498 #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
\r
1499 #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
\r
1500 #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
\r
1501 #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
\r
1502 #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
\r
1503 #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
\r
1504 #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
\r
1505 #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
\r
1506 #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
\r
1507 #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
\r
1508 #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
\r
1509 #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
\r
1510 #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
\r
1511 #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
\r
1512 #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
\r
1513 #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
\r
1514 #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
\r
1515 #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
\r
1516 #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
\r
1517 #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
\r
1518 #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
\r
1519 #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
\r
1520 #define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
\r
1521 #define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */
\r
1522 #define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */
\r
1523 #define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */
\r
1525 /****************** Bit definition for ADC_SMPR2 register *******************/
\r
1526 #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
\r
1527 #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
1528 #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
1529 #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
1530 #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
\r
1531 #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
\r
1532 #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
\r
1533 #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
\r
1534 #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
\r
1535 #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
\r
1536 #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
\r
1537 #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
\r
1538 #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
\r
1539 #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
\r
1540 #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
\r
1541 #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
\r
1542 #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
\r
1543 #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
\r
1544 #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
\r
1545 #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
\r
1546 #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
\r
1547 #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
\r
1548 #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
\r
1549 #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
\r
1550 #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
\r
1551 #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
\r
1552 #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
\r
1553 #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
\r
1554 #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
\r
1555 #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
\r
1556 #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
\r
1557 #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
\r
1558 #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
\r
1559 #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
\r
1560 #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
\r
1561 #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
\r
1562 #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
\r
1563 #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
\r
1564 #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
\r
1565 #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
\r
1567 /****************** Bit definition for ADC_JOFR1 register *******************/
\r
1568 #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 1 */
\r
1570 /****************** Bit definition for ADC_JOFR2 register *******************/
\r
1571 #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 2 */
\r
1573 /****************** Bit definition for ADC_JOFR3 register *******************/
\r
1574 #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 3 */
\r
1576 /****************** Bit definition for ADC_JOFR4 register *******************/
\r
1577 #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 4 */
\r
1579 /******************* Bit definition for ADC_HTR register ********************/
\r
1580 #define ADC_HTR_HT ((uint32_t)0x0FFF) /*!<Analog watchdog high threshold */
\r
1582 /******************* Bit definition for ADC_LTR register ********************/
\r
1583 #define ADC_LTR_LT ((uint32_t)0x0FFF) /*!<Analog watchdog low threshold */
\r
1585 /******************* Bit definition for ADC_SQR1 register *******************/
\r
1586 #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
\r
1587 #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
1588 #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
1589 #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
1590 #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
1591 #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
\r
1592 #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
\r
1593 #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
\r
1594 #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
\r
1595 #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
\r
1596 #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
\r
1597 #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
\r
1598 #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
\r
1599 #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
\r
1600 #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
\r
1601 #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
\r
1602 #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
\r
1603 #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
\r
1604 #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
\r
1605 #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
\r
1606 #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
\r
1607 #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
\r
1608 #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
\r
1609 #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
\r
1610 #define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
\r
1611 #define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
\r
1612 #define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
\r
1613 #define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
\r
1614 #define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
\r
1616 /******************* Bit definition for ADC_SQR2 register *******************/
\r
1617 #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
\r
1618 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
1619 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
1620 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
1621 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
1622 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
\r
1623 #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
\r
1624 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
\r
1625 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
\r
1626 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
\r
1627 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
\r
1628 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
\r
1629 #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
\r
1630 #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
\r
1631 #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
\r
1632 #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
\r
1633 #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
\r
1634 #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
\r
1635 #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
\r
1636 #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
\r
1637 #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
\r
1638 #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
\r
1639 #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
\r
1640 #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
\r
1641 #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
\r
1642 #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
\r
1643 #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
\r
1644 #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
\r
1645 #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
\r
1646 #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
\r
1647 #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
\r
1648 #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
\r
1649 #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
\r
1650 #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
\r
1651 #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
\r
1652 #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
\r
1654 /******************* Bit definition for ADC_SQR3 register *******************/
\r
1655 #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
\r
1656 #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
1657 #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
1658 #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
1659 #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
1660 #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
\r
1661 #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
\r
1662 #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
\r
1663 #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
\r
1664 #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
\r
1665 #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
\r
1666 #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
\r
1667 #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
\r
1668 #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
\r
1669 #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
\r
1670 #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
\r
1671 #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
\r
1672 #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
\r
1673 #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
\r
1674 #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
\r
1675 #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
\r
1676 #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
\r
1677 #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
\r
1678 #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
\r
1679 #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
\r
1680 #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
\r
1681 #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
\r
1682 #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
\r
1683 #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
\r
1684 #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
\r
1685 #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
\r
1686 #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
\r
1687 #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
\r
1688 #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
\r
1689 #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
\r
1690 #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
\r
1692 /******************* Bit definition for ADC_JSQR register *******************/
\r
1693 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
\r
1694 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
1695 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
1696 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
1697 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
1698 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
\r
1699 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
\r
1700 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
\r
1701 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
\r
1702 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
\r
1703 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
\r
1704 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
\r
1705 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
\r
1706 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
\r
1707 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
\r
1708 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
\r
1709 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
\r
1710 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
\r
1711 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
\r
1712 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
\r
1713 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
\r
1714 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
\r
1715 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
\r
1716 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
\r
1717 #define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
\r
1718 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
\r
1719 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
\r
1721 /******************* Bit definition for ADC_JDR1 register *******************/
\r
1722 #define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
\r
1724 /******************* Bit definition for ADC_JDR2 register *******************/
\r
1725 #define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
\r
1727 /******************* Bit definition for ADC_JDR3 register *******************/
\r
1728 #define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
\r
1730 /******************* Bit definition for ADC_JDR4 register *******************/
\r
1731 #define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
\r
1733 /******************** Bit definition for ADC_DR register ********************/
\r
1734 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
\r
1735 #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
\r
1737 /******************* Bit definition for ADC_CSR register ********************/
\r
1738 #define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */
\r
1739 #define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */
\r
1740 #define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */
\r
1741 #define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */
\r
1742 #define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */
\r
1743 #define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */
\r
1744 #define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */
\r
1745 #define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */
\r
1746 #define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */
\r
1747 #define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */
\r
1748 #define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */
\r
1749 #define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */
\r
1750 #define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */
\r
1751 #define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */
\r
1752 #define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */
\r
1753 #define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */
\r
1754 #define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */
\r
1755 #define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */
\r
1757 /******************* Bit definition for ADC_CCR register ********************/
\r
1758 #define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
\r
1759 #define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
1760 #define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
1761 #define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
1762 #define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
1763 #define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */
\r
1764 #define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
\r
1765 #define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */
\r
1766 #define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */
\r
1767 #define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */
\r
1768 #define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */
\r
1769 #define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */
\r
1770 #define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
\r
1771 #define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */
\r
1772 #define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */
\r
1773 #define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */
\r
1774 #define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
\r
1775 #define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
\r
1776 #define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */
\r
1777 #define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
\r
1779 /******************* Bit definition for ADC_CDR register ********************/
\r
1780 #define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */
\r
1781 #define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */
\r
1783 /******************************************************************************/
\r
1785 /* Controller Area Network */
\r
1787 /******************************************************************************/
\r
1788 /*!<CAN control and status registers */
\r
1789 /******************* Bit definition for CAN_MCR register ********************/
\r
1790 #define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */
\r
1791 #define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */
\r
1792 #define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */
\r
1793 #define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */
\r
1794 #define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */
\r
1795 #define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */
\r
1796 #define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */
\r
1797 #define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */
\r
1798 #define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */
\r
1800 /******************* Bit definition for CAN_MSR register ********************/
\r
1801 #define CAN_MSR_INAK ((uint32_t)0x00000001) /*!<Initialization Acknowledge */
\r
1802 #define CAN_MSR_SLAK ((uint32_t)0x00000002) /*!<Sleep Acknowledge */
\r
1803 #define CAN_MSR_ERRI ((uint32_t)0x00000004) /*!<Error Interrupt */
\r
1804 #define CAN_MSR_WKUI ((uint32_t)0x00000008) /*!<Wakeup Interrupt */
\r
1805 #define CAN_MSR_SLAKI ((uint32_t)0x00000010) /*!<Sleep Acknowledge Interrupt */
\r
1806 #define CAN_MSR_TXM ((uint32_t)0x00000100) /*!<Transmit Mode */
\r
1807 #define CAN_MSR_RXM ((uint32_t)0x00000200) /*!<Receive Mode */
\r
1808 #define CAN_MSR_SAMP ((uint32_t)0x00000400) /*!<Last Sample Point */
\r
1809 #define CAN_MSR_RX ((uint32_t)0x00000800) /*!<CAN Rx Signal */
\r
1811 /******************* Bit definition for CAN_TSR register ********************/
\r
1812 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
\r
1813 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
\r
1814 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
\r
1815 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
\r
1816 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
\r
1817 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
\r
1818 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
\r
1819 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
\r
1820 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
\r
1821 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
\r
1822 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
\r
1823 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
\r
1824 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
\r
1825 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
\r
1826 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
\r
1827 #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
\r
1829 #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
\r
1830 #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
\r
1831 #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
\r
1832 #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
\r
1834 #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
\r
1835 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
\r
1836 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
\r
1837 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
\r
1839 /******************* Bit definition for CAN_RF0R register *******************/
\r
1840 #define CAN_RF0R_FMP0 ((uint32_t)0x00000003) /*!<FIFO 0 Message Pending */
\r
1841 #define CAN_RF0R_FULL0 ((uint32_t)0x00000008) /*!<FIFO 0 Full */
\r
1842 #define CAN_RF0R_FOVR0 ((uint32_t)0x00000010) /*!<FIFO 0 Overrun */
\r
1843 #define CAN_RF0R_RFOM0 ((uint32_t)0x00000020) /*!<Release FIFO 0 Output Mailbox */
\r
1845 /******************* Bit definition for CAN_RF1R register *******************/
\r
1846 #define CAN_RF1R_FMP1 ((uint32_t)0x00000003) /*!<FIFO 1 Message Pending */
\r
1847 #define CAN_RF1R_FULL1 ((uint32_t)0x00000008) /*!<FIFO 1 Full */
\r
1848 #define CAN_RF1R_FOVR1 ((uint32_t)0x00000010) /*!<FIFO 1 Overrun */
\r
1849 #define CAN_RF1R_RFOM1 ((uint32_t)0x00000020) /*!<Release FIFO 1 Output Mailbox */
\r
1851 /******************** Bit definition for CAN_IER register *******************/
\r
1852 #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
\r
1853 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
\r
1854 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
\r
1855 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
\r
1856 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
\r
1857 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
\r
1858 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
\r
1859 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
\r
1860 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
\r
1861 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
\r
1862 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
\r
1863 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
\r
1864 #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
\r
1865 #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
\r
1867 /******************** Bit definition for CAN_ESR register *******************/
\r
1868 #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
\r
1869 #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
\r
1870 #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
\r
1872 #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
\r
1873 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
\r
1874 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
\r
1875 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
\r
1877 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
\r
1878 #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
\r
1880 /******************* Bit definition for CAN_BTR register ********************/
\r
1881 #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
\r
1882 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
\r
1883 #define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Bit 0 */
\r
1884 #define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Bit 1 */
\r
1885 #define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Bit 2 */
\r
1886 #define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Bit 3 */
\r
1887 #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
\r
1888 #define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */
\r
1889 #define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */
\r
1890 #define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */
\r
1891 #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
\r
1892 #define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Bit 0 */
\r
1893 #define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Bit 1 */
\r
1894 #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
\r
1895 #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
\r
1897 /*!<Mailbox registers */
\r
1898 /****************** Bit definition for CAN_TI0R register ********************/
\r
1899 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
\r
1900 #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
\r
1901 #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
\r
1902 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
\r
1903 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
\r
1905 /****************** Bit definition for CAN_TDT0R register *******************/
\r
1906 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
\r
1907 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
\r
1908 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
\r
1910 /****************** Bit definition for CAN_TDL0R register *******************/
\r
1911 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
\r
1912 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
\r
1913 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
\r
1914 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
\r
1916 /****************** Bit definition for CAN_TDH0R register *******************/
\r
1917 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
\r
1918 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
\r
1919 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
\r
1920 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
\r
1922 /******************* Bit definition for CAN_TI1R register *******************/
\r
1923 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
\r
1924 #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
\r
1925 #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
\r
1926 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
\r
1927 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
\r
1929 /******************* Bit definition for CAN_TDT1R register ******************/
\r
1930 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
\r
1931 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
\r
1932 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
\r
1934 /******************* Bit definition for CAN_TDL1R register ******************/
\r
1935 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
\r
1936 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
\r
1937 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
\r
1938 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
\r
1940 /******************* Bit definition for CAN_TDH1R register ******************/
\r
1941 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
\r
1942 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
\r
1943 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
\r
1944 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
\r
1946 /******************* Bit definition for CAN_TI2R register *******************/
\r
1947 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
\r
1948 #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
\r
1949 #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
\r
1950 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
\r
1951 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
\r
1953 /******************* Bit definition for CAN_TDT2R register ******************/
\r
1954 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
\r
1955 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
\r
1956 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
\r
1958 /******************* Bit definition for CAN_TDL2R register ******************/
\r
1959 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
\r
1960 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
\r
1961 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
\r
1962 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
\r
1964 /******************* Bit definition for CAN_TDH2R register ******************/
\r
1965 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
\r
1966 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
\r
1967 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
\r
1968 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
\r
1970 /******************* Bit definition for CAN_RI0R register *******************/
\r
1971 #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
\r
1972 #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
\r
1973 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
\r
1974 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
\r
1976 /******************* Bit definition for CAN_RDT0R register ******************/
\r
1977 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
\r
1978 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
\r
1979 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
\r
1981 /******************* Bit definition for CAN_RDL0R register ******************/
\r
1982 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
\r
1983 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
\r
1984 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
\r
1985 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
\r
1987 /******************* Bit definition for CAN_RDH0R register ******************/
\r
1988 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
\r
1989 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
\r
1990 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
\r
1991 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
\r
1993 /******************* Bit definition for CAN_RI1R register *******************/
\r
1994 #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
\r
1995 #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
\r
1996 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
\r
1997 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
\r
1999 /******************* Bit definition for CAN_RDT1R register ******************/
\r
2000 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
\r
2001 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
\r
2002 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
\r
2004 /******************* Bit definition for CAN_RDL1R register ******************/
\r
2005 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
\r
2006 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
\r
2007 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
\r
2008 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
\r
2010 /******************* Bit definition for CAN_RDH1R register ******************/
\r
2011 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
\r
2012 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
\r
2013 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
\r
2014 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
\r
2016 /*!<CAN filter registers */
\r
2017 /******************* Bit definition for CAN_FMR register ********************/
\r
2018 #define CAN_FMR_FINIT ((uint8_t)0x01) /*!<Filter Init Mode */
\r
2019 #define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */
\r
2021 /******************* Bit definition for CAN_FM1R register *******************/
\r
2022 #define CAN_FM1R_FBM ((uint32_t)0x3FFF) /*!<Filter Mode */
\r
2023 #define CAN_FM1R_FBM0 ((uint32_t)0x0001) /*!<Filter Init Mode bit 0 */
\r
2024 #define CAN_FM1R_FBM1 ((uint32_t)0x0002) /*!<Filter Init Mode bit 1 */
\r
2025 #define CAN_FM1R_FBM2 ((uint32_t)0x0004) /*!<Filter Init Mode bit 2 */
\r
2026 #define CAN_FM1R_FBM3 ((uint32_t)0x0008) /*!<Filter Init Mode bit 3 */
\r
2027 #define CAN_FM1R_FBM4 ((uint32_t)0x0010) /*!<Filter Init Mode bit 4 */
\r
2028 #define CAN_FM1R_FBM5 ((uint32_t)0x0020) /*!<Filter Init Mode bit 5 */
\r
2029 #define CAN_FM1R_FBM6 ((uint32_t)0x0040) /*!<Filter Init Mode bit 6 */
\r
2030 #define CAN_FM1R_FBM7 ((uint32_t)0x0080) /*!<Filter Init Mode bit 7 */
\r
2031 #define CAN_FM1R_FBM8 ((uint32_t)0x0100) /*!<Filter Init Mode bit 8 */
\r
2032 #define CAN_FM1R_FBM9 ((uint32_t)0x0200) /*!<Filter Init Mode bit 9 */
\r
2033 #define CAN_FM1R_FBM10 ((uint32_t)0x0400) /*!<Filter Init Mode bit 10 */
\r
2034 #define CAN_FM1R_FBM11 ((uint32_t)0x0800) /*!<Filter Init Mode bit 11 */
\r
2035 #define CAN_FM1R_FBM12 ((uint32_t)0x1000) /*!<Filter Init Mode bit 12 */
\r
2036 #define CAN_FM1R_FBM13 ((uint32_t)0x2000) /*!<Filter Init Mode bit 13 */
\r
2038 /******************* Bit definition for CAN_FS1R register *******************/
\r
2039 #define CAN_FS1R_FSC ((uint32_t)0x00003FFF) /*!<Filter Scale Configuration */
\r
2040 #define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
\r
2041 #define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
\r
2042 #define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
\r
2043 #define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */
\r
2044 #define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */
\r
2045 #define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */
\r
2046 #define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */
\r
2047 #define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */
\r
2048 #define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */
\r
2049 #define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */
\r
2050 #define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */
\r
2051 #define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
\r
2052 #define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
\r
2053 #define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
\r
2055 /****************** Bit definition for CAN_FFA1R register *******************/
\r
2056 #define CAN_FFA1R_FFA ((uint32_t)0x00003FFF) /*!<Filter FIFO Assignment */
\r
2057 #define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment for Filter 0 */
\r
2058 #define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment for Filter 1 */
\r
2059 #define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment for Filter 2 */
\r
2060 #define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment for Filter 3 */
\r
2061 #define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment for Filter 4 */
\r
2062 #define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment for Filter 5 */
\r
2063 #define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment for Filter 6 */
\r
2064 #define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment for Filter 7 */
\r
2065 #define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment for Filter 8 */
\r
2066 #define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment for Filter 9 */
\r
2067 #define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment for Filter 10 */
\r
2068 #define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment for Filter 11 */
\r
2069 #define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment for Filter 12 */
\r
2070 #define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment for Filter 13 */
\r
2072 /******************* Bit definition for CAN_FA1R register *******************/
\r
2073 #define CAN_FA1R_FACT ((uint32_t)0x00003FFF) /*!<Filter Active */
\r
2074 #define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter 0 Active */
\r
2075 #define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter 1 Active */
\r
2076 #define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter 2 Active */
\r
2077 #define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter 3 Active */
\r
2078 #define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter 4 Active */
\r
2079 #define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter 5 Active */
\r
2080 #define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter 6 Active */
\r
2081 #define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter 7 Active */
\r
2082 #define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter 8 Active */
\r
2083 #define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter 9 Active */
\r
2084 #define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter 10 Active */
\r
2085 #define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter 11 Active */
\r
2086 #define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter 12 Active */
\r
2087 #define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter 13 Active */
\r
2089 /******************* Bit definition for CAN_F0R1 register *******************/
\r
2090 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2091 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2092 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2093 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2094 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2095 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2096 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2097 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2098 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2099 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2100 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2101 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2102 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2103 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2104 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2105 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2106 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2107 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2108 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2109 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2110 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2111 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2112 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2113 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2114 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2115 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2116 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2117 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2118 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2119 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2120 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2121 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2123 /******************* Bit definition for CAN_F1R1 register *******************/
\r
2124 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2125 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2126 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2127 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2128 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2129 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2130 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2131 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2132 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2133 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2134 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2135 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2136 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2137 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2138 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2139 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2140 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2141 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2142 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2143 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2144 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2145 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2146 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2147 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2148 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2149 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2150 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2151 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2152 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2153 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2154 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2155 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2157 /******************* Bit definition for CAN_F2R1 register *******************/
\r
2158 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2159 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2160 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2161 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2162 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2163 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2164 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2165 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2166 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2167 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2168 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2169 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2170 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2171 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2172 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2173 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2174 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2175 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2176 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2177 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2178 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2179 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2180 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2181 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2182 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2183 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2184 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2185 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2186 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2187 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2188 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2189 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2191 /******************* Bit definition for CAN_F3R1 register *******************/
\r
2192 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2193 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2194 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2195 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2196 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2197 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2198 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2199 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2200 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2201 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2202 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2203 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2204 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2205 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2206 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2207 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2208 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2209 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2210 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2211 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2212 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2213 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2214 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2215 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2216 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2217 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2218 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2219 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2220 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2221 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2222 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2223 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2225 /******************* Bit definition for CAN_F4R1 register *******************/
\r
2226 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2227 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2228 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2229 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2230 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2231 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2232 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2233 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2234 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2235 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2236 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2237 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2238 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2239 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2240 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2241 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2242 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2243 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2244 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2245 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2246 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2247 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2248 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2249 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2250 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2251 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2252 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2253 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2254 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2255 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2256 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2257 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2259 /******************* Bit definition for CAN_F5R1 register *******************/
\r
2260 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2261 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2262 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2263 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2264 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2265 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2266 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2267 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2268 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2269 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2270 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2271 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2272 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2273 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2274 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2275 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2276 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2277 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2278 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2279 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2280 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2281 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2282 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2283 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2284 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2285 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2286 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2287 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2288 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2289 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2290 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2291 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2293 /******************* Bit definition for CAN_F6R1 register *******************/
\r
2294 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2295 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2296 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2297 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2298 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2299 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2300 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2301 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2302 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2303 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2304 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2305 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2306 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2307 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2308 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2309 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2310 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2311 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2312 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2313 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2314 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2315 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2316 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2317 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2318 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2319 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2320 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2321 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2322 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2323 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2324 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2325 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2327 /******************* Bit definition for CAN_F7R1 register *******************/
\r
2328 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2329 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2330 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2331 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2332 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2333 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2334 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2335 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2336 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2337 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2338 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2339 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2340 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2341 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2342 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2343 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2344 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2345 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2346 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2347 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2348 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2349 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2350 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2351 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2352 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2353 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2354 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2355 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2356 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2357 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2358 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2359 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2361 /******************* Bit definition for CAN_F8R1 register *******************/
\r
2362 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2363 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2364 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2365 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2366 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2367 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2368 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2369 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2370 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2371 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2372 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2373 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2374 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2375 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2376 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2377 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2378 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2379 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2380 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2381 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2382 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2383 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2384 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2385 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2386 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2387 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2388 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2389 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2390 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2391 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2392 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2393 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2395 /******************* Bit definition for CAN_F9R1 register *******************/
\r
2396 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2397 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2398 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2399 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2400 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2401 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2402 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2403 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2404 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2405 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2406 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2407 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2408 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2409 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2410 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2411 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2412 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2413 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2414 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2415 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2416 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2417 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2418 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2419 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2420 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2421 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2422 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2423 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2424 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2425 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2426 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2427 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2429 /******************* Bit definition for CAN_F10R1 register ******************/
\r
2430 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2431 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2432 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2433 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2434 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2435 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2436 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2437 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2438 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2439 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2440 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2441 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2442 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2443 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2444 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2445 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2446 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2447 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2448 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2449 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2450 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2451 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2452 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2453 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2454 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2455 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2456 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2457 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2458 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2459 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2460 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2461 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2463 /******************* Bit definition for CAN_F11R1 register ******************/
\r
2464 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2465 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2466 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2467 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2468 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2469 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2470 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2471 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2472 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2473 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2474 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2475 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2476 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2477 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2478 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2479 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2480 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2481 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2482 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2483 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2484 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2485 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2486 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2487 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2488 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2489 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2490 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2491 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2492 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2493 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2494 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2495 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2497 /******************* Bit definition for CAN_F12R1 register ******************/
\r
2498 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2499 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2500 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2501 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2502 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2503 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2504 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2505 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2506 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2507 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2508 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2509 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2510 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2511 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2512 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2513 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2514 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2515 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2516 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2517 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2518 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2519 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2520 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2521 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2522 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2523 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2524 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2525 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2526 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2527 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2528 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2529 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2531 /******************* Bit definition for CAN_F13R1 register ******************/
\r
2532 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2533 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2534 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2535 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2536 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2537 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2538 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2539 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2540 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2541 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2542 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2543 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2544 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2545 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2546 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2547 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2548 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2549 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2550 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2551 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2552 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2553 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2554 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2555 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2556 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2557 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2558 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2559 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2560 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2561 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2562 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2563 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2565 /******************* Bit definition for CAN_F0R2 register *******************/
\r
2566 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2567 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2568 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2569 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2570 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2571 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2572 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2573 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2574 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2575 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2576 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2577 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2578 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2579 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2580 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2581 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2582 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2583 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2584 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2585 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2586 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2587 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2588 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2589 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2590 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2591 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2592 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2593 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2594 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2595 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2596 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2597 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2599 /******************* Bit definition for CAN_F1R2 register *******************/
\r
2600 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2601 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2602 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2603 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2604 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2605 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2606 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2607 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2608 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2609 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2610 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2611 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2612 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2613 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2614 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2615 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2616 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2617 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2618 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2619 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2620 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2621 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2622 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2623 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2624 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2625 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2626 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2627 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2628 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2629 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2630 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2631 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2633 /******************* Bit definition for CAN_F2R2 register *******************/
\r
2634 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2635 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2636 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2637 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2638 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2639 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2640 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2641 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2642 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2643 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2644 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2645 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2646 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2647 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2648 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2649 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2650 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2651 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2652 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2653 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2654 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2655 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2656 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2657 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2658 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2659 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2660 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2661 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2662 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2663 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2664 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2665 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2667 /******************* Bit definition for CAN_F3R2 register *******************/
\r
2668 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2669 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2670 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2671 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2672 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2673 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2674 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2675 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2676 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2677 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2678 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2679 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2680 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2681 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2682 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2683 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2684 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2685 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2686 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2687 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2688 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2689 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2690 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2691 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2692 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2693 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2694 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2695 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2696 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2697 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2698 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2699 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2701 /******************* Bit definition for CAN_F4R2 register *******************/
\r
2702 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2703 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2704 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2705 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2706 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2707 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2708 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2709 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2710 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2711 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2712 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2713 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2714 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2715 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2716 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2717 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2718 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2719 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2720 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2721 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2722 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2723 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2724 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2725 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2726 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2727 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2728 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2729 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2730 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2731 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2732 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2733 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2735 /******************* Bit definition for CAN_F5R2 register *******************/
\r
2736 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2737 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2738 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2739 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2740 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2741 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2742 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2743 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2744 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2745 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2746 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2747 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2748 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2749 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2750 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2751 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2752 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2753 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2754 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2755 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2756 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2757 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2758 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2759 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2760 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2761 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2762 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2763 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2764 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2765 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2766 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2767 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2769 /******************* Bit definition for CAN_F6R2 register *******************/
\r
2770 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2771 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2772 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2773 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2774 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2775 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2776 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2777 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2778 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2779 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2780 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2781 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2782 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2783 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2784 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2785 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2786 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2787 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2788 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2789 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2790 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2791 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2792 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2793 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2794 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2795 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2796 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2797 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2798 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2799 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2800 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2801 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2803 /******************* Bit definition for CAN_F7R2 register *******************/
\r
2804 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2805 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2806 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2807 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2808 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2809 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2810 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2811 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2812 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2813 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2814 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2815 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2816 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2817 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2818 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2819 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2820 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2821 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2822 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2823 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2824 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2825 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2826 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2827 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2828 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2829 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2830 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2831 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2832 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2833 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2834 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2835 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2837 /******************* Bit definition for CAN_F8R2 register *******************/
\r
2838 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2839 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2840 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2841 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2842 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2843 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2844 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2845 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2846 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2847 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2848 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2849 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2850 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2851 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2852 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2853 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2854 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2855 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2856 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2857 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2858 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2859 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2860 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2861 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2862 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2863 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2864 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2865 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2866 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2867 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2868 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2869 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2871 /******************* Bit definition for CAN_F9R2 register *******************/
\r
2872 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2873 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2874 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2875 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2876 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2877 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2878 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2879 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2880 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2881 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2882 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2883 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2884 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2885 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2886 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2887 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2888 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2889 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2890 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2891 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2892 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2893 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2894 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2895 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2896 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2897 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2898 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2899 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2900 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2901 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2902 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2903 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2905 /******************* Bit definition for CAN_F10R2 register ******************/
\r
2906 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2907 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2908 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2909 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2910 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2911 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2912 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2913 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2914 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2915 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2916 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2917 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2918 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2919 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2920 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2921 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2922 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2923 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2924 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2925 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2926 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2927 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2928 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2929 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2930 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2931 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2932 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2933 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2934 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2935 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2936 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2937 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2939 /******************* Bit definition for CAN_F11R2 register ******************/
\r
2940 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2941 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2942 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2943 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2944 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2945 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2946 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2947 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2948 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2949 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2950 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2951 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2952 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2953 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2954 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2955 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2956 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2957 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2958 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2959 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2960 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2961 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2962 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2963 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2964 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2965 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
2966 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
2967 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
2968 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
2969 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
2970 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
2971 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
2973 /******************* Bit definition for CAN_F12R2 register ******************/
\r
2974 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
2975 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
2976 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
2977 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
2978 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
2979 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
2980 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
2981 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
2982 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
2983 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
2984 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
2985 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
2986 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
2987 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
2988 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
2989 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
2990 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
2991 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
2992 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
2993 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
2994 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
2995 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
2996 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
2997 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
2998 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
2999 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
3000 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
3001 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
3002 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
3003 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
3004 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
3005 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
3007 /******************* Bit definition for CAN_F13R2 register ******************/
\r
3008 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
\r
3009 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
\r
3010 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
\r
3011 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
\r
3012 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
\r
3013 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
\r
3014 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
\r
3015 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
\r
3016 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
\r
3017 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
\r
3018 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
\r
3019 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
\r
3020 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
\r
3021 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
\r
3022 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
\r
3023 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
\r
3024 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
\r
3025 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
\r
3026 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
\r
3027 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
\r
3028 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
\r
3029 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
\r
3030 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
\r
3031 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
\r
3032 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
\r
3033 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
\r
3034 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
\r
3035 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
\r
3036 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
\r
3037 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
\r
3038 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
\r
3039 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
\r
3041 /******************************************************************************/
\r
3043 /* HDMI-CEC (CEC) */
\r
3045 /******************************************************************************/
\r
3047 /******************* Bit definition for CEC_CR register *********************/
\r
3048 #define CEC_CR_CECEN ((uint32_t)0x00000001) /*!< CEC Enable */
\r
3049 #define CEC_CR_TXSOM ((uint32_t)0x00000002) /*!< CEC Tx Start Of Message */
\r
3050 #define CEC_CR_TXEOM ((uint32_t)0x00000004) /*!< CEC Tx End Of Message */
\r
3052 /******************* Bit definition for CEC_CFGR register *******************/
\r
3053 #define CEC_CFGR_SFT ((uint32_t)0x00000007) /*!< CEC Signal Free Time */
\r
3054 #define CEC_CFGR_RXTOL ((uint32_t)0x00000008) /*!< CEC Tolerance */
\r
3055 #define CEC_CFGR_BRESTP ((uint32_t)0x00000010) /*!< CEC Rx Stop */
\r
3056 #define CEC_CFGR_BREGEN ((uint32_t)0x00000020) /*!< CEC Bit Rising Error generation */
\r
3057 #define CEC_CFGR_LBPEGEN ((uint32_t)0x00000040) /*!< CEC Long Period Error generation */
\r
3058 #define CEC_CFGR_BRDNOGEN ((uint32_t)0x00000080) /*!< CEC Broadcast no Error generation */
\r
3059 #define CEC_CFGR_SFTOPT ((uint32_t)0x00000100) /*!< CEC Signal Free Time optional */
\r
3060 #define CEC_CFGR_OAR ((uint32_t)0x7FFF0000) /*!< CEC Own Address */
\r
3061 #define CEC_CFGR_LSTN ((uint32_t)0x80000000) /*!< CEC Listen mode */
\r
3063 /******************* Bit definition for CEC_TXDR register *******************/
\r
3064 #define CEC_TXDR_TXD ((uint32_t)0x000000FF) /*!< CEC Tx Data */
\r
3066 /******************* Bit definition for CEC_RXDR register *******************/
\r
3067 #define CEC_TXDR_RXD ((uint32_t)0x000000FF) /*!< CEC Rx Data */
\r
3069 /******************* Bit definition for CEC_ISR register ********************/
\r
3070 #define CEC_ISR_RXBR ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received */
\r
3071 #define CEC_ISR_RXEND ((uint32_t)0x00000002) /*!< CEC End Of Reception */
\r
3072 #define CEC_ISR_RXOVR ((uint32_t)0x00000004) /*!< CEC Rx-Overrun */
\r
3073 #define CEC_ISR_BRE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error */
\r
3074 #define CEC_ISR_SBPE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error */
\r
3075 #define CEC_ISR_LBPE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error */
\r
3076 #define CEC_ISR_RXACKE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge */
\r
3077 #define CEC_ISR_ARBLST ((uint32_t)0x00000080) /*!< CEC Arbitration Lost */
\r
3078 #define CEC_ISR_TXBR ((uint32_t)0x00000100) /*!< CEC Tx Byte Request */
\r
3079 #define CEC_ISR_TXEND ((uint32_t)0x00000200) /*!< CEC End of Transmission */
\r
3080 #define CEC_ISR_TXUDR ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun */
\r
3081 #define CEC_ISR_TXERR ((uint32_t)0x00000800) /*!< CEC Tx-Error */
\r
3082 #define CEC_ISR_TXACKE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge */
\r
3084 /******************* Bit definition for CEC_IER register ********************/
\r
3085 #define CEC_IER_RXBRIE ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received IT Enable */
\r
3086 #define CEC_IER_RXENDIE ((uint32_t)0x00000002) /*!< CEC End Of Reception IT Enable */
\r
3087 #define CEC_IER_RXOVRIE ((uint32_t)0x00000004) /*!< CEC Rx-Overrun IT Enable */
\r
3088 #define CEC_IER_BREIE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error IT Enable */
\r
3089 #define CEC_IER_SBPEIE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error IT Enable*/
\r
3090 #define CEC_IER_LBPEIE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error IT Enable */
\r
3091 #define CEC_IER_RXACKEIE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge IT Enable */
\r
3092 #define CEC_IER_ARBLSTIE ((uint32_t)0x00000080) /*!< CEC Arbitration Lost IT Enable */
\r
3093 #define CEC_IER_TXBRIE ((uint32_t)0x00000100) /*!< CEC Tx Byte Request IT Enable */
\r
3094 #define CEC_IER_TXENDIE ((uint32_t)0x00000200) /*!< CEC End of Transmission IT Enable */
\r
3095 #define CEC_IER_TXUDRIE ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun IT Enable */
\r
3096 #define CEC_IER_TXERRIE ((uint32_t)0x00000800) /*!< CEC Tx-Error IT Enable */
\r
3097 #define CEC_IER_TXACKEIE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge IT Enable */
\r
3099 /******************************************************************************/
\r
3101 /* CRC calculation unit */
\r
3103 /******************************************************************************/
\r
3104 /******************* Bit definition for CRC_DR register *********************/
\r
3105 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
\r
3107 /******************* Bit definition for CRC_IDR register ********************/
\r
3108 #define CRC_IDR_IDR ((uint32_t)0x000000FF) /*!< General-purpose 8-bit data register bits */
\r
3110 /******************** Bit definition for CRC_CR register ********************/
\r
3111 #define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
\r
3112 #define CRC_CR_POLYSIZE ((uint32_t)0x00000018) /*!< Polynomial size bits */
\r
3113 #define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */
\r
3114 #define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */
\r
3115 #define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
\r
3116 #define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< Bit 0 */
\r
3117 #define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< Bit 1 */
\r
3118 #define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
\r
3120 /******************* Bit definition for CRC_INIT register *******************/
\r
3121 #define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
\r
3123 /******************* Bit definition for CRC_POL register ********************/
\r
3124 #define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */
\r
3126 /******************************************************************************/
\r
3128 /* Digital to Analog Converter */
\r
3130 /******************************************************************************/
\r
3131 /******************** Bit definition for DAC_CR register ********************/
\r
3132 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
\r
3133 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
\r
3134 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
\r
3136 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
\r
3137 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
\r
3138 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
\r
3139 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
\r
3141 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
\r
3142 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
\r
3143 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
\r
3145 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
\r
3146 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
\r
3147 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
\r
3148 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
\r
3149 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
\r
3151 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
\r
3152 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
\r
3153 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
\r
3154 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
\r
3156 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
\r
3157 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
\r
3158 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
\r
3159 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
\r
3161 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
\r
3162 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
\r
3163 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
\r
3165 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
\r
3166 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
\r
3167 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
\r
3168 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
\r
3169 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
\r
3171 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
\r
3173 /***************** Bit definition for DAC_SWTRIGR register ******************/
\r
3174 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x01) /*!<DAC channel1 software trigger */
\r
3175 #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x02) /*!<DAC channel2 software trigger */
\r
3177 /***************** Bit definition for DAC_DHR12R1 register ******************/
\r
3178 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
\r
3180 /***************** Bit definition for DAC_DHR12L1 register ******************/
\r
3181 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
\r
3183 /****************** Bit definition for DAC_DHR8R1 register ******************/
\r
3184 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
\r
3186 /***************** Bit definition for DAC_DHR12R2 register ******************/
\r
3187 #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
\r
3189 /***************** Bit definition for DAC_DHR12L2 register ******************/
\r
3190 #define DAC_DHR12L2_DACC2DHR ((uint32_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
\r
3192 /****************** Bit definition for DAC_DHR8R2 register ******************/
\r
3193 #define DAC_DHR8R2_DACC2DHR ((uint32_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
\r
3195 /***************** Bit definition for DAC_DHR12RD register ******************/
\r
3196 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
\r
3197 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
\r
3199 /***************** Bit definition for DAC_DHR12LD register ******************/
\r
3200 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
\r
3201 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
\r
3203 /****************** Bit definition for DAC_DHR8RD register ******************/
\r
3204 #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */
\r
3205 #define DAC_DHR8RD_DACC2DHR ((uint32_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */
\r
3207 /******************* Bit definition for DAC_DOR1 register *******************/
\r
3208 #define DAC_DOR1_DACC1DOR ((uint32_t)0x0FFF) /*!<DAC channel1 data output */
\r
3210 /******************* Bit definition for DAC_DOR2 register *******************/
\r
3211 #define DAC_DOR2_DACC2DOR ((uint32_t)0x0FFF) /*!<DAC channel2 data output */
\r
3213 /******************** Bit definition for DAC_SR register ********************/
\r
3214 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
\r
3215 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
\r
3217 /******************************************************************************/
\r
3221 /******************************************************************************/
\r
3223 /******************************************************************************/
\r
3227 /******************************************************************************/
\r
3228 /******************** Bits definition for DCMI_CR register ******************/
\r
3229 #define DCMI_CR_CAPTURE ((uint32_t)0x00000001)
\r
3230 #define DCMI_CR_CM ((uint32_t)0x00000002)
\r
3231 #define DCMI_CR_CROP ((uint32_t)0x00000004)
\r
3232 #define DCMI_CR_JPEG ((uint32_t)0x00000008)
\r
3233 #define DCMI_CR_ESS ((uint32_t)0x00000010)
\r
3234 #define DCMI_CR_PCKPOL ((uint32_t)0x00000020)
\r
3235 #define DCMI_CR_HSPOL ((uint32_t)0x00000040)
\r
3236 #define DCMI_CR_VSPOL ((uint32_t)0x00000080)
\r
3237 #define DCMI_CR_FCRC_0 ((uint32_t)0x00000100)
\r
3238 #define DCMI_CR_FCRC_1 ((uint32_t)0x00000200)
\r
3239 #define DCMI_CR_EDM_0 ((uint32_t)0x00000400)
\r
3240 #define DCMI_CR_EDM_1 ((uint32_t)0x00000800)
\r
3241 #define DCMI_CR_CRE ((uint32_t)0x00001000)
\r
3242 #define DCMI_CR_ENABLE ((uint32_t)0x00004000)
\r
3243 #define DCMI_CR_BSM ((uint32_t)0x00030000)
\r
3244 #define DCMI_CR_BSM_0 ((uint32_t)0x00010000)
\r
3245 #define DCMI_CR_BSM_1 ((uint32_t)0x00020000)
\r
3246 #define DCMI_CR_OEBS ((uint32_t)0x00040000)
\r
3247 #define DCMI_CR_LSM ((uint32_t)0x00080000)
\r
3248 #define DCMI_CR_OELS ((uint32_t)0x00100000)
\r
3250 /******************** Bits definition for DCMI_SR register ******************/
\r
3251 #define DCMI_SR_HSYNC ((uint32_t)0x00000001)
\r
3252 #define DCMI_SR_VSYNC ((uint32_t)0x00000002)
\r
3253 #define DCMI_SR_FNE ((uint32_t)0x00000004)
\r
3255 /******************** Bits definition for DCMI_RISR register ****************/
\r
3256 #define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001)
\r
3257 #define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002)
\r
3258 #define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004)
\r
3259 #define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008)
\r
3260 #define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010)
\r
3262 /******************** Bits definition for DCMI_IER register *****************/
\r
3263 #define DCMI_IER_FRAME_IE ((uint32_t)0x00000001)
\r
3264 #define DCMI_IER_OVF_IE ((uint32_t)0x00000002)
\r
3265 #define DCMI_IER_ERR_IE ((uint32_t)0x00000004)
\r
3266 #define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008)
\r
3267 #define DCMI_IER_LINE_IE ((uint32_t)0x00000010)
\r
3269 /******************** Bits definition for DCMI_MISR register ****************/
\r
3270 #define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001)
\r
3271 #define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002)
\r
3272 #define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004)
\r
3273 #define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008)
\r
3274 #define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010)
\r
3276 /******************** Bits definition for DCMI_ICR register *****************/
\r
3277 #define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001)
\r
3278 #define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002)
\r
3279 #define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004)
\r
3280 #define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008)
\r
3281 #define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010)
\r
3283 /******************************************************************************/
\r
3285 /* DMA Controller */
\r
3287 /******************************************************************************/
\r
3288 /******************** Bits definition for DMA_SxCR register *****************/
\r
3289 #define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
\r
3290 #define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
\r
3291 #define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
\r
3292 #define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
\r
3293 #define DMA_SxCR_MBURST ((uint32_t)0x01800000)
\r
3294 #define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
\r
3295 #define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
\r
3296 #define DMA_SxCR_PBURST ((uint32_t)0x00600000)
\r
3297 #define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
\r
3298 #define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
\r
3299 #define DMA_SxCR_ACK ((uint32_t)0x00100000)
\r
3300 #define DMA_SxCR_CT ((uint32_t)0x00080000)
\r
3301 #define DMA_SxCR_DBM ((uint32_t)0x00040000)
\r
3302 #define DMA_SxCR_PL ((uint32_t)0x00030000)
\r
3303 #define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
\r
3304 #define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
\r
3305 #define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
\r
3306 #define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
\r
3307 #define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
\r
3308 #define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
\r
3309 #define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
\r
3310 #define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
\r
3311 #define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
\r
3312 #define DMA_SxCR_MINC ((uint32_t)0x00000400)
\r
3313 #define DMA_SxCR_PINC ((uint32_t)0x00000200)
\r
3314 #define DMA_SxCR_CIRC ((uint32_t)0x00000100)
\r
3315 #define DMA_SxCR_DIR ((uint32_t)0x000000C0)
\r
3316 #define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
\r
3317 #define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
\r
3318 #define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
\r
3319 #define DMA_SxCR_TCIE ((uint32_t)0x00000010)
\r
3320 #define DMA_SxCR_HTIE ((uint32_t)0x00000008)
\r
3321 #define DMA_SxCR_TEIE ((uint32_t)0x00000004)
\r
3322 #define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
\r
3323 #define DMA_SxCR_EN ((uint32_t)0x00000001)
\r
3325 /******************** Bits definition for DMA_SxCNDTR register **************/
\r
3326 #define DMA_SxNDT ((uint32_t)0x0000FFFF)
\r
3327 #define DMA_SxNDT_0 ((uint32_t)0x00000001)
\r
3328 #define DMA_SxNDT_1 ((uint32_t)0x00000002)
\r
3329 #define DMA_SxNDT_2 ((uint32_t)0x00000004)
\r
3330 #define DMA_SxNDT_3 ((uint32_t)0x00000008)
\r
3331 #define DMA_SxNDT_4 ((uint32_t)0x00000010)
\r
3332 #define DMA_SxNDT_5 ((uint32_t)0x00000020)
\r
3333 #define DMA_SxNDT_6 ((uint32_t)0x00000040)
\r
3334 #define DMA_SxNDT_7 ((uint32_t)0x00000080)
\r
3335 #define DMA_SxNDT_8 ((uint32_t)0x00000100)
\r
3336 #define DMA_SxNDT_9 ((uint32_t)0x00000200)
\r
3337 #define DMA_SxNDT_10 ((uint32_t)0x00000400)
\r
3338 #define DMA_SxNDT_11 ((uint32_t)0x00000800)
\r
3339 #define DMA_SxNDT_12 ((uint32_t)0x00001000)
\r
3340 #define DMA_SxNDT_13 ((uint32_t)0x00002000)
\r
3341 #define DMA_SxNDT_14 ((uint32_t)0x00004000)
\r
3342 #define DMA_SxNDT_15 ((uint32_t)0x00008000)
\r
3344 /******************** Bits definition for DMA_SxFCR register ****************/
\r
3345 #define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
\r
3346 #define DMA_SxFCR_FS ((uint32_t)0x00000038)
\r
3347 #define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
\r
3348 #define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
\r
3349 #define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
\r
3350 #define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
\r
3351 #define DMA_SxFCR_FTH ((uint32_t)0x00000003)
\r
3352 #define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
\r
3353 #define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
\r
3355 /******************** Bits definition for DMA_LISR register *****************/
\r
3356 #define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
\r
3357 #define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
\r
3358 #define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
\r
3359 #define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
\r
3360 #define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
\r
3361 #define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
\r
3362 #define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
\r
3363 #define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
\r
3364 #define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
\r
3365 #define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
\r
3366 #define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
\r
3367 #define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
\r
3368 #define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
\r
3369 #define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
\r
3370 #define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
\r
3371 #define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
\r
3372 #define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
\r
3373 #define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
\r
3374 #define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
\r
3375 #define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
\r
3377 /******************** Bits definition for DMA_HISR register *****************/
\r
3378 #define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
\r
3379 #define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
\r
3380 #define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
\r
3381 #define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
\r
3382 #define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
\r
3383 #define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
\r
3384 #define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
\r
3385 #define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
\r
3386 #define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
\r
3387 #define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
\r
3388 #define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
\r
3389 #define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
\r
3390 #define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
\r
3391 #define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
\r
3392 #define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
\r
3393 #define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
\r
3394 #define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
\r
3395 #define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
\r
3396 #define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
\r
3397 #define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
\r
3399 /******************** Bits definition for DMA_LIFCR register ****************/
\r
3400 #define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
\r
3401 #define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
\r
3402 #define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
\r
3403 #define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
\r
3404 #define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
\r
3405 #define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
\r
3406 #define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
\r
3407 #define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
\r
3408 #define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
\r
3409 #define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
\r
3410 #define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
\r
3411 #define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
\r
3412 #define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
\r
3413 #define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
\r
3414 #define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
\r
3415 #define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
\r
3416 #define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
\r
3417 #define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
\r
3418 #define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
\r
3419 #define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
\r
3421 /******************** Bits definition for DMA_HIFCR register ****************/
\r
3422 #define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
\r
3423 #define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
\r
3424 #define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
\r
3425 #define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
\r
3426 #define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
\r
3427 #define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
\r
3428 #define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
\r
3429 #define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
\r
3430 #define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
\r
3431 #define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
\r
3432 #define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
\r
3433 #define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
\r
3434 #define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
\r
3435 #define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
\r
3436 #define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
\r
3437 #define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
\r
3438 #define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
\r
3439 #define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
\r
3440 #define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
\r
3441 #define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
\r
3443 /******************************************************************************/
\r
3445 /* AHB Master DMA2D Controller (DMA2D) */
\r
3447 /******************************************************************************/
\r
3449 /******************** Bit definition for DMA2D_CR register ******************/
\r
3451 #define DMA2D_CR_START ((uint32_t)0x00000001) /*!< Start transfer */
\r
3452 #define DMA2D_CR_SUSP ((uint32_t)0x00000002) /*!< Suspend transfer */
\r
3453 #define DMA2D_CR_ABORT ((uint32_t)0x00000004) /*!< Abort transfer */
\r
3454 #define DMA2D_CR_TEIE ((uint32_t)0x00000100) /*!< Transfer Error Interrupt Enable */
\r
3455 #define DMA2D_CR_TCIE ((uint32_t)0x00000200) /*!< Transfer Complete Interrupt Enable */
\r
3456 #define DMA2D_CR_TWIE ((uint32_t)0x00000400) /*!< Transfer Watermark Interrupt Enable */
\r
3457 #define DMA2D_CR_CAEIE ((uint32_t)0x00000800) /*!< CLUT Access Error Interrupt Enable */
\r
3458 #define DMA2D_CR_CTCIE ((uint32_t)0x00001000) /*!< CLUT Transfer Complete Interrupt Enable */
\r
3459 #define DMA2D_CR_CEIE ((uint32_t)0x00002000) /*!< Configuration Error Interrupt Enable */
\r
3460 #define DMA2D_CR_MODE ((uint32_t)0x00030000) /*!< DMA2D Mode */
\r
3462 /******************** Bit definition for DMA2D_ISR register *****************/
\r
3464 #define DMA2D_ISR_TEIF ((uint32_t)0x00000001) /*!< Transfer Error Interrupt Flag */
\r
3465 #define DMA2D_ISR_TCIF ((uint32_t)0x00000002) /*!< Transfer Complete Interrupt Flag */
\r
3466 #define DMA2D_ISR_TWIF ((uint32_t)0x00000004) /*!< Transfer Watermark Interrupt Flag */
\r
3467 #define DMA2D_ISR_CAEIF ((uint32_t)0x00000008) /*!< CLUT Access Error Interrupt Flag */
\r
3468 #define DMA2D_ISR_CTCIF ((uint32_t)0x00000010) /*!< CLUT Transfer Complete Interrupt Flag */
\r
3469 #define DMA2D_ISR_CEIF ((uint32_t)0x00000020) /*!< Configuration Error Interrupt Flag */
\r
3471 /******************** Bit definition for DMA2D_IFSR register ****************/
\r
3473 #define DMA2D_IFSR_CTEIF ((uint32_t)0x00000001) /*!< Clears Transfer Error Interrupt Flag */
\r
3474 #define DMA2D_IFSR_CTCIF ((uint32_t)0x00000002) /*!< Clears Transfer Complete Interrupt Flag */
\r
3475 #define DMA2D_IFSR_CTWIF ((uint32_t)0x00000004) /*!< Clears Transfer Watermark Interrupt Flag */
\r
3476 #define DMA2D_IFSR_CCAEIF ((uint32_t)0x00000008) /*!< Clears CLUT Access Error Interrupt Flag */
\r
3477 #define DMA2D_IFSR_CCTCIF ((uint32_t)0x00000010) /*!< Clears CLUT Transfer Complete Interrupt Flag */
\r
3478 #define DMA2D_IFSR_CCEIF ((uint32_t)0x00000020) /*!< Clears Configuration Error Interrupt Flag */
\r
3480 /******************** Bit definition for DMA2D_FGMAR register ***************/
\r
3482 #define DMA2D_FGMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
\r
3484 /******************** Bit definition for DMA2D_FGOR register ****************/
\r
3486 #define DMA2D_FGOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */
\r
3488 /******************** Bit definition for DMA2D_BGMAR register ***************/
\r
3490 #define DMA2D_BGMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
\r
3492 /******************** Bit definition for DMA2D_BGOR register ****************/
\r
3494 #define DMA2D_BGOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */
\r
3496 /******************** Bit definition for DMA2D_FGPFCCR register *************/
\r
3498 #define DMA2D_FGPFCCR_CM ((uint32_t)0x0000000F) /*!< Color mode */
\r
3499 #define DMA2D_FGPFCCR_CCM ((uint32_t)0x00000010) /*!< CLUT Color mode */
\r
3500 #define DMA2D_FGPFCCR_START ((uint32_t)0x00000020) /*!< Start */
\r
3501 #define DMA2D_FGPFCCR_CS ((uint32_t)0x0000FF00) /*!< CLUT size */
\r
3502 #define DMA2D_FGPFCCR_AM ((uint32_t)0x00030000) /*!< Alpha mode */
\r
3503 #define DMA2D_FGPFCCR_ALPHA ((uint32_t)0xFF000000) /*!< Alpha value */
\r
3505 /******************** Bit definition for DMA2D_FGCOLR register **************/
\r
3507 #define DMA2D_FGCOLR_BLUE ((uint32_t)0x000000FF) /*!< Blue Value */
\r
3508 #define DMA2D_FGCOLR_GREEN ((uint32_t)0x0000FF00) /*!< Green Value */
\r
3509 #define DMA2D_FGCOLR_RED ((uint32_t)0x00FF0000) /*!< Red Value */
\r
3511 /******************** Bit definition for DMA2D_BGPFCCR register *************/
\r
3513 #define DMA2D_BGPFCCR_CM ((uint32_t)0x0000000F) /*!< Color mode */
\r
3514 #define DMA2D_BGPFCCR_CCM ((uint32_t)0x00000010) /*!< CLUT Color mode */
\r
3515 #define DMA2D_BGPFCCR_START ((uint32_t)0x00000020) /*!< Start */
\r
3516 #define DMA2D_BGPFCCR_CS ((uint32_t)0x0000FF00) /*!< CLUT size */
\r
3517 #define DMA2D_BGPFCCR_AM ((uint32_t)0x00030000) /*!< Alpha Mode */
\r
3518 #define DMA2D_BGPFCCR_ALPHA ((uint32_t)0xFF000000) /*!< Alpha value */
\r
3520 /******************** Bit definition for DMA2D_BGCOLR register **************/
\r
3522 #define DMA2D_BGCOLR_BLUE ((uint32_t)0x000000FF) /*!< Blue Value */
\r
3523 #define DMA2D_BGCOLR_GREEN ((uint32_t)0x0000FF00) /*!< Green Value */
\r
3524 #define DMA2D_BGCOLR_RED ((uint32_t)0x00FF0000) /*!< Red Value */
\r
3526 /******************** Bit definition for DMA2D_FGCMAR register **************/
\r
3528 #define DMA2D_FGCMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
\r
3530 /******************** Bit definition for DMA2D_BGCMAR register **************/
\r
3532 #define DMA2D_BGCMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
\r
3534 /******************** Bit definition for DMA2D_OPFCCR register **************/
\r
3536 #define DMA2D_OPFCCR_CM ((uint32_t)0x00000007) /*!< Color mode */
\r
3538 /******************** Bit definition for DMA2D_OCOLR register ***************/
\r
3540 /*!<Mode_ARGB8888/RGB888 */
\r
3542 #define DMA2D_OCOLR_BLUE_1 ((uint32_t)0x000000FF) /*!< BLUE Value */
\r
3543 #define DMA2D_OCOLR_GREEN_1 ((uint32_t)0x0000FF00) /*!< GREEN Value */
\r
3544 #define DMA2D_OCOLR_RED_1 ((uint32_t)0x00FF0000) /*!< Red Value */
\r
3545 #define DMA2D_OCOLR_ALPHA_1 ((uint32_t)0xFF000000) /*!< Alpha Channel Value */
\r
3547 /*!<Mode_RGB565 */
\r
3548 #define DMA2D_OCOLR_BLUE_2 ((uint32_t)0x0000001F) /*!< BLUE Value */
\r
3549 #define DMA2D_OCOLR_GREEN_2 ((uint32_t)0x000007E0) /*!< GREEN Value */
\r
3550 #define DMA2D_OCOLR_RED_2 ((uint32_t)0x0000F800) /*!< Red Value */
\r
3552 /*!<Mode_ARGB1555 */
\r
3553 #define DMA2D_OCOLR_BLUE_3 ((uint32_t)0x0000001F) /*!< BLUE Value */
\r
3554 #define DMA2D_OCOLR_GREEN_3 ((uint32_t)0x000003E0) /*!< GREEN Value */
\r
3555 #define DMA2D_OCOLR_RED_3 ((uint32_t)0x00007C00) /*!< Red Value */
\r
3556 #define DMA2D_OCOLR_ALPHA_3 ((uint32_t)0x00008000) /*!< Alpha Channel Value */
\r
3558 /*!<Mode_ARGB4444 */
\r
3559 #define DMA2D_OCOLR_BLUE_4 ((uint32_t)0x0000000F) /*!< BLUE Value */
\r
3560 #define DMA2D_OCOLR_GREEN_4 ((uint32_t)0x000000F0) /*!< GREEN Value */
\r
3561 #define DMA2D_OCOLR_RED_4 ((uint32_t)0x00000F00) /*!< Red Value */
\r
3562 #define DMA2D_OCOLR_ALPHA_4 ((uint32_t)0x0000F000) /*!< Alpha Channel Value */
\r
3564 /******************** Bit definition for DMA2D_OMAR register ****************/
\r
3566 #define DMA2D_OMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
\r
3568 /******************** Bit definition for DMA2D_OOR register *****************/
\r
3570 #define DMA2D_OOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */
\r
3572 /******************** Bit definition for DMA2D_NLR register *****************/
\r
3574 #define DMA2D_NLR_NL ((uint32_t)0x0000FFFF) /*!< Number of Lines */
\r
3575 #define DMA2D_NLR_PL ((uint32_t)0x3FFF0000) /*!< Pixel per Lines */
\r
3577 /******************** Bit definition for DMA2D_LWR register *****************/
\r
3579 #define DMA2D_LWR_LW ((uint32_t)0x0000FFFF) /*!< Line Watermark */
\r
3581 /******************** Bit definition for DMA2D_AMTCR register ***************/
\r
3583 #define DMA2D_AMTCR_EN ((uint32_t)0x00000001) /*!< Enable */
\r
3584 #define DMA2D_AMTCR_DT ((uint32_t)0x0000FF00) /*!< Dead Time */
\r
3588 /******************** Bit definition for DMA2D_FGCLUT register **************/
\r
3590 /******************** Bit definition for DMA2D_BGCLUT register **************/
\r
3593 /******************************************************************************/
\r
3595 /* External Interrupt/Event Controller */
\r
3597 /******************************************************************************/
\r
3598 /******************* Bit definition for EXTI_IMR register *******************/
\r
3599 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
\r
3600 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
\r
3601 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
\r
3602 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
\r
3603 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
\r
3604 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
\r
3605 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
\r
3606 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
\r
3607 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
\r
3608 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
\r
3609 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
\r
3610 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
\r
3611 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
\r
3612 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
\r
3613 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
\r
3614 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
\r
3615 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
\r
3616 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
\r
3617 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
\r
3618 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
\r
3619 #define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
\r
3620 #define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
\r
3621 #define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
\r
3622 #define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
\r
3624 /******************* Bit definition for EXTI_EMR register *******************/
\r
3625 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
\r
3626 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
\r
3627 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
\r
3628 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
\r
3629 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
\r
3630 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
\r
3631 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
\r
3632 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
\r
3633 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
\r
3634 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
\r
3635 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
\r
3636 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
\r
3637 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
\r
3638 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
\r
3639 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
\r
3640 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
\r
3641 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
\r
3642 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
\r
3643 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
\r
3644 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
\r
3645 #define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
\r
3646 #define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
\r
3647 #define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
\r
3648 #define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
\r
3650 /****************** Bit definition for EXTI_RTSR register *******************/
\r
3651 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
\r
3652 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
\r
3653 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
\r
3654 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
\r
3655 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
\r
3656 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
\r
3657 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
\r
3658 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
\r
3659 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
\r
3660 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
\r
3661 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
\r
3662 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
\r
3663 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
\r
3664 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
\r
3665 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
\r
3666 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
\r
3667 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
\r
3668 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
\r
3669 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
\r
3670 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
\r
3671 #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
\r
3672 #define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
\r
3673 #define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
\r
3674 #define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
\r
3676 /****************** Bit definition for EXTI_FTSR register *******************/
\r
3677 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
\r
3678 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
\r
3679 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
\r
3680 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
\r
3681 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
\r
3682 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
\r
3683 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
\r
3684 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
\r
3685 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
\r
3686 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
\r
3687 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
\r
3688 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
\r
3689 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
\r
3690 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
\r
3691 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
\r
3692 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
\r
3693 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
\r
3694 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
\r
3695 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
\r
3696 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
\r
3697 #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
\r
3698 #define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
\r
3699 #define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
\r
3700 #define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
\r
3702 /****************** Bit definition for EXTI_SWIER register ******************/
\r
3703 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
\r
3704 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
\r
3705 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
\r
3706 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
\r
3707 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
\r
3708 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
\r
3709 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
\r
3710 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
\r
3711 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
\r
3712 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
\r
3713 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
\r
3714 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
\r
3715 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
\r
3716 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
\r
3717 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
\r
3718 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
\r
3719 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
\r
3720 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
\r
3721 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
\r
3722 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
\r
3723 #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
\r
3724 #define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
\r
3725 #define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
\r
3726 #define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
\r
3728 /******************* Bit definition for EXTI_PR register ********************/
\r
3729 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
\r
3730 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
\r
3731 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
\r
3732 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
\r
3733 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
\r
3734 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
\r
3735 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
\r
3736 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
\r
3737 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
\r
3738 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
\r
3739 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
\r
3740 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
\r
3741 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
\r
3742 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
\r
3743 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
\r
3744 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
\r
3745 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
\r
3746 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
\r
3747 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
\r
3748 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
\r
3749 #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
\r
3750 #define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
\r
3751 #define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
\r
3752 #define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */
\r
3754 /******************************************************************************/
\r
3758 /******************************************************************************/
\r
3759 /******************* Bits definition for FLASH_ACR register *****************/
\r
3760 #define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
\r
3761 #define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
\r
3762 #define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
\r
3763 #define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
\r
3764 #define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
\r
3765 #define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
\r
3766 #define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
\r
3767 #define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
\r
3768 #define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
\r
3769 #define FLASH_ACR_LATENCY_8WS ((uint32_t)0x00000008)
\r
3770 #define FLASH_ACR_LATENCY_9WS ((uint32_t)0x00000009)
\r
3771 #define FLASH_ACR_LATENCY_10WS ((uint32_t)0x0000000A)
\r
3772 #define FLASH_ACR_LATENCY_11WS ((uint32_t)0x0000000B)
\r
3773 #define FLASH_ACR_LATENCY_12WS ((uint32_t)0x0000000C)
\r
3774 #define FLASH_ACR_LATENCY_13WS ((uint32_t)0x0000000D)
\r
3775 #define FLASH_ACR_LATENCY_14WS ((uint32_t)0x0000000E)
\r
3776 #define FLASH_ACR_LATENCY_15WS ((uint32_t)0x0000000F)
\r
3777 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
\r
3778 #define FLASH_ACR_ARTEN ((uint32_t)0x00000200)
\r
3779 #define FLASH_ACR_ARTRST ((uint32_t)0x00000800)
\r
3781 /******************* Bits definition for FLASH_SR register ******************/
\r
3782 #define FLASH_SR_EOP ((uint32_t)0x00000001)
\r
3783 #define FLASH_SR_OPERR ((uint32_t)0x00000002)
\r
3784 #define FLASH_SR_WRPERR ((uint32_t)0x00000010)
\r
3785 #define FLASH_SR_PGAERR ((uint32_t)0x00000020)
\r
3786 #define FLASH_SR_PGPERR ((uint32_t)0x00000040)
\r
3787 #define FLASH_SR_ERSERR ((uint32_t)0x00000080)
\r
3788 #define FLASH_SR_BSY ((uint32_t)0x00010000)
\r
3790 /******************* Bits definition for FLASH_CR register ******************/
\r
3791 #define FLASH_CR_PG ((uint32_t)0x00000001)
\r
3792 #define FLASH_CR_SER ((uint32_t)0x00000002)
\r
3793 #define FLASH_CR_MER ((uint32_t)0x00000004)
\r
3794 #define FLASH_CR_SNB ((uint32_t)0x00000078)
\r
3795 #define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
\r
3796 #define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
\r
3797 #define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
\r
3798 #define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
\r
3799 #define FLASH_CR_PSIZE ((uint32_t)0x00000300)
\r
3800 #define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
\r
3801 #define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
\r
3802 #define FLASH_CR_STRT ((uint32_t)0x00010000)
\r
3803 #define FLASH_CR_EOPIE ((uint32_t)0x01000000)
\r
3804 #define FLASH_CR_ERRIE ((uint32_t)0x02000000)
\r
3805 #define FLASH_CR_LOCK ((uint32_t)0x80000000)
\r
3807 /******************* Bits definition for FLASH_OPTCR register ***************/
\r
3808 #define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
\r
3809 #define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
\r
3810 #define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
\r
3811 #define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
\r
3812 #define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
\r
3813 #define FLASH_OPTCR_IWDG_SW ((uint32_t)0x00000010)
\r
3814 #define FLASH_OPTCR_WWDG_SW ((uint32_t)0x00000020)
\r
3815 #define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
\r
3816 #define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
\r
3817 #define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)
\r
3818 #define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
\r
3819 #define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
\r
3820 #define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
\r
3821 #define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
\r
3822 #define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
\r
3823 #define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
\r
3824 #define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
\r
3825 #define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
\r
3826 #define FLASH_OPTCR_nWRP ((uint32_t)0x00FF0000)
\r
3827 #define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
\r
3828 #define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
\r
3829 #define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
\r
3830 #define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
\r
3831 #define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
\r
3832 #define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
\r
3833 #define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
\r
3834 #define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
\r
3835 #define FLASH_OPTCR_IWDG_STOP ((uint32_t)0x40000000)
\r
3836 #define FLASH_OPTCR_IWDG_STDBY ((uint32_t)0x80000000)
\r
3838 /******************* Bits definition for FLASH_OPTCR1 register ***************/
\r
3839 #define FLASH_OPTCR1_BOOT_ADD0 ((uint32_t)0x0000FFFF)
\r
3840 #define FLASH_OPTCR1_BOOT_ADD1 ((uint32_t)0xFFFF0000)
\r
3844 /******************************************************************************/
\r
3846 /* Flexible Memory Controller */
\r
3848 /******************************************************************************/
\r
3849 /****************** Bit definition for FMC_BCR1 register *******************/
\r
3850 #define FMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
\r
3851 #define FMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
\r
3853 #define FMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
\r
3854 #define FMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
\r
3855 #define FMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
\r
3857 #define FMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
\r
3858 #define FMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
\r
3859 #define FMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
\r
3861 #define FMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
\r
3862 #define FMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
\r
3863 #define FMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
\r
3864 #define FMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
\r
3865 #define FMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
\r
3866 #define FMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
\r
3867 #define FMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
\r
3868 #define FMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
\r
3869 #define FMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
\r
3870 #define FMC_BCR1_CPSIZE ((uint32_t)0x00070000) /*!<CRAM page size */
\r
3871 #define FMC_BCR1_CPSIZE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
\r
3872 #define FMC_BCR1_CPSIZE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
\r
3873 #define FMC_BCR1_CPSIZE_2 ((uint32_t)0x00040000) /*!<Bit 2 */
\r
3874 #define FMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
\r
3875 #define FMC_BCR1_CCLKEN ((uint32_t)0x00100000) /*!<Continous clock enable */
\r
3876 #define FMC_BCR1_WFDIS ((uint32_t)0x00200000) /*!<Write FIFO Disable */
\r
3878 /****************** Bit definition for FMC_BCR2 register *******************/
\r
3879 #define FMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
\r
3880 #define FMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
\r
3882 #define FMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
\r
3883 #define FMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
\r
3884 #define FMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
\r
3886 #define FMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
\r
3887 #define FMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
\r
3888 #define FMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
\r
3890 #define FMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
\r
3891 #define FMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
\r
3892 #define FMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
\r
3893 #define FMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
\r
3894 #define FMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
\r
3895 #define FMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
\r
3896 #define FMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
\r
3897 #define FMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
\r
3898 #define FMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
\r
3899 #define FMC_BCR2_CPSIZE ((uint32_t)0x00070000) /*!<CRAM page size */
\r
3900 #define FMC_BCR2_CPSIZE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
\r
3901 #define FMC_BCR2_CPSIZE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
\r
3902 #define FMC_BCR2_CPSIZE_2 ((uint32_t)0x00040000) /*!<Bit 2 */
\r
3903 #define FMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
\r
3905 /****************** Bit definition for FMC_BCR3 register *******************/
\r
3906 #define FMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
\r
3907 #define FMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
\r
3909 #define FMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
\r
3910 #define FMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
\r
3911 #define FMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
\r
3913 #define FMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
\r
3914 #define FMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
\r
3915 #define FMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
\r
3917 #define FMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
\r
3918 #define FMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
\r
3919 #define FMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
\r
3920 #define FMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
\r
3921 #define FMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
\r
3922 #define FMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
\r
3923 #define FMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
\r
3924 #define FMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
\r
3925 #define FMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
\r
3926 #define FMC_BCR3_CPSIZE ((uint32_t)0x00070000) /*!<CRAM page size */
\r
3927 #define FMC_BCR3_CPSIZE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
\r
3928 #define FMC_BCR3_CPSIZE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
\r
3929 #define FMC_BCR3_CPSIZE_2 ((uint32_t)0x00040000) /*!<Bit 2 */
\r
3930 #define FMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
\r
3932 /****************** Bit definition for FMC_BCR4 register *******************/
\r
3933 #define FMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
\r
3934 #define FMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
\r
3936 #define FMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
\r
3937 #define FMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
\r
3938 #define FMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
\r
3940 #define FMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
\r
3941 #define FMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
\r
3942 #define FMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
\r
3944 #define FMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
\r
3945 #define FMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
\r
3946 #define FMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
\r
3947 #define FMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
\r
3948 #define FMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
\r
3949 #define FMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
\r
3950 #define FMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
\r
3951 #define FMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
\r
3952 #define FMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
\r
3953 #define FMC_BCR4_CPSIZE ((uint32_t)0x00070000) /*!<CRAM page size */
\r
3954 #define FMC_BCR4_CPSIZE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
\r
3955 #define FMC_BCR4_CPSIZE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
\r
3956 #define FMC_BCR4_CPSIZE_2 ((uint32_t)0x00040000) /*!<Bit 2 */
\r
3957 #define FMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
\r
3959 /****************** Bit definition for FMC_BTR1 register ******************/
\r
3960 #define FMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
\r
3961 #define FMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
3962 #define FMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
3963 #define FMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
3964 #define FMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
3966 #define FMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
\r
3967 #define FMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
\r
3968 #define FMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
\r
3969 #define FMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
\r
3970 #define FMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
\r
3972 #define FMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
\r
3973 #define FMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
\r
3974 #define FMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
\r
3975 #define FMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
\r
3976 #define FMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
\r
3977 #define FMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
\r
3978 #define FMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
\r
3979 #define FMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
\r
3980 #define FMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
\r
3982 #define FMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
\r
3983 #define FMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
\r
3984 #define FMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
\r
3985 #define FMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
\r
3986 #define FMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
\r
3988 #define FMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
\r
3989 #define FMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
\r
3990 #define FMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
\r
3991 #define FMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
\r
3992 #define FMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
\r
3994 #define FMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
\r
3995 #define FMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
\r
3996 #define FMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
\r
3997 #define FMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
\r
3998 #define FMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
\r
4000 #define FMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
\r
4001 #define FMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
\r
4002 #define FMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
\r
4004 /****************** Bit definition for FMC_BTR2 register *******************/
\r
4005 #define FMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
\r
4006 #define FMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
4007 #define FMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
4008 #define FMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
4009 #define FMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
4011 #define FMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
\r
4012 #define FMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
\r
4013 #define FMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
\r
4014 #define FMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
\r
4015 #define FMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
\r
4017 #define FMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
\r
4018 #define FMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
\r
4019 #define FMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
\r
4020 #define FMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
\r
4021 #define FMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
\r
4022 #define FMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
\r
4023 #define FMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
\r
4024 #define FMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
\r
4025 #define FMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
\r
4027 #define FMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
\r
4028 #define FMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
\r
4029 #define FMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
\r
4030 #define FMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
\r
4031 #define FMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
\r
4033 #define FMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
\r
4034 #define FMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
\r
4035 #define FMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
\r
4036 #define FMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
\r
4037 #define FMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
\r
4039 #define FMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
\r
4040 #define FMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
\r
4041 #define FMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
\r
4042 #define FMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
\r
4043 #define FMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
\r
4045 #define FMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
\r
4046 #define FMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
\r
4047 #define FMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
\r
4049 /******************* Bit definition for FMC_BTR3 register *******************/
\r
4050 #define FMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
\r
4051 #define FMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
4052 #define FMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
4053 #define FMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
4054 #define FMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
4056 #define FMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
\r
4057 #define FMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
\r
4058 #define FMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
\r
4059 #define FMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
\r
4060 #define FMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
\r
4062 #define FMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
\r
4063 #define FMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
\r
4064 #define FMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
\r
4065 #define FMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
\r
4066 #define FMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
\r
4067 #define FMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
\r
4068 #define FMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
\r
4069 #define FMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
\r
4070 #define FMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
\r
4072 #define FMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
\r
4073 #define FMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
\r
4074 #define FMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
\r
4075 #define FMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
\r
4076 #define FMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
\r
4078 #define FMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
\r
4079 #define FMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
\r
4080 #define FMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
\r
4081 #define FMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
\r
4082 #define FMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
\r
4084 #define FMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
\r
4085 #define FMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
\r
4086 #define FMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
\r
4087 #define FMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
\r
4088 #define FMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
\r
4090 #define FMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
\r
4091 #define FMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
\r
4092 #define FMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
\r
4094 /****************** Bit definition for FMC_BTR4 register *******************/
\r
4095 #define FMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
\r
4096 #define FMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
4097 #define FMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
4098 #define FMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
4099 #define FMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
4101 #define FMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
\r
4102 #define FMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
\r
4103 #define FMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
\r
4104 #define FMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
\r
4105 #define FMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
\r
4107 #define FMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
\r
4108 #define FMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
\r
4109 #define FMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
\r
4110 #define FMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
\r
4111 #define FMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
\r
4112 #define FMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
\r
4113 #define FMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
\r
4114 #define FMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
\r
4115 #define FMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
\r
4117 #define FMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
\r
4118 #define FMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
\r
4119 #define FMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
\r
4120 #define FMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
\r
4121 #define FMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
\r
4123 #define FMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
\r
4124 #define FMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
\r
4125 #define FMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
\r
4126 #define FMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
\r
4127 #define FMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
\r
4129 #define FMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
\r
4130 #define FMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
\r
4131 #define FMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
\r
4132 #define FMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
\r
4133 #define FMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
\r
4135 #define FMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
\r
4136 #define FMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
\r
4137 #define FMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
\r
4139 /****************** Bit definition for FMC_BWTR1 register ******************/
\r
4140 #define FMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
\r
4141 #define FMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
4142 #define FMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
4143 #define FMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
4144 #define FMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
4146 #define FMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
\r
4147 #define FMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
\r
4148 #define FMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
\r
4149 #define FMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
\r
4150 #define FMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
\r
4152 #define FMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
\r
4153 #define FMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
\r
4154 #define FMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
\r
4155 #define FMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
\r
4156 #define FMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
\r
4157 #define FMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
\r
4158 #define FMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
\r
4159 #define FMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
\r
4160 #define FMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
\r
4162 #define FMC_BWTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
\r
4163 #define FMC_BWTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
\r
4164 #define FMC_BWTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
\r
4165 #define FMC_BWTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
\r
4166 #define FMC_BWTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
\r
4168 #define FMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
\r
4169 #define FMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
\r
4170 #define FMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
\r
4172 /****************** Bit definition for FMC_BWTR2 register ******************/
\r
4173 #define FMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
\r
4174 #define FMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
4175 #define FMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
4176 #define FMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
4177 #define FMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
4179 #define FMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
\r
4180 #define FMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
\r
4181 #define FMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
\r
4182 #define FMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
\r
4183 #define FMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
\r
4185 #define FMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
\r
4186 #define FMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
\r
4187 #define FMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
\r
4188 #define FMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
\r
4189 #define FMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
\r
4190 #define FMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
\r
4191 #define FMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
\r
4192 #define FMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
\r
4193 #define FMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
\r
4195 #define FMC_BWTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
\r
4196 #define FMC_BWTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
\r
4197 #define FMC_BWTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
\r
4198 #define FMC_BWTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
\r
4199 #define FMC_BWTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
\r
4201 #define FMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
\r
4202 #define FMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
\r
4203 #define FMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
\r
4205 /****************** Bit definition for FMC_BWTR3 register ******************/
\r
4206 #define FMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
\r
4207 #define FMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
4208 #define FMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
4209 #define FMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
4210 #define FMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
4212 #define FMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
\r
4213 #define FMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
\r
4214 #define FMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
\r
4215 #define FMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
\r
4216 #define FMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
\r
4218 #define FMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
\r
4219 #define FMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
\r
4220 #define FMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
\r
4221 #define FMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
\r
4222 #define FMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
\r
4223 #define FMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
\r
4224 #define FMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
\r
4225 #define FMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
\r
4226 #define FMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
\r
4228 #define FMC_BWTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
\r
4229 #define FMC_BWTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
\r
4230 #define FMC_BWTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
\r
4231 #define FMC_BWTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
\r
4232 #define FMC_BWTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
\r
4234 #define FMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
\r
4235 #define FMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
\r
4236 #define FMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
\r
4238 /****************** Bit definition for FMC_BWTR4 register ******************/
\r
4239 #define FMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
\r
4240 #define FMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
4241 #define FMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
4242 #define FMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
4243 #define FMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
4245 #define FMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
\r
4246 #define FMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
\r
4247 #define FMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
\r
4248 #define FMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
\r
4249 #define FMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
\r
4251 #define FMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
\r
4252 #define FMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
\r
4253 #define FMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
\r
4254 #define FMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
\r
4255 #define FMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
\r
4256 #define FMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
\r
4257 #define FMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
\r
4258 #define FMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
\r
4259 #define FMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
\r
4261 #define FMC_BWTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
\r
4262 #define FMC_BWTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
\r
4263 #define FMC_BWTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
\r
4264 #define FMC_BWTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
\r
4265 #define FMC_BWTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
\r
4267 #define FMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
\r
4268 #define FMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
\r
4269 #define FMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
\r
4271 /****************** Bit definition for FMC_PCR register *******************/
\r
4272 #define FMC_PCR_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
\r
4273 #define FMC_PCR_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
\r
4274 #define FMC_PCR_PTYP ((uint32_t)0x00000008) /*!<Memory type */
\r
4276 #define FMC_PCR_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
\r
4277 #define FMC_PCR_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
\r
4278 #define FMC_PCR_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
\r
4280 #define FMC_PCR_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
\r
4282 #define FMC_PCR_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
\r
4283 #define FMC_PCR_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
\r
4284 #define FMC_PCR_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
\r
4285 #define FMC_PCR_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
\r
4286 #define FMC_PCR_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
\r
4288 #define FMC_PCR_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
\r
4289 #define FMC_PCR_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
\r
4290 #define FMC_PCR_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
\r
4291 #define FMC_PCR_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
\r
4292 #define FMC_PCR_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
\r
4294 #define FMC_PCR_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
\r
4295 #define FMC_PCR_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
\r
4296 #define FMC_PCR_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
\r
4297 #define FMC_PCR_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
\r
4299 /******************* Bit definition for FMC_SR register *******************/
\r
4300 #define FMC_SR_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
\r
4301 #define FMC_SR_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
\r
4302 #define FMC_SR_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
\r
4303 #define FMC_SR_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
\r
4304 #define FMC_SR_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
\r
4305 #define FMC_SR_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
\r
4306 #define FMC_SR_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
\r
4308 /****************** Bit definition for FMC_PMEM register ******************/
\r
4309 #define FMC_PMEM_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
\r
4310 #define FMC_PMEM_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
4311 #define FMC_PMEM_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
4312 #define FMC_PMEM_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
4313 #define FMC_PMEM_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
4314 #define FMC_PMEM_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
\r
4315 #define FMC_PMEM_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
\r
4316 #define FMC_PMEM_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
\r
4317 #define FMC_PMEM_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
\r
4319 #define FMC_PMEM_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
\r
4320 #define FMC_PMEM_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
\r
4321 #define FMC_PMEM_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
\r
4322 #define FMC_PMEM_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
\r
4323 #define FMC_PMEM_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
\r
4324 #define FMC_PMEM_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
\r
4325 #define FMC_PMEM_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
\r
4326 #define FMC_PMEM_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
\r
4327 #define FMC_PMEM_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
\r
4329 #define FMC_PMEM_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
\r
4330 #define FMC_PMEM_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
\r
4331 #define FMC_PMEM_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
\r
4332 #define FMC_PMEM_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
\r
4333 #define FMC_PMEM_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
\r
4334 #define FMC_PMEM_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
\r
4335 #define FMC_PMEM_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
\r
4336 #define FMC_PMEM_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
\r
4337 #define FMC_PMEM_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
\r
4339 #define FMC_PMEM_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
\r
4340 #define FMC_PMEM_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
\r
4341 #define FMC_PMEM_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
\r
4342 #define FMC_PMEM_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
\r
4343 #define FMC_PMEM_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
\r
4344 #define FMC_PMEM_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
\r
4345 #define FMC_PMEM_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
\r
4346 #define FMC_PMEM_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
\r
4347 #define FMC_PMEM_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
\r
4349 /****************** Bit definition for FMC_PATT register ******************/
\r
4350 #define FMC_PATT_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
\r
4351 #define FMC_PATT_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
4352 #define FMC_PATT_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
4353 #define FMC_PATT_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
4354 #define FMC_PATT_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
4355 #define FMC_PATT_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
\r
4356 #define FMC_PATT_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
\r
4357 #define FMC_PATT_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
\r
4358 #define FMC_PATT_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
\r
4360 #define FMC_PATT_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
\r
4361 #define FMC_PATT_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
\r
4362 #define FMC_PATT_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
\r
4363 #define FMC_PATT_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
\r
4364 #define FMC_PATT_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
\r
4365 #define FMC_PATT_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
\r
4366 #define FMC_PATT_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
\r
4367 #define FMC_PATT_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
\r
4368 #define FMC_PATT_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
\r
4370 #define FMC_PATT_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
\r
4371 #define FMC_PATT_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
\r
4372 #define FMC_PATT_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
\r
4373 #define FMC_PATT_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
\r
4374 #define FMC_PATT_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
\r
4375 #define FMC_PATT_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
\r
4376 #define FMC_PATT_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
\r
4377 #define FMC_PATT_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
\r
4378 #define FMC_PATT_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
\r
4380 #define FMC_PATT_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
\r
4381 #define FMC_PATT_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
\r
4382 #define FMC_PATT_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
\r
4383 #define FMC_PATT_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
\r
4384 #define FMC_PATT_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
\r
4385 #define FMC_PATT_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
\r
4386 #define FMC_PATT_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
\r
4387 #define FMC_PATT_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
\r
4388 #define FMC_PATT_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
\r
4390 /****************** Bit definition for FMC_ECCR register ******************/
\r
4391 #define FMC_ECCR_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
\r
4393 /****************** Bit definition for FMC_SDCR1 register ******************/
\r
4394 #define FMC_SDCR1_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */
\r
4395 #define FMC_SDCR1_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
4396 #define FMC_SDCR1_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
4398 #define FMC_SDCR1_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */
\r
4399 #define FMC_SDCR1_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */
\r
4400 #define FMC_SDCR1_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */
\r
4402 #define FMC_SDCR1_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */
\r
4403 #define FMC_SDCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
\r
4404 #define FMC_SDCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
\r
4406 #define FMC_SDCR1_NB ((uint32_t)0x00000040) /*!<Number of internal bank */
\r
4408 #define FMC_SDCR1_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */
\r
4409 #define FMC_SDCR1_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */
\r
4410 #define FMC_SDCR1_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */
\r
4412 #define FMC_SDCR1_WP ((uint32_t)0x00000200) /*!<Write protection */
\r
4414 #define FMC_SDCR1_SDCLK ((uint32_t)0x00000C00) /*!<SDRAM clock configuration */
\r
4415 #define FMC_SDCR1_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */
\r
4416 #define FMC_SDCR1_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */
\r
4418 #define FMC_SDCR1_RBURST ((uint32_t)0x00001000) /*!<Read burst */
\r
4420 #define FMC_SDCR1_RPIPE ((uint32_t)0x00006000) /*!<Write protection */
\r
4421 #define FMC_SDCR1_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */
\r
4422 #define FMC_SDCR1_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */
\r
4424 /****************** Bit definition for FMC_SDCR2 register ******************/
\r
4425 #define FMC_SDCR2_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */
\r
4426 #define FMC_SDCR2_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
4427 #define FMC_SDCR2_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
4429 #define FMC_SDCR2_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */
\r
4430 #define FMC_SDCR2_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */
\r
4431 #define FMC_SDCR2_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */
\r
4433 #define FMC_SDCR2_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */
\r
4434 #define FMC_SDCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
\r
4435 #define FMC_SDCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
\r
4437 #define FMC_SDCR2_NB ((uint32_t)0x00000040) /*!<Number of internal bank */
\r
4439 #define FMC_SDCR2_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */
\r
4440 #define FMC_SDCR2_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */
\r
4441 #define FMC_SDCR2_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */
\r
4443 #define FMC_SDCR2_WP ((uint32_t)0x00000200) /*!<Write protection */
\r
4445 #define FMC_SDCR2_SDCLK ((uint32_t)0x00000C00) /*!<SDCLK[1:0] (SDRAM clock configuration) */
\r
4446 #define FMC_SDCR2_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */
\r
4447 #define FMC_SDCR2_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */
\r
4449 #define FMC_SDCR2_RBURST ((uint32_t)0x00001000) /*!<Read burst */
\r
4451 #define FMC_SDCR2_RPIPE ((uint32_t)0x00006000) /*!<RPIPE[1:0](Read pipe) */
\r
4452 #define FMC_SDCR2_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */
\r
4453 #define FMC_SDCR2_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */
\r
4455 /****************** Bit definition for FMC_SDTR1 register ******************/
\r
4456 #define FMC_SDTR1_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */
\r
4457 #define FMC_SDTR1_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
4458 #define FMC_SDTR1_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
4459 #define FMC_SDTR1_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
4460 #define FMC_SDTR1_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
4462 #define FMC_SDTR1_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */
\r
4463 #define FMC_SDTR1_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */
\r
4464 #define FMC_SDTR1_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */
\r
4465 #define FMC_SDTR1_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */
\r
4466 #define FMC_SDTR1_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */
\r
4468 #define FMC_SDTR1_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */
\r
4469 #define FMC_SDTR1_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */
\r
4470 #define FMC_SDTR1_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */
\r
4471 #define FMC_SDTR1_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */
\r
4472 #define FMC_SDTR1_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */
\r
4474 #define FMC_SDTR1_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */
\r
4475 #define FMC_SDTR1_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
\r
4476 #define FMC_SDTR1_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
\r
4477 #define FMC_SDTR1_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
\r
4479 #define FMC_SDTR1_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */
\r
4480 #define FMC_SDTR1_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */
\r
4481 #define FMC_SDTR1_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */
\r
4482 #define FMC_SDTR1_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */
\r
4484 #define FMC_SDTR1_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */
\r
4485 #define FMC_SDTR1_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */
\r
4486 #define FMC_SDTR1_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */
\r
4487 #define FMC_SDTR1_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */
\r
4489 #define FMC_SDTR1_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */
\r
4490 #define FMC_SDTR1_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */
\r
4491 #define FMC_SDTR1_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */
\r
4492 #define FMC_SDTR1_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */
\r
4494 /****************** Bit definition for FMC_SDTR2 register ******************/
\r
4495 #define FMC_SDTR2_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */
\r
4496 #define FMC_SDTR2_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
4497 #define FMC_SDTR2_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
4498 #define FMC_SDTR2_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
4499 #define FMC_SDTR2_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
4501 #define FMC_SDTR2_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */
\r
4502 #define FMC_SDTR2_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */
\r
4503 #define FMC_SDTR2_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */
\r
4504 #define FMC_SDTR2_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */
\r
4505 #define FMC_SDTR2_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */
\r
4507 #define FMC_SDTR2_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */
\r
4508 #define FMC_SDTR2_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */
\r
4509 #define FMC_SDTR2_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */
\r
4510 #define FMC_SDTR2_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */
\r
4511 #define FMC_SDTR2_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */
\r
4513 #define FMC_SDTR2_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */
\r
4514 #define FMC_SDTR2_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
\r
4515 #define FMC_SDTR2_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
\r
4516 #define FMC_SDTR2_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
\r
4518 #define FMC_SDTR2_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */
\r
4519 #define FMC_SDTR2_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */
\r
4520 #define FMC_SDTR2_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */
\r
4521 #define FMC_SDTR2_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */
\r
4523 #define FMC_SDTR2_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */
\r
4524 #define FMC_SDTR2_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */
\r
4525 #define FMC_SDTR2_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */
\r
4526 #define FMC_SDTR2_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */
\r
4528 #define FMC_SDTR2_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */
\r
4529 #define FMC_SDTR2_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */
\r
4530 #define FMC_SDTR2_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */
\r
4531 #define FMC_SDTR2_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */
\r
4533 /****************** Bit definition for FMC_SDCMR register ******************/
\r
4534 #define FMC_SDCMR_MODE ((uint32_t)0x00000007) /*!<MODE[2:0] bits (Command mode) */
\r
4535 #define FMC_SDCMR_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
4536 #define FMC_SDCMR_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
4537 #define FMC_SDCMR_MODE_2 ((uint32_t)0x00000003) /*!<Bit 2 */
\r
4539 #define FMC_SDCMR_CTB2 ((uint32_t)0x00000008) /*!<Command target 2 */
\r
4541 #define FMC_SDCMR_CTB1 ((uint32_t)0x00000010) /*!<Command target 1 */
\r
4543 #define FMC_SDCMR_NRFS ((uint32_t)0x000001E0) /*!<NRFS[3:0] bits (Number of auto-refresh) */
\r
4544 #define FMC_SDCMR_NRFS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
\r
4545 #define FMC_SDCMR_NRFS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
\r
4546 #define FMC_SDCMR_NRFS_2 ((uint32_t)0x00000080) /*!<Bit 2 */
\r
4547 #define FMC_SDCMR_NRFS_3 ((uint32_t)0x00000100) /*!<Bit 3 */
\r
4549 #define FMC_SDCMR_MRD ((uint32_t)0x003FFE00) /*!<MRD[12:0] bits (Mode register definition) */
\r
4551 /****************** Bit definition for FMC_SDRTR register ******************/
\r
4552 #define FMC_SDRTR_CRE ((uint32_t)0x00000001) /*!<Clear refresh error flag */
\r
4554 #define FMC_SDRTR_COUNT ((uint32_t)0x00003FFE) /*!<COUNT[12:0] bits (Refresh timer count) */
\r
4556 #define FMC_SDRTR_REIE ((uint32_t)0x00004000) /*!<RES interupt enable */
\r
4558 /****************** Bit definition for FMC_SDSR register ******************/
\r
4559 #define FMC_SDSR_RE ((uint32_t)0x00000001) /*!<Refresh error flag */
\r
4561 #define FMC_SDSR_MODES1 ((uint32_t)0x00000006) /*!<MODES1[1:0]bits (Status mode for bank 1) */
\r
4562 #define FMC_SDSR_MODES1_0 ((uint32_t)0x00000002) /*!<Bit 0 */
\r
4563 #define FMC_SDSR_MODES1_1 ((uint32_t)0x00000004) /*!<Bit 1 */
\r
4565 #define FMC_SDSR_MODES2 ((uint32_t)0x00000018) /*!<MODES2[1:0]bits (Status mode for bank 2) */
\r
4566 #define FMC_SDSR_MODES2_0 ((uint32_t)0x00000008) /*!<Bit 0 */
\r
4567 #define FMC_SDSR_MODES2_1 ((uint32_t)0x00000010) /*!<Bit 1 */
\r
4569 #define FMC_SDSR_BUSY ((uint32_t)0x00000020) /*!<Busy status */
\r
4571 /******************************************************************************/
\r
4573 /* General Purpose I/O */
\r
4575 /******************************************************************************/
\r
4576 /****************** Bits definition for GPIO_MODER register *****************/
\r
4577 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
\r
4578 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
\r
4579 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
\r
4581 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
\r
4582 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
\r
4583 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
\r
4585 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
\r
4586 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
\r
4587 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
\r
4589 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
\r
4590 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
\r
4591 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
\r
4593 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
\r
4594 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
\r
4595 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
\r
4597 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
\r
4598 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
\r
4599 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
\r
4601 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
\r
4602 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
\r
4603 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
\r
4605 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
\r
4606 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
\r
4607 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
\r
4609 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
\r
4610 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
\r
4611 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
\r
4613 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
\r
4614 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
\r
4615 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
\r
4617 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
\r
4618 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
\r
4619 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
\r
4621 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
\r
4622 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
\r
4623 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
\r
4625 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
\r
4626 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
\r
4627 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
\r
4629 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
\r
4630 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
\r
4631 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
\r
4633 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
\r
4634 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
\r
4635 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
\r
4637 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
\r
4638 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
\r
4639 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
\r
4641 /****************** Bits definition for GPIO_OTYPER register ****************/
\r
4642 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
\r
4643 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
\r
4644 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
\r
4645 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
\r
4646 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
\r
4647 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
\r
4648 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
\r
4649 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
\r
4650 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
\r
4651 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
\r
4652 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
\r
4653 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
\r
4654 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
\r
4655 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
\r
4656 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
\r
4657 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
\r
4659 /****************** Bits definition for GPIO_OSPEEDR register ***************/
\r
4660 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
\r
4661 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
\r
4662 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
\r
4664 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
\r
4665 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
\r
4666 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
\r
4668 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
\r
4669 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
\r
4670 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
\r
4672 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
\r
4673 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
\r
4674 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
\r
4676 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
\r
4677 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
\r
4678 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
\r
4680 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
\r
4681 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
\r
4682 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
\r
4684 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
\r
4685 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
\r
4686 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
\r
4688 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
\r
4689 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
\r
4690 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
\r
4692 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
\r
4693 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
\r
4694 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
\r
4696 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
\r
4697 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
\r
4698 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
\r
4700 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
\r
4701 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
\r
4702 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
\r
4704 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
\r
4705 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
\r
4706 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
\r
4708 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
\r
4709 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
\r
4710 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
\r
4712 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
\r
4713 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
\r
4714 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
\r
4716 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
\r
4717 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
\r
4718 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
\r
4720 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
\r
4721 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
\r
4722 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
\r
4724 /****************** Bits definition for GPIO_PUPDR register *****************/
\r
4725 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
\r
4726 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
\r
4727 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
\r
4729 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
\r
4730 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
\r
4731 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
\r
4733 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
\r
4734 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
\r
4735 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
\r
4737 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
\r
4738 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
\r
4739 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
\r
4741 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
\r
4742 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
\r
4743 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
\r
4745 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
\r
4746 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
\r
4747 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
\r
4749 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
\r
4750 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
\r
4751 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
\r
4753 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
\r
4754 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
\r
4755 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
\r
4757 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
\r
4758 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
\r
4759 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
\r
4761 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
\r
4762 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
\r
4763 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
\r
4765 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
\r
4766 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
\r
4767 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
\r
4769 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
\r
4770 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
\r
4771 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
\r
4773 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
\r
4774 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
\r
4775 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
\r
4777 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
\r
4778 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
\r
4779 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
\r
4781 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
\r
4782 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
\r
4783 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
\r
4785 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
\r
4786 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
\r
4787 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
\r
4789 /****************** Bits definition for GPIO_IDR register *******************/
\r
4790 #define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
\r
4791 #define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
\r
4792 #define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
\r
4793 #define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
\r
4794 #define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
\r
4795 #define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
\r
4796 #define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
\r
4797 #define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
\r
4798 #define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
\r
4799 #define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
\r
4800 #define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
\r
4801 #define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
\r
4802 #define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
\r
4803 #define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
\r
4804 #define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
\r
4805 #define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
\r
4807 /****************** Bits definition for GPIO_ODR register *******************/
\r
4808 #define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
\r
4809 #define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
\r
4810 #define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
\r
4811 #define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
\r
4812 #define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
\r
4813 #define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
\r
4814 #define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
\r
4815 #define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
\r
4816 #define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
\r
4817 #define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
\r
4818 #define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
\r
4819 #define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
\r
4820 #define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
\r
4821 #define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
\r
4822 #define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
\r
4823 #define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
\r
4825 /****************** Bits definition for GPIO_BSRR register ******************/
\r
4826 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
\r
4827 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
\r
4828 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
\r
4829 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
\r
4830 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
\r
4831 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
\r
4832 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
\r
4833 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
\r
4834 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
\r
4835 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
\r
4836 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
\r
4837 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
\r
4838 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
\r
4839 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
\r
4840 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
\r
4841 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
\r
4842 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
\r
4843 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
\r
4844 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
\r
4845 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
\r
4846 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
\r
4847 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
\r
4848 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
\r
4849 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
\r
4850 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
\r
4851 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
\r
4852 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
\r
4853 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
\r
4854 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
\r
4855 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
\r
4856 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
\r
4857 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
\r
4859 /****************** Bit definition for GPIO_LCKR register *********************/
\r
4860 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
\r
4861 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
\r
4862 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
\r
4863 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
\r
4864 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
\r
4865 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
\r
4866 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
\r
4867 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
\r
4868 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
\r
4869 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
\r
4870 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
\r
4871 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
\r
4872 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
\r
4873 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
\r
4874 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
\r
4875 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
\r
4876 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
\r
4878 /******************************************************************************/
\r
4880 /* Inter-integrated Circuit Interface (I2C) */
\r
4882 /******************************************************************************/
\r
4883 /******************* Bit definition for I2C_CR1 register *******************/
\r
4884 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
\r
4885 #define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
\r
4886 #define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
\r
4887 #define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
\r
4888 #define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
\r
4889 #define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
\r
4890 #define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
\r
4891 #define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
\r
4892 #define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
\r
4893 #define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
\r
4894 #define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
\r
4895 #define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
\r
4896 #define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
\r
4897 #define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
\r
4898 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
\r
4899 #define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
\r
4900 #define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
\r
4901 #define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
\r
4902 #define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
\r
4903 #define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
\r
4904 #define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
\r
4906 /****************** Bit definition for I2C_CR2 register ********************/
\r
4907 #define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
\r
4908 #define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
\r
4909 #define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
\r
4910 #define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
\r
4911 #define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
\r
4912 #define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
\r
4913 #define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
\r
4914 #define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
\r
4915 #define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
\r
4916 #define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
\r
4917 #define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
\r
4919 /******************* Bit definition for I2C_OAR1 register ******************/
\r
4920 #define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
\r
4921 #define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
\r
4922 #define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
\r
4924 /******************* Bit definition for I2C_OAR2 register ******************/
\r
4925 #define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
\r
4926 #define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
\r
4927 #define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
\r
4929 /******************* Bit definition for I2C_TIMINGR register *******************/
\r
4930 #define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
\r
4931 #define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
\r
4932 #define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
\r
4933 #define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
\r
4934 #define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
\r
4936 /******************* Bit definition for I2C_TIMEOUTR register *******************/
\r
4937 #define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
\r
4938 #define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
\r
4939 #define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
\r
4940 #define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B */
\r
4941 #define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
\r
4943 /****************** Bit definition for I2C_ISR register *********************/
\r
4944 #define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
\r
4945 #define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
\r
4946 #define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
\r
4947 #define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode) */
\r
4948 #define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
\r
4949 #define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
\r
4950 #define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
\r
4951 #define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
\r
4952 #define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
\r
4953 #define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
\r
4954 #define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
\r
4955 #define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
\r
4956 #define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
\r
4957 #define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
\r
4958 #define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
\r
4959 #define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
\r
4960 #define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
\r
4962 /****************** Bit definition for I2C_ICR register *********************/
\r
4963 #define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
\r
4964 #define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
\r
4965 #define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
\r
4966 #define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
\r
4967 #define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
\r
4968 #define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
\r
4969 #define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
\r
4970 #define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
\r
4971 #define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
\r
4973 /****************** Bit definition for I2C_PECR register *********************/
\r
4974 #define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
\r
4976 /****************** Bit definition for I2C_RXDR register *********************/
\r
4977 #define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
\r
4979 /****************** Bit definition for I2C_TXDR register *********************/
\r
4980 #define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
\r
4983 /******************************************************************************/
\r
4985 /* Independent WATCHDOG */
\r
4987 /******************************************************************************/
\r
4988 /******************* Bit definition for IWDG_KR register ********************/
\r
4989 #define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!<Key value (write only, read 0000h) */
\r
4991 /******************* Bit definition for IWDG_PR register ********************/
\r
4992 #define IWDG_PR_PR ((uint32_t)0x07) /*!<PR[2:0] (Prescaler divider) */
\r
4993 #define IWDG_PR_PR_0 ((uint32_t)0x01) /*!<Bit 0 */
\r
4994 #define IWDG_PR_PR_1 ((uint32_t)0x02) /*!<Bit 1 */
\r
4995 #define IWDG_PR_PR_2 ((uint32_t)0x04) /*!<Bit 2 */
\r
4997 /******************* Bit definition for IWDG_RLR register *******************/
\r
4998 #define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!<Watchdog counter reload value */
\r
5000 /******************* Bit definition for IWDG_SR register ********************/
\r
5001 #define IWDG_SR_PVU ((uint32_t)0x01) /*!< Watchdog prescaler value update */
\r
5002 #define IWDG_SR_RVU ((uint32_t)0x02) /*!< Watchdog counter reload value update */
\r
5003 #define IWDG_SR_WVU ((uint32_t)0x04) /*!< Watchdog counter window value update */
\r
5005 /******************* Bit definition for IWDG_KR register ********************/
\r
5006 #define IWDG_WINR_WIN ((uint32_t)0x0FFF) /*!< Watchdog counter window value */
\r
5008 /******************************************************************************/
\r
5010 /* LCD-TFT Display Controller (LTDC) */
\r
5012 /******************************************************************************/
\r
5014 /******************** Bit definition for LTDC_SSCR register *****************/
\r
5016 #define LTDC_SSCR_VSH ((uint32_t)0x000007FF) /*!< Vertical Synchronization Height */
\r
5017 #define LTDC_SSCR_HSW ((uint32_t)0x0FFF0000) /*!< Horizontal Synchronization Width */
\r
5019 /******************** Bit definition for LTDC_BPCR register *****************/
\r
5021 #define LTDC_BPCR_AVBP ((uint32_t)0x000007FF) /*!< Accumulated Vertical Back Porch */
\r
5022 #define LTDC_BPCR_AHBP ((uint32_t)0x0FFF0000) /*!< Accumulated Horizontal Back Porch */
\r
5024 /******************** Bit definition for LTDC_AWCR register *****************/
\r
5026 #define LTDC_AWCR_AAH ((uint32_t)0x000007FF) /*!< Accumulated Active heigh */
\r
5027 #define LTDC_AWCR_AAW ((uint32_t)0x0FFF0000) /*!< Accumulated Active Width */
\r
5029 /******************** Bit definition for LTDC_TWCR register *****************/
\r
5031 #define LTDC_TWCR_TOTALH ((uint32_t)0x000007FF) /*!< Total Heigh */
\r
5032 #define LTDC_TWCR_TOTALW ((uint32_t)0x0FFF0000) /*!< Total Width */
\r
5034 /******************** Bit definition for LTDC_GCR register ******************/
\r
5036 #define LTDC_GCR_LTDCEN ((uint32_t)0x00000001) /*!< LCD-TFT controller enable bit */
\r
5037 #define LTDC_GCR_DBW ((uint32_t)0x00000070) /*!< Dither Blue Width */
\r
5038 #define LTDC_GCR_DGW ((uint32_t)0x00000700) /*!< Dither Green Width */
\r
5039 #define LTDC_GCR_DRW ((uint32_t)0x00007000) /*!< Dither Red Width */
\r
5040 #define LTDC_GCR_DTEN ((uint32_t)0x00010000) /*!< Dither Enable */
\r
5041 #define LTDC_GCR_PCPOL ((uint32_t)0x10000000) /*!< Pixel Clock Polarity */
\r
5042 #define LTDC_GCR_DEPOL ((uint32_t)0x20000000) /*!< Data Enable Polarity */
\r
5043 #define LTDC_GCR_VSPOL ((uint32_t)0x40000000) /*!< Vertical Synchronization Polarity */
\r
5044 #define LTDC_GCR_HSPOL ((uint32_t)0x80000000) /*!< Horizontal Synchronization Polarity */
\r
5046 /******************** Bit definition for LTDC_SRCR register *****************/
\r
5048 #define LTDC_SRCR_IMR ((uint32_t)0x00000001) /*!< Immediate Reload */
\r
5049 #define LTDC_SRCR_VBR ((uint32_t)0x00000002) /*!< Vertical Blanking Reload */
\r
5051 /******************** Bit definition for LTDC_BCCR register *****************/
\r
5053 #define LTDC_BCCR_BCBLUE ((uint32_t)0x000000FF) /*!< Background Blue value */
\r
5054 #define LTDC_BCCR_BCGREEN ((uint32_t)0x0000FF00) /*!< Background Green value */
\r
5055 #define LTDC_BCCR_BCRED ((uint32_t)0x00FF0000) /*!< Background Red value */
\r
5057 /******************** Bit definition for LTDC_IER register ******************/
\r
5059 #define LTDC_IER_LIE ((uint32_t)0x00000001) /*!< Line Interrupt Enable */
\r
5060 #define LTDC_IER_FUIE ((uint32_t)0x00000002) /*!< FIFO Underrun Interrupt Enable */
\r
5061 #define LTDC_IER_TERRIE ((uint32_t)0x00000004) /*!< Transfer Error Interrupt Enable */
\r
5062 #define LTDC_IER_RRIE ((uint32_t)0x00000008) /*!< Register Reload interrupt enable */
\r
5064 /******************** Bit definition for LTDC_ISR register ******************/
\r
5066 #define LTDC_ISR_LIF ((uint32_t)0x00000001) /*!< Line Interrupt Flag */
\r
5067 #define LTDC_ISR_FUIF ((uint32_t)0x00000002) /*!< FIFO Underrun Interrupt Flag */
\r
5068 #define LTDC_ISR_TERRIF ((uint32_t)0x00000004) /*!< Transfer Error Interrupt Flag */
\r
5069 #define LTDC_ISR_RRIF ((uint32_t)0x00000008) /*!< Register Reload interrupt Flag */
\r
5071 /******************** Bit definition for LTDC_ICR register ******************/
\r
5073 #define LTDC_ICR_CLIF ((uint32_t)0x00000001) /*!< Clears the Line Interrupt Flag */
\r
5074 #define LTDC_ICR_CFUIF ((uint32_t)0x00000002) /*!< Clears the FIFO Underrun Interrupt Flag */
\r
5075 #define LTDC_ICR_CTERRIF ((uint32_t)0x00000004) /*!< Clears the Transfer Error Interrupt Flag */
\r
5076 #define LTDC_ICR_CRRIF ((uint32_t)0x00000008) /*!< Clears Register Reload interrupt Flag */
\r
5078 /******************** Bit definition for LTDC_LIPCR register ****************/
\r
5080 #define LTDC_LIPCR_LIPOS ((uint32_t)0x000007FF) /*!< Line Interrupt Position */
\r
5082 /******************** Bit definition for LTDC_CPSR register *****************/
\r
5084 #define LTDC_CPSR_CYPOS ((uint32_t)0x0000FFFF) /*!< Current Y Position */
\r
5085 #define LTDC_CPSR_CXPOS ((uint32_t)0xFFFF0000) /*!< Current X Position */
\r
5087 /******************** Bit definition for LTDC_CDSR register *****************/
\r
5089 #define LTDC_CDSR_VDES ((uint32_t)0x00000001) /*!< Vertical Data Enable Status */
\r
5090 #define LTDC_CDSR_HDES ((uint32_t)0x00000002) /*!< Horizontal Data Enable Status */
\r
5091 #define LTDC_CDSR_VSYNCS ((uint32_t)0x00000004) /*!< Vertical Synchronization Status */
\r
5092 #define LTDC_CDSR_HSYNCS ((uint32_t)0x00000008) /*!< Horizontal Synchronization Status */
\r
5094 /******************** Bit definition for LTDC_LxCR register *****************/
\r
5096 #define LTDC_LxCR_LEN ((uint32_t)0x00000001) /*!< Layer Enable */
\r
5097 #define LTDC_LxCR_COLKEN ((uint32_t)0x00000002) /*!< Color Keying Enable */
\r
5098 #define LTDC_LxCR_CLUTEN ((uint32_t)0x00000010) /*!< Color Lockup Table Enable */
\r
5100 /******************** Bit definition for LTDC_LxWHPCR register **************/
\r
5102 #define LTDC_LxWHPCR_WHSTPOS ((uint32_t)0x00000FFF) /*!< Window Horizontal Start Position */
\r
5103 #define LTDC_LxWHPCR_WHSPPOS ((uint32_t)0xFFFF0000) /*!< Window Horizontal Stop Position */
\r
5105 /******************** Bit definition for LTDC_LxWVPCR register **************/
\r
5107 #define LTDC_LxWVPCR_WVSTPOS ((uint32_t)0x00000FFF) /*!< Window Vertical Start Position */
\r
5108 #define LTDC_LxWVPCR_WVSPPOS ((uint32_t)0xFFFF0000) /*!< Window Vertical Stop Position */
\r
5110 /******************** Bit definition for LTDC_LxCKCR register ***************/
\r
5112 #define LTDC_LxCKCR_CKBLUE ((uint32_t)0x000000FF) /*!< Color Key Blue value */
\r
5113 #define LTDC_LxCKCR_CKGREEN ((uint32_t)0x0000FF00) /*!< Color Key Green value */
\r
5114 #define LTDC_LxCKCR_CKRED ((uint32_t)0x00FF0000) /*!< Color Key Red value */
\r
5116 /******************** Bit definition for LTDC_LxPFCR register ***************/
\r
5118 #define LTDC_LxPFCR_PF ((uint32_t)0x00000007) /*!< Pixel Format */
\r
5120 /******************** Bit definition for LTDC_LxCACR register ***************/
\r
5122 #define LTDC_LxCACR_CONSTA ((uint32_t)0x000000FF) /*!< Constant Alpha */
\r
5124 /******************** Bit definition for LTDC_LxDCCR register ***************/
\r
5126 #define LTDC_LxDCCR_DCBLUE ((uint32_t)0x000000FF) /*!< Default Color Blue */
\r
5127 #define LTDC_LxDCCR_DCGREEN ((uint32_t)0x0000FF00) /*!< Default Color Green */
\r
5128 #define LTDC_LxDCCR_DCRED ((uint32_t)0x00FF0000) /*!< Default Color Red */
\r
5129 #define LTDC_LxDCCR_DCALPHA ((uint32_t)0xFF000000) /*!< Default Color Alpha */
\r
5131 /******************** Bit definition for LTDC_LxBFCR register ***************/
\r
5133 #define LTDC_LxBFCR_BF2 ((uint32_t)0x00000007) /*!< Blending Factor 2 */
\r
5134 #define LTDC_LxBFCR_BF1 ((uint32_t)0x00000700) /*!< Blending Factor 1 */
\r
5136 /******************** Bit definition for LTDC_LxCFBAR register **************/
\r
5138 #define LTDC_LxCFBAR_CFBADD ((uint32_t)0xFFFFFFFF) /*!< Color Frame Buffer Start Address */
\r
5140 /******************** Bit definition for LTDC_LxCFBLR register **************/
\r
5142 #define LTDC_LxCFBLR_CFBLL ((uint32_t)0x00001FFF) /*!< Color Frame Buffer Line Length */
\r
5143 #define LTDC_LxCFBLR_CFBP ((uint32_t)0x1FFF0000) /*!< Color Frame Buffer Pitch in bytes */
\r
5145 /******************** Bit definition for LTDC_LxCFBLNR register *************/
\r
5147 #define LTDC_LxCFBLNR_CFBLNBR ((uint32_t)0x000007FF) /*!< Frame Buffer Line Number */
\r
5149 /******************** Bit definition for LTDC_LxCLUTWR register *************/
\r
5151 #define LTDC_LxCLUTWR_BLUE ((uint32_t)0x000000FF) /*!< Blue value */
\r
5152 #define LTDC_LxCLUTWR_GREEN ((uint32_t)0x0000FF00) /*!< Green value */
\r
5153 #define LTDC_LxCLUTWR_RED ((uint32_t)0x00FF0000) /*!< Red value */
\r
5154 #define LTDC_LxCLUTWR_CLUTADD ((uint32_t)0xFF000000) /*!< CLUT address */
\r
5157 /******************************************************************************/
\r
5159 /* Power Control */
\r
5161 /******************************************************************************/
\r
5162 /******************** Bit definition for PWR_CR1 register ********************/
\r
5163 #define PWR_CR1_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */
\r
5164 #define PWR_CR1_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
\r
5165 #define PWR_CR1_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
\r
5166 #define PWR_CR1_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
\r
5168 #define PWR_CR1_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
\r
5169 #define PWR_CR1_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
\r
5170 #define PWR_CR1_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
\r
5171 #define PWR_CR1_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
\r
5173 /*!< PVD level configuration */
\r
5174 #define PWR_CR1_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
\r
5175 #define PWR_CR1_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
\r
5176 #define PWR_CR1_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
\r
5177 #define PWR_CR1_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
\r
5178 #define PWR_CR1_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
\r
5179 #define PWR_CR1_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
\r
5180 #define PWR_CR1_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
\r
5181 #define PWR_CR1_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
\r
5183 #define PWR_CR1_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
\r
5184 #define PWR_CR1_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
\r
5186 #define PWR_CR1_LPUDS ((uint32_t)0x00000400) /*!< Low-power regulator in deepsleep under-drive mode */
\r
5187 #define PWR_CR1_MRUDS ((uint32_t)0x00000800) /*!< Main regulator in deepsleep under-drive mode */
\r
5189 #define PWR_CR1_ADCDC1 ((uint32_t)0x00002000) /*!< Refer to AN4073 on how to use this bit */
\r
5191 #define PWR_CR1_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
\r
5192 #define PWR_CR1_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
\r
5193 #define PWR_CR1_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
\r
5195 #define PWR_CR1_ODEN ((uint32_t)0x00010000) /*!< Over Drive enable */
\r
5196 #define PWR_CR1_ODSWEN ((uint32_t)0x00020000) /*!< Over Drive switch enabled */
\r
5197 #define PWR_CR1_UDEN ((uint32_t)0x000C0000) /*!< Under Drive enable in stop mode */
\r
5198 #define PWR_CR1_UDEN_0 ((uint32_t)0x00040000) /*!< Bit 0 */
\r
5199 #define PWR_CR1_UDEN_1 ((uint32_t)0x00080000) /*!< Bit 1 */
\r
5201 /******************* Bit definition for PWR_CSR1 register ********************/
\r
5202 #define PWR_CSR1_WUIF ((uint32_t)0x00000001) /*!< Wake up internal Flag */
\r
5203 #define PWR_CSR1_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
\r
5204 #define PWR_CSR1_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
\r
5205 #define PWR_CSR1_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */
\r
5206 #define PWR_CSR1_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */
\r
5207 #define PWR_CSR1_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */
\r
5209 #define PWR_CSR1_ODRDY ((uint32_t)0x00010000) /*!< Over Drive generator ready */
\r
5210 #define PWR_CSR1_ODSWRDY ((uint32_t)0x00020000) /*!< Over Drive Switch ready */
\r
5211 #define PWR_CSR1_UDSWRDY ((uint32_t)0x000C0000) /*!< Under Drive ready */
\r
5213 /******************** Bit definition for PWR_CR2 register ********************/
\r
5214 #define PWR_CR2_CWUPF1 ((uint32_t)0x00000001) /*!< Clear Wakeup Pin Flag for PA0 */
\r
5215 #define PWR_CR2_CWUPF2 ((uint32_t)0x00000002) /*!< Clear Wakeup Pin Flag for PA2 */
\r
5216 #define PWR_CR2_CWUPF3 ((uint32_t)0x00000004) /*!< Clear Wakeup Pin Flag for PC1 */
\r
5217 #define PWR_CR2_CWUPF4 ((uint32_t)0x00000008) /*!< Clear Wakeup Pin Flag for PC13 */
\r
5218 #define PWR_CR2_CWUPF5 ((uint32_t)0x00000010) /*!< Clear Wakeup Pin Flag for PI8 */
\r
5219 #define PWR_CR2_CWUPF6 ((uint32_t)0x00000020) /*!< Clear Wakeup Pin Flag for PI11 */
\r
5221 #define PWR_CR2_WUPP1 ((uint32_t)0x00000100) /*!< Wakeup Pin Polarity bit for PA0 */
\r
5222 #define PWR_CR2_WUPP2 ((uint32_t)0x00000200) /*!< Wakeup Pin Polarity bit for PA2 */
\r
5223 #define PWR_CR2_WUPP3 ((uint32_t)0x00000400) /*!< Wakeup Pin Polarity bit for PC1 */
\r
5224 #define PWR_CR2_WUPP4 ((uint32_t)0x00000800) /*!< Wakeup Pin Polarity bit for PC13 */
\r
5225 #define PWR_CR2_WUPP5 ((uint32_t)0x00001000) /*!< Wakeup Pin Polarity bit for PI8 */
\r
5226 #define PWR_CR2_WUPP6 ((uint32_t)0x00002000) /*!< Wakeup Pin Polarity bit for PI11 */
\r
5228 /******************* Bit definition for PWR_CSR2 register ********************/
\r
5229 #define PWR_CSR2_WUPF1 ((uint32_t)0x00000001) /*!< Wakeup Pin Flag for PA0 */
\r
5230 #define PWR_CSR2_WUPF2 ((uint32_t)0x00000002) /*!< Wakeup Pin Flag for PA2 */
\r
5231 #define PWR_CSR2_WUPF3 ((uint32_t)0x00000004) /*!< Wakeup Pin Flag for PC1 */
\r
5232 #define PWR_CSR2_WUPF4 ((uint32_t)0x00000008) /*!< Wakeup Pin Flag for PC13 */
\r
5233 #define PWR_CSR2_WUPF5 ((uint32_t)0x00000010) /*!< Wakeup Pin Flag for PI8 */
\r
5234 #define PWR_CSR2_WUPF6 ((uint32_t)0x00000020) /*!< Wakeup Pin Flag for PI11 */
\r
5236 #define PWR_CSR2_EWUP1 ((uint32_t)0x00000100) /*!< Enable Wakeup Pin PA0 */
\r
5237 #define PWR_CSR2_EWUP2 ((uint32_t)0x00000200) /*!< Enable Wakeup Pin PA2 */
\r
5238 #define PWR_CSR2_EWUP3 ((uint32_t)0x00000400) /*!< Enable Wakeup Pin PC1 */
\r
5239 #define PWR_CSR2_EWUP4 ((uint32_t)0x00000800) /*!< Enable Wakeup Pin PC13 */
\r
5240 #define PWR_CSR2_EWUP5 ((uint32_t)0x00001000) /*!< Enable Wakeup Pin PI8 */
\r
5241 #define PWR_CSR2_EWUP6 ((uint32_t)0x00002000) /*!< Enable Wakeup Pin PI11 */
\r
5243 /******************************************************************************/
\r
5247 /******************************************************************************/
\r
5248 /***************** Bit definition for QUADSPI_CR register *******************/
\r
5249 #define QUADSPI_CR_EN ((uint32_t)0x00000001) /*!< Enable */
\r
5250 #define QUADSPI_CR_ABORT ((uint32_t)0x00000002) /*!< Abort request */
\r
5251 #define QUADSPI_CR_DMAEN ((uint32_t)0x00000004) /*!< DMA Enable */
\r
5252 #define QUADSPI_CR_TCEN ((uint32_t)0x00000008) /*!< Timeout Counter Enable */
\r
5253 #define QUADSPI_CR_SSHIFT ((uint32_t)0x00000010) /*!< Sample Shift */
\r
5254 #define QUADSPI_CR_DFM ((uint32_t)0x00000040) /*!< Dual Flash Mode */
\r
5255 #define QUADSPI_CR_FSEL ((uint32_t)0x00000080) /*!< Flash Select */
\r
5256 #define QUADSPI_CR_FTHRES ((uint32_t)0x00000F00) /*!< FTHRES[3:0] FIFO Level */
\r
5257 #define QUADSPI_CR_FTHRES_0 ((uint32_t)0x00000100) /*!< Bit 0 */
\r
5258 #define QUADSPI_CR_FTHRES_1 ((uint32_t)0x00000200) /*!< Bit 1 */
\r
5259 #define QUADSPI_CR_FTHRES_2 ((uint32_t)0x00000400) /*!< Bit 2 */
\r
5260 #define QUADSPI_CR_FTHRES_3 ((uint32_t)0x00000800) /*!< Bit 3 */
\r
5261 #define QUADSPI_CR_TEIE ((uint32_t)0x00010000) /*!< Transfer Error Interrupt Enable */
\r
5262 #define QUADSPI_CR_TCIE ((uint32_t)0x00020000) /*!< Transfer Complete Interrupt Enable */
\r
5263 #define QUADSPI_CR_FTIE ((uint32_t)0x00040000) /*!< FIFO Threshold Interrupt Enable */
\r
5264 #define QUADSPI_CR_SMIE ((uint32_t)0x00080000) /*!< Status Match Interrupt Enable */
\r
5265 #define QUADSPI_CR_TOIE ((uint32_t)0x00100000) /*!< TimeOut Interrupt Enable */
\r
5266 #define QUADSPI_CR_APMS ((uint32_t)0x00400000) /*!< Bit 1 */
\r
5267 #define QUADSPI_CR_PMM ((uint32_t)0x00800000) /*!< Polling Match Mode */
\r
5268 #define QUADSPI_CR_PRESCALER ((uint32_t)0xFF000000) /*!< PRESCALER[7:0] Clock prescaler */
\r
5269 #define QUADSPI_CR_PRESCALER_0 ((uint32_t)0x01000000) /*!< Bit 0 */
\r
5270 #define QUADSPI_CR_PRESCALER_1 ((uint32_t)0x02000000) /*!< Bit 1 */
\r
5271 #define QUADSPI_CR_PRESCALER_2 ((uint32_t)0x04000000) /*!< Bit 2 */
\r
5272 #define QUADSPI_CR_PRESCALER_3 ((uint32_t)0x08000000) /*!< Bit 3 */
\r
5273 #define QUADSPI_CR_PRESCALER_4 ((uint32_t)0x10000000) /*!< Bit 4 */
\r
5274 #define QUADSPI_CR_PRESCALER_5 ((uint32_t)0x20000000) /*!< Bit 5 */
\r
5275 #define QUADSPI_CR_PRESCALER_6 ((uint32_t)0x40000000) /*!< Bit 6 */
\r
5276 #define QUADSPI_CR_PRESCALER_7 ((uint32_t)0x80000000) /*!< Bit 7 */
\r
5278 /***************** Bit definition for QUADSPI_DCR register ******************/
\r
5279 #define QUADSPI_DCR_CKMODE ((uint32_t)0x00000001) /*!< Mode 0 / Mode 3 */
\r
5280 #define QUADSPI_DCR_CSHT ((uint32_t)0x00000700) /*!< CSHT[2:0]: ChipSelect High Time */
\r
5281 #define QUADSPI_DCR_CSHT_0 ((uint32_t)0x00000100) /*!< Bit 0 */
\r
5282 #define QUADSPI_DCR_CSHT_1 ((uint32_t)0x00000200) /*!< Bit 1 */
\r
5283 #define QUADSPI_DCR_CSHT_2 ((uint32_t)0x00000400) /*!< Bit 2 */
\r
5284 #define QUADSPI_DCR_FSIZE ((uint32_t)0x001F0000) /*!< FSIZE[4:0]: Flash Size */
\r
5285 #define QUADSPI_DCR_FSIZE_0 ((uint32_t)0x00010000) /*!< Bit 0 */
\r
5286 #define QUADSPI_DCR_FSIZE_1 ((uint32_t)0x00020000) /*!< Bit 1 */
\r
5287 #define QUADSPI_DCR_FSIZE_2 ((uint32_t)0x00040000) /*!< Bit 2 */
\r
5288 #define QUADSPI_DCR_FSIZE_3 ((uint32_t)0x00080000) /*!< Bit 3 */
\r
5289 #define QUADSPI_DCR_FSIZE_4 ((uint32_t)0x00100000) /*!< Bit 4 */
\r
5291 /****************** Bit definition for QUADSPI_SR register *******************/
\r
5292 #define QUADSPI_SR_TEF ((uint32_t)0x00000001) /*!< Transfer Error Flag */
\r
5293 #define QUADSPI_SR_TCF ((uint32_t)0x00000002) /*!< Transfer Complete Flag */
\r
5294 #define QUADSPI_SR_FTF ((uint32_t)0x00000004) /*!< FIFO Threshlod Flag */
\r
5295 #define QUADSPI_SR_SMF ((uint32_t)0x00000008) /*!< Status Match Flag */
\r
5296 #define QUADSPI_SR_TOF ((uint32_t)0x00000010) /*!< Timeout Flag */
\r
5297 #define QUADSPI_SR_BUSY ((uint32_t)0x00000020) /*!< Busy */
\r
5298 #define QUADSPI_SR_FLEVEL ((uint32_t)0x00001F00) /*!< FIFO Threshlod Flag */
\r
5299 #define QUADSPI_SR_FLEVEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
\r
5300 #define QUADSPI_SR_FLEVEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
\r
5301 #define QUADSPI_SR_FLEVEL_2 ((uint32_t)0x00000400) /*!< Bit 2 */
\r
5302 #define QUADSPI_SR_FLEVEL_3 ((uint32_t)0x00000800) /*!< Bit 3 */
\r
5303 #define QUADSPI_SR_FLEVEL_4 ((uint32_t)0x00001000) /*!< Bit 4 */
\r
5305 /****************** Bit definition for QUADSPI_FCR register ******************/
\r
5306 #define QUADSPI_FCR_CTEF ((uint32_t)0x00000001) /*!< Clear Transfer Error Flag */
\r
5307 #define QUADSPI_FCR_CTCF ((uint32_t)0x00000002) /*!< Clear Transfer Complete Flag */
\r
5308 #define QUADSPI_FCR_CSMF ((uint32_t)0x00000008) /*!< Clear Status Match Flag */
\r
5309 #define QUADSPI_FCR_CTOF ((uint32_t)0x00000010) /*!< Clear Timeout Flag */
\r
5311 /****************** Bit definition for QUADSPI_DLR register ******************/
\r
5312 #define QUADSPI_DLR_DL ((uint32_t)0xFFFFFFFF) /*!< DL[31:0]: Data Length */
\r
5314 /****************** Bit definition for QUADSPI_CCR register ******************/
\r
5315 #define QUADSPI_CCR_INSTRUCTION ((uint32_t)0x000000FF) /*!< INSTRUCTION[7:0]: Instruction */
\r
5316 #define QUADSPI_CCR_INSTRUCTION_0 ((uint32_t)0x00000001) /*!< Bit 0 */
\r
5317 #define QUADSPI_CCR_INSTRUCTION_1 ((uint32_t)0x00000002) /*!< Bit 1 */
\r
5318 #define QUADSPI_CCR_INSTRUCTION_2 ((uint32_t)0x00000004) /*!< Bit 2 */
\r
5319 #define QUADSPI_CCR_INSTRUCTION_3 ((uint32_t)0x00000008) /*!< Bit 3 */
\r
5320 #define QUADSPI_CCR_INSTRUCTION_4 ((uint32_t)0x00000010) /*!< Bit 4 */
\r
5321 #define QUADSPI_CCR_INSTRUCTION_5 ((uint32_t)0x00000020) /*!< Bit 5 */
\r
5322 #define QUADSPI_CCR_INSTRUCTION_6 ((uint32_t)0x00000040) /*!< Bit 6 */
\r
5323 #define QUADSPI_CCR_INSTRUCTION_7 ((uint32_t)0x00000080) /*!< Bit 7 */
\r
5324 #define QUADSPI_CCR_IMODE ((uint32_t)0x00000300) /*!< IMODE[1:0]: Instruction Mode */
\r
5325 #define QUADSPI_CCR_IMODE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
\r
5326 #define QUADSPI_CCR_IMODE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
\r
5327 #define QUADSPI_CCR_ADMODE ((uint32_t)0x00000C00) /*!< ADMODE[1:0]: Address Mode */
\r
5328 #define QUADSPI_CCR_ADMODE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
\r
5329 #define QUADSPI_CCR_ADMODE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
\r
5330 #define QUADSPI_CCR_ADSIZE ((uint32_t)0x00003000) /*!< ADSIZE[1:0]: Address Size */
\r
5331 #define QUADSPI_CCR_ADSIZE_0 ((uint32_t)0x00001000) /*!< Bit 0 */
\r
5332 #define QUADSPI_CCR_ADSIZE_1 ((uint32_t)0x00002000) /*!< Bit 1 */
\r
5333 #define QUADSPI_CCR_ABMODE ((uint32_t)0x0000C000) /*!< ABMODE[1:0]: Alternate Bytes Mode */
\r
5334 #define QUADSPI_CCR_ABMODE_0 ((uint32_t)0x00004000) /*!< Bit 0 */
\r
5335 #define QUADSPI_CCR_ABMODE_1 ((uint32_t)0x00008000) /*!< Bit 1 */
\r
5336 #define QUADSPI_CCR_ABSIZE ((uint32_t)0x00030000) /*!< ABSIZE[1:0]: Instruction Mode */
\r
5337 #define QUADSPI_CCR_ABSIZE_0 ((uint32_t)0x00010000) /*!< Bit 0 */
\r
5338 #define QUADSPI_CCR_ABSIZE_1 ((uint32_t)0x00020000) /*!< Bit 1 */
\r
5339 #define QUADSPI_CCR_DCYC ((uint32_t)0x007C0000) /*!< DCYC[4:0]: Dummy Cycles */
\r
5340 #define QUADSPI_CCR_DCYC_0 ((uint32_t)0x00040000) /*!< Bit 0 */
\r
5341 #define QUADSPI_CCR_DCYC_1 ((uint32_t)0x00080000) /*!< Bit 1 */
\r
5342 #define QUADSPI_CCR_DCYC_2 ((uint32_t)0x00100000) /*!< Bit 2 */
\r
5343 #define QUADSPI_CCR_DCYC_3 ((uint32_t)0x00200000) /*!< Bit 3 */
\r
5344 #define QUADSPI_CCR_DCYC_4 ((uint32_t)0x00400000) /*!< Bit 4 */
\r
5345 #define QUADSPI_CCR_DMODE ((uint32_t)0x03000000) /*!< DMODE[1:0]: Data Mode */
\r
5346 #define QUADSPI_CCR_DMODE_0 ((uint32_t)0x01000000) /*!< Bit 0 */
\r
5347 #define QUADSPI_CCR_DMODE_1 ((uint32_t)0x02000000) /*!< Bit 1 */
\r
5348 #define QUADSPI_CCR_FMODE ((uint32_t)0x0C000000) /*!< FMODE[1:0]: Functional Mode */
\r
5349 #define QUADSPI_CCR_FMODE_0 ((uint32_t)0x04000000) /*!< Bit 0 */
\r
5350 #define QUADSPI_CCR_FMODE_1 ((uint32_t)0x08000000) /*!< Bit 1 */
\r
5351 #define QUADSPI_CCR_SIOO ((uint32_t)0x10000000) /*!< SIOO: Send Instruction Only Once Mode */
\r
5352 #define QUADSPI_CCR_DHHC ((uint32_t)0x40000000) /*!< DHHC: Delay Half Hclk Cycle */
\r
5353 #define QUADSPI_CCR_DDRM ((uint32_t)0x80000000) /*!< DDRM: Double Data Rate Mode */
\r
5354 /****************** Bit definition for QUADSPI_AR register *******************/
\r
5355 #define QUADSPI_AR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< ADDRESS[31:0]: Address */
\r
5357 /****************** Bit definition for QUADSPI_ABR register ******************/
\r
5358 #define QUADSPI_ABR_ALTERNATE ((uint32_t)0xFFFFFFFF) /*!< ALTERNATE[31:0]: Alternate Bytes */
\r
5360 /****************** Bit definition for QUADSPI_DR register *******************/
\r
5361 #define QUADSPI_DR_DATA ((uint32_t)0xFFFFFFFF) /*!< DATA[31:0]: Data */
\r
5363 /****************** Bit definition for QUADSPI_PSMKR register ****************/
\r
5364 #define QUADSPI_PSMKR_MASK ((uint32_t)0xFFFFFFFF) /*!< MASK[31:0]: Status Mask */
\r
5366 /****************** Bit definition for QUADSPI_PSMAR register ****************/
\r
5367 #define QUADSPI_PSMAR_MATCH ((uint32_t)0xFFFFFFFF) /*!< MATCH[31:0]: Status Match */
\r
5369 /****************** Bit definition for QUADSPI_PIR register *****************/
\r
5370 #define QUADSPI_PIR_INTERVAL ((uint32_t)0x0000FFFF) /*!< INTERVAL[15:0]: Polling Interval */
\r
5372 /****************** Bit definition for QUADSPI_LPTR register *****************/
\r
5373 #define QUADSPI_LPTR_TIMEOUT ((uint32_t)0x0000FFFF) /*!< TIMEOUT[15:0]: Timeout period */
\r
5375 /******************************************************************************/
\r
5377 /* Reset and Clock Control */
\r
5379 /******************************************************************************/
\r
5380 /******************** Bit definition for RCC_CR register ********************/
\r
5381 #define RCC_CR_HSION ((uint32_t)0x00000001)
\r
5382 #define RCC_CR_HSIRDY ((uint32_t)0x00000002)
\r
5384 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
\r
5385 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008) /*!<Bit 0 */
\r
5386 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010) /*!<Bit 1 */
\r
5387 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020) /*!<Bit 2 */
\r
5388 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040) /*!<Bit 3 */
\r
5389 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080) /*!<Bit 4 */
\r
5391 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
\r
5392 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
\r
5393 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
\r
5394 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
\r
5395 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
\r
5396 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
\r
5397 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000) /*!<Bit 5 */
\r
5398 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000) /*!<Bit 6 */
\r
5399 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000) /*!<Bit 7 */
\r
5401 #define RCC_CR_HSEON ((uint32_t)0x00010000)
\r
5402 #define RCC_CR_HSERDY ((uint32_t)0x00020000)
\r
5403 #define RCC_CR_HSEBYP ((uint32_t)0x00040000)
\r
5404 #define RCC_CR_CSSON ((uint32_t)0x00080000)
\r
5405 #define RCC_CR_PLLON ((uint32_t)0x01000000)
\r
5406 #define RCC_CR_PLLRDY ((uint32_t)0x02000000)
\r
5407 #define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
\r
5408 #define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
\r
5409 #define RCC_CR_PLLSAION ((uint32_t)0x10000000)
\r
5410 #define RCC_CR_PLLSAIRDY ((uint32_t)0x20000000)
\r
5412 /******************** Bit definition for RCC_PLLCFGR register ***************/
\r
5413 #define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
\r
5414 #define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
\r
5415 #define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
\r
5416 #define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
\r
5417 #define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
\r
5418 #define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
\r
5419 #define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
\r
5421 #define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
\r
5422 #define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
\r
5423 #define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
\r
5424 #define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
\r
5425 #define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
\r
5426 #define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
\r
5427 #define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
\r
5428 #define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
\r
5429 #define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
\r
5430 #define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
\r
5432 #define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
\r
5433 #define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
\r
5434 #define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
\r
5436 #define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
\r
5437 #define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
\r
5438 #define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
\r
5440 #define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
\r
5441 #define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
\r
5442 #define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
\r
5443 #define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
\r
5444 #define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
\r
5446 /******************** Bit definition for RCC_CFGR register ******************/
\r
5447 /*!< SW configuration */
\r
5448 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
\r
5449 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
\r
5450 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
\r
5452 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
\r
5453 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
\r
5454 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
\r
5456 /*!< SWS configuration */
\r
5457 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
\r
5458 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
\r
5459 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
\r
5461 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
\r
5462 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
\r
5463 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
\r
5465 /*!< HPRE configuration */
\r
5466 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
\r
5467 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
\r
5468 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
\r
5469 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
\r
5470 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
\r
5472 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
\r
5473 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
\r
5474 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
\r
5475 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
\r
5476 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
\r
5477 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
\r
5478 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
\r
5479 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
\r
5480 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
\r
5482 /*!< PPRE1 configuration */
\r
5483 #define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
\r
5484 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
\r
5485 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
\r
5486 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
\r
5488 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
\r
5489 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
\r
5490 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
\r
5491 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
\r
5492 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
\r
5494 /*!< PPRE2 configuration */
\r
5495 #define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
\r
5496 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
\r
5497 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
\r
5498 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
\r
5500 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
\r
5501 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
\r
5502 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
\r
5503 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
\r
5504 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
\r
5506 /*!< RTCPRE configuration */
\r
5507 #define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
\r
5508 #define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
\r
5509 #define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
\r
5510 #define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
\r
5511 #define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
\r
5512 #define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
\r
5514 /*!< MCO1 configuration */
\r
5515 #define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
\r
5516 #define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
\r
5517 #define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
\r
5519 #define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
\r
5521 #define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
\r
5522 #define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
\r
5523 #define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
\r
5524 #define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
\r
5526 #define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
\r
5527 #define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
\r
5528 #define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
\r
5529 #define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
\r
5531 #define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
\r
5532 #define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
\r
5533 #define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
\r
5535 /******************** Bit definition for RCC_CIR register *******************/
\r
5536 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
\r
5537 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
\r
5538 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
\r
5539 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
\r
5540 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
\r
5541 #define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
\r
5542 #define RCC_CIR_PLLSAIRDYF ((uint32_t)0x00000040)
\r
5543 #define RCC_CIR_CSSF ((uint32_t)0x00000080)
\r
5544 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
\r
5545 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
\r
5546 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
\r
5547 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
\r
5548 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
\r
5549 #define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
\r
5550 #define RCC_CIR_PLLSAIRDYIE ((uint32_t)0x00004000)
\r
5551 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
\r
5552 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
\r
5553 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
\r
5554 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
\r
5555 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
\r
5556 #define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
\r
5557 #define RCC_CIR_PLLSAIRDYC ((uint32_t)0x00400000)
\r
5558 #define RCC_CIR_CSSC ((uint32_t)0x00800000)
\r
5560 /******************** Bit definition for RCC_AHB1RSTR register **************/
\r
5561 #define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
\r
5562 #define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
\r
5563 #define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
\r
5564 #define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
\r
5565 #define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
\r
5566 #define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)
\r
5567 #define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)
\r
5568 #define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
\r
5569 #define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100)
\r
5570 #define RCC_AHB1RSTR_GPIOJRST ((uint32_t)0x00000200)
\r
5571 #define RCC_AHB1RSTR_GPIOKRST ((uint32_t)0x00000400)
\r
5572 #define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
\r
5573 #define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
\r
5574 #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
\r
5575 #define RCC_AHB1RSTR_DMA2DRST ((uint32_t)0x00800000)
\r
5576 #define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
\r
5577 #define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x20000000)
\r
5579 /******************** Bit definition for RCC_AHB2RSTR register **************/
\r
5580 #define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
\r
5581 #define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)
\r
5582 #define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
\r
5584 /******************** Bit definition for RCC_AHB3RSTR register **************/
\r
5586 #define RCC_AHB3RSTR_FMCRST ((uint32_t)0x00000001)
\r
5587 #define RCC_AHB3RSTR_QSPIRST ((uint32_t)0x00000002)
\r
5589 /******************** Bit definition for RCC_APB1RSTR register **************/
\r
5590 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
\r
5591 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
\r
5592 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
\r
5593 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
\r
5594 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
\r
5595 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
\r
5596 #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
\r
5597 #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)
\r
5598 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)
\r
5599 #define RCC_APB1RSTR_LPTIM1RST ((uint32_t)0x00000200)
\r
5600 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
\r
5601 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
\r
5602 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
\r
5603 #define RCC_APB1RSTR_SPDIFRXRST ((uint32_t)0x00010000)
\r
5604 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
\r
5605 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)
\r
5606 #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
\r
5607 #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
\r
5608 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
\r
5609 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
\r
5610 #define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
\r
5611 #define RCC_APB1RSTR_I2C4RST ((uint32_t)0x01000000)
\r
5612 #define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)
\r
5613 #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)
\r
5614 #define RCC_APB1RSTR_CECRST ((uint32_t)0x08000000)
\r
5615 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
\r
5616 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
\r
5617 #define RCC_APB1RSTR_UART7RST ((uint32_t)0x40000000)
\r
5618 #define RCC_APB1RSTR_UART8RST ((uint32_t)0x80000000)
\r
5620 /******************** Bit definition for RCC_APB2RSTR register **************/
\r
5621 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
\r
5622 #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)
\r
5623 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
\r
5624 #define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
\r
5625 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
\r
5626 #define RCC_APB2RSTR_SDMMC1RST ((uint32_t)0x00000800)
\r
5627 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
\r
5628 #define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000)
\r
5629 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
\r
5630 #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
\r
5631 #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
\r
5632 #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
\r
5633 #define RCC_APB2RSTR_SPI5RST ((uint32_t)0x00100000)
\r
5634 #define RCC_APB2RSTR_SPI6RST ((uint32_t)0x00200000)
\r
5635 #define RCC_APB2RSTR_SAI1RST ((uint32_t)0x00400000)
\r
5636 #define RCC_APB2RSTR_SAI2RST ((uint32_t)0x00800000)
\r
5637 #define RCC_APB2RSTR_LTDCRST ((uint32_t)0x04000000)
\r
5639 /******************** Bit definition for RCC_AHB1ENR register ***************/
\r
5640 #define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
\r
5641 #define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
\r
5642 #define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
\r
5643 #define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
\r
5644 #define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
\r
5645 #define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)
\r
5646 #define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)
\r
5647 #define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
\r
5648 #define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100)
\r
5649 #define RCC_AHB1ENR_GPIOJEN ((uint32_t)0x00000200)
\r
5650 #define RCC_AHB1ENR_GPIOKEN ((uint32_t)0x00000400)
\r
5651 #define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
\r
5652 #define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
\r
5653 #define RCC_AHB1ENR_DTCMRAMEN ((uint32_t)0x00100000)
\r
5654 #define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
\r
5655 #define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
\r
5656 #define RCC_AHB1ENR_DMA2DEN ((uint32_t)0x00800000)
\r
5657 #define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000)
\r
5658 #define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000)
\r
5659 #define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000)
\r
5660 #define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000)
\r
5661 #define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)
\r
5662 #define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)
\r
5664 /******************** Bit definition for RCC_AHB2ENR register ***************/
\r
5665 #define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001)
\r
5666 #define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)
\r
5667 #define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
\r
5669 /******************** Bit definition for RCC_AHB3ENR register ***************/
\r
5671 #define RCC_AHB3ENR_FMCEN ((uint32_t)0x00000001)
\r
5672 #define RCC_AHB3ENR_QSPIEN ((uint32_t)0x00000002)
\r
5674 /******************** Bit definition for RCC_APB1ENR register ***************/
\r
5675 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
\r
5676 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
\r
5677 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
\r
5678 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
\r
5679 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
\r
5680 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
\r
5681 #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)
\r
5682 #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)
\r
5683 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)
\r
5684 #define RCC_APB1ENR_LPTIM1EN ((uint32_t)0x00000200)
\r
5685 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
\r
5686 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
\r
5687 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
\r
5688 #define RCC_APB1ENR_SPDIFRXEN ((uint32_t)0x00010000)
\r
5689 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
\r
5690 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)
\r
5691 #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
\r
5692 #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
\r
5693 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
\r
5694 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
\r
5695 #define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
\r
5696 #define RCC_APB1ENR_I2C4EN ((uint32_t)0x01000000)
\r
5697 #define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)
\r
5698 #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)
\r
5699 #define RCC_APB1ENR_CECEN ((uint32_t)0x08000000)
\r
5700 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
\r
5701 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
\r
5702 #define RCC_APB1ENR_UART7EN ((uint32_t)0x40000000)
\r
5703 #define RCC_APB1ENR_UART8EN ((uint32_t)0x80000000)
\r
5705 /******************** Bit definition for RCC_APB2ENR register ***************/
\r
5706 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
\r
5707 #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)
\r
5708 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
\r
5709 #define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
\r
5710 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
\r
5711 #define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)
\r
5712 #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)
\r
5713 #define RCC_APB2ENR_SDMMC1EN ((uint32_t)0x00000800)
\r
5714 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
\r
5715 #define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000)
\r
5716 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
\r
5717 #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
\r
5718 #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
\r
5719 #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
\r
5720 #define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000)
\r
5721 #define RCC_APB2ENR_SPI6EN ((uint32_t)0x00200000)
\r
5722 #define RCC_APB2ENR_SAI1EN ((uint32_t)0x00400000)
\r
5723 #define RCC_APB2ENR_SAI2EN ((uint32_t)0x00800000)
\r
5724 #define RCC_APB2ENR_LTDCEN ((uint32_t)0x04000000)
\r
5726 /******************** Bit definition for RCC_AHB1LPENR register *************/
\r
5727 #define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
\r
5728 #define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
\r
5729 #define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
\r
5730 #define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
\r
5731 #define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
\r
5732 #define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)
\r
5733 #define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)
\r
5734 #define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
\r
5735 #define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)
\r
5736 #define RCC_AHB1LPENR_GPIOJLPEN ((uint32_t)0x00000200)
\r
5737 #define RCC_AHB1LPENR_GPIOKLPEN ((uint32_t)0x00000400)
\r
5739 #define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
\r
5740 #define RCC_AHB1LPENR_AXILPEN ((uint32_t)0x00002000)
\r
5741 #define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
\r
5742 #define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
\r
5743 #define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
\r
5744 #define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
\r
5745 #define RCC_AHB1LPENR_DTCMLPEN ((uint32_t)0x00100000)
\r
5746 #define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
\r
5747 #define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
\r
5748 #define RCC_AHB1LPENR_DMA2DLPEN ((uint32_t)0x00800000)
\r
5749 #define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)
\r
5750 #define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000)
\r
5751 #define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000)
\r
5752 #define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000)
\r
5753 #define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)
\r
5754 #define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)
\r
5756 /******************** Bit definition for RCC_AHB2LPENR register *************/
\r
5757 #define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001)
\r
5758 #define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)
\r
5759 #define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
\r
5761 /******************** Bit definition for RCC_AHB3LPENR register *************/
\r
5762 #define RCC_AHB3LPENR_FMCLPEN ((uint32_t)0x00000001)
\r
5763 #define RCC_AHB3LPENR_QSPILPEN ((uint32_t)0x00000002)
\r
5764 /******************** Bit definition for RCC_APB1LPENR register *************/
\r
5765 #define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
\r
5766 #define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
\r
5767 #define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
\r
5768 #define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
\r
5769 #define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)
\r
5770 #define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)
\r
5771 #define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)
\r
5772 #define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)
\r
5773 #define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)
\r
5774 #define RCC_APB1LPENR_LPTIM1LPEN ((uint32_t)0x00000200)
\r
5775 #define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
\r
5776 #define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
\r
5777 #define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
\r
5778 #define RCC_APB1LPENR_SPDIFRXLPEN ((uint32_t)0x00010000)
\r
5779 #define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
\r
5780 #define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)
\r
5781 #define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)
\r
5782 #define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)
\r
5783 #define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
\r
5784 #define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
\r
5785 #define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
\r
5786 #define RCC_APB1LPENR_I2C4LPEN ((uint32_t)0x01000000)
\r
5787 #define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)
\r
5788 #define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)
\r
5789 #define RCC_APB1LPENR_CECLPEN ((uint32_t)0x08000000)
\r
5790 #define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
\r
5791 #define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
\r
5792 #define RCC_APB1LPENR_UART7LPEN ((uint32_t)0x40000000)
\r
5793 #define RCC_APB1LPENR_UART8LPEN ((uint32_t)0x80000000)
\r
5795 /******************** Bit definition for RCC_APB2LPENR register *************/
\r
5796 #define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
\r
5797 #define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)
\r
5798 #define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
\r
5799 #define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
\r
5800 #define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
\r
5801 #define RCC_APB2LPENR_ADC2LPEN ((uint32_t)0x00000200)
\r
5802 #define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)
\r
5803 #define RCC_APB2LPENR_SDMMC1LPEN ((uint32_t)0x00000800)
\r
5804 #define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
\r
5805 #define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000)
\r
5806 #define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
\r
5807 #define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
\r
5808 #define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
\r
5809 #define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
\r
5810 #define RCC_APB2LPENR_SPI5LPEN ((uint32_t)0x00100000)
\r
5811 #define RCC_APB2LPENR_SPI6LPEN ((uint32_t)0x00200000)
\r
5812 #define RCC_APB2LPENR_SAI1LPEN ((uint32_t)0x00400000)
\r
5813 #define RCC_APB2LPENR_SAI2LPEN ((uint32_t)0x00800000)
\r
5814 #define RCC_APB2LPENR_LTDCLPEN ((uint32_t)0x04000000)
\r
5816 /******************** Bit definition for RCC_BDCR register ******************/
\r
5817 #define RCC_BDCR_LSEON ((uint32_t)0x00000001)
\r
5818 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
\r
5819 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
\r
5820 #define RCC_BDCR_LSEDRV ((uint32_t)0x00000018)
\r
5821 #define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008)
\r
5822 #define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010)
\r
5823 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
\r
5824 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
\r
5825 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
\r
5826 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
\r
5827 #define RCC_BDCR_BDRST ((uint32_t)0x00010000)
\r
5829 /******************** Bit definition for RCC_CSR register *******************/
\r
5830 #define RCC_CSR_LSION ((uint32_t)0x00000001)
\r
5831 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
\r
5832 #define RCC_CSR_RMVF ((uint32_t)0x01000000)
\r
5833 #define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
\r
5834 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000)
\r
5835 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
\r
5836 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
\r
5837 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000)
\r
5838 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
\r
5839 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
\r
5841 /******************** Bit definition for RCC_SSCGR register *****************/
\r
5842 #define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
\r
5843 #define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
\r
5844 #define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
\r
5845 #define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
\r
5847 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
\r
5848 #define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
\r
5849 #define RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040)
\r
5850 #define RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080)
\r
5851 #define RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100)
\r
5852 #define RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200)
\r
5853 #define RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400)
\r
5854 #define RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800)
\r
5855 #define RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000)
\r
5856 #define RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000)
\r
5857 #define RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000)
\r
5859 #define RCC_PLLI2SCFGR_PLLI2SP ((uint32_t)0x00030000)
\r
5860 #define RCC_PLLI2SCFGR_PLLI2SP_0 ((uint32_t)0x00010000)
\r
5861 #define RCC_PLLI2SCFGR_PLLI2SP_1 ((uint32_t)0x00020000)
\r
5863 #define RCC_PLLI2SCFGR_PLLI2SQ ((uint32_t)0x0F000000)
\r
5864 #define RCC_PLLI2SCFGR_PLLI2SQ_0 ((uint32_t)0x01000000)
\r
5865 #define RCC_PLLI2SCFGR_PLLI2SQ_1 ((uint32_t)0x02000000)
\r
5866 #define RCC_PLLI2SCFGR_PLLI2SQ_2 ((uint32_t)0x04000000)
\r
5867 #define RCC_PLLI2SCFGR_PLLI2SQ_3 ((uint32_t)0x08000000)
\r
5869 #define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
\r
5870 #define RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000)
\r
5871 #define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000)
\r
5872 #define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000)
\r
5874 /******************** Bit definition for RCC_PLLSAICFGR register ************/
\r
5875 #define RCC_PLLSAICFGR_PLLSAIN ((uint32_t)0x00007FC0)
\r
5876 #define RCC_PLLSAICFGR_PLLSAIN_0 ((uint32_t)0x00000040)
\r
5877 #define RCC_PLLSAICFGR_PLLSAIN_1 ((uint32_t)0x00000080)
\r
5878 #define RCC_PLLSAICFGR_PLLSAIN_2 ((uint32_t)0x00000100)
\r
5879 #define RCC_PLLSAICFGR_PLLSAIN_3 ((uint32_t)0x00000200)
\r
5880 #define RCC_PLLSAICFGR_PLLSAIN_4 ((uint32_t)0x00000400)
\r
5881 #define RCC_PLLSAICFGR_PLLSAIN_5 ((uint32_t)0x00000800)
\r
5882 #define RCC_PLLSAICFGR_PLLSAIN_6 ((uint32_t)0x00001000)
\r
5883 #define RCC_PLLSAICFGR_PLLSAIN_7 ((uint32_t)0x00002000)
\r
5884 #define RCC_PLLSAICFGR_PLLSAIN_8 ((uint32_t)0x00004000)
\r
5886 #define RCC_PLLSAICFGR_PLLSAIP ((uint32_t)0x00030000)
\r
5887 #define RCC_PLLSAICFGR_PLLSAIP_0 ((uint32_t)0x00010000)
\r
5888 #define RCC_PLLSAICFGR_PLLSAIP_1 ((uint32_t)0x00020000)
\r
5890 #define RCC_PLLSAICFGR_PLLSAIQ ((uint32_t)0x0F000000)
\r
5891 #define RCC_PLLSAICFGR_PLLSAIQ_0 ((uint32_t)0x01000000)
\r
5892 #define RCC_PLLSAICFGR_PLLSAIQ_1 ((uint32_t)0x02000000)
\r
5893 #define RCC_PLLSAICFGR_PLLSAIQ_2 ((uint32_t)0x04000000)
\r
5894 #define RCC_PLLSAICFGR_PLLSAIQ_3 ((uint32_t)0x08000000)
\r
5896 #define RCC_PLLSAICFGR_PLLSAIR ((uint32_t)0x70000000)
\r
5897 #define RCC_PLLSAICFGR_PLLSAIR_0 ((uint32_t)0x10000000)
\r
5898 #define RCC_PLLSAICFGR_PLLSAIR_1 ((uint32_t)0x20000000)
\r
5899 #define RCC_PLLSAICFGR_PLLSAIR_2 ((uint32_t)0x40000000)
\r
5901 /******************** Bit definition for RCC_DCKCFGR1 register ***************/
\r
5902 #define RCC_DCKCFGR1_PLLI2SDIVQ ((uint32_t)0x0000001F)
\r
5903 #define RCC_DCKCFGR1_PLLI2SDIVQ_0 ((uint32_t)0x00000001)
\r
5904 #define RCC_DCKCFGR1_PLLI2SDIVQ_1 ((uint32_t)0x00000002)
\r
5905 #define RCC_DCKCFGR1_PLLI2SDIVQ_2 ((uint32_t)0x00000004)
\r
5906 #define RCC_DCKCFGR1_PLLI2SDIVQ_3 ((uint32_t)0x00000008)
\r
5907 #define RCC_DCKCFGR1_PLLI2SDIVQ_4 ((uint32_t)0x00000010)
\r
5909 #define RCC_DCKCFGR1_PLLSAIDIVQ ((uint32_t)0x00001F00)
\r
5910 #define RCC_DCKCFGR1_PLLSAIDIVQ_0 ((uint32_t)0x00000100)
\r
5911 #define RCC_DCKCFGR1_PLLSAIDIVQ_1 ((uint32_t)0x00000200)
\r
5912 #define RCC_DCKCFGR1_PLLSAIDIVQ_2 ((uint32_t)0x00000400)
\r
5913 #define RCC_DCKCFGR1_PLLSAIDIVQ_3 ((uint32_t)0x00000800)
\r
5914 #define RCC_DCKCFGR1_PLLSAIDIVQ_4 ((uint32_t)0x00001000)
\r
5916 #define RCC_DCKCFGR1_PLLSAIDIVR ((uint32_t)0x00030000)
\r
5917 #define RCC_DCKCFGR1_PLLSAIDIVR_0 ((uint32_t)0x00010000)
\r
5918 #define RCC_DCKCFGR1_PLLSAIDIVR_1 ((uint32_t)0x00020000)
\r
5920 #define RCC_DCKCFGR1_SAI1SEL ((uint32_t)0x00300000)
\r
5921 #define RCC_DCKCFGR1_SAI1SEL_0 ((uint32_t)0x00100000)
\r
5922 #define RCC_DCKCFGR1_SAI1SEL_1 ((uint32_t)0x00200000)
\r
5924 #define RCC_DCKCFGR1_SAI2SEL ((uint32_t)0x00C00000)
\r
5925 #define RCC_DCKCFGR1_SAI2SEL_0 ((uint32_t)0x00400000)
\r
5926 #define RCC_DCKCFGR1_SAI2SEL_1 ((uint32_t)0x00800000)
\r
5928 #define RCC_DCKCFGR1_TIMPRE ((uint32_t)0x01000000)
\r
5930 /******************** Bit definition for RCC_DCKCFGR2 register ***************/
\r
5931 #define RCC_DCKCFGR2_USART1SEL ((uint32_t)0x00000003)
\r
5932 #define RCC_DCKCFGR2_USART1SEL_0 ((uint32_t)0x00000001)
\r
5933 #define RCC_DCKCFGR2_USART1SEL_1 ((uint32_t)0x00000002)
\r
5934 #define RCC_DCKCFGR2_USART2SEL ((uint32_t)0x0000000C)
\r
5935 #define RCC_DCKCFGR2_USART2SEL_0 ((uint32_t)0x00000004)
\r
5936 #define RCC_DCKCFGR2_USART2SEL_1 ((uint32_t)0x00000008)
\r
5937 #define RCC_DCKCFGR2_USART3SEL ((uint32_t)0x00000030)
\r
5938 #define RCC_DCKCFGR2_USART3SEL_0 ((uint32_t)0x00000010)
\r
5939 #define RCC_DCKCFGR2_USART3SEL_1 ((uint32_t)0x00000020)
\r
5940 #define RCC_DCKCFGR2_UART4SEL ((uint32_t)0x000000C0)
\r
5941 #define RCC_DCKCFGR2_UART4SEL_0 ((uint32_t)0x00000040)
\r
5942 #define RCC_DCKCFGR2_UART4SEL_1 ((uint32_t)0x00000080)
\r
5943 #define RCC_DCKCFGR2_UART5SEL ((uint32_t)0x00000300)
\r
5944 #define RCC_DCKCFGR2_UART5SEL_0 ((uint32_t)0x00000100)
\r
5945 #define RCC_DCKCFGR2_UART5SEL_1 ((uint32_t)0x00000200)
\r
5946 #define RCC_DCKCFGR2_USART6SEL ((uint32_t)0x00000C00)
\r
5947 #define RCC_DCKCFGR2_USART6SEL_0 ((uint32_t)0x00000400)
\r
5948 #define RCC_DCKCFGR2_USART6SEL_1 ((uint32_t)0x00000800)
\r
5949 #define RCC_DCKCFGR2_UART7SEL ((uint32_t)0x00003000)
\r
5950 #define RCC_DCKCFGR2_UART7SEL_0 ((uint32_t)0x00001000)
\r
5951 #define RCC_DCKCFGR2_UART7SEL_1 ((uint32_t)0x00002000)
\r
5952 #define RCC_DCKCFGR2_UART8SEL ((uint32_t)0x0000C000)
\r
5953 #define RCC_DCKCFGR2_UART8SEL_0 ((uint32_t)0x00004000)
\r
5954 #define RCC_DCKCFGR2_UART8SEL_1 ((uint32_t)0x00008000)
\r
5955 #define RCC_DCKCFGR2_I2C1SEL ((uint32_t)0x00030000)
\r
5956 #define RCC_DCKCFGR2_I2C1SEL_0 ((uint32_t)0x00010000)
\r
5957 #define RCC_DCKCFGR2_I2C1SEL_1 ((uint32_t)0x00020000)
\r
5958 #define RCC_DCKCFGR2_I2C2SEL ((uint32_t)0x000C0000)
\r
5959 #define RCC_DCKCFGR2_I2C2SEL_0 ((uint32_t)0x00040000)
\r
5960 #define RCC_DCKCFGR2_I2C2SEL_1 ((uint32_t)0x00080000)
\r
5961 #define RCC_DCKCFGR2_I2C3SEL ((uint32_t)0x00300000)
\r
5962 #define RCC_DCKCFGR2_I2C3SEL_0 ((uint32_t)0x00100000)
\r
5963 #define RCC_DCKCFGR2_I2C3SEL_1 ((uint32_t)0x00200000)
\r
5964 #define RCC_DCKCFGR2_I2C4SEL ((uint32_t)0x00C00000)
\r
5965 #define RCC_DCKCFGR2_I2C4SEL_0 ((uint32_t)0x00400000)
\r
5966 #define RCC_DCKCFGR2_I2C4SEL_1 ((uint32_t)0x00800000)
\r
5967 #define RCC_DCKCFGR2_LPTIM1SEL ((uint32_t)0x03000000)
\r
5968 #define RCC_DCKCFGR2_LPTIM1SEL_0 ((uint32_t)0x01000000)
\r
5969 #define RCC_DCKCFGR2_LPTIM1SEL_1 ((uint32_t)0x02000000)
\r
5970 #define RCC_DCKCFGR2_CECSEL ((uint32_t)0x04000000)
\r
5971 #define RCC_DCKCFGR2_CK48MSEL ((uint32_t)0x08000000)
\r
5972 #define RCC_DCKCFGR2_SDMMC1SEL ((uint32_t)0x10000000)
\r
5974 /******************************************************************************/
\r
5978 /******************************************************************************/
\r
5979 /******************** Bits definition for RNG_CR register *******************/
\r
5980 #define RNG_CR_RNGEN ((uint32_t)0x00000004)
\r
5981 #define RNG_CR_IE ((uint32_t)0x00000008)
\r
5983 /******************** Bits definition for RNG_SR register *******************/
\r
5984 #define RNG_SR_DRDY ((uint32_t)0x00000001)
\r
5985 #define RNG_SR_CECS ((uint32_t)0x00000002)
\r
5986 #define RNG_SR_SECS ((uint32_t)0x00000004)
\r
5987 #define RNG_SR_CEIS ((uint32_t)0x00000020)
\r
5988 #define RNG_SR_SEIS ((uint32_t)0x00000040)
\r
5990 /******************************************************************************/
\r
5992 /* Real-Time Clock (RTC) */
\r
5994 /******************************************************************************/
\r
5995 /******************** Bits definition for RTC_TR register *******************/
\r
5996 #define RTC_TR_PM ((uint32_t)0x00400000)
\r
5997 #define RTC_TR_HT ((uint32_t)0x00300000)
\r
5998 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
\r
5999 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
\r
6000 #define RTC_TR_HU ((uint32_t)0x000F0000)
\r
6001 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
\r
6002 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
\r
6003 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
\r
6004 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
\r
6005 #define RTC_TR_MNT ((uint32_t)0x00007000)
\r
6006 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
\r
6007 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
\r
6008 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
\r
6009 #define RTC_TR_MNU ((uint32_t)0x00000F00)
\r
6010 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
\r
6011 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
\r
6012 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
\r
6013 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
\r
6014 #define RTC_TR_ST ((uint32_t)0x00000070)
\r
6015 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
\r
6016 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
\r
6017 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
\r
6018 #define RTC_TR_SU ((uint32_t)0x0000000F)
\r
6019 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
\r
6020 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
\r
6021 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
\r
6022 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
\r
6024 /******************** Bits definition for RTC_DR register *******************/
\r
6025 #define RTC_DR_YT ((uint32_t)0x00F00000)
\r
6026 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
\r
6027 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
\r
6028 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
\r
6029 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
\r
6030 #define RTC_DR_YU ((uint32_t)0x000F0000)
\r
6031 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
\r
6032 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
\r
6033 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
\r
6034 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
\r
6035 #define RTC_DR_WDU ((uint32_t)0x0000E000)
\r
6036 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
\r
6037 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
\r
6038 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
\r
6039 #define RTC_DR_MT ((uint32_t)0x00001000)
\r
6040 #define RTC_DR_MU ((uint32_t)0x00000F00)
\r
6041 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
\r
6042 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
\r
6043 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
\r
6044 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
\r
6045 #define RTC_DR_DT ((uint32_t)0x00000030)
\r
6046 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
\r
6047 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
\r
6048 #define RTC_DR_DU ((uint32_t)0x0000000F)
\r
6049 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
\r
6050 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
\r
6051 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
\r
6052 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
\r
6054 /******************** Bits definition for RTC_CR register *******************/
\r
6055 #define RTC_CR_ITSE ((uint32_t)0x01000000)
\r
6056 #define RTC_CR_COE ((uint32_t)0x00800000)
\r
6057 #define RTC_CR_OSEL ((uint32_t)0x00600000)
\r
6058 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
\r
6059 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
\r
6060 #define RTC_CR_POL ((uint32_t)0x00100000)
\r
6061 #define RTC_CR_COSEL ((uint32_t)0x00080000)
\r
6062 #define RTC_CR_BCK ((uint32_t)0x00040000)
\r
6063 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
\r
6064 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
\r
6065 #define RTC_CR_TSIE ((uint32_t)0x00008000)
\r
6066 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
\r
6067 #define RTC_CR_ALRBIE ((uint32_t)0x00002000)
\r
6068 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
\r
6069 #define RTC_CR_TSE ((uint32_t)0x00000800)
\r
6070 #define RTC_CR_WUTE ((uint32_t)0x00000400)
\r
6071 #define RTC_CR_ALRBE ((uint32_t)0x00000200)
\r
6072 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
\r
6073 #define RTC_CR_FMT ((uint32_t)0x00000040)
\r
6074 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
\r
6075 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
\r
6076 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
\r
6077 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
\r
6078 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
\r
6079 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
\r
6080 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
\r
6082 /******************** Bits definition for RTC_ISR register ******************/
\r
6083 #define RTC_ISR_ITSF ((uint32_t)0x00020000)
\r
6084 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
\r
6085 #define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
\r
6086 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
\r
6087 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
\r
6088 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
\r
6089 #define RTC_ISR_TSF ((uint32_t)0x00000800)
\r
6090 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
\r
6091 #define RTC_ISR_ALRBF ((uint32_t)0x00000200)
\r
6092 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
\r
6093 #define RTC_ISR_INIT ((uint32_t)0x00000080)
\r
6094 #define RTC_ISR_INITF ((uint32_t)0x00000040)
\r
6095 #define RTC_ISR_RSF ((uint32_t)0x00000020)
\r
6096 #define RTC_ISR_INITS ((uint32_t)0x00000010)
\r
6097 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
\r
6098 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
\r
6099 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
\r
6100 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
\r
6102 /******************** Bits definition for RTC_PRER register *****************/
\r
6103 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
\r
6104 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
\r
6106 /******************** Bits definition for RTC_WUTR register *****************/
\r
6107 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
\r
6109 /******************** Bits definition for RTC_ALRMAR register ***************/
\r
6110 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
\r
6111 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
\r
6112 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
\r
6113 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
\r
6114 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
\r
6115 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
\r
6116 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
\r
6117 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
\r
6118 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
\r
6119 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
\r
6120 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
\r
6121 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
\r
6122 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
\r
6123 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
\r
6124 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
\r
6125 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
\r
6126 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
\r
6127 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
\r
6128 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
\r
6129 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
\r
6130 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
\r
6131 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
\r
6132 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
\r
6133 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
\r
6134 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
\r
6135 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
\r
6136 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
\r
6137 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
\r
6138 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
\r
6139 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
\r
6140 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
\r
6141 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
\r
6142 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
\r
6143 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
\r
6144 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
\r
6145 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
\r
6146 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
\r
6147 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
\r
6148 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
\r
6149 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
\r
6151 /******************** Bits definition for RTC_ALRMBR register ***************/
\r
6152 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
\r
6153 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
\r
6154 #define RTC_ALRMBR_DT ((uint32_t)0x30000000)
\r
6155 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
\r
6156 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
\r
6157 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
\r
6158 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
\r
6159 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
\r
6160 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
\r
6161 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
\r
6162 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
\r
6163 #define RTC_ALRMBR_PM ((uint32_t)0x00400000)
\r
6164 #define RTC_ALRMBR_HT ((uint32_t)0x00300000)
\r
6165 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
\r
6166 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
\r
6167 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
\r
6168 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
\r
6169 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
\r
6170 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
\r
6171 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
\r
6172 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
\r
6173 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
\r
6174 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
\r
6175 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
\r
6176 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
\r
6177 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
\r
6178 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
\r
6179 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
\r
6180 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
\r
6181 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
\r
6182 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
\r
6183 #define RTC_ALRMBR_ST ((uint32_t)0x00000070)
\r
6184 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
\r
6185 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
\r
6186 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
\r
6187 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
\r
6188 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
\r
6189 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
\r
6190 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
\r
6191 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
\r
6193 /******************** Bits definition for RTC_WPR register ******************/
\r
6194 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
\r
6196 /******************** Bits definition for RTC_SSR register ******************/
\r
6197 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
\r
6199 /******************** Bits definition for RTC_SHIFTR register ***************/
\r
6200 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
\r
6201 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
\r
6203 /******************** Bits definition for RTC_TSTR register *****************/
\r
6204 #define RTC_TSTR_PM ((uint32_t)0x00400000)
\r
6205 #define RTC_TSTR_HT ((uint32_t)0x00300000)
\r
6206 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
\r
6207 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
\r
6208 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
\r
6209 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
\r
6210 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
\r
6211 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
\r
6212 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
\r
6213 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
\r
6214 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
\r
6215 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
\r
6216 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
\r
6217 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
\r
6218 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
\r
6219 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
\r
6220 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
\r
6221 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
\r
6222 #define RTC_TSTR_ST ((uint32_t)0x00000070)
\r
6223 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
\r
6224 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
\r
6225 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
\r
6226 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
\r
6227 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
\r
6228 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
\r
6229 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
\r
6230 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
\r
6232 /******************** Bits definition for RTC_TSDR register *****************/
\r
6233 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
\r
6234 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
\r
6235 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
\r
6236 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
\r
6237 #define RTC_TSDR_MT ((uint32_t)0x00001000)
\r
6238 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
\r
6239 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
\r
6240 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
\r
6241 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
\r
6242 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
\r
6243 #define RTC_TSDR_DT ((uint32_t)0x00000030)
\r
6244 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
\r
6245 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
\r
6246 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
\r
6247 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
\r
6248 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
\r
6249 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
\r
6250 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
\r
6252 /******************** Bits definition for RTC_TSSSR register ****************/
\r
6253 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
\r
6255 /******************** Bits definition for RTC_CAL register *****************/
\r
6256 #define RTC_CALR_CALP ((uint32_t)0x00008000)
\r
6257 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
\r
6258 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
\r
6259 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
\r
6260 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
\r
6261 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
\r
6262 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
\r
6263 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
\r
6264 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
\r
6265 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
\r
6266 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
\r
6267 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
\r
6268 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
\r
6270 /******************** Bits definition for RTC_TAMPCR register ****************/
\r
6271 #define RTC_TAMPCR_TAMP3MF ((uint32_t)0x01000000)
\r
6272 #define RTC_TAMPCR_TAMP3NOERASE ((uint32_t)0x00800000)
\r
6273 #define RTC_TAMPCR_TAMP3IE ((uint32_t)0x00400000)
\r
6274 #define RTC_TAMPCR_TAMP2MF ((uint32_t)0x00200000)
\r
6275 #define RTC_TAMPCR_TAMP2NOERASE ((uint32_t)0x00100000)
\r
6276 #define RTC_TAMPCR_TAMP2IE ((uint32_t)0x00080000)
\r
6277 #define RTC_TAMPCR_TAMP1MF ((uint32_t)0x00040000)
\r
6278 #define RTC_TAMPCR_TAMP1NOERASE ((uint32_t)0x00020000)
\r
6279 #define RTC_TAMPCR_TAMP1IE ((uint32_t)0x00010000)
\r
6280 #define RTC_TAMPCR_TAMPPUDIS ((uint32_t)0x00008000)
\r
6281 #define RTC_TAMPCR_TAMPPRCH ((uint32_t)0x00006000)
\r
6282 #define RTC_TAMPCR_TAMPPRCH_0 ((uint32_t)0x00002000)
\r
6283 #define RTC_TAMPCR_TAMPPRCH_1 ((uint32_t)0x00004000)
\r
6284 #define RTC_TAMPCR_TAMPFLT ((uint32_t)0x00001800)
\r
6285 #define RTC_TAMPCR_TAMPFLT_0 ((uint32_t)0x00000800)
\r
6286 #define RTC_TAMPCR_TAMPFLT_1 ((uint32_t)0x00001000)
\r
6287 #define RTC_TAMPCR_TAMPFREQ ((uint32_t)0x00000700)
\r
6288 #define RTC_TAMPCR_TAMPFREQ_0 ((uint32_t)0x00000100)
\r
6289 #define RTC_TAMPCR_TAMPFREQ_1 ((uint32_t)0x00000200)
\r
6290 #define RTC_TAMPCR_TAMPFREQ_2 ((uint32_t)0x00000400)
\r
6291 #define RTC_TAMPCR_TAMPTS ((uint32_t)0x00000080)
\r
6292 #define RTC_TAMPCR_TAMP3_TRG ((uint32_t)0x00000040)
\r
6293 #define RTC_TAMPCR_TAMP3E ((uint32_t)0x00000020)
\r
6294 #define RTC_TAMPCR_TAMP2_TRG ((uint32_t)0x00000010)
\r
6295 #define RTC_TAMPCR_TAMP2E ((uint32_t)0x00000008)
\r
6296 #define RTC_TAMPCR_TAMPIE ((uint32_t)0x00000004)
\r
6297 #define RTC_TAMPCR_TAMP1_TRG ((uint32_t)0x00000002)
\r
6298 #define RTC_TAMPCR_TAMP1E ((uint32_t)0x00000001)
\r
6300 /******************** Bits definition for RTC_ALRMASSR register *************/
\r
6301 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
\r
6302 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
\r
6303 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
\r
6304 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
\r
6305 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
\r
6306 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
\r
6308 /******************** Bits definition for RTC_ALRMBSSR register *************/
\r
6309 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
\r
6310 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
\r
6311 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
\r
6312 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
\r
6313 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
\r
6314 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
\r
6316 /******************** Bits definition for RTC_OR register ****************/
\r
6317 #define RTC_OR_TSINSEL ((uint32_t)0x00000006)
\r
6318 #define RTC_OR_TSINSEL_0 ((uint32_t)0x00000002)
\r
6319 #define RTC_OR_TSINSEL_1 ((uint32_t)0x00000004)
\r
6320 #define RTC_OR_ALARMTYPE ((uint32_t)0x00000008)
\r
6323 /******************** Bits definition for RTC_BKP0R register ****************/
\r
6324 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
\r
6326 /******************** Bits definition for RTC_BKP1R register ****************/
\r
6327 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
\r
6329 /******************** Bits definition for RTC_BKP2R register ****************/
\r
6330 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
\r
6332 /******************** Bits definition for RTC_BKP3R register ****************/
\r
6333 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
\r
6335 /******************** Bits definition for RTC_BKP4R register ****************/
\r
6336 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
\r
6338 /******************** Bits definition for RTC_BKP5R register ****************/
\r
6339 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
\r
6341 /******************** Bits definition for RTC_BKP6R register ****************/
\r
6342 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
\r
6344 /******************** Bits definition for RTC_BKP7R register ****************/
\r
6345 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
\r
6347 /******************** Bits definition for RTC_BKP8R register ****************/
\r
6348 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
\r
6350 /******************** Bits definition for RTC_BKP9R register ****************/
\r
6351 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
\r
6353 /******************** Bits definition for RTC_BKP10R register ***************/
\r
6354 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
\r
6356 /******************** Bits definition for RTC_BKP11R register ***************/
\r
6357 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
\r
6359 /******************** Bits definition for RTC_BKP12R register ***************/
\r
6360 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
\r
6362 /******************** Bits definition for RTC_BKP13R register ***************/
\r
6363 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
\r
6365 /******************** Bits definition for RTC_BKP14R register ***************/
\r
6366 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
\r
6368 /******************** Bits definition for RTC_BKP15R register ***************/
\r
6369 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
\r
6371 /******************** Bits definition for RTC_BKP16R register ***************/
\r
6372 #define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
\r
6374 /******************** Bits definition for RTC_BKP17R register ***************/
\r
6375 #define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
\r
6377 /******************** Bits definition for RTC_BKP18R register ***************/
\r
6378 #define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
\r
6380 /******************** Bits definition for RTC_BKP19R register ***************/
\r
6381 #define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
\r
6383 /******************** Bits definition for RTC_BKP20R register ***************/
\r
6384 #define RTC_BKP20R ((uint32_t)0xFFFFFFFF)
\r
6386 /******************** Bits definition for RTC_BKP21R register ***************/
\r
6387 #define RTC_BKP21R ((uint32_t)0xFFFFFFFF)
\r
6389 /******************** Bits definition for RTC_BKP22R register ***************/
\r
6390 #define RTC_BKP22R ((uint32_t)0xFFFFFFFF)
\r
6392 /******************** Bits definition for RTC_BKP23R register ***************/
\r
6393 #define RTC_BKP23R ((uint32_t)0xFFFFFFFF)
\r
6395 /******************** Bits definition for RTC_BKP24R register ***************/
\r
6396 #define RTC_BKP24R ((uint32_t)0xFFFFFFFF)
\r
6398 /******************** Bits definition for RTC_BKP25R register ***************/
\r
6399 #define RTC_BKP25R ((uint32_t)0xFFFFFFFF)
\r
6401 /******************** Bits definition for RTC_BKP26R register ***************/
\r
6402 #define RTC_BKP26R ((uint32_t)0xFFFFFFFF)
\r
6404 /******************** Bits definition for RTC_BKP27R register ***************/
\r
6405 #define RTC_BKP27R ((uint32_t)0xFFFFFFFF)
\r
6407 /******************** Bits definition for RTC_BKP28R register ***************/
\r
6408 #define RTC_BKP28R ((uint32_t)0xFFFFFFFF)
\r
6410 /******************** Bits definition for RTC_BKP29R register ***************/
\r
6411 #define RTC_BKP29R ((uint32_t)0xFFFFFFFF)
\r
6413 /******************** Bits definition for RTC_BKP30R register ***************/
\r
6414 #define RTC_BKP30R ((uint32_t)0xFFFFFFFF)
\r
6416 /******************** Bits definition for RTC_BKP31R register ***************/
\r
6417 #define RTC_BKP31R ((uint32_t)0xFFFFFFFF)
\r
6419 /******************** Number of backup registers ******************************/
\r
6420 #define RTC_BKP_NUMBER ((uint32_t)0x00000020)
\r
6423 /******************************************************************************/
\r
6425 /* Serial Audio Interface */
\r
6427 /******************************************************************************/
\r
6428 /******************** Bit definition for SAI_GCR register *******************/
\r
6429 #define SAI_GCR_SYNCIN ((uint32_t)0x00000003) /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
\r
6430 #define SAI_GCR_SYNCIN_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
6431 #define SAI_GCR_SYNCIN_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
6433 #define SAI_GCR_SYNCOUT ((uint32_t)0x00000030) /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
\r
6434 #define SAI_GCR_SYNCOUT_0 ((uint32_t)0x00000010) /*!<Bit 0 */
\r
6435 #define SAI_GCR_SYNCOUT_1 ((uint32_t)0x00000020) /*!<Bit 1 */
\r
6437 /******************* Bit definition for SAI_xCR1 register *******************/
\r
6438 #define SAI_xCR1_MODE ((uint32_t)0x00000003) /*!<MODE[1:0] bits (Audio Block Mode) */
\r
6439 #define SAI_xCR1_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
6440 #define SAI_xCR1_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
6442 #define SAI_xCR1_PRTCFG ((uint32_t)0x0000000C) /*!<PRTCFG[1:0] bits (Protocol Configuration) */
\r
6443 #define SAI_xCR1_PRTCFG_0 ((uint32_t)0x00000004) /*!<Bit 0 */
\r
6444 #define SAI_xCR1_PRTCFG_1 ((uint32_t)0x00000008) /*!<Bit 1 */
\r
6446 #define SAI_xCR1_DS ((uint32_t)0x000000E0) /*!<DS[1:0] bits (Data Size) */
\r
6447 #define SAI_xCR1_DS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
\r
6448 #define SAI_xCR1_DS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
\r
6449 #define SAI_xCR1_DS_2 ((uint32_t)0x00000080) /*!<Bit 2 */
\r
6451 #define SAI_xCR1_LSBFIRST ((uint32_t)0x00000100) /*!<LSB First Configuration */
\r
6452 #define SAI_xCR1_CKSTR ((uint32_t)0x00000200) /*!<ClocK STRobing edge */
\r
6454 #define SAI_xCR1_SYNCEN ((uint32_t)0x00000C00) /*!<SYNCEN[1:0](SYNChronization ENable) */
\r
6455 #define SAI_xCR1_SYNCEN_0 ((uint32_t)0x00000400) /*!<Bit 0 */
\r
6456 #define SAI_xCR1_SYNCEN_1 ((uint32_t)0x00000800) /*!<Bit 1 */
\r
6458 #define SAI_xCR1_MONO ((uint32_t)0x00001000) /*!<Mono mode */
\r
6459 #define SAI_xCR1_OUTDRIV ((uint32_t)0x00002000) /*!<Output Drive */
\r
6460 #define SAI_xCR1_SAIEN ((uint32_t)0x00010000) /*!<Audio Block enable */
\r
6461 #define SAI_xCR1_DMAEN ((uint32_t)0x00020000) /*!<DMA enable */
\r
6462 #define SAI_xCR1_NODIV ((uint32_t)0x00080000) /*!<No Divider Configuration */
\r
6464 #define SAI_xCR1_MCKDIV ((uint32_t)0x00F00000) /*!<MCKDIV[3:0] (Master ClocK Divider) */
\r
6465 #define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
\r
6466 #define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
\r
6467 #define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
\r
6468 #define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
\r
6470 /******************* Bit definition for SAI_xCR2 register *******************/
\r
6471 #define SAI_xCR2_FTH ((uint32_t)0x00000007) /*!<FTH[2:0](Fifo THreshold) */
\r
6472 #define SAI_xCR2_FTH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
6473 #define SAI_xCR2_FTH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
6474 #define SAI_xCR2_FTH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
6476 #define SAI_xCR2_FFLUSH ((uint32_t)0x00000008) /*!<Fifo FLUSH */
\r
6477 #define SAI_xCR2_TRIS ((uint32_t)0x00000010) /*!<TRIState Management on data line */
\r
6478 #define SAI_xCR2_MUTE ((uint32_t)0x00000020) /*!<Mute mode */
\r
6479 #define SAI_xCR2_MUTEVAL ((uint32_t)0x00000040) /*!<Muate value */
\r
6481 #define SAI_xCR2_MUTECNT ((uint32_t)0x00001F80) /*!<MUTECNT[5:0] (MUTE counter) */
\r
6482 #define SAI_xCR2_MUTECNT_0 ((uint32_t)0x00000080) /*!<Bit 0 */
\r
6483 #define SAI_xCR2_MUTECNT_1 ((uint32_t)0x00000100) /*!<Bit 1 */
\r
6484 #define SAI_xCR2_MUTECNT_2 ((uint32_t)0x00000200) /*!<Bit 2 */
\r
6485 #define SAI_xCR2_MUTECNT_3 ((uint32_t)0x00000400) /*!<Bit 3 */
\r
6486 #define SAI_xCR2_MUTECNT_4 ((uint32_t)0x00000800) /*!<Bit 4 */
\r
6487 #define SAI_xCR2_MUTECNT_5 ((uint32_t)0x00001000) /*!<Bit 5 */
\r
6489 #define SAI_xCR2_CPL ((uint32_t)0x00080000) /*!< Complement Bit */
\r
6491 #define SAI_xCR2_COMP ((uint32_t)0x0000C000) /*!<COMP[1:0] (Companding mode) */
\r
6492 #define SAI_xCR2_COMP_0 ((uint32_t)0x00004000) /*!<Bit 0 */
\r
6493 #define SAI_xCR2_COMP_1 ((uint32_t)0x00008000) /*!<Bit 1 */
\r
6495 /****************** Bit definition for SAI_xFRCR register *******************/
\r
6496 #define SAI_xFRCR_FRL ((uint32_t)0x000000FF) /*!<FRL[1:0](Frame length) */
\r
6497 #define SAI_xFRCR_FRL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
6498 #define SAI_xFRCR_FRL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
6499 #define SAI_xFRCR_FRL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
6500 #define SAI_xFRCR_FRL_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
6501 #define SAI_xFRCR_FRL_4 ((uint32_t)0x00000010) /*!<Bit 4 */
\r
6502 #define SAI_xFRCR_FRL_5 ((uint32_t)0x00000020) /*!<Bit 5 */
\r
6503 #define SAI_xFRCR_FRL_6 ((uint32_t)0x00000040) /*!<Bit 6 */
\r
6504 #define SAI_xFRCR_FRL_7 ((uint32_t)0x00000080) /*!<Bit 7 */
\r
6506 #define SAI_xFRCR_FSALL ((uint32_t)0x00007F00) /*!<FRL[1:0] (Frame synchronization active level length) */
\r
6507 #define SAI_xFRCR_FSALL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
\r
6508 #define SAI_xFRCR_FSALL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
\r
6509 #define SAI_xFRCR_FSALL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
\r
6510 #define SAI_xFRCR_FSALL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
\r
6511 #define SAI_xFRCR_FSALL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
\r
6512 #define SAI_xFRCR_FSALL_5 ((uint32_t)0x00002000) /*!<Bit 5 */
\r
6513 #define SAI_xFRCR_FSALL_6 ((uint32_t)0x00004000) /*!<Bit 6 */
\r
6515 #define SAI_xFRCR_FSDEF ((uint32_t)0x00010000) /*!< Frame Synchronization Definition */
\r
6516 #define SAI_xFRCR_FSPO ((uint32_t)0x00020000) /*!<Frame Synchronization POLarity */
\r
6517 #define SAI_xFRCR_FSOFF ((uint32_t)0x00040000) /*!<Frame Synchronization OFFset */
\r
6519 /****************** Bit definition for SAI_xSLOTR register *******************/
\r
6520 #define SAI_xSLOTR_FBOFF ((uint32_t)0x0000001F) /*!<FRL[4:0](First Bit Offset) */
\r
6521 #define SAI_xSLOTR_FBOFF_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
6522 #define SAI_xSLOTR_FBOFF_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
6523 #define SAI_xSLOTR_FBOFF_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
6524 #define SAI_xSLOTR_FBOFF_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
6525 #define SAI_xSLOTR_FBOFF_4 ((uint32_t)0x00000010) /*!<Bit 4 */
\r
6527 #define SAI_xSLOTR_SLOTSZ ((uint32_t)0x000000C0) /*!<SLOTSZ[1:0] (Slot size) */
\r
6528 #define SAI_xSLOTR_SLOTSZ_0 ((uint32_t)0x00000040) /*!<Bit 0 */
\r
6529 #define SAI_xSLOTR_SLOTSZ_1 ((uint32_t)0x00000080) /*!<Bit 1 */
\r
6531 #define SAI_xSLOTR_NBSLOT ((uint32_t)0x00000F00) /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
\r
6532 #define SAI_xSLOTR_NBSLOT_0 ((uint32_t)0x00000100) /*!<Bit 0 */
\r
6533 #define SAI_xSLOTR_NBSLOT_1 ((uint32_t)0x00000200) /*!<Bit 1 */
\r
6534 #define SAI_xSLOTR_NBSLOT_2 ((uint32_t)0x00000400) /*!<Bit 2 */
\r
6535 #define SAI_xSLOTR_NBSLOT_3 ((uint32_t)0x00000800) /*!<Bit 3 */
\r
6537 #define SAI_xSLOTR_SLOTEN ((uint32_t)0xFFFF0000) /*!<SLOTEN[15:0] (Slot Enable) */
\r
6539 /******************* Bit definition for SAI_xIMR register *******************/
\r
6540 #define SAI_xIMR_OVRUDRIE ((uint32_t)0x00000001) /*!<Overrun underrun interrupt enable */
\r
6541 #define SAI_xIMR_MUTEDETIE ((uint32_t)0x00000002) /*!<Mute detection interrupt enable */
\r
6542 #define SAI_xIMR_WCKCFGIE ((uint32_t)0x00000004) /*!<Wrong Clock Configuration interrupt enable */
\r
6543 #define SAI_xIMR_FREQIE ((uint32_t)0x00000008) /*!<FIFO request interrupt enable */
\r
6544 #define SAI_xIMR_CNRDYIE ((uint32_t)0x00000010) /*!<Codec not ready interrupt enable */
\r
6545 #define SAI_xIMR_AFSDETIE ((uint32_t)0x00000020) /*!<Anticipated frame synchronization detection interrupt enable */
\r
6546 #define SAI_xIMR_LFSDETIE ((uint32_t)0x00000040) /*!<Late frame synchronization detection interrupt enable */
\r
6548 /******************** Bit definition for SAI_xSR register *******************/
\r
6549 #define SAI_xSR_OVRUDR ((uint32_t)0x00000001) /*!<Overrun underrun */
\r
6550 #define SAI_xSR_MUTEDET ((uint32_t)0x00000002) /*!<Mute detection */
\r
6551 #define SAI_xSR_WCKCFG ((uint32_t)0x00000004) /*!<Wrong Clock Configuration */
\r
6552 #define SAI_xSR_FREQ ((uint32_t)0x00000008) /*!<FIFO request */
\r
6553 #define SAI_xSR_CNRDY ((uint32_t)0x00000010) /*!<Codec not ready */
\r
6554 #define SAI_xSR_AFSDET ((uint32_t)0x00000020) /*!<Anticipated frame synchronization detection */
\r
6555 #define SAI_xSR_LFSDET ((uint32_t)0x00000040) /*!<Late frame synchronization detection */
\r
6557 #define SAI_xSR_FLVL ((uint32_t)0x00070000) /*!<FLVL[2:0] (FIFO Level Threshold) */
\r
6558 #define SAI_xSR_FLVL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
\r
6559 #define SAI_xSR_FLVL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
\r
6560 #define SAI_xSR_FLVL_2 ((uint32_t)0x00030000) /*!<Bit 2 */
\r
6562 /****************** Bit definition for SAI_xCLRFR register ******************/
\r
6563 #define SAI_xCLRFR_COVRUDR ((uint32_t)0x00000001) /*!<Clear Overrun underrun */
\r
6564 #define SAI_xCLRFR_CMUTEDET ((uint32_t)0x00000002) /*!<Clear Mute detection */
\r
6565 #define SAI_xCLRFR_CWCKCFG ((uint32_t)0x00000004) /*!<Clear Wrong Clock Configuration */
\r
6566 #define SAI_xCLRFR_CFREQ ((uint32_t)0x00000008) /*!<Clear FIFO request */
\r
6567 #define SAI_xCLRFR_CCNRDY ((uint32_t)0x00000010) /*!<Clear Codec not ready */
\r
6568 #define SAI_xCLRFR_CAFSDET ((uint32_t)0x00000020) /*!<Clear Anticipated frame synchronization detection */
\r
6569 #define SAI_xCLRFR_CLFSDET ((uint32_t)0x00000040) /*!<Clear Late frame synchronization detection */
\r
6571 /****************** Bit definition for SAI_xDR register *********************/
\r
6572 #define SAI_xDR_DATA ((uint32_t)0xFFFFFFFF)
\r
6574 /******************************************************************************/
\r
6576 /* SPDIF-RX Interface */
\r
6578 /******************************************************************************/
\r
6579 /******************** Bit definition for SPDIF_CR register *******************/
\r
6580 #define SPDIFRX_CR_SPDIFEN ((uint32_t)0x00000003) /*!<Peripheral Block Enable */
\r
6581 #define SPDIFRX_CR_RXDMAEN ((uint32_t)0x00000004) /*!<Receiver DMA Enable for data flow */
\r
6582 #define SPDIFRX_CR_RXSTEO ((uint32_t)0x00000008) /*!<Stereo Mode */
\r
6583 #define SPDIFRX_CR_DRFMT ((uint32_t)0x00000030) /*!<RX Data format */
\r
6584 #define SPDIFRX_CR_PMSK ((uint32_t)0x00000040) /*!<Mask Parity error bit */
\r
6585 #define SPDIFRX_CR_VMSK ((uint32_t)0x00000080) /*!<Mask of Validity bit */
\r
6586 #define SPDIFRX_CR_CUMSK ((uint32_t)0x00000100) /*!<Mask of channel status and user bits */
\r
6587 #define SPDIFRX_CR_PTMSK ((uint32_t)0x00000200) /*!<Mask of Preamble Type bits */
\r
6588 #define SPDIFRX_CR_CBDMAEN ((uint32_t)0x00000400) /*!<Control Buffer DMA ENable for control flow */
\r
6589 #define SPDIFRX_CR_CHSEL ((uint32_t)0x00000800) /*!<Channel Selection */
\r
6590 #define SPDIFRX_CR_NBTR ((uint32_t)0x00003000) /*!<Maximum allowed re-tries during synchronization phase */
\r
6591 #define SPDIFRX_CR_WFA ((uint32_t)0x00004000) /*!<Wait For Activity */
\r
6592 #define SPDIFRX_CR_INSEL ((uint32_t)0x00070000) /*!<SPDIF input selection */
\r
6594 /******************* Bit definition for SPDIFRX_IMR register *******************/
\r
6595 #define SPDIFRX_IMR_RXNEIE ((uint32_t)0x00000001) /*!<RXNE interrupt enable */
\r
6596 #define SPDIFRX_IMR_CSRNEIE ((uint32_t)0x00000002) /*!<Control Buffer Ready Interrupt Enable */
\r
6597 #define SPDIFRX_IMR_PERRIE ((uint32_t)0x00000004) /*!<Parity error interrupt enable */
\r
6598 #define SPDIFRX_IMR_OVRIE ((uint32_t)0x00000008) /*!<Overrun error Interrupt Enable */
\r
6599 #define SPDIFRX_IMR_SBLKIE ((uint32_t)0x00000010) /*!<Synchronization Block Detected Interrupt Enable */
\r
6600 #define SPDIFRX_IMR_SYNCDIE ((uint32_t)0x00000020) /*!<Synchronization Done */
\r
6601 #define SPDIFRX_IMR_IFEIE ((uint32_t)0x00000040) /*!<Serial Interface Error Interrupt Enable */
\r
6603 /******************* Bit definition for SPDIFRX_SR register *******************/
\r
6604 #define SPDIFRX_SR_RXNE ((uint32_t)0x00000001) /*!<Read data register not empty */
\r
6605 #define SPDIFRX_SR_CSRNE ((uint32_t)0x00000002) /*!<The Control Buffer register is not empty */
\r
6606 #define SPDIFRX_SR_PERR ((uint32_t)0x00000004) /*!<Parity error */
\r
6607 #define SPDIFRX_SR_OVR ((uint32_t)0x00000008) /*!<Overrun error */
\r
6608 #define SPDIFRX_SR_SBD ((uint32_t)0x00000010) /*!<Synchronization Block Detected */
\r
6609 #define SPDIFRX_SR_SYNCD ((uint32_t)0x00000020) /*!<Synchronization Done */
\r
6610 #define SPDIFRX_SR_FERR ((uint32_t)0x00000040) /*!<Framing error */
\r
6611 #define SPDIFRX_SR_SERR ((uint32_t)0x00000080) /*!<Synchronization error */
\r
6612 #define SPDIFRX_SR_TERR ((uint32_t)0x00000100) /*!<Time-out error */
\r
6613 #define SPDIFRX_SR_WIDTH5 ((uint32_t)0x7FFF0000) /*!<Duration of 5 symbols counted with spdif_clk */
\r
6615 /******************* Bit definition for SPDIFRX_IFCR register *******************/
\r
6616 #define SPDIFRX_IFCR_PERRCF ((uint32_t)0x00000004) /*!<Clears the Parity error flag */
\r
6617 #define SPDIFRX_IFCR_OVRCF ((uint32_t)0x00000008) /*!<Clears the Overrun error flag */
\r
6618 #define SPDIFRX_IFCR_SBDCF ((uint32_t)0x00000010) /*!<Clears the Synchronization Block Detected flag */
\r
6619 #define SPDIFRX_IFCR_SYNCDCF ((uint32_t)0x00000020) /*!<Clears the Synchronization Done flag */
\r
6621 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
\r
6622 #define SPDIFRX_DR0_DR ((uint32_t)0x00FFFFFF) /*!<Data value */
\r
6623 #define SPDIFRX_DR0_PE ((uint32_t)0x01000000) /*!<Parity Error bit */
\r
6624 #define SPDIFRX_DR0_V ((uint32_t)0x02000000) /*!<Validity bit */
\r
6625 #define SPDIFRX_DR0_U ((uint32_t)0x04000000) /*!<User bit */
\r
6626 #define SPDIFRX_DR0_C ((uint32_t)0x08000000) /*!<Channel Status bit */
\r
6627 #define SPDIFRX_DR0_PT ((uint32_t)0x30000000) /*!<Preamble Type */
\r
6629 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
\r
6630 #define SPDIFRX_DR1_DR ((uint32_t)0xFFFFFF00) /*!<Data value */
\r
6631 #define SPDIFRX_DR1_PT ((uint32_t)0x00000030) /*!<Preamble Type */
\r
6632 #define SPDIFRX_DR1_C ((uint32_t)0x00000008) /*!<Channel Status bit */
\r
6633 #define SPDIFRX_DR1_U ((uint32_t)0x00000004) /*!<User bit */
\r
6634 #define SPDIFRX_DR1_V ((uint32_t)0x00000002) /*!<Validity bit */
\r
6635 #define SPDIFRX_DR1_PE ((uint32_t)0x00000001) /*!<Parity Error bit */
\r
6637 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
\r
6638 #define SPDIFRX_DR1_DRNL1 ((uint32_t)0xFFFF0000) /*!<Data value Channel B */
\r
6639 #define SPDIFRX_DR1_DRNL2 ((uint32_t)0x0000FFFF) /*!<Data value Channel A */
\r
6641 /******************* Bit definition for SPDIFRX_CSR register *******************/
\r
6642 #define SPDIFRX_CSR_USR ((uint32_t)0x0000FFFF) /*!<User data information */
\r
6643 #define SPDIFRX_CSR_CS ((uint32_t)0x00FF0000) /*!<Channel A status information */
\r
6644 #define SPDIFRX_CSR_SOB ((uint32_t)0x01000000) /*!<Start Of Block */
\r
6646 /******************* Bit definition for SPDIFRX_DIR register *******************/
\r
6647 #define SPDIFRX_DIR_THI ((uint32_t)0x000013FF) /*!<Threshold LOW */
\r
6648 #define SPDIFRX_DIR_TLO ((uint32_t)0x1FFF0000) /*!<Threshold HIGH */
\r
6651 /******************************************************************************/
\r
6653 /* SD host Interface */
\r
6655 /******************************************************************************/
\r
6656 /****************** Bit definition for SDMMC_POWER register ******************/
\r
6657 #define SDMMC_POWER_PWRCTRL ((uint32_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
\r
6658 #define SDMMC_POWER_PWRCTRL_0 ((uint32_t)0x01) /*!<Bit 0 */
\r
6659 #define SDMMC_POWER_PWRCTRL_1 ((uint32_t)0x02) /*!<Bit 1 */
\r
6661 /****************** Bit definition for SDMMC_CLKCR register ******************/
\r
6662 #define SDMMC_CLKCR_CLKDIV ((uint32_t)0x00FF) /*!<Clock divide factor */
\r
6663 #define SDMMC_CLKCR_CLKEN ((uint32_t)0x0100) /*!<Clock enable bit */
\r
6664 #define SDMMC_CLKCR_PWRSAV ((uint32_t)0x0200) /*!<Power saving configuration bit */
\r
6665 #define SDMMC_CLKCR_BYPASS ((uint32_t)0x0400) /*!<Clock divider bypass enable bit */
\r
6667 #define SDMMC_CLKCR_WIDBUS ((uint32_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
\r
6668 #define SDMMC_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /*!<Bit 0 */
\r
6669 #define SDMMC_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /*!<Bit 1 */
\r
6671 #define SDMMC_CLKCR_NEGEDGE ((uint32_t)0x2000) /*!<SDMMC_CK dephasing selection bit */
\r
6672 #define SDMMC_CLKCR_HWFC_EN ((uint32_t)0x4000) /*!<HW Flow Control enable */
\r
6674 /******************* Bit definition for SDMMC_ARG register *******************/
\r
6675 #define SDMMC_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */
\r
6677 /******************* Bit definition for SDMMC_CMD register *******************/
\r
6678 #define SDMMC_CMD_CMDINDEX ((uint32_t)0x003F) /*!<Command Index */
\r
6680 #define SDMMC_CMD_WAITRESP ((uint32_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */
\r
6681 #define SDMMC_CMD_WAITRESP_0 ((uint32_t)0x0040) /*!< Bit 0 */
\r
6682 #define SDMMC_CMD_WAITRESP_1 ((uint32_t)0x0080) /*!< Bit 1 */
\r
6684 #define SDMMC_CMD_WAITINT ((uint32_t)0x0100) /*!<CPSM Waits for Interrupt Request */
\r
6685 #define SDMMC_CMD_WAITPEND ((uint32_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
\r
6686 #define SDMMC_CMD_CPSMEN ((uint32_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */
\r
6687 #define SDMMC_CMD_SDIOSUSPEND ((uint32_t)0x0800) /*!<SD I/O suspend command */
\r
6689 /***************** Bit definition for SDMMC_RESPCMD register *****************/
\r
6690 #define SDMMC_RESPCMD_RESPCMD ((uint32_t)0x3F) /*!<Response command index */
\r
6692 /****************** Bit definition for SDMMC_RESP0 register ******************/
\r
6693 #define SDMMC_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
\r
6695 /****************** Bit definition for SDMMC_RESP1 register ******************/
\r
6696 #define SDMMC_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
\r
6698 /****************** Bit definition for SDMMC_RESP2 register ******************/
\r
6699 #define SDMMC_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
\r
6701 /****************** Bit definition for SDMMC_RESP3 register ******************/
\r
6702 #define SDMMC_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
\r
6704 /****************** Bit definition for SDMMC_RESP4 register ******************/
\r
6705 #define SDMMC_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
\r
6707 /****************** Bit definition for SDMMC_DTIMER register *****************/
\r
6708 #define SDMMC_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */
\r
6710 /****************** Bit definition for SDMMC_DLEN register *******************/
\r
6711 #define SDMMC_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */
\r
6713 /****************** Bit definition for SDMMC_DCTRL register ******************/
\r
6714 #define SDMMC_DCTRL_DTEN ((uint32_t)0x0001) /*!<Data transfer enabled bit */
\r
6715 #define SDMMC_DCTRL_DTDIR ((uint32_t)0x0002) /*!<Data transfer direction selection */
\r
6716 #define SDMMC_DCTRL_DTMODE ((uint32_t)0x0004) /*!<Data transfer mode selection */
\r
6717 #define SDMMC_DCTRL_DMAEN ((uint32_t)0x0008) /*!<DMA enabled bit */
\r
6719 #define SDMMC_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
\r
6720 #define SDMMC_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /*!<Bit 0 */
\r
6721 #define SDMMC_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /*!<Bit 1 */
\r
6722 #define SDMMC_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /*!<Bit 2 */
\r
6723 #define SDMMC_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /*!<Bit 3 */
\r
6725 #define SDMMC_DCTRL_RWSTART ((uint32_t)0x0100) /*!<Read wait start */
\r
6726 #define SDMMC_DCTRL_RWSTOP ((uint32_t)0x0200) /*!<Read wait stop */
\r
6727 #define SDMMC_DCTRL_RWMOD ((uint32_t)0x0400) /*!<Read wait mode */
\r
6728 #define SDMMC_DCTRL_SDIOEN ((uint32_t)0x0800) /*!<SD I/O enable functions */
\r
6730 /****************** Bit definition for SDMMC_DCOUNT register *****************/
\r
6731 #define SDMMC_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */
\r
6733 /****************** Bit definition for SDMMC_STA register ********************/
\r
6734 #define SDMMC_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */
\r
6735 #define SDMMC_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */
\r
6736 #define SDMMC_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */
\r
6737 #define SDMMC_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */
\r
6738 #define SDMMC_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */
\r
6739 #define SDMMC_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */
\r
6740 #define SDMMC_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */
\r
6741 #define SDMMC_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */
\r
6742 #define SDMMC_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */
\r
6743 #define SDMMC_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */
\r
6744 #define SDMMC_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */
\r
6745 #define SDMMC_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */
\r
6746 #define SDMMC_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */
\r
6747 #define SDMMC_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
\r
6748 #define SDMMC_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
\r
6749 #define SDMMC_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */
\r
6750 #define SDMMC_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */
\r
6751 #define SDMMC_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */
\r
6752 #define SDMMC_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */
\r
6753 #define SDMMC_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */
\r
6754 #define SDMMC_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */
\r
6755 #define SDMMC_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDMMC interrupt received */
\r
6757 /******************* Bit definition for SDMMC_ICR register *******************/
\r
6758 #define SDMMC_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */
\r
6759 #define SDMMC_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */
\r
6760 #define SDMMC_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */
\r
6761 #define SDMMC_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */
\r
6762 #define SDMMC_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */
\r
6763 #define SDMMC_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */
\r
6764 #define SDMMC_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */
\r
6765 #define SDMMC_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */
\r
6766 #define SDMMC_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */
\r
6767 #define SDMMC_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */
\r
6768 #define SDMMC_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDMMCIT flag clear bit */
\r
6770 /****************** Bit definition for SDMMC_MASK register *******************/
\r
6771 #define SDMMC_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */
\r
6772 #define SDMMC_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */
\r
6773 #define SDMMC_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */
\r
6774 #define SDMMC_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */
\r
6775 #define SDMMC_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */
\r
6776 #define SDMMC_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */
\r
6777 #define SDMMC_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */
\r
6778 #define SDMMC_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */
\r
6779 #define SDMMC_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */
\r
6780 #define SDMMC_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */
\r
6781 #define SDMMC_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
\r
6782 #define SDMMC_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */
\r
6783 #define SDMMC_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */
\r
6784 #define SDMMC_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */
\r
6785 #define SDMMC_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */
\r
6786 #define SDMMC_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */
\r
6787 #define SDMMC_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */
\r
6788 #define SDMMC_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */
\r
6789 #define SDMMC_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */
\r
6790 #define SDMMC_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */
\r
6791 #define SDMMC_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */
\r
6792 #define SDMMC_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDMMC Mode Interrupt Received interrupt Enable */
\r
6794 /***************** Bit definition for SDMMC_FIFOCNT register *****************/
\r
6795 #define SDMMC_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */
\r
6797 /****************** Bit definition for SDMMC_FIFO register *******************/
\r
6798 #define SDMMC_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */
\r
6800 /******************************************************************************/
\r
6802 /* Serial Peripheral Interface (SPI) */
\r
6804 /******************************************************************************/
\r
6805 /******************* Bit definition for SPI_CR1 register ********************/
\r
6806 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
\r
6807 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
\r
6808 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
\r
6809 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
\r
6810 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
\r
6811 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
\r
6812 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
\r
6813 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
\r
6814 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
\r
6815 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
\r
6816 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
\r
6817 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
\r
6818 #define SPI_CR1_CRCL ((uint32_t)0x00000800) /*!< CRC Length */
\r
6819 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
\r
6820 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
\r
6821 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
\r
6822 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
\r
6824 /******************* Bit definition for SPI_CR2 register ********************/
\r
6825 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
\r
6826 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
\r
6827 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
\r
6828 #define SPI_CR2_NSSP ((uint32_t)0x00000008) /*!< NSS pulse management Enable */
\r
6829 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */
\r
6830 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
\r
6831 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
\r
6832 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
\r
6833 #define SPI_CR2_DS ((uint32_t)0x00000F00) /*!< DS[3:0] Data Size */
\r
6834 #define SPI_CR2_DS_0 ((uint32_t)0x00000100) /*!< Bit 0 */
\r
6835 #define SPI_CR2_DS_1 ((uint32_t)0x00000200) /*!< Bit 1 */
\r
6836 #define SPI_CR2_DS_2 ((uint32_t)0x00000400) /*!< Bit 2 */
\r
6837 #define SPI_CR2_DS_3 ((uint32_t)0x00000800) /*!< Bit 3 */
\r
6838 #define SPI_CR2_FRXTH ((uint32_t)0x00001000) /*!< FIFO reception Threshold */
\r
6839 #define SPI_CR2_LDMARX ((uint32_t)0x00002000) /*!< Last DMA transfer for reception */
\r
6840 #define SPI_CR2_LDMATX ((uint32_t)0x00004000) /*!< Last DMA transfer for transmission */
\r
6842 /******************** Bit definition for SPI_SR register ********************/
\r
6843 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
\r
6844 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
\r
6845 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
\r
6846 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
\r
6847 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
\r
6848 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
\r
6849 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
\r
6850 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
\r
6851 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */
\r
6852 #define SPI_SR_FRLVL ((uint32_t)0x00000600) /*!< FIFO Reception Level */
\r
6853 #define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
\r
6854 #define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
\r
6855 #define SPI_SR_FTLVL ((uint32_t)0x00001800) /*!< FIFO Transmission Level */
\r
6856 #define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /*!< Bit 0 */
\r
6857 #define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /*!< Bit 1 */
\r
6859 /******************** Bit definition for SPI_DR register ********************/
\r
6860 #define SPI_DR_DR ((uint32_t)0xFFFF) /*!< Data Register */
\r
6862 /******************* Bit definition for SPI_CRCPR register ******************/
\r
6863 #define SPI_CRCPR_CRCPOLY ((uint32_t)0xFFFF) /*!< CRC polynomial register */
\r
6865 /****************** Bit definition for SPI_RXCRCR register ******************/
\r
6866 #define SPI_RXCRCR_RXCRC ((uint32_t)0xFFFF) /*!< Rx CRC Register */
\r
6868 /****************** Bit definition for SPI_TXCRCR register ******************/
\r
6869 #define SPI_TXCRCR_TXCRC ((uint32_t)0xFFFF) /*!< Tx CRC Register */
\r
6871 /****************** Bit definition for SPI_I2SCFGR register *****************/
\r
6872 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
\r
6873 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
\r
6874 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
\r
6875 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
\r
6876 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
\r
6877 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
\r
6878 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
\r
6879 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
\r
6880 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
\r
6881 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
\r
6882 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
\r
6883 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
\r
6884 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
\r
6885 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
\r
6886 #define SPI_I2SCFGR_ASTRTEN ((uint32_t)0x00001000) /*!<Asynchronous start enable */
\r
6888 /****************** Bit definition for SPI_I2SPR register *******************/
\r
6889 #define SPI_I2SPR_I2SDIV ((uint32_t)0x00FF) /*!<I2S Linear prescaler */
\r
6890 #define SPI_I2SPR_ODD ((uint32_t)0x0100) /*!<Odd factor for the prescaler */
\r
6891 #define SPI_I2SPR_MCKOE ((uint32_t)0x0200) /*!<Master Clock Output Enable */
\r
6894 /******************************************************************************/
\r
6898 /******************************************************************************/
\r
6899 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
\r
6900 #define SYSCFG_MEMRMP_MEM_BOOT ((uint32_t)0x00000001) /*!< Boot information after Reset */
\r
6902 #define SYSCFG_MEMRMP_SWP_FMC ((uint32_t)0x00000C00) /*!< FMC Memory Mapping swapping */
\r
6903 #define SYSCFG_MEMRMP_SWP_FMC_0 ((uint32_t)0x00000400)
\r
6904 #define SYSCFG_MEMRMP_SWP_FMC_1 ((uint32_t)0x00000800)
\r
6906 /****************** Bit definition for SYSCFG_PMC register ******************/
\r
6907 #define SYSCFG_PMC_ADCxDC2 ((uint32_t)0x00070000) /*!< Refer to AN4073 on how to use this bit */
\r
6908 #define SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit */
\r
6909 #define SYSCFG_PMC_ADC2DC2 ((uint32_t)0x00020000) /*!< Refer to AN4073 on how to use this bit */
\r
6910 #define SYSCFG_PMC_ADC3DC2 ((uint32_t)0x00040000) /*!< Refer to AN4073 on how to use this bit */
\r
6912 #define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */
\r
6914 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
\r
6915 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x000F) /*!<EXTI 0 configuration */
\r
6916 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00F0) /*!<EXTI 1 configuration */
\r
6917 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x0F00) /*!<EXTI 2 configuration */
\r
6918 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0xF000) /*!<EXTI 3 configuration */
\r
6920 * @brief EXTI0 configuration
\r
6922 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x0000) /*!<PA[0] pin */
\r
6923 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x0001) /*!<PB[0] pin */
\r
6924 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x0002) /*!<PC[0] pin */
\r
6925 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x0003) /*!<PD[0] pin */
\r
6926 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x0004) /*!<PE[0] pin */
\r
6927 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x0005) /*!<PF[0] pin */
\r
6928 #define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x0006) /*!<PG[0] pin */
\r
6929 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x0007) /*!<PH[0] pin */
\r
6930 #define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x0008) /*!<PI[0] pin */
\r
6931 #define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x0009) /*!<PJ[0] pin */
\r
6932 #define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x000A) /*!<PK[0] pin */
\r
6935 * @brief EXTI1 configuration
\r
6937 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x0000) /*!<PA[1] pin */
\r
6938 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x0010) /*!<PB[1] pin */
\r
6939 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x0020) /*!<PC[1] pin */
\r
6940 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x0030) /*!<PD[1] pin */
\r
6941 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x0040) /*!<PE[1] pin */
\r
6942 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x0050) /*!<PF[1] pin */
\r
6943 #define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x0060) /*!<PG[1] pin */
\r
6944 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x0070) /*!<PH[1] pin */
\r
6945 #define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x0080) /*!<PI[1] pin */
\r
6946 #define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x0090) /*!<PJ[1] pin */
\r
6947 #define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x00A0) /*!<PK[1] pin */
\r
6950 * @brief EXTI2 configuration
\r
6952 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x0000) /*!<PA[2] pin */
\r
6953 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x0100) /*!<PB[2] pin */
\r
6954 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x0200) /*!<PC[2] pin */
\r
6955 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x0300) /*!<PD[2] pin */
\r
6956 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x0400) /*!<PE[2] pin */
\r
6957 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x0500) /*!<PF[2] pin */
\r
6958 #define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x0600) /*!<PG[2] pin */
\r
6959 #define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x0700) /*!<PH[2] pin */
\r
6960 #define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x0800) /*!<PI[2] pin */
\r
6961 #define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x0900) /*!<PJ[2] pin */
\r
6962 #define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x0A00) /*!<PK[2] pin */
\r
6965 * @brief EXTI3 configuration
\r
6967 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x0000) /*!<PA[3] pin */
\r
6968 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x1000) /*!<PB[3] pin */
\r
6969 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x2000) /*!<PC[3] pin */
\r
6970 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x3000) /*!<PD[3] pin */
\r
6971 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x4000) /*!<PE[3] pin */
\r
6972 #define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x5000) /*!<PF[3] pin */
\r
6973 #define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x6000) /*!<PG[3] pin */
\r
6974 #define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x7000) /*!<PH[3] pin */
\r
6975 #define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x8000) /*!<PI[3] pin */
\r
6976 #define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x9000) /*!<PJ[3] pin */
\r
6977 #define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0xA000) /*!<PK[3] pin */
\r
6979 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
\r
6980 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x000F) /*!<EXTI 4 configuration */
\r
6981 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00F0) /*!<EXTI 5 configuration */
\r
6982 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x0F00) /*!<EXTI 6 configuration */
\r
6983 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0xF000) /*!<EXTI 7 configuration */
\r
6985 * @brief EXTI4 configuration
\r
6987 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x0000) /*!<PA[4] pin */
\r
6988 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x0001) /*!<PB[4] pin */
\r
6989 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x0002) /*!<PC[4] pin */
\r
6990 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x0003) /*!<PD[4] pin */
\r
6991 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x0004) /*!<PE[4] pin */
\r
6992 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x0005) /*!<PF[4] pin */
\r
6993 #define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x0006) /*!<PG[4] pin */
\r
6994 #define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x0007) /*!<PH[4] pin */
\r
6995 #define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x0008) /*!<PI[4] pin */
\r
6996 #define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x0009) /*!<PJ[4] pin */
\r
6997 #define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x000A) /*!<PK[4] pin */
\r
7000 * @brief EXTI5 configuration
\r
7002 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x0000) /*!<PA[5] pin */
\r
7003 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x0010) /*!<PB[5] pin */
\r
7004 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x0020) /*!<PC[5] pin */
\r
7005 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x0030) /*!<PD[5] pin */
\r
7006 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x0040) /*!<PE[5] pin */
\r
7007 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x0050) /*!<PF[5] pin */
\r
7008 #define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x0060) /*!<PG[5] pin */
\r
7009 #define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x0070) /*!<PH[5] pin */
\r
7010 #define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x0080) /*!<PI[5] pin */
\r
7011 #define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x0090) /*!<PJ[5] pin */
\r
7012 #define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x00A0) /*!<PK[5] pin */
\r
7015 * @brief EXTI6 configuration
\r
7017 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x0000) /*!<PA[6] pin */
\r
7018 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x0100) /*!<PB[6] pin */
\r
7019 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x0200) /*!<PC[6] pin */
\r
7020 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x0300) /*!<PD[6] pin */
\r
7021 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x0400) /*!<PE[6] pin */
\r
7022 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x0500) /*!<PF[6] pin */
\r
7023 #define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x0600) /*!<PG[6] pin */
\r
7024 #define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x0700) /*!<PH[6] pin */
\r
7025 #define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x0800) /*!<PI[6] pin */
\r
7026 #define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x0900) /*!<PJ[6] pin */
\r
7027 #define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x0A00) /*!<PK[6] pin */
\r
7030 * @brief EXTI7 configuration
\r
7032 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x0000) /*!<PA[7] pin */
\r
7033 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x1000) /*!<PB[7] pin */
\r
7034 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x2000) /*!<PC[7] pin */
\r
7035 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x3000) /*!<PD[7] pin */
\r
7036 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x4000) /*!<PE[7] pin */
\r
7037 #define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x5000) /*!<PF[7] pin */
\r
7038 #define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x6000) /*!<PG[7] pin */
\r
7039 #define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x7000) /*!<PH[7] pin */
\r
7040 #define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x8000) /*!<PI[7] pin */
\r
7041 #define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x9000) /*!<PJ[7] pin */
\r
7042 #define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0xA000) /*!<PK[7] pin */
\r
7044 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
\r
7045 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x000F) /*!<EXTI 8 configuration */
\r
7046 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00F0) /*!<EXTI 9 configuration */
\r
7047 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x0F00) /*!<EXTI 10 configuration */
\r
7048 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0xF000) /*!<EXTI 11 configuration */
\r
7051 * @brief EXTI8 configuration
\r
7053 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x0000) /*!<PA[8] pin */
\r
7054 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x0001) /*!<PB[8] pin */
\r
7055 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x0002) /*!<PC[8] pin */
\r
7056 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x0003) /*!<PD[8] pin */
\r
7057 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x0004) /*!<PE[8] pin */
\r
7058 #define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x0005) /*!<PF[8] pin */
\r
7059 #define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x0006) /*!<PG[8] pin */
\r
7060 #define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x0007) /*!<PH[8] pin */
\r
7061 #define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x0008) /*!<PI[8] pin */
\r
7062 #define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x0009) /*!<PJ[8] pin */
\r
7065 * @brief EXTI9 configuration
\r
7067 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x0000) /*!<PA[9] pin */
\r
7068 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x0010) /*!<PB[9] pin */
\r
7069 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x0020) /*!<PC[9] pin */
\r
7070 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x0030) /*!<PD[9] pin */
\r
7071 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x0040) /*!<PE[9] pin */
\r
7072 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x0050) /*!<PF[9] pin */
\r
7073 #define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x0060) /*!<PG[9] pin */
\r
7074 #define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x0070) /*!<PH[9] pin */
\r
7075 #define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x0080) /*!<PI[9] pin */
\r
7076 #define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x0090) /*!<PJ[9] pin */
\r
7079 * @brief EXTI10 configuration
\r
7081 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x0000) /*!<PA[10] pin */
\r
7082 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x0100) /*!<PB[10] pin */
\r
7083 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x0200) /*!<PC[10] pin */
\r
7084 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x0300) /*!<PD[10] pin */
\r
7085 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x0400) /*!<PE[10] pin */
\r
7086 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x0500) /*!<PF[10] pin */
\r
7087 #define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x0600) /*!<PG[10] pin */
\r
7088 #define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x0700) /*!<PH[10] pin */
\r
7089 #define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x0800) /*!<PI[10] pin */
\r
7090 #define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x0900) /*!<PJ[10] pin */
\r
7093 * @brief EXTI11 configuration
\r
7095 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x0000) /*!<PA[11] pin */
\r
7096 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x1000) /*!<PB[11] pin */
\r
7097 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x2000) /*!<PC[11] pin */
\r
7098 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x3000) /*!<PD[11] pin */
\r
7099 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x4000) /*!<PE[11] pin */
\r
7100 #define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x5000) /*!<PF[11] pin */
\r
7101 #define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x6000) /*!<PG[11] pin */
\r
7102 #define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x7000) /*!<PH[11] pin */
\r
7103 #define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x8000) /*!<PI[11] pin */
\r
7104 #define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x9000) /*!<PJ[11] pin */
\r
7107 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
\r
7108 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x000F) /*!<EXTI 12 configuration */
\r
7109 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00F0) /*!<EXTI 13 configuration */
\r
7110 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x0F00) /*!<EXTI 14 configuration */
\r
7111 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0xF000) /*!<EXTI 15 configuration */
\r
7113 * @brief EXTI12 configuration
\r
7115 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x0000) /*!<PA[12] pin */
\r
7116 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x0001) /*!<PB[12] pin */
\r
7117 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x0002) /*!<PC[12] pin */
\r
7118 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x0003) /*!<PD[12] pin */
\r
7119 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x0004) /*!<PE[12] pin */
\r
7120 #define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x0005) /*!<PF[12] pin */
\r
7121 #define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x0006) /*!<PG[12] pin */
\r
7122 #define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x0007) /*!<PH[12] pin */
\r
7123 #define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x0008) /*!<PI[12] pin */
\r
7124 #define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x0009) /*!<PJ[12] pin */
\r
7127 * @brief EXTI13 configuration
\r
7129 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x0000) /*!<PA[13] pin */
\r
7130 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x0010) /*!<PB[13] pin */
\r
7131 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x0020) /*!<PC[13] pin */
\r
7132 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x0030) /*!<PD[13] pin */
\r
7133 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x0040) /*!<PE[13] pin */
\r
7134 #define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x0050) /*!<PF[13] pin */
\r
7135 #define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x0060) /*!<PG[13] pin */
\r
7136 #define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x0070) /*!<PH[13] pin */
\r
7137 #define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x0008) /*!<PI[13] pin */
\r
7138 #define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x0009) /*!<PJ[13] pin */
\r
7141 * @brief EXTI14 configuration
\r
7143 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x0000) /*!<PA[14] pin */
\r
7144 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x0100) /*!<PB[14] pin */
\r
7145 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x0200) /*!<PC[14] pin */
\r
7146 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x0300) /*!<PD[14] pin */
\r
7147 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x0400) /*!<PE[14] pin */
\r
7148 #define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x0500) /*!<PF[14] pin */
\r
7149 #define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x0600) /*!<PG[14] pin */
\r
7150 #define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x0700) /*!<PH[14] pin */
\r
7151 #define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x0800) /*!<PI[14] pin */
\r
7152 #define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x0900) /*!<PJ[14] pin */
\r
7155 * @brief EXTI15 configuration
\r
7157 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x0000) /*!<PA[15] pin */
\r
7158 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x1000) /*!<PB[15] pin */
\r
7159 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x2000) /*!<PC[15] pin */
\r
7160 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x3000) /*!<PD[15] pin */
\r
7161 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x4000) /*!<PE[15] pin */
\r
7162 #define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x5000) /*!<PF[15] pin */
\r
7163 #define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x6000) /*!<PG[15] pin */
\r
7164 #define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x7000) /*!<PH[15] pin */
\r
7165 #define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x8000) /*!<PI[15] pin */
\r
7166 #define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x9000) /*!<PJ[15] pin */
\r
7168 /****************** Bit definition for SYSCFG_CMPCR register ****************/
\r
7169 #define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell power-down */
\r
7170 #define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell ready flag*/
\r
7172 /******************************************************************************/
\r
7176 /******************************************************************************/
\r
7177 /******************* Bit definition for TIM_CR1 register ********************/
\r
7178 #define TIM_CR1_CEN ((uint32_t)0x0001) /*!<Counter enable */
\r
7179 #define TIM_CR1_UDIS ((uint32_t)0x0002) /*!<Update disable */
\r
7180 #define TIM_CR1_URS ((uint32_t)0x0004) /*!<Update request source */
\r
7181 #define TIM_CR1_OPM ((uint32_t)0x0008) /*!<One pulse mode */
\r
7182 #define TIM_CR1_DIR ((uint32_t)0x0010) /*!<Direction */
\r
7184 #define TIM_CR1_CMS ((uint32_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
\r
7185 #define TIM_CR1_CMS_0 ((uint32_t)0x0020) /*!<Bit 0 */
\r
7186 #define TIM_CR1_CMS_1 ((uint32_t)0x0040) /*!<Bit 1 */
\r
7188 #define TIM_CR1_ARPE ((uint32_t)0x0080) /*!<Auto-reload preload enable */
\r
7190 #define TIM_CR1_CKD ((uint32_t)0x0300) /*!<CKD[1:0] bits (clock division) */
\r
7191 #define TIM_CR1_CKD_0 ((uint32_t)0x0100) /*!<Bit 0 */
\r
7192 #define TIM_CR1_CKD_1 ((uint32_t)0x0200) /*!<Bit 1 */
\r
7193 #define TIM_CR1_UIFREMAP ((uint32_t)0x0800) /*!<UIF status bit */
\r
7195 /******************* Bit definition for TIM_CR2 register ********************/
\r
7196 #define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
\r
7197 #define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
\r
7198 #define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
\r
7200 #define TIM_CR2_OIS5 ((uint32_t)0x00010000) /*!<Output Idle state 4 (OC4 output) */
\r
7201 #define TIM_CR2_OIS6 ((uint32_t)0x00040000) /*!<Output Idle state 4 (OC4 output) */
\r
7203 #define TIM_CR2_MMS ((uint32_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
\r
7204 #define TIM_CR2_MMS_0 ((uint32_t)0x0010) /*!<Bit 0 */
\r
7205 #define TIM_CR2_MMS_1 ((uint32_t)0x0020) /*!<Bit 1 */
\r
7206 #define TIM_CR2_MMS_2 ((uint32_t)0x0040) /*!<Bit 2 */
\r
7208 #define TIM_CR2_MMS2 ((uint32_t)0x00F00000) /*!<MMS[2:0] bits (Master Mode Selection) */
\r
7209 #define TIM_CR2_MMS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */
\r
7210 #define TIM_CR2_MMS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */
\r
7211 #define TIM_CR2_MMS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */
\r
7212 #define TIM_CR2_MMS2_3 ((uint32_t)0x00800000) /*!<Bit 2 */
\r
7214 #define TIM_CR2_TI1S ((uint32_t)0x0080) /*!<TI1 Selection */
\r
7215 #define TIM_CR2_OIS1 ((uint32_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
\r
7216 #define TIM_CR2_OIS1N ((uint32_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
\r
7217 #define TIM_CR2_OIS2 ((uint32_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
\r
7218 #define TIM_CR2_OIS2N ((uint32_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
\r
7219 #define TIM_CR2_OIS3 ((uint32_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
\r
7220 #define TIM_CR2_OIS3N ((uint32_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
\r
7221 #define TIM_CR2_OIS4 ((uint32_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
\r
7223 /******************* Bit definition for TIM_SMCR register *******************/
\r
7224 #define TIM_SMCR_SMS ((uint32_t)0x00010007) /*!<SMS[2:0] bits (Slave mode selection) */
\r
7225 #define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
7226 #define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
7227 #define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
7228 #define TIM_SMCR_SMS_3 ((uint32_t)0x00010000) /*!<Bit 3 */
\r
7229 #define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
\r
7231 #define TIM_SMCR_TS ((uint32_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
\r
7232 #define TIM_SMCR_TS_0 ((uint32_t)0x0010) /*!<Bit 0 */
\r
7233 #define TIM_SMCR_TS_1 ((uint32_t)0x0020) /*!<Bit 1 */
\r
7234 #define TIM_SMCR_TS_2 ((uint32_t)0x0040) /*!<Bit 2 */
\r
7236 #define TIM_SMCR_MSM ((uint32_t)0x0080) /*!<Master/slave mode */
\r
7238 #define TIM_SMCR_ETF ((uint32_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
\r
7239 #define TIM_SMCR_ETF_0 ((uint32_t)0x0100) /*!<Bit 0 */
\r
7240 #define TIM_SMCR_ETF_1 ((uint32_t)0x0200) /*!<Bit 1 */
\r
7241 #define TIM_SMCR_ETF_2 ((uint32_t)0x0400) /*!<Bit 2 */
\r
7242 #define TIM_SMCR_ETF_3 ((uint32_t)0x0800) /*!<Bit 3 */
\r
7244 #define TIM_SMCR_ETPS ((uint32_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
\r
7245 #define TIM_SMCR_ETPS_0 ((uint32_t)0x1000) /*!<Bit 0 */
\r
7246 #define TIM_SMCR_ETPS_1 ((uint32_t)0x2000) /*!<Bit 1 */
\r
7249 #define TIM_SMCR_ECE ((uint32_t)0x4000) /*!<External clock enable */
\r
7250 #define TIM_SMCR_ETP ((uint32_t)0x8000) /*!<External trigger polarity */
\r
7252 /******************* Bit definition for TIM_DIER register *******************/
\r
7253 #define TIM_DIER_UIE ((uint32_t)0x0001) /*!<Update interrupt enable */
\r
7254 #define TIM_DIER_CC1IE ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
\r
7255 #define TIM_DIER_CC2IE ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
\r
7256 #define TIM_DIER_CC3IE ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
\r
7257 #define TIM_DIER_CC4IE ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
\r
7258 #define TIM_DIER_COMIE ((uint32_t)0x0020) /*!<COM interrupt enable */
\r
7259 #define TIM_DIER_TIE ((uint32_t)0x0040) /*!<Trigger interrupt enable */
\r
7260 #define TIM_DIER_BIE ((uint32_t)0x0080) /*!<Break interrupt enable */
\r
7261 #define TIM_DIER_UDE ((uint32_t)0x0100) /*!<Update DMA request enable */
\r
7262 #define TIM_DIER_CC1DE ((uint32_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
\r
7263 #define TIM_DIER_CC2DE ((uint32_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
\r
7264 #define TIM_DIER_CC3DE ((uint32_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
\r
7265 #define TIM_DIER_CC4DE ((uint32_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
\r
7266 #define TIM_DIER_COMDE ((uint32_t)0x2000) /*!<COM DMA request enable */
\r
7267 #define TIM_DIER_TDE ((uint32_t)0x4000) /*!<Trigger DMA request enable */
\r
7269 /******************** Bit definition for TIM_SR register ********************/
\r
7270 #define TIM_SR_UIF ((uint32_t)0x0001) /*!<Update interrupt Flag */
\r
7271 #define TIM_SR_CC1IF ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
\r
7272 #define TIM_SR_CC2IF ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
\r
7273 #define TIM_SR_CC3IF ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
\r
7274 #define TIM_SR_CC4IF ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
\r
7275 #define TIM_SR_COMIF ((uint32_t)0x0020) /*!<COM interrupt Flag */
\r
7276 #define TIM_SR_TIF ((uint32_t)0x0040) /*!<Trigger interrupt Flag */
\r
7277 #define TIM_SR_BIF ((uint32_t)0x0080) /*!<Break interrupt Flag */
\r
7278 #define TIM_SR_B2IF ((uint32_t)0x0100) /*!<Break2 interrupt Flag */
\r
7279 #define TIM_SR_CC1OF ((uint32_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
\r
7280 #define TIM_SR_CC2OF ((uint32_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
\r
7281 #define TIM_SR_CC3OF ((uint32_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
\r
7282 #define TIM_SR_CC4OF ((uint32_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
\r
7284 /******************* Bit definition for TIM_EGR register ********************/
\r
7285 #define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
\r
7286 #define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
\r
7287 #define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
\r
7288 #define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
\r
7289 #define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
\r
7290 #define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
\r
7291 #define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
\r
7292 #define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
\r
7293 #define TIM_EGR_B2G ((uint32_t)0x00000100) /*!<Break2 Generation */
\r
7295 /****************** Bit definition for TIM_CCMR1 register *******************/
\r
7296 #define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
\r
7297 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
7298 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
7300 #define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
\r
7301 #define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
\r
7303 #define TIM_CCMR1_OC1M ((uint32_t)0x00010070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
\r
7304 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
\r
7305 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
\r
7306 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
\r
7307 #define TIM_CCMR1_OC1M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
\r
7309 #define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
\r
7311 #define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
\r
7312 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
\r
7313 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
\r
7315 #define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
\r
7316 #define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
\r
7318 #define TIM_CCMR1_OC2M ((uint32_t)0x01007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
\r
7319 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
\r
7320 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
\r
7321 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
\r
7322 #define TIM_CCMR1_OC2M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
\r
7324 #define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
\r
7326 /*----------------------------------------------------------------------------*/
\r
7328 #define TIM_CCMR1_IC1PSC ((uint32_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
\r
7329 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
\r
7330 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
\r
7332 #define TIM_CCMR1_IC1F ((uint32_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
\r
7333 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x0010) /*!<Bit 0 */
\r
7334 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x0020) /*!<Bit 1 */
\r
7335 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x0040) /*!<Bit 2 */
\r
7336 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x0080) /*!<Bit 3 */
\r
7338 #define TIM_CCMR1_IC2PSC ((uint32_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
\r
7339 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
\r
7340 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
\r
7342 #define TIM_CCMR1_IC2F ((uint32_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
\r
7343 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x1000) /*!<Bit 0 */
\r
7344 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x2000) /*!<Bit 1 */
\r
7345 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x4000) /*!<Bit 2 */
\r
7346 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x8000) /*!<Bit 3 */
\r
7348 /****************** Bit definition for TIM_CCMR2 register *******************/
\r
7349 #define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
\r
7350 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
7351 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
7353 #define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
\r
7354 #define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
\r
7356 #define TIM_CCMR2_OC3M ((uint32_t)0x00010070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
\r
7357 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
\r
7358 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
\r
7359 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
\r
7360 #define TIM_CCMR2_OC3M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
\r
7364 #define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
\r
7366 #define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
\r
7367 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
\r
7368 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
\r
7370 #define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
\r
7371 #define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
\r
7373 #define TIM_CCMR2_OC4M ((uint32_t)0x01007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
\r
7374 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
\r
7375 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
\r
7376 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
\r
7377 #define TIM_CCMR2_OC4M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
\r
7379 #define TIM_CCMR2_OC4CE ((uint32_t)0x8000) /*!<Output Compare 4 Clear Enable */
\r
7381 /*----------------------------------------------------------------------------*/
\r
7383 #define TIM_CCMR2_IC3PSC ((uint32_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
\r
7384 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
\r
7385 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
\r
7387 #define TIM_CCMR2_IC3F ((uint32_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
\r
7388 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x0010) /*!<Bit 0 */
\r
7389 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x0020) /*!<Bit 1 */
\r
7390 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x0040) /*!<Bit 2 */
\r
7391 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x0080) /*!<Bit 3 */
\r
7393 #define TIM_CCMR2_IC4PSC ((uint32_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
\r
7394 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
\r
7395 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
\r
7397 #define TIM_CCMR2_IC4F ((uint32_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
\r
7398 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x1000) /*!<Bit 0 */
\r
7399 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x2000) /*!<Bit 1 */
\r
7400 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x4000) /*!<Bit 2 */
\r
7401 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x8000) /*!<Bit 3 */
\r
7403 /******************* Bit definition for TIM_CCER register *******************/
\r
7404 #define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
\r
7405 #define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
\r
7406 #define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
\r
7407 #define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
\r
7408 #define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
\r
7409 #define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
\r
7410 #define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
\r
7411 #define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
\r
7412 #define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
\r
7413 #define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
\r
7414 #define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
\r
7415 #define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
\r
7416 #define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
\r
7417 #define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
\r
7418 #define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
\r
7419 #define TIM_CCER_CC5E ((uint32_t)0x00010000) /*!<Capture/Compare 5 output enable */
\r
7420 #define TIM_CCER_CC5P ((uint32_t)0x00020000) /*!<Capture/Compare 5 output Polarity */
\r
7421 #define TIM_CCER_CC6E ((uint32_t)0x00100000) /*!<Capture/Compare 6 output enable */
\r
7422 #define TIM_CCER_CC6P ((uint32_t)0x00200000) /*!<Capture/Compare 6 output Polarity */
\r
7425 /******************* Bit definition for TIM_CNT register ********************/
\r
7426 #define TIM_CNT_CNT ((uint32_t)0xFFFF) /*!<Counter Value */
\r
7428 /******************* Bit definition for TIM_PSC register ********************/
\r
7429 #define TIM_PSC_PSC ((uint32_t)0xFFFF) /*!<Prescaler Value */
\r
7431 /******************* Bit definition for TIM_ARR register ********************/
\r
7432 #define TIM_ARR_ARR ((uint32_t)0xFFFF) /*!<actual auto-reload Value */
\r
7434 /******************* Bit definition for TIM_RCR register ********************/
\r
7435 #define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */
\r
7437 /******************* Bit definition for TIM_CCR1 register *******************/
\r
7438 #define TIM_CCR1_CCR1 ((uint32_t)0xFFFF) /*!<Capture/Compare 1 Value */
\r
7440 /******************* Bit definition for TIM_CCR2 register *******************/
\r
7441 #define TIM_CCR2_CCR2 ((uint32_t)0xFFFF) /*!<Capture/Compare 2 Value */
\r
7443 /******************* Bit definition for TIM_CCR3 register *******************/
\r
7444 #define TIM_CCR3_CCR3 ((uint32_t)0xFFFF) /*!<Capture/Compare 3 Value */
\r
7446 /******************* Bit definition for TIM_CCR4 register *******************/
\r
7447 #define TIM_CCR4_CCR4 ((uint32_t)0xFFFF) /*!<Capture/Compare 4 Value */
\r
7449 /******************* Bit definition for TIM_BDTR register *******************/
\r
7450 #define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
\r
7451 #define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
7452 #define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
7453 #define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
7454 #define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
7455 #define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
\r
7456 #define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
\r
7457 #define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
\r
7458 #define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
\r
7460 #define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
\r
7461 #define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
\r
7462 #define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
\r
7464 #define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
\r
7465 #define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
\r
7466 #define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable */
\r
7467 #define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity */
\r
7468 #define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
\r
7469 #define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
\r
7470 #define TIM_BDTR_BKF ((uint32_t)0x000F0000) /*!<Break Filter for Break1 */
\r
7471 #define TIM_BDTR_BK2F ((uint32_t)0x00F00000) /*!<Break Filter for Break2 */
\r
7472 #define TIM_BDTR_BK2E ((uint32_t)0x01000000) /*!<Break enable for Break2 */
\r
7473 #define TIM_BDTR_BK2P ((uint32_t)0x02000000) /*!<Break Polarity for Break2 */
\r
7475 /******************* Bit definition for TIM_DCR register ********************/
\r
7476 #define TIM_DCR_DBA ((uint32_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
\r
7477 #define TIM_DCR_DBA_0 ((uint32_t)0x0001) /*!<Bit 0 */
\r
7478 #define TIM_DCR_DBA_1 ((uint32_t)0x0002) /*!<Bit 1 */
\r
7479 #define TIM_DCR_DBA_2 ((uint32_t)0x0004) /*!<Bit 2 */
\r
7480 #define TIM_DCR_DBA_3 ((uint32_t)0x0008) /*!<Bit 3 */
\r
7481 #define TIM_DCR_DBA_4 ((uint32_t)0x0010) /*!<Bit 4 */
\r
7483 #define TIM_DCR_DBL ((uint32_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
\r
7484 #define TIM_DCR_DBL_0 ((uint32_t)0x0100) /*!<Bit 0 */
\r
7485 #define TIM_DCR_DBL_1 ((uint32_t)0x0200) /*!<Bit 1 */
\r
7486 #define TIM_DCR_DBL_2 ((uint32_t)0x0400) /*!<Bit 2 */
\r
7487 #define TIM_DCR_DBL_3 ((uint32_t)0x0800) /*!<Bit 3 */
\r
7488 #define TIM_DCR_DBL_4 ((uint32_t)0x1000) /*!<Bit 4 */
\r
7490 /******************* Bit definition for TIM_DMAR register *******************/
\r
7491 #define TIM_DMAR_DMAB ((uint32_t)0xFFFF) /*!<DMA register for burst accesses */
\r
7493 /******************* Bit definition for TIM_OR register *********************/
\r
7494 #define TIM_OR_TI4_RMP ((uint32_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
\r
7495 #define TIM_OR_TI4_RMP_0 ((uint32_t)0x0040) /*!<Bit 0 */
\r
7496 #define TIM_OR_TI4_RMP_1 ((uint32_t)0x0080) /*!<Bit 1 */
\r
7497 #define TIM_OR_ITR1_RMP ((uint32_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
\r
7498 #define TIM_OR_ITR1_RMP_0 ((uint32_t)0x0400) /*!<Bit 0 */
\r
7499 #define TIM_OR_ITR1_RMP_1 ((uint32_t)0x0800) /*!<Bit 1 */
\r
7501 /****************** Bit definition for TIM_CCMR3 register *******************/
\r
7502 #define TIM_CCMR3_OC5FE ((uint32_t)0x00000004) /*!<Output Compare 5 Fast enable */
\r
7503 #define TIM_CCMR3_OC5PE ((uint32_t)0x00000008) /*!<Output Compare 5 Preload enable */
\r
7505 #define TIM_CCMR3_OC5M ((uint32_t)0x00010070) /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
\r
7506 #define TIM_CCMR3_OC5M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
\r
7507 #define TIM_CCMR3_OC5M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
\r
7508 #define TIM_CCMR3_OC5M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
\r
7509 #define TIM_CCMR3_OC5M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
\r
7511 #define TIM_CCMR3_OC5CE ((uint32_t)0x00000080) /*!<Output Compare 5 Clear Enable */
\r
7513 #define TIM_CCMR3_OC6FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
\r
7514 #define TIM_CCMR3_OC6PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
\r
7516 #define TIM_CCMR3_OC6M ((uint32_t)0x01007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
\r
7517 #define TIM_CCMR3_OC6M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
\r
7518 #define TIM_CCMR3_OC6M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
\r
7519 #define TIM_CCMR3_OC6M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
\r
7520 #define TIM_CCMR3_OC6M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
\r
7522 #define TIM_CCMR3_OC6CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
\r
7524 /******************* Bit definition for TIM_CCR5 register *******************/
\r
7525 #define TIM_CCR5_CCR5 ((uint32_t)0xFFFFFFFF) /*!<Capture/Compare 5 Value */
\r
7526 #define TIM_CCR5_GC5C1 ((uint32_t)0x20000000) /*!<Group Channel 5 and Channel 1 */
\r
7527 #define TIM_CCR5_GC5C2 ((uint32_t)0x40000000) /*!<Group Channel 5 and Channel 2 */
\r
7528 #define TIM_CCR5_GC5C3 ((uint32_t)0x80000000) /*!<Group Channel 5 and Channel 3 */
\r
7530 /******************* Bit definition for TIM_CCR6 register *******************/
\r
7531 #define TIM_CCR6_CCR6 ((uint16_t)0xFFFF) /*!<Capture/Compare 6 Value */
\r
7533 /******************************************************************************/
\r
7535 /* Low Power Timer (LPTIM) */
\r
7537 /******************************************************************************/
\r
7538 /****************** Bit definition for LPTIM_ISR register *******************/
\r
7539 #define LPTIM_ISR_CMPM ((uint32_t)0x00000001) /*!< Compare match */
\r
7540 #define LPTIM_ISR_ARRM ((uint32_t)0x00000002) /*!< Autoreload match */
\r
7541 #define LPTIM_ISR_EXTTRIG ((uint32_t)0x00000004) /*!< External trigger edge event */
\r
7542 #define LPTIM_ISR_CMPOK ((uint32_t)0x00000008) /*!< Compare register update OK */
\r
7543 #define LPTIM_ISR_ARROK ((uint32_t)0x00000010) /*!< Autoreload register update OK */
\r
7544 #define LPTIM_ISR_UP ((uint32_t)0x00000020) /*!< Counter direction change down to up */
\r
7545 #define LPTIM_ISR_DOWN ((uint32_t)0x00000040) /*!< Counter direction change up to down */
\r
7547 /****************** Bit definition for LPTIM_ICR register *******************/
\r
7548 #define LPTIM_ICR_CMPMCF ((uint32_t)0x00000001) /*!< Compare match Clear Flag */
\r
7549 #define LPTIM_ICR_ARRMCF ((uint32_t)0x00000002) /*!< Autoreload match Clear Flag */
\r
7550 #define LPTIM_ICR_EXTTRIGCF ((uint32_t)0x00000004) /*!< External trigger edge event Clear Flag */
\r
7551 #define LPTIM_ICR_CMPOKCF ((uint32_t)0x00000008) /*!< Compare register update OK Clear Flag */
\r
7552 #define LPTIM_ICR_ARROKCF ((uint32_t)0x00000010) /*!< Autoreload register update OK Clear Flag */
\r
7553 #define LPTIM_ICR_UPCF ((uint32_t)0x00000020) /*!< Counter direction change down to up Clear Flag */
\r
7554 #define LPTIM_ICR_DOWNCF ((uint32_t)0x00000040) /*!< Counter direction change up to down Clear Flag */
\r
7556 /****************** Bit definition for LPTIM_IER register ********************/
\r
7557 #define LPTIM_IER_CMPMIE ((uint32_t)0x00000001) /*!< Compare match Interrupt Enable */
\r
7558 #define LPTIM_IER_ARRMIE ((uint32_t)0x00000002) /*!< Autoreload match Interrupt Enable */
\r
7559 #define LPTIM_IER_EXTTRIGIE ((uint32_t)0x00000004) /*!< External trigger edge event Interrupt Enable */
\r
7560 #define LPTIM_IER_CMPOKIE ((uint32_t)0x00000008) /*!< Compare register update OK Interrupt Enable */
\r
7561 #define LPTIM_IER_ARROKIE ((uint32_t)0x00000010) /*!< Autoreload register update OK Interrupt Enable */
\r
7562 #define LPTIM_IER_UPIE ((uint32_t)0x00000020) /*!< Counter direction change down to up Interrupt Enable */
\r
7563 #define LPTIM_IER_DOWNIE ((uint32_t)0x00000040) /*!< Counter direction change up to down Interrupt Enable */
\r
7565 /****************** Bit definition for LPTIM_CFGR register *******************/
\r
7566 #define LPTIM_CFGR_CKSEL ((uint32_t)0x00000001) /*!< Clock selector */
\r
7568 #define LPTIM_CFGR_CKPOL ((uint32_t)0x00000006) /*!< CKPOL[1:0] bits (Clock polarity) */
\r
7569 #define LPTIM_CFGR_CKPOL_0 ((uint32_t)0x00000002) /*!< Bit 0 */
\r
7570 #define LPTIM_CFGR_CKPOL_1 ((uint32_t)0x00000004) /*!< Bit 1 */
\r
7572 #define LPTIM_CFGR_CKFLT ((uint32_t)0x00000018) /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
\r
7573 #define LPTIM_CFGR_CKFLT_0 ((uint32_t)0x00000008) /*!< Bit 0 */
\r
7574 #define LPTIM_CFGR_CKFLT_1 ((uint32_t)0x00000010) /*!< Bit 1 */
\r
7576 #define LPTIM_CFGR_TRGFLT ((uint32_t)0x000000C0) /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
\r
7577 #define LPTIM_CFGR_TRGFLT_0 ((uint32_t)0x00000040) /*!< Bit 0 */
\r
7578 #define LPTIM_CFGR_TRGFLT_1 ((uint32_t)0x00000080) /*!< Bit 1 */
\r
7580 #define LPTIM_CFGR_PRESC ((uint32_t)0x00000E00) /*!< PRESC[2:0] bits (Clock prescaler) */
\r
7581 #define LPTIM_CFGR_PRESC_0 ((uint32_t)0x00000200) /*!< Bit 0 */
\r
7582 #define LPTIM_CFGR_PRESC_1 ((uint32_t)0x00000400) /*!< Bit 1 */
\r
7583 #define LPTIM_CFGR_PRESC_2 ((uint32_t)0x00000800) /*!< Bit 2 */
\r
7585 #define LPTIM_CFGR_TRIGSEL ((uint32_t)0x0000E000) /*!< TRIGSEL[2:0]] bits (Trigger selector) */
\r
7586 #define LPTIM_CFGR_TRIGSEL_0 ((uint32_t)0x00002000) /*!< Bit 0 */
\r
7587 #define LPTIM_CFGR_TRIGSEL_1 ((uint32_t)0x00004000) /*!< Bit 1 */
\r
7588 #define LPTIM_CFGR_TRIGSEL_2 ((uint32_t)0x00008000) /*!< Bit 2 */
\r
7590 #define LPTIM_CFGR_TRIGEN ((uint32_t)0x00060000) /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
\r
7591 #define LPTIM_CFGR_TRIGEN_0 ((uint32_t)0x00020000) /*!< Bit 0 */
\r
7592 #define LPTIM_CFGR_TRIGEN_1 ((uint32_t)0x00040000) /*!< Bit 1 */
\r
7594 #define LPTIM_CFGR_TIMOUT ((uint32_t)0x00080000) /*!< Timout enable */
\r
7595 #define LPTIM_CFGR_WAVE ((uint32_t)0x00100000) /*!< Waveform shape */
\r
7596 #define LPTIM_CFGR_WAVPOL ((uint32_t)0x00200000) /*!< Waveform shape polarity */
\r
7597 #define LPTIM_CFGR_PRELOAD ((uint32_t)0x00400000) /*!< Reg update mode */
\r
7598 #define LPTIM_CFGR_COUNTMODE ((uint32_t)0x00800000) /*!< Counter mode enable */
\r
7599 #define LPTIM_CFGR_ENC ((uint32_t)0x01000000) /*!< Encoder mode enable */
\r
7601 /****************** Bit definition for LPTIM_CR register ********************/
\r
7602 #define LPTIM_CR_ENABLE ((uint32_t)0x00000001) /*!< LPTIMer enable */
\r
7603 #define LPTIM_CR_SNGSTRT ((uint32_t)0x00080002) /*!< Timer start in single mode */
\r
7604 #define LPTIM_CR_CNTSTRT ((uint32_t)0x00000004) /*!< Timer start in continuous mode */
\r
7606 /****************** Bit definition for LPTIM_CMP register *******************/
\r
7607 #define LPTIM_CMP_CMP ((uint32_t)0x0000FFFF) /*!< Compare register */
\r
7609 /****************** Bit definition for LPTIM_ARR register *******************/
\r
7610 #define LPTIM_ARR_ARR ((uint32_t)0x0000FFFF) /*!< Auto reload register */
\r
7612 /****************** Bit definition for LPTIM_CNT register *******************/
\r
7613 #define LPTIM_CNT_CNT ((uint32_t)0x0000FFFF) /*!< Counter register */
\r
7614 /******************************************************************************/
\r
7616 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
\r
7618 /******************************************************************************/
\r
7619 /****************** Bit definition for USART_CR1 register *******************/
\r
7620 #define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
\r
7621 #define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
\r
7622 #define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
\r
7623 #define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
\r
7624 #define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
\r
7625 #define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
\r
7626 #define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
\r
7627 #define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
\r
7628 #define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
\r
7629 #define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
\r
7630 #define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
\r
7631 #define USART_CR1_M ((uint32_t)0x10001000) /*!< Word length */
\r
7632 #define USART_CR1_M_0 ((uint32_t)0x00001000) /*!< Word length - Bit 0 */
\r
7633 #define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
\r
7634 #define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
\r
7635 #define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
\r
7636 #define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
\r
7637 #define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
\r
7638 #define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
\r
7639 #define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
\r
7640 #define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
\r
7641 #define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
\r
7642 #define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
\r
7643 #define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
\r
7644 #define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
\r
7645 #define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
\r
7646 #define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
\r
7647 #define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
\r
7648 #define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
\r
7649 #define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
\r
7650 #define USART_CR1_M_1 ((uint32_t)0x10000000) /*!< Word length - Bit 1 */
\r
7652 /****************** Bit definition for USART_CR2 register *******************/
\r
7653 #define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
\r
7654 #define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
\r
7655 #define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
\r
7656 #define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
\r
7657 #define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
\r
7658 #define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
\r
7659 #define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
\r
7660 #define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
\r
7661 #define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
\r
7662 #define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
\r
7663 #define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
\r
7664 #define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
\r
7665 #define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
\r
7666 #define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
\r
7667 #define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
\r
7668 #define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
\r
7669 #define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable */
\r
7670 #define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
\r
7671 #define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
\r
7672 #define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
\r
7673 #define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
\r
7674 #define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
\r
7676 /****************** Bit definition for USART_CR3 register *******************/
\r
7677 #define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
\r
7678 #define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
\r
7679 #define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
\r
7680 #define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
\r
7681 #define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
\r
7682 #define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
\r
7683 #define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
\r
7684 #define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
\r
7685 #define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
\r
7686 #define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
\r
7687 #define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
\r
7688 #define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
\r
7689 #define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
\r
7690 #define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
\r
7691 #define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
\r
7692 #define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
\r
7693 #define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
\r
7694 #define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
\r
7695 #define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
\r
7696 #define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
\r
7698 /****************** Bit definition for USART_BRR register *******************/
\r
7699 #define USART_BRR_DIV_FRACTION ((uint32_t)0x000F) /*!< Fraction of USARTDIV */
\r
7700 #define USART_BRR_DIV_MANTISSA ((uint32_t)0xFFF0) /*!< Mantissa of USARTDIV */
\r
7702 /****************** Bit definition for USART_GTPR register ******************/
\r
7703 #define USART_GTPR_PSC ((uint32_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */
\r
7704 #define USART_GTPR_GT ((uint32_t)0xFF00) /*!< GT[7:0] bits (Guard time value) */
\r
7707 /******************* Bit definition for USART_RTOR register *****************/
\r
7708 #define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
\r
7709 #define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
\r
7711 /******************* Bit definition for USART_RQR register ******************/
\r
7712 #define USART_RQR_ABRRQ ((uint32_t)0x0001) /*!< Auto-Baud Rate Request */
\r
7713 #define USART_RQR_SBKRQ ((uint32_t)0x0002) /*!< Send Break Request */
\r
7714 #define USART_RQR_MMRQ ((uint32_t)0x0004) /*!< Mute Mode Request */
\r
7715 #define USART_RQR_RXFRQ ((uint32_t)0x0008) /*!< Receive Data flush Request */
\r
7716 #define USART_RQR_TXFRQ ((uint32_t)0x0010) /*!< Transmit data flush Request */
\r
7718 /******************* Bit definition for USART_ISR register ******************/
\r
7719 #define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
\r
7720 #define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
\r
7721 #define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
\r
7722 #define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
\r
7723 #define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
\r
7724 #define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
\r
7725 #define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
\r
7726 #define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
\r
7727 #define USART_ISR_LBD ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
\r
7728 #define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
\r
7729 #define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
\r
7730 #define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
\r
7731 #define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
\r
7732 #define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
\r
7733 #define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
\r
7734 #define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
\r
7735 #define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
\r
7736 #define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
\r
7737 #define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
\r
7738 #define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
\r
7739 #define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
\r
7740 #define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
\r
7742 /******************* Bit definition for USART_ICR register ******************/
\r
7743 #define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
\r
7744 #define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
\r
7745 #define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
\r
7746 #define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
\r
7747 #define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
\r
7748 #define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
\r
7749 #define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
\r
7750 #define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
\r
7751 #define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
\r
7752 #define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
\r
7753 #define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
\r
7754 #define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
\r
7756 /******************* Bit definition for USART_RDR register ******************/
\r
7757 #define USART_RDR_RDR ((uint32_t)0x01FF) /*!< RDR[8:0] bits (Receive Data value) */
\r
7759 /******************* Bit definition for USART_TDR register ******************/
\r
7760 #define USART_TDR_TDR ((uint32_t)0x01FF) /*!< TDR[8:0] bits (Transmit Data value) */
\r
7762 /******************************************************************************/
\r
7764 /* Window WATCHDOG */
\r
7766 /******************************************************************************/
\r
7767 /******************* Bit definition for WWDG_CR register ********************/
\r
7768 #define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
\r
7769 #define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
\r
7770 #define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
\r
7771 #define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
\r
7772 #define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
\r
7773 #define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
\r
7774 #define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
\r
7775 #define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
\r
7777 #define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
\r
7779 /******************* Bit definition for WWDG_CFR register *******************/
\r
7780 #define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
\r
7781 #define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
\r
7782 #define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
\r
7783 #define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
\r
7784 #define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
\r
7785 #define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
\r
7786 #define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
\r
7787 #define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
\r
7789 #define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
\r
7790 #define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
\r
7791 #define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
\r
7793 #define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
\r
7795 /******************* Bit definition for WWDG_SR register ********************/
\r
7796 #define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
\r
7798 /******************************************************************************/
\r
7802 /******************************************************************************/
\r
7803 /******************** Bit definition for DBGMCU_IDCODE register *************/
\r
7804 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
\r
7805 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
\r
7807 /******************** Bit definition for DBGMCU_CR register *****************/
\r
7808 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
\r
7809 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
\r
7810 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
\r
7811 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
\r
7813 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
\r
7814 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!<Bit 0 */
\r
7815 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!<Bit 1 */
\r
7817 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
\r
7818 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
\r
7819 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
\r
7820 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
\r
7821 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
\r
7822 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
\r
7823 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
\r
7824 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
\r
7825 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
\r
7826 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
\r
7827 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
\r
7828 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
\r
7829 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
\r
7830 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
\r
7831 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
\r
7832 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
\r
7833 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
\r
7834 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
\r
7836 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
\r
7837 #define DBGMCU_APB1_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
\r
7838 #define DBGMCU_APB1_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
\r
7839 #define DBGMCU_APB1_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
\r
7840 #define DBGMCU_APB1_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
\r
7841 #define DBGMCU_APB1_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
\r
7843 /******************************************************************************/
\r
7845 /* Ethernet MAC Registers bits definitions */
\r
7847 /******************************************************************************/
\r
7848 /* Bit definition for Ethernet MAC Control Register register */
\r
7849 #define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */
\r
7850 #define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */
\r
7851 #define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */
\r
7852 #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
\r
7853 #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
\r
7854 #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
\r
7855 #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
\r
7856 #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
\r
7857 #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
\r
7858 #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
\r
7859 #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
\r
7860 #define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
\r
7861 #define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */
\r
7862 #define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */
\r
7863 #define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */
\r
7864 #define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */
\r
7865 #define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */
\r
7866 #define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */
\r
7867 #define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
\r
7868 #define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
\r
7869 a transmission attempt during retries after a collision: 0 =< r <2^k */
\r
7870 #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */
\r
7871 #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */
\r
7872 #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */
\r
7873 #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */
\r
7874 #define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */
\r
7875 #define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */
\r
7876 #define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */
\r
7878 /* Bit definition for Ethernet MAC Frame Filter Register */
\r
7879 #define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */
\r
7880 #define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */
\r
7881 #define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */
\r
7882 #define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */
\r
7883 #define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
\r
7884 #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
\r
7885 #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
\r
7886 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
\r
7887 #define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */
\r
7888 #define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */
\r
7889 #define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */
\r
7890 #define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */
\r
7891 #define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */
\r
7892 #define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */
\r
7894 /* Bit definition for Ethernet MAC Hash Table High Register */
\r
7895 #define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */
\r
7897 /* Bit definition for Ethernet MAC Hash Table Low Register */
\r
7898 #define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */
\r
7900 /* Bit definition for Ethernet MAC MII Address Register */
\r
7901 #define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */
\r
7902 #define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */
\r
7903 #define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
\r
7904 #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
\r
7905 #define ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
\r
7906 #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
\r
7907 #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
\r
7908 #define ETH_MACMIIAR_CR_Div102 ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
\r
7909 #define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */
\r
7910 #define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */
\r
7912 /* Bit definition for Ethernet MAC MII Data Register */
\r
7913 #define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
\r
7915 /* Bit definition for Ethernet MAC Flow Control Register */
\r
7916 #define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */
\r
7917 #define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */
\r
7918 #define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
\r
7919 #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
\r
7920 #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
\r
7921 #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
\r
7922 #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
\r
7923 #define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */
\r
7924 #define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */
\r
7925 #define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */
\r
7926 #define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */
\r
7928 /* Bit definition for Ethernet MAC VLAN Tag Register */
\r
7929 #define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
\r
7930 #define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
\r
7932 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
\r
7933 #define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
\r
7934 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
\r
7935 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
\r
7936 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
\r
7937 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
\r
7938 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
\r
7939 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
\r
7940 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
\r
7941 RSVD - Filter1 Command - RSVD - Filter0 Command
\r
7942 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
\r
7943 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
\r
7944 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
\r
7946 /* Bit definition for Ethernet MAC PMT Control and Status Register */
\r
7947 #define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
\r
7948 #define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */
\r
7949 #define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */
\r
7950 #define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */
\r
7951 #define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
\r
7952 #define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */
\r
7953 #define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */
\r
7955 /* Bit definition for Ethernet MAC Status Register */
\r
7956 #define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */
\r
7957 #define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */
\r
7958 #define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */
\r
7959 #define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */
\r
7960 #define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */
\r
7962 /* Bit definition for Ethernet MAC Interrupt Mask Register */
\r
7963 #define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
\r
7964 #define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */
\r
7966 /* Bit definition for Ethernet MAC Address0 High Register */
\r
7967 #define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */
\r
7969 /* Bit definition for Ethernet MAC Address0 Low Register */
\r
7970 #define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */
\r
7972 /* Bit definition for Ethernet MAC Address1 High Register */
\r
7973 #define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */
\r
7974 #define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */
\r
7975 #define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
\r
7976 #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
\r
7977 #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
\r
7978 #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
\r
7979 #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
\r
7980 #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
\r
7981 #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
\r
7982 #define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */
\r
7984 /* Bit definition for Ethernet MAC Address1 Low Register */
\r
7985 #define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */
\r
7987 /* Bit definition for Ethernet MAC Address2 High Register */
\r
7988 #define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */
\r
7989 #define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */
\r
7990 #define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
\r
7991 #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
\r
7992 #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
\r
7993 #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
\r
7994 #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
\r
7995 #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
\r
7996 #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
\r
7997 #define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */
\r
7999 /* Bit definition for Ethernet MAC Address2 Low Register */
\r
8000 #define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */
\r
8002 /* Bit definition for Ethernet MAC Address3 High Register */
\r
8003 #define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */
\r
8004 #define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */
\r
8005 #define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
\r
8006 #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
\r
8007 #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
\r
8008 #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
\r
8009 #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
\r
8010 #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
\r
8011 #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
\r
8012 #define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */
\r
8014 /* Bit definition for Ethernet MAC Address3 Low Register */
\r
8015 #define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */
\r
8017 /******************************************************************************/
\r
8018 /* Ethernet MMC Registers bits definition */
\r
8019 /******************************************************************************/
\r
8021 /* Bit definition for Ethernet MMC Contol Register */
\r
8022 #define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset */
\r
8023 #define ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset */
\r
8024 #define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */
\r
8025 #define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */
\r
8026 #define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */
\r
8027 #define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */
\r
8029 /* Bit definition for Ethernet MMC Receive Interrupt Register */
\r
8030 #define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
\r
8031 #define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
\r
8032 #define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
\r
8034 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
\r
8035 #define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
\r
8036 #define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
\r
8037 #define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
\r
8039 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
\r
8040 #define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
\r
8041 #define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
\r
8042 #define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
\r
8044 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
\r
8045 #define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
\r
8046 #define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
\r
8047 #define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
\r
8049 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
\r
8050 #define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
\r
8052 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
\r
8053 #define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
\r
8055 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
\r
8056 #define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */
\r
8058 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
\r
8059 #define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
\r
8061 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
\r
8062 #define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
\r
8064 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
\r
8065 #define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */
\r
8067 /******************************************************************************/
\r
8068 /* Ethernet PTP Registers bits definition */
\r
8069 /******************************************************************************/
\r
8071 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
\r
8072 #define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */
\r
8073 #define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */
\r
8074 #define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */
\r
8075 #define ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */
\r
8076 #define ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */
\r
8077 #define ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */
\r
8078 #define ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */
\r
8079 #define ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */
\r
8080 #define ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */
\r
8082 #define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */
\r
8083 #define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
\r
8084 #define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */
\r
8085 #define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */
\r
8086 #define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
\r
8087 #define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */
\r
8089 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
\r
8090 #define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */
\r
8092 /* Bit definition for Ethernet PTP Time Stamp High Register */
\r
8093 #define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */
\r
8095 /* Bit definition for Ethernet PTP Time Stamp Low Register */
\r
8096 #define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */
\r
8097 #define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */
\r
8099 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
\r
8100 #define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */
\r
8102 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
\r
8103 #define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
\r
8104 #define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */
\r
8106 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
\r
8107 #define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */
\r
8109 /* Bit definition for Ethernet PTP Target Time High Register */
\r
8110 #define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */
\r
8112 /* Bit definition for Ethernet PTP Target Time Low Register */
\r
8113 #define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */
\r
8115 /* Bit definition for Ethernet PTP Time Stamp Status Register */
\r
8116 #define ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */
\r
8117 #define ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */
\r
8119 /******************************************************************************/
\r
8120 /* Ethernet DMA Registers bits definition */
\r
8121 /******************************************************************************/
\r
8123 /* Bit definition for Ethernet DMA Bus Mode Register */
\r
8124 #define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */
\r
8125 #define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */
\r
8126 #define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */
\r
8127 #define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */
\r
8128 #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
\r
8129 #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
\r
8130 #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
\r
8131 #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
\r
8132 #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
\r
8133 #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
\r
8134 #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
\r
8135 #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
\r
8136 #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
\r
8137 #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
\r
8138 #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
\r
8139 #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
\r
8140 #define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */
\r
8141 #define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
\r
8142 #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */
\r
8143 #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */
\r
8144 #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */
\r
8145 #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
\r
8146 #define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */
\r
8147 #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
\r
8148 #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
\r
8149 #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
\r
8150 #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
\r
8151 #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
\r
8152 #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
\r
8153 #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
\r
8154 #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
\r
8155 #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
\r
8156 #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
\r
8157 #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
\r
8158 #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
\r
8159 #define ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */
\r
8160 #define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */
\r
8161 #define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */
\r
8162 #define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */
\r
8164 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
\r
8165 #define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */
\r
8167 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
\r
8168 #define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */
\r
8170 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
\r
8171 #define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */
\r
8173 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
\r
8174 #define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */
\r
8176 /* Bit definition for Ethernet DMA Status Register */
\r
8177 #define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */
\r
8178 #define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */
\r
8179 #define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */
\r
8180 #define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */
\r
8181 /* combination with EBS[2:0] for GetFlagStatus function */
\r
8182 #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
\r
8183 #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
\r
8184 #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
\r
8185 #define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */
\r
8186 #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
\r
8187 #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
\r
8188 #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */
\r
8189 #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */
\r
8190 #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
\r
8191 #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
\r
8192 #define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */
\r
8193 #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
\r
8194 #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
\r
8195 #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */
\r
8196 #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
\r
8197 #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */
\r
8198 #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
\r
8199 #define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */
\r
8200 #define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */
\r
8201 #define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */
\r
8202 #define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */
\r
8203 #define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */
\r
8204 #define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */
\r
8205 #define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */
\r
8206 #define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */
\r
8207 #define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */
\r
8208 #define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */
\r
8209 #define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */
\r
8210 #define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */
\r
8211 #define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
\r
8212 #define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */
\r
8213 #define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */
\r
8215 /* Bit definition for Ethernet DMA Operation Mode Register */
\r
8216 #define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
\r
8217 #define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */
\r
8218 #define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */
\r
8219 #define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */
\r
8220 #define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */
\r
8221 #define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */
\r
8222 #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
\r
8223 #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
\r
8224 #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
\r
8225 #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
\r
8226 #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
\r
8227 #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
\r
8228 #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
\r
8229 #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
\r
8230 #define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */
\r
8231 #define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */
\r
8232 #define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */
\r
8233 #define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */
\r
8234 #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
\r
8235 #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
\r
8236 #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
\r
8237 #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
\r
8238 #define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */
\r
8239 #define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */
\r
8241 /* Bit definition for Ethernet DMA Interrupt Enable Register */
\r
8242 #define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */
\r
8243 #define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
\r
8244 #define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */
\r
8245 #define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
\r
8246 #define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */
\r
8247 #define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
\r
8248 #define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
\r
8249 #define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
\r
8250 #define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */
\r
8251 #define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
\r
8252 #define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
\r
8253 #define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
\r
8254 #define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
\r
8255 #define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
\r
8256 #define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */
\r
8258 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
\r
8259 #define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
\r
8260 #define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
\r
8261 #define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
\r
8262 #define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */
\r
8264 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
\r
8265 #define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */
\r
8267 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
\r
8268 #define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */
\r
8270 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
\r
8271 #define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */
\r
8273 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
\r
8274 #define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
\r
8276 /******************************************************************************/
\r
8280 /******************************************************************************/
\r
8281 /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
\r
8282 #define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) /*!< Session request success */
\r
8283 #define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) /*!< Session request */
\r
8284 #define USB_OTG_GOTGCTL_VBVALOEN ((uint32_t)0x00000004) /*!< VBUS valid override enable */
\r
8285 #define USB_OTG_GOTGCTL_VBVALOVAL ((uint32_t)0x00000008) /*!< VBUS valid override value */
\r
8286 #define USB_OTG_GOTGCTL_AVALOEN ((uint32_t)0x00000010) /*!< A-peripheral session valid override enable */
\r
8287 #define USB_OTG_GOTGCTL_AVALOVAL ((uint32_t)0x00000020) /*!< A-peripheral session valid override value */
\r
8288 #define USB_OTG_GOTGCTL_BVALOEN ((uint32_t)0x00000040) /*!< B-peripheral session valid override enable */
\r
8289 #define USB_OTG_GOTGCTL_BVALOVAL ((uint32_t)0x00000080) /*!< B-peripheral session valid override value */
\r
8290 #define USB_OTG_GOTGCTL_HNGSCS ((uint32_t)0x00000100) /*!< Host set HNP enable */
\r
8291 #define USB_OTG_GOTGCTL_HNPRQ ((uint32_t)0x00000200) /*!< HNP request */
\r
8292 #define USB_OTG_GOTGCTL_HSHNPEN ((uint32_t)0x00000400) /*!< Host set HNP enable */
\r
8293 #define USB_OTG_GOTGCTL_DHNPEN ((uint32_t)0x00000800) /*!< Device HNP enabled */
\r
8294 #define USB_OTG_GOTGCTL_EHEN ((uint32_t)0x00001000) /*!< Embedded host enable */
\r
8295 #define USB_OTG_GOTGCTL_CIDSTS ((uint32_t)0x00010000) /*!< Connector ID status */
\r
8296 #define USB_OTG_GOTGCTL_DBCT ((uint32_t)0x00020000) /*!< Long/short debounce time */
\r
8297 #define USB_OTG_GOTGCTL_ASVLD ((uint32_t)0x00040000) /*!< A-session valid */
\r
8298 #define USB_OTG_GOTGCTL_BSESVLD ((uint32_t)0x00080000) /*!< B-session valid */
\r
8299 #define USB_OTG_GOTGCTL_OTGVER ((uint32_t)0x00100000) /*!< OTG version */
\r
8301 /******************** Bit definition forUSB_OTG_HCFG register ********************/
\r
8303 #define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) /*!< FS/LS PHY clock select */
\r
8304 #define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
8305 #define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
8306 #define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) /*!< FS- and LS-only support */
\r
8308 /******************** Bit definition forUSB_OTG_DCFG register ********************/
\r
8310 #define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) /*!< Device speed */
\r
8311 #define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
8312 #define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
8313 #define USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004) /*!< Nonzero-length status OUT handshake */
\r
8315 #define USB_OTG_DCFG_DAD ((uint32_t)0x000007F0) /*!< Device address */
\r
8316 #define USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
\r
8317 #define USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
\r
8318 #define USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
\r
8319 #define USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
\r
8320 #define USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100) /*!<Bit 4 */
\r
8321 #define USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200) /*!<Bit 5 */
\r
8322 #define USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400) /*!<Bit 6 */
\r
8324 #define USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800) /*!< Periodic (micro)frame interval */
\r
8325 #define USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800) /*!<Bit 0 */
\r
8326 #define USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000) /*!<Bit 1 */
\r
8328 #define USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000) /*!< Periodic scheduling interval */
\r
8329 #define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
\r
8330 #define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
\r
8332 /******************** Bit definition forUSB_OTG_PCGCR register ********************/
\r
8333 #define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) /*!< Stop PHY clock */
\r
8334 #define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) /*!< Gate HCLK */
\r
8335 #define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) /*!< PHY suspended */
\r
8337 /******************** Bit definition forUSB_OTG_GOTGINT register ********************/
\r
8338 #define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) /*!< Session end detected */
\r
8339 #define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) /*!< Session request success status change */
\r
8340 #define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) /*!< Host negotiation success status change */
\r
8341 #define USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000) /*!< Host negotiation detected */
\r
8342 #define USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000) /*!< A-device timeout change */
\r
8343 #define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) /*!< Debounce done */
\r
8344 #define USB_OTG_GOTGINT_IDCHNG ((uint32_t)0x00100000) /*!< Change in ID pin input value */
\r
8346 /******************** Bit definition forUSB_OTG_DCTL register ********************/
\r
8347 #define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) /*!< Remote wakeup signaling */
\r
8348 #define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) /*!< Soft disconnect */
\r
8349 #define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) /*!< Global IN NAK status */
\r
8350 #define USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008) /*!< Global OUT NAK status */
\r
8352 #define USB_OTG_DCTL_TCTL ((uint32_t)0x00000070) /*!< Test control */
\r
8353 #define USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010) /*!<Bit 0 */
\r
8354 #define USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020) /*!<Bit 1 */
\r
8355 #define USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040) /*!<Bit 2 */
\r
8356 #define USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080) /*!< Set global IN NAK */
\r
8357 #define USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100) /*!< Clear global IN NAK */
\r
8358 #define USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200) /*!< Set global OUT NAK */
\r
8359 #define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) /*!< Clear global OUT NAK */
\r
8360 #define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) /*!< Power-on programming done */
\r
8362 /******************** Bit definition forUSB_OTG_HFIR register ********************/
\r
8363 #define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) /*!< Frame interval */
\r
8365 /******************** Bit definition forUSB_OTG_HFNUM register ********************/
\r
8366 #define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) /*!< Frame number */
\r
8367 #define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) /*!< Frame time remaining */
\r
8369 /******************** Bit definition forUSB_OTG_DSTS register ********************/
\r
8370 #define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) /*!< Suspend status */
\r
8372 #define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) /*!< Enumerated speed */
\r
8373 #define USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002) /*!<Bit 0 */
\r
8374 #define USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004) /*!<Bit 1 */
\r
8375 #define USB_OTG_DSTS_EERR ((uint32_t)0x00000008) /*!< Erratic error */
\r
8376 #define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) /*!< Frame number of the received SOF */
\r
8378 /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
\r
8379 #define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) /*!< Global interrupt mask */
\r
8380 #define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) /*!< Burst length/type */
\r
8381 #define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
\r
8382 #define USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
\r
8383 #define USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008) /*!<Bit 2 */
\r
8384 #define USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010) /*!<Bit 3 */
\r
8385 #define USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020) /*!< DMA enable */
\r
8386 #define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) /*!< TxFIFO empty level */
\r
8387 #define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) /*!< Periodic TxFIFO empty level */
\r
8389 /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
\r
8391 #define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) /*!< FS timeout calibration */
\r
8392 #define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
8393 #define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
8394 #define USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
8395 #define USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040) /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
\r
8396 #define USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100) /*!< SRP-capable */
\r
8397 #define USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200) /*!< HNP-capable */
\r
8398 #define USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00) /*!< USB turnaround time */
\r
8399 #define USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400) /*!<Bit 0 */
\r
8400 #define USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800) /*!<Bit 1 */
\r
8401 #define USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000) /*!<Bit 2 */
\r
8402 #define USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000) /*!<Bit 3 */
\r
8403 #define USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000) /*!< PHY Low-power clock select */
\r
8404 #define USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000) /*!< ULPI FS/LS select */
\r
8405 #define USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000) /*!< ULPI Auto-resume */
\r
8406 #define USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000) /*!< ULPI Clock SuspendM */
\r
8407 #define USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000) /*!< ULPI External VBUS Drive */
\r
8408 #define USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000) /*!< ULPI external VBUS indicator */
\r
8409 #define USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000) /*!< TermSel DLine pulsing selection */
\r
8410 #define USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000) /*!< Indicator complement */
\r
8411 #define USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000) /*!< Indicator pass through */
\r
8412 #define USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000) /*!< ULPI interface protect disable */
\r
8413 #define USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000) /*!< Forced host mode */
\r
8414 #define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) /*!< Forced peripheral mode */
\r
8415 #define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) /*!< Corrupt Tx packet */
\r
8417 /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
\r
8418 #define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) /*!< Core soft reset */
\r
8419 #define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) /*!< HCLK soft reset */
\r
8420 #define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) /*!< Host frame counter reset */
\r
8421 #define USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010) /*!< RxFIFO flush */
\r
8422 #define USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020) /*!< TxFIFO flush */
\r
8423 #define USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0) /*!< TxFIFO number */
\r
8424 #define USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040) /*!<Bit 0 */
\r
8425 #define USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080) /*!<Bit 1 */
\r
8426 #define USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100) /*!<Bit 2 */
\r
8427 #define USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200) /*!<Bit 3 */
\r
8428 #define USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400) /*!<Bit 4 */
\r
8429 #define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) /*!< DMA request signal */
\r
8430 #define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) /*!< AHB master idle */
\r
8432 /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
\r
8433 #define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
\r
8434 #define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
\r
8435 #define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
\r
8436 #define USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
\r
8437 #define USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
\r
8438 #define USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
\r
8439 #define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
\r
8440 #define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
\r
8442 /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
\r
8443 #define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) /*!< Periodic transmit data FIFO space available */
\r
8444 #define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) /*!< Periodic transmit request queue space available */
\r
8445 #define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
\r
8446 #define USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
\r
8447 #define USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
\r
8448 #define USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
\r
8449 #define USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
\r
8450 #define USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
\r
8451 #define USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
\r
8452 #define USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
\r
8454 #define USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000) /*!< Top of the periodic transmit request queue */
\r
8455 #define USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
\r
8456 #define USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
\r
8457 #define USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
\r
8458 #define USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
\r
8459 #define USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
\r
8460 #define USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
\r
8461 #define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
\r
8462 #define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) /*!<Bit 7 */
\r
8464 /******************** Bit definition forUSB_OTG_HAINT register ********************/
\r
8465 #define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) /*!< Channel interrupts */
\r
8467 /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
\r
8468 #define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
\r
8469 #define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
\r
8470 #define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /*!< SETUP phase done mask */
\r
8471 #define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled mask */
\r
8472 #define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received mask */
\r
8473 #define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /*!< OUT packet error mask */
\r
8474 #define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
\r
8476 /******************** Bit definition forUSB_OTG_GINTSTS register ********************/
\r
8477 #define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) /*!< Current mode of operation */
\r
8478 #define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) /*!< Mode mismatch interrupt */
\r
8479 #define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt */
\r
8480 #define USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008) /*!< Start of frame */
\r
8481 #define USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010) /*!< RxFIFO nonempty */
\r
8482 #define USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty */
\r
8483 #define USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040) /*!< Global IN nonperiodic NAK effective */
\r
8484 #define USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080) /*!< Global OUT NAK effective */
\r
8485 #define USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400) /*!< Early suspend */
\r
8486 #define USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800) /*!< USB suspend */
\r
8487 #define USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000) /*!< USB reset */
\r
8488 #define USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000) /*!< Enumeration done */
\r
8489 #define USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt */
\r
8490 #define USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000) /*!< End of periodic frame interrupt */
\r
8491 #define USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000) /*!< IN endpoint interrupt */
\r
8492 #define USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoint interrupt */
\r
8493 #define USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer */
\r
8494 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000) /*!< Incomplete periodic transfer */
\r
8495 #define USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000) /*!< Data fetch suspended */
\r
8496 #define USB_OTG_GINTSTS_RSTDET ((uint32_t)0x00800000) /*!< Reset detected interrupt */
\r
8497 #define USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000) /*!< Host port interrupt */
\r
8498 #define USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000) /*!< Host channels interrupt */
\r
8499 #define USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty */
\r
8500 #define USB_OTG_GINTSTS_LPMINT ((uint32_t)0x08000000) /*!< LPM interrupt */
\r
8501 #define USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000) /*!< Connector ID status change */
\r
8502 #define USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt */
\r
8503 #define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt */
\r
8504 #define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt */
\r
8506 /******************** Bit definition forUSB_OTG_GINTMSK register ********************/
\r
8507 #define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) /*!< Mode mismatch interrupt mask */
\r
8508 #define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt mask */
\r
8509 #define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) /*!< Start of frame mask */
\r
8510 #define USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010) /*!< Receive FIFO nonempty mask */
\r
8511 #define USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty mask */
\r
8512 #define USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040) /*!< Global nonperiodic IN NAK effective mask */
\r
8513 #define USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080) /*!< Global OUT NAK effective mask */
\r
8514 #define USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400) /*!< Early suspend mask */
\r
8515 #define USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800) /*!< USB suspend mask */
\r
8516 #define USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000) /*!< USB reset mask */
\r
8517 #define USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000) /*!< Enumeration done mask */
\r
8518 #define USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt mask */
\r
8519 #define USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000) /*!< End of periodic frame interrupt mask */
\r
8520 #define USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000) /*!< Endpoint mismatch interrupt mask */
\r
8521 #define USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000) /*!< IN endpoints interrupt mask */
\r
8522 #define USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoints interrupt mask */
\r
8523 #define USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer mask */
\r
8524 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000) /*!< Incomplete periodic transfer mask */
\r
8525 #define USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000) /*!< Data fetch suspended mask */
\r
8526 #define USB_OTG_GINTMSK_RSTDEM ((uint32_t)0x00800000) /*!< Reset detected interrupt mask */
\r
8527 #define USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000) /*!< Host port interrupt mask */
\r
8528 #define USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000) /*!< Host channels interrupt mask */
\r
8529 #define USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty mask */
\r
8530 #define USB_OTG_GINTMSK_LPMINTM ((uint32_t)0x08000000) /*!< LPM interrupt Mask */
\r
8531 #define USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000) /*!< Connector ID status change mask */
\r
8532 #define USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt mask */
\r
8533 #define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt mask */
\r
8534 #define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt mask */
\r
8536 /******************** Bit definition forUSB_OTG_DAINT register ********************/
\r
8537 #define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) /*!< IN endpoint interrupt bits */
\r
8538 #define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) /*!< OUT endpoint interrupt bits */
\r
8540 /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
\r
8541 #define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) /*!< Channel interrupt mask */
\r
8543 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
\r
8544 #define USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000F) /*!< IN EP interrupt mask bits */
\r
8545 #define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /*!< OUT EP interrupt mask bits */
\r
8546 #define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /*!< OUT EP interrupt mask bits */
\r
8547 #define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /*!< OUT EP interrupt mask bits */
\r
8549 /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
\r
8550 #define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) /*!< IN EP interrupt mask bits */
\r
8551 #define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) /*!< OUT EP interrupt mask bits */
\r
8553 /******************** Bit definition for OTG register ********************/
\r
8555 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
\r
8556 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
8557 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
8558 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
8559 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
8560 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
\r
8562 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
\r
8563 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
\r
8564 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
\r
8566 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
\r
8567 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
\r
8568 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
\r
8569 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
\r
8570 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
\r
8572 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
\r
8573 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
8574 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
8575 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
8576 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
8578 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
\r
8579 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
\r
8580 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
\r
8581 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
\r
8582 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
\r
8584 /******************** Bit definition for OTG register ********************/
\r
8586 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
\r
8587 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
8588 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
8589 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
8590 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
8591 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
\r
8593 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
\r
8594 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
\r
8595 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
\r
8597 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
\r
8598 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
\r
8599 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
\r
8600 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
\r
8601 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
\r
8603 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
\r
8604 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
8605 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
8606 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
8607 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
8609 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
\r
8610 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
\r
8611 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
\r
8612 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
\r
8613 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
\r
8615 /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
\r
8616 #define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) /*!< RxFIFO depth */
\r
8618 /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
\r
8619 #define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) /*!< Device VBUS discharge time */
\r
8621 /******************** Bit definition for OTG register ********************/
\r
8622 #define USB_OTG_NPTXFSA ((uint32_t)0x0000FFFF) /*!< Nonperiodic transmit RAM start address */
\r
8623 #define USB_OTG_NPTXFD ((uint32_t)0xFFFF0000) /*!< Nonperiodic TxFIFO depth */
\r
8624 #define USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) /*!< Endpoint 0 transmit RAM start address */
\r
8625 #define USB_OTG_TX0FD ((uint32_t)0xFFFF0000) /*!< Endpoint 0 TxFIFO depth */
\r
8627 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
\r
8628 #define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) /*!< Device VBUS pulsing time */
\r
8630 /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
\r
8631 #define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) /*!< Nonperiodic TxFIFO space available */
\r
8633 #define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) /*!< Nonperiodic transmit request queue space available */
\r
8634 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
\r
8635 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
\r
8636 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
\r
8637 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
\r
8638 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
\r
8639 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
\r
8640 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
\r
8641 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
\r
8643 #define USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000) /*!< Top of the nonperiodic transmit request queue */
\r
8644 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
\r
8645 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
\r
8646 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
\r
8647 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
\r
8648 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
\r
8649 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
\r
8650 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
\r
8652 /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
\r
8653 #define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) /*!< Nonisochronous IN endpoints threshold enable */
\r
8654 #define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) /*!< ISO IN endpoint threshold enable */
\r
8656 #define USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FC) /*!< Transmit threshold length */
\r
8657 #define USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004) /*!<Bit 0 */
\r
8658 #define USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008) /*!<Bit 1 */
\r
8659 #define USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010) /*!<Bit 2 */
\r
8660 #define USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020) /*!<Bit 3 */
\r
8661 #define USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040) /*!<Bit 4 */
\r
8662 #define USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080) /*!<Bit 5 */
\r
8663 #define USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100) /*!<Bit 6 */
\r
8664 #define USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200) /*!<Bit 7 */
\r
8665 #define USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400) /*!<Bit 8 */
\r
8666 #define USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000) /*!< Receive threshold enable */
\r
8668 #define USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000) /*!< Receive threshold length */
\r
8669 #define USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000) /*!<Bit 0 */
\r
8670 #define USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000) /*!<Bit 1 */
\r
8671 #define USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000) /*!<Bit 2 */
\r
8672 #define USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000) /*!<Bit 3 */
\r
8673 #define USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000) /*!<Bit 4 */
\r
8674 #define USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000) /*!<Bit 5 */
\r
8675 #define USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000) /*!<Bit 6 */
\r
8676 #define USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000) /*!<Bit 7 */
\r
8677 #define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) /*!<Bit 8 */
\r
8678 #define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) /*!< Arbiter parking enable */
\r
8680 /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
\r
8681 #define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) /*!< IN EP Tx FIFO empty interrupt mask bits */
\r
8683 /******************** Bit definition forUSB_OTG_DEACHINT register ********************/
\r
8684 #define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) /*!< IN endpoint 1interrupt bit */
\r
8685 #define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) /*!< OUT endpoint 1 interrupt bit */
\r
8687 /******************** Bit definition forUSB_OTG_GCCFG register ********************/
\r
8688 #define USB_OTG_GCCFG_DCDET ((uint32_t)0x00000001) /*!< Data contact detection (DCD) status */
\r
8689 #define USB_OTG_GCCFG_PDET ((uint32_t)0x00000002) /*!< Primary detection (PD) status */
\r
8690 #define USB_OTG_GCCFG_SDET ((uint32_t)0x00000004) /*!< Secondary detection (SD) status */
\r
8691 #define USB_OTG_GCCFG_PS2DET ((uint32_t)0x00000008) /*!< DM pull-up detection status */
\r
8692 #define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) /*!< Power down */
\r
8693 #define USB_OTG_GCCFG_BCDEN ((uint32_t)0x00020000) /*!< Battery charging detector (BCD) enable */
\r
8694 #define USB_OTG_GCCFG_DCDEN ((uint32_t)0x00040000) /*!< Data contact detection (DCD) mode enable*/
\r
8695 #define USB_OTG_GCCFG_PDEN ((uint32_t)0x00080000) /*!< Primary detection (PD) mode enable*/
\r
8696 #define USB_OTG_GCCFG_SDEN ((uint32_t)0x00100000) /*!< Secondary detection (SD) mode enable */
\r
8697 #define USB_OTG_GCCFG_VBDEN ((uint32_t)0x00200000) /*!< USB VBUS Detection Enable */
\r
8699 /******************** Bit definition forUSB_OTG_GPWRDN) register ********************/
\r
8700 #define USB_OTG_GPWRDN_ADPMEN ((uint32_t)0x00000001) /*!< ADP module enable */
\r
8701 #define USB_OTG_GPWRDN_ADPIF ((uint32_t)0x00800000) /*!< ADP Interrupt flag */
\r
8703 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
\r
8704 #define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) /*!< IN Endpoint 1 interrupt mask bit */
\r
8705 #define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) /*!< OUT Endpoint 1 interrupt mask bit */
\r
8707 /******************** Bit definition forUSB_OTG_CID register ********************/
\r
8708 #define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) /*!< Product ID field */
\r
8710 /******************** Bit definition for USB_OTG_GLPMCFG register ********************/
\r
8711 #define USB_OTG_GLPMCFG_LPMEN ((uint32_t)0x00000001) /*!< LPM support enable */
\r
8712 #define USB_OTG_GLPMCFG_LPMACK ((uint32_t)0x00000002) /*!< LPM Token acknowledge enable */
\r
8713 #define USB_OTG_GLPMCFG_BESL ((uint32_t)0x0000003C) /*!< BESL value received with last ACKed LPM Token */
\r
8714 #define USB_OTG_GLPMCFG_REMWAKE ((uint32_t)0x00000040) /*!< bRemoteWake value received with last ACKed LPM Token */
\r
8715 #define USB_OTG_GLPMCFG_L1SSEN ((uint32_t)0x00000080) /*!< L1 shallow sleep enable */
\r
8716 #define USB_OTG_GLPMCFG_BESLTHRS ((uint32_t)0x00000F00) /*!< BESL threshold */
\r
8717 #define USB_OTG_GLPMCFG_L1DSEN ((uint32_t)0x00001000) /*!< L1 deep sleep enable */
\r
8718 #define USB_OTG_GLPMCFG_LPMRSP ((uint32_t)0x00006000) /*!< LPM response */
\r
8719 #define USB_OTG_GLPMCFG_SLPSTS ((uint32_t)0x00008000) /*!< Port sleep status */
\r
8720 #define USB_OTG_GLPMCFG_L1RSMOK ((uint32_t)0x00010000) /*!< Sleep State Resume OK */
\r
8721 #define USB_OTG_GLPMCFG_LPMCHIDX ((uint32_t)0x001E0000) /*!< LPM Channel Index */
\r
8722 #define USB_OTG_GLPMCFG_LPMRCNT ((uint32_t)0x00E00000) /*!< LPM retry count */
\r
8723 #define USB_OTG_GLPMCFG_SNDLPM ((uint32_t)0x01000000) /*!< Send LPM transaction */
\r
8724 #define USB_OTG_GLPMCFG_LPMRCNTSTS ((uint32_t)0x0E000000) /*!< LPM retry count status */
\r
8725 #define USB_OTG_GLPMCFG_ENBESL ((uint32_t)0x10000000) /*!< Enable best effort service latency */
\r
8727 /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
\r
8728 #define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
\r
8729 #define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
\r
8730 #define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
\r
8731 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
\r
8732 #define USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
\r
8733 #define USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
\r
8734 #define USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
\r
8735 #define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
\r
8736 #define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
\r
8738 /******************** Bit definition forUSB_OTG_HPRT register ********************/
\r
8739 #define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) /*!< Port connect status */
\r
8740 #define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) /*!< Port connect detected */
\r
8741 #define USB_OTG_HPRT_PENA ((uint32_t)0x00000004) /*!< Port enable */
\r
8742 #define USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008) /*!< Port enable/disable change */
\r
8743 #define USB_OTG_HPRT_POCA ((uint32_t)0x00000010) /*!< Port overcurrent active */
\r
8744 #define USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020) /*!< Port overcurrent change */
\r
8745 #define USB_OTG_HPRT_PRES ((uint32_t)0x00000040) /*!< Port resume */
\r
8746 #define USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080) /*!< Port suspend */
\r
8747 #define USB_OTG_HPRT_PRST ((uint32_t)0x00000100) /*!< Port reset */
\r
8749 #define USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00) /*!< Port line status */
\r
8750 #define USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400) /*!<Bit 0 */
\r
8751 #define USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800) /*!<Bit 1 */
\r
8752 #define USB_OTG_HPRT_PPWR ((uint32_t)0x00001000) /*!< Port power */
\r
8754 #define USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000) /*!< Port test control */
\r
8755 #define USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000) /*!<Bit 0 */
\r
8756 #define USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000) /*!<Bit 1 */
\r
8757 #define USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000) /*!<Bit 2 */
\r
8758 #define USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000) /*!<Bit 3 */
\r
8760 #define USB_OTG_HPRT_PSPD ((uint32_t)0x00060000) /*!< Port speed */
\r
8761 #define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
\r
8762 #define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
\r
8764 /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
\r
8765 #define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
\r
8766 #define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
\r
8767 #define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask */
\r
8768 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
\r
8769 #define USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
\r
8770 #define USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
\r
8771 #define USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< OUT packet error mask */
\r
8772 #define USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
\r
8773 #define USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000) /*!< Bubble error interrupt mask */
\r
8774 #define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
\r
8775 #define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) /*!< NYET interrupt mask */
\r
8777 /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
\r
8778 #define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) /*!< Host periodic TxFIFO start address */
\r
8779 #define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) /*!< Host periodic TxFIFO depth */
\r
8781 /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
\r
8782 #define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
\r
8783 #define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
\r
8784 #define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) /*!< Even/odd frame */
\r
8785 #define USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
\r
8787 #define USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
\r
8788 #define USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
\r
8789 #define USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
\r
8790 #define USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
\r
8792 #define USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000) /*!< TxFIFO number */
\r
8793 #define USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000) /*!<Bit 0 */
\r
8794 #define USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000) /*!<Bit 1 */
\r
8795 #define USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000) /*!<Bit 2 */
\r
8796 #define USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000) /*!<Bit 3 */
\r
8797 #define USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
\r
8798 #define USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
\r
8799 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
\r
8800 #define USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
\r
8801 #define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
\r
8802 #define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
\r
8804 /******************** Bit definition forUSB_OTG_HCCHAR register ********************/
\r
8805 #define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
\r
8807 #define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) /*!< Endpoint number */
\r
8808 #define USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800) /*!<Bit 0 */
\r
8809 #define USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000) /*!<Bit 1 */
\r
8810 #define USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000) /*!<Bit 2 */
\r
8811 #define USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000) /*!<Bit 3 */
\r
8812 #define USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000) /*!< Endpoint direction */
\r
8813 #define USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000) /*!< Low-speed device */
\r
8815 #define USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
\r
8816 #define USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
\r
8817 #define USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
\r
8819 #define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /*!< Multi Count (MC) / Error Count (EC) */
\r
8820 #define USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000) /*!<Bit 0 */
\r
8821 #define USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000) /*!<Bit 1 */
\r
8823 #define USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000) /*!< Device address */
\r
8824 #define USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000) /*!<Bit 0 */
\r
8825 #define USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000) /*!<Bit 1 */
\r
8826 #define USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000) /*!<Bit 2 */
\r
8827 #define USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000) /*!<Bit 3 */
\r
8828 #define USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000) /*!<Bit 4 */
\r
8829 #define USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000) /*!<Bit 5 */
\r
8830 #define USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000) /*!<Bit 6 */
\r
8831 #define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /*!< Odd frame */
\r
8832 #define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /*!< Channel disable */
\r
8833 #define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /*!< Channel enable */
\r
8835 /******************** Bit definition forUSB_OTG_HCSPLT register ********************/
\r
8837 #define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) /*!< Port address */
\r
8838 #define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) /*!<Bit 0 */
\r
8839 #define USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002) /*!<Bit 1 */
\r
8840 #define USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004) /*!<Bit 2 */
\r
8841 #define USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008) /*!<Bit 3 */
\r
8842 #define USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010) /*!<Bit 4 */
\r
8843 #define USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020) /*!<Bit 5 */
\r
8844 #define USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040) /*!<Bit 6 */
\r
8846 #define USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80) /*!< Hub address */
\r
8847 #define USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080) /*!<Bit 0 */
\r
8848 #define USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100) /*!<Bit 1 */
\r
8849 #define USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200) /*!<Bit 2 */
\r
8850 #define USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400) /*!<Bit 3 */
\r
8851 #define USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800) /*!<Bit 4 */
\r
8852 #define USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000) /*!<Bit 5 */
\r
8853 #define USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000) /*!<Bit 6 */
\r
8855 #define USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000) /*!< XACTPOS */
\r
8856 #define USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000) /*!<Bit 0 */
\r
8857 #define USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000) /*!<Bit 1 */
\r
8858 #define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) /*!< Do complete split */
\r
8859 #define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) /*!< Split enable */
\r
8861 /******************** Bit definition forUSB_OTG_HCINT register ********************/
\r
8862 #define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed */
\r
8863 #define USB_OTG_HCINT_CHH ((uint32_t)0x00000002) /*!< Channel halted */
\r
8864 #define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
\r
8865 #define USB_OTG_HCINT_STALL ((uint32_t)0x00000008) /*!< STALL response received interrupt */
\r
8866 #define USB_OTG_HCINT_NAK ((uint32_t)0x00000010) /*!< NAK response received interrupt */
\r
8867 #define USB_OTG_HCINT_ACK ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt */
\r
8868 #define USB_OTG_HCINT_NYET ((uint32_t)0x00000040) /*!< Response received interrupt */
\r
8869 #define USB_OTG_HCINT_TXERR ((uint32_t)0x00000080) /*!< Transaction error */
\r
8870 #define USB_OTG_HCINT_BBERR ((uint32_t)0x00000100) /*!< Babble error */
\r
8871 #define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) /*!< Frame overrun */
\r
8872 #define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) /*!< Data toggle error */
\r
8874 /******************** Bit definition forUSB_OTG_DIEPINT register ********************/
\r
8875 #define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
\r
8876 #define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
\r
8877 #define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) /*!< Timeout condition */
\r
8878 #define USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010) /*!< IN token received when TxFIFO is empty */
\r
8879 #define USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040) /*!< IN endpoint NAK effective */
\r
8880 #define USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080) /*!< Transmit FIFO empty */
\r
8881 #define USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100) /*!< Transmit Fifo Underrun */
\r
8882 #define USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200) /*!< Buffer not available interrupt */
\r
8883 #define USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800) /*!< Packet dropped status */
\r
8884 #define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) /*!< Babble error interrupt */
\r
8885 #define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) /*!< NAK interrupt */
\r
8887 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
\r
8888 #define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed mask */
\r
8889 #define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) /*!< Channel halted mask */
\r
8890 #define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
\r
8891 #define USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008) /*!< STALL response received interrupt mask */
\r
8892 #define USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010) /*!< NAK response received interrupt mask */
\r
8893 #define USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt mask */
\r
8894 #define USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040) /*!< response received interrupt mask */
\r
8895 #define USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080) /*!< Transaction error mask */
\r
8896 #define USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100) /*!< Babble error mask */
\r
8897 #define USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200) /*!< Frame overrun mask */
\r
8898 #define USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400) /*!< Data toggle error mask */
\r
8900 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
\r
8902 #define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
\r
8903 #define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
\r
8904 #define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) /*!< Packet count */
\r
8905 /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
\r
8906 #define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
\r
8907 #define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
\r
8908 #define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) /*!< Do PING */
\r
8909 #define USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000) /*!< Data PID */
\r
8910 #define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) /*!<Bit 0 */
\r
8911 #define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) /*!<Bit 1 */
\r
8913 /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
\r
8914 #define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
\r
8916 /******************** Bit definition forUSB_OTG_HCDMA register ********************/
\r
8917 #define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
\r
8919 /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
\r
8920 #define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /*!< IN endpoint TxFIFO space available */
\r
8922 /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
\r
8923 #define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) /*!< IN endpoint FIFOx transmit RAM start address */
\r
8924 #define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) /*!< IN endpoint TxFIFO depth */
\r
8926 /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
\r
8927 #define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */ /*!<Bit 1 */
\r
8928 #define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
\r
8929 #define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
\r
8930 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
\r
8931 #define USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
\r
8932 #define USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
\r
8933 #define USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
\r
8934 #define USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
\r
8935 #define USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000) /*!< Snoop mode */
\r
8936 #define USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
\r
8937 #define USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
\r
8938 #define USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
\r
8939 #define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
\r
8940 #define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
\r
8942 /******************** Bit definition forUSB_OTG_DOEPINT register ********************/
\r
8943 #define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
\r
8944 #define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
\r
8945 #define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /*!< SETUP phase done */
\r
8946 #define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled */
\r
8947 #define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received */
\r
8948 #define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /*!< NYET interrupt */
\r
8950 /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
\r
8952 #define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
\r
8953 #define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
\r
8955 #define USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000) /*!< SETUP packet count */
\r
8956 #define USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000) /*!<Bit 0 */
\r
8957 #define USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000) /*!<Bit 1 */
\r
8959 /******************** Bit definition for PCGCCTL register ********************/
\r
8960 #define USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001) /*!< SETUP packet count */
\r
8961 #define USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002) /*!<Bit 0 */
\r
8962 #define USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010) /*!<Bit 1 */
\r
8972 /** @addtogroup Exported_macros
\r
8976 /******************************* ADC Instances ********************************/
\r
8977 #define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) || \
\r
8978 ((__INSTANCE__) == ADC2) || \
\r
8979 ((__INSTANCE__) == ADC3))
\r
8981 /******************************* CAN Instances ********************************/
\r
8982 #define IS_CAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == CAN1) || \
\r
8983 ((__INSTANCE__) == CAN2))
\r
8985 /******************************* CRC Instances ********************************/
\r
8986 #define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC)
\r
8988 /******************************* DAC Instances ********************************/
\r
8989 #define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC)
\r
8991 /******************************* DCMI Instances *******************************/
\r
8992 #define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
\r
8994 /******************************* DMA2D Instances *******************************/
\r
8995 #define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
\r
8997 /******************************** DMA Instances *******************************/
\r
8998 #define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) || \
\r
8999 ((__INSTANCE__) == DMA1_Stream1) || \
\r
9000 ((__INSTANCE__) == DMA1_Stream2) || \
\r
9001 ((__INSTANCE__) == DMA1_Stream3) || \
\r
9002 ((__INSTANCE__) == DMA1_Stream4) || \
\r
9003 ((__INSTANCE__) == DMA1_Stream5) || \
\r
9004 ((__INSTANCE__) == DMA1_Stream6) || \
\r
9005 ((__INSTANCE__) == DMA1_Stream7) || \
\r
9006 ((__INSTANCE__) == DMA2_Stream0) || \
\r
9007 ((__INSTANCE__) == DMA2_Stream1) || \
\r
9008 ((__INSTANCE__) == DMA2_Stream2) || \
\r
9009 ((__INSTANCE__) == DMA2_Stream3) || \
\r
9010 ((__INSTANCE__) == DMA2_Stream4) || \
\r
9011 ((__INSTANCE__) == DMA2_Stream5) || \
\r
9012 ((__INSTANCE__) == DMA2_Stream6) || \
\r
9013 ((__INSTANCE__) == DMA2_Stream7))
\r
9015 /******************************* GPIO Instances *******************************/
\r
9016 #define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
\r
9017 ((__INSTANCE__) == GPIOB) || \
\r
9018 ((__INSTANCE__) == GPIOC) || \
\r
9019 ((__INSTANCE__) == GPIOD) || \
\r
9020 ((__INSTANCE__) == GPIOE) || \
\r
9021 ((__INSTANCE__) == GPIOF) || \
\r
9022 ((__INSTANCE__) == GPIOG) || \
\r
9023 ((__INSTANCE__) == GPIOH) || \
\r
9024 ((__INSTANCE__) == GPIOI) || \
\r
9025 ((__INSTANCE__) == GPIOJ) || \
\r
9026 ((__INSTANCE__) == GPIOK))
\r
9028 #define IS_GPIO_AF_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
\r
9029 ((__INSTANCE__) == GPIOB) || \
\r
9030 ((__INSTANCE__) == GPIOC) || \
\r
9031 ((__INSTANCE__) == GPIOD) || \
\r
9032 ((__INSTANCE__) == GPIOE) || \
\r
9033 ((__INSTANCE__) == GPIOF) || \
\r
9034 ((__INSTANCE__) == GPIOG) || \
\r
9035 ((__INSTANCE__) == GPIOH) || \
\r
9036 ((__INSTANCE__) == GPIOI) || \
\r
9037 ((__INSTANCE__) == GPIOJ) || \
\r
9038 ((__INSTANCE__) == GPIOK))
\r
9040 /****************************** CEC Instances *********************************/
\r
9041 #define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
\r
9043 /****************************** QSPI Instances *********************************/
\r
9044 #define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
\r
9047 /******************************** I2C Instances *******************************/
\r
9048 #define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \
\r
9049 ((__INSTANCE__) == I2C2) || \
\r
9050 ((__INSTANCE__) == I2C3) || \
\r
9051 ((__INSTANCE__) == I2C4))
\r
9053 /******************************** I2S Instances *******************************/
\r
9054 #define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
\r
9055 ((__INSTANCE__) == SPI2) || \
\r
9056 ((__INSTANCE__) == SPI3))
\r
9058 /******************************* LPTIM Instances ********************************/
\r
9059 #define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
\r
9061 /****************************** LTDC Instances ********************************/
\r
9062 #define IS_LTDC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LTDC)
\r
9064 /******************************* RNG Instances ********************************/
\r
9065 #define IS_RNG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RNG)
\r
9067 /****************************** RTC Instances *********************************/
\r
9068 #define IS_RTC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RTC)
\r
9070 /******************************* SAI Instances ********************************/
\r
9071 #define IS_SAI_BLOCK_PERIPH(__PERIPH__) (((__PERIPH__) == SAI1_Block_A) || \
\r
9072 ((__PERIPH__) == SAI1_Block_B) || \
\r
9073 ((__PERIPH__) == SAI2_Block_A) || \
\r
9074 ((__PERIPH__) == SAI2_Block_B))
\r
9077 /******************************** SDMMC Instances *******************************/
\r
9078 #define IS_SDMMC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SDMMC1)
\r
9081 /****************************** SPDIFRX Instances *********************************/
\r
9082 #define IS_SPDIFRX_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPDIFRX)
\r
9084 /******************************** SPI Instances *******************************/
\r
9085 #define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
\r
9086 ((__INSTANCE__) == SPI2) || \
\r
9087 ((__INSTANCE__) == SPI3) || \
\r
9088 ((__INSTANCE__) == SPI4) || \
\r
9089 ((__INSTANCE__) == SPI5) || \
\r
9090 ((__INSTANCE__) == SPI6))
\r
9092 /****************** TIM Instances : All supported instances *******************/
\r
9093 #define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
\r
9094 ((__INSTANCE__) == TIM2) || \
\r
9095 ((__INSTANCE__) == TIM3) || \
\r
9096 ((__INSTANCE__) == TIM4) || \
\r
9097 ((__INSTANCE__) == TIM5) || \
\r
9098 ((__INSTANCE__) == TIM6) || \
\r
9099 ((__INSTANCE__) == TIM7) || \
\r
9100 ((__INSTANCE__) == TIM8) || \
\r
9101 ((__INSTANCE__) == TIM9) || \
\r
9102 ((__INSTANCE__) == TIM10) || \
\r
9103 ((__INSTANCE__) == TIM11) || \
\r
9104 ((__INSTANCE__) == TIM12) || \
\r
9105 ((__INSTANCE__) == TIM13) || \
\r
9106 ((__INSTANCE__) == TIM14))
\r
9108 /************* TIM Instances : at least 1 capture/compare channel *************/
\r
9109 #define IS_TIM_CC1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
\r
9110 ((__INSTANCE__) == TIM2) || \
\r
9111 ((__INSTANCE__) == TIM3) || \
\r
9112 ((__INSTANCE__) == TIM4) || \
\r
9113 ((__INSTANCE__) == TIM5) || \
\r
9114 ((__INSTANCE__) == TIM8) || \
\r
9115 ((__INSTANCE__) == TIM9) || \
\r
9116 ((__INSTANCE__) == TIM10) || \
\r
9117 ((__INSTANCE__) == TIM11) || \
\r
9118 ((__INSTANCE__) == TIM12) || \
\r
9119 ((__INSTANCE__) == TIM13) || \
\r
9120 ((__INSTANCE__) == TIM14))
\r
9122 /************ TIM Instances : at least 2 capture/compare channels *************/
\r
9123 #define IS_TIM_CC2_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
\r
9124 ((__INSTANCE__) == TIM2) || \
\r
9125 ((__INSTANCE__) == TIM3) || \
\r
9126 ((__INSTANCE__) == TIM4) || \
\r
9127 ((__INSTANCE__) == TIM5) || \
\r
9128 ((__INSTANCE__) == TIM8) || \
\r
9129 ((__INSTANCE__) == TIM9) || \
\r
9130 ((__INSTANCE__) == TIM12))
\r
9132 /************ TIM Instances : at least 3 capture/compare channels *************/
\r
9133 #define IS_TIM_CC3_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
\r
9134 ((__INSTANCE__) == TIM2) || \
\r
9135 ((__INSTANCE__) == TIM3) || \
\r
9136 ((__INSTANCE__) == TIM4) || \
\r
9137 ((__INSTANCE__) == TIM5) || \
\r
9138 ((__INSTANCE__) == TIM8))
\r
9140 /************ TIM Instances : at least 4 capture/compare channels *************/
\r
9141 #define IS_TIM_CC4_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
\r
9142 ((__INSTANCE__) == TIM2) || \
\r
9143 ((__INSTANCE__) == TIM3) || \
\r
9144 ((__INSTANCE__) == TIM4) || \
\r
9145 ((__INSTANCE__) == TIM5) || \
\r
9146 ((__INSTANCE__) == TIM8))
\r
9148 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
\r
9149 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(__INSTANCE__) \
\r
9150 (((__INSTANCE__) == TIM1) || \
\r
9151 ((__INSTANCE__) == TIM8))
\r
9153 /****************** TIM Instances : supporting OCxREF clear *******************/
\r
9154 #define IS_TIM_OCXREF_CLEAR_INSTANCE(__INSTANCE__)\
\r
9155 (((__INSTANCE__) == TIM1) || \
\r
9156 ((__INSTANCE__) == TIM2) || \
\r
9157 ((__INSTANCE__) == TIM3) || \
\r
9158 ((__INSTANCE__) == TIM4) || \
\r
9159 ((__INSTANCE__) == TIM8))
\r
9161 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
\r
9162 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(__INSTANCE__)\
\r
9163 (((__INSTANCE__) == TIM1) || \
\r
9164 ((__INSTANCE__) == TIM2) || \
\r
9165 ((__INSTANCE__) == TIM3) || \
\r
9166 ((__INSTANCE__) == TIM4) || \
\r
9167 ((__INSTANCE__) == TIM5) || \
\r
9168 ((__INSTANCE__) == TIM8))
\r
9170 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
\r
9171 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(__INSTANCE__)\
\r
9172 (((__INSTANCE__) == TIM1) || \
\r
9173 ((__INSTANCE__) == TIM2) || \
\r
9174 ((__INSTANCE__) == TIM3) || \
\r
9175 ((__INSTANCE__) == TIM4) || \
\r
9176 ((__INSTANCE__) == TIM5) || \
\r
9177 ((__INSTANCE__) == TIM8))
\r
9178 /****************** TIM Instances : at least 5 capture/compare channels *******/
\r
9179 #define IS_TIM_CC5_INSTANCE(__INSTANCE__)\
\r
9180 (((__INSTANCE__) == TIM1) || \
\r
9181 ((__INSTANCE__) == TIM8) )
\r
9183 /****************** TIM Instances : at least 6 capture/compare channels *******/
\r
9184 #define IS_TIM_CC6_INSTANCE(__INSTANCE__)\
\r
9185 (((__INSTANCE__) == TIM1) || \
\r
9186 ((__INSTANCE__) == TIM8))
\r
9189 /******************** TIM Instances : Advanced-control timers *****************/
\r
9190 #define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
\r
9191 ((__INSTANCE__) == TIM8))
\r
9193 /****************** TIM Instances : supporting 2 break inputs *****************/
\r
9194 #define IS_TIM_BREAK_INSTANCE(__INSTANCE__)\
\r
9195 (((__INSTANCE__) == TIM1) || \
\r
9196 ((__INSTANCE__) == TIM8))
\r
9198 /******************* TIM Instances : Timer input XOR function *****************/
\r
9199 #define IS_TIM_XOR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
\r
9200 ((__INSTANCE__) == TIM2) || \
\r
9201 ((__INSTANCE__) == TIM3) || \
\r
9202 ((__INSTANCE__) == TIM4) || \
\r
9203 ((__INSTANCE__) == TIM5) || \
\r
9204 ((__INSTANCE__) == TIM8))
\r
9206 /****************** TIM Instances : DMA requests generation (UDE) *************/
\r
9207 #define IS_TIM_DMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
\r
9208 ((__INSTANCE__) == TIM2) || \
\r
9209 ((__INSTANCE__) == TIM3) || \
\r
9210 ((__INSTANCE__) == TIM4) || \
\r
9211 ((__INSTANCE__) == TIM5) || \
\r
9212 ((__INSTANCE__) == TIM6) || \
\r
9213 ((__INSTANCE__) == TIM7) || \
\r
9214 ((__INSTANCE__) == TIM8))
\r
9216 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
\r
9217 #define IS_TIM_DMA_CC_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
\r
9218 ((__INSTANCE__) == TIM2) || \
\r
9219 ((__INSTANCE__) == TIM3) || \
\r
9220 ((__INSTANCE__) == TIM4) || \
\r
9221 ((__INSTANCE__) == TIM5) || \
\r
9222 ((__INSTANCE__) == TIM8))
\r
9224 /************ TIM Instances : DMA requests generation (COMDE) *****************/
\r
9225 #define IS_TIM_CCDMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
\r
9226 ((__INSTANCE__) == TIM2) || \
\r
9227 ((__INSTANCE__) == TIM3) || \
\r
9228 ((__INSTANCE__) == TIM4) || \
\r
9229 ((__INSTANCE__) == TIM5) || \
\r
9230 ((__INSTANCE__) == TIM8))
\r
9232 /******************** TIM Instances : DMA burst feature ***********************/
\r
9233 #define IS_TIM_DMABURST_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
\r
9234 ((__INSTANCE__) == TIM2) || \
\r
9235 ((__INSTANCE__) == TIM3) || \
\r
9236 ((__INSTANCE__) == TIM4) || \
\r
9237 ((__INSTANCE__) == TIM5) || \
\r
9238 ((__INSTANCE__) == TIM8))
\r
9240 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
\r
9241 #define IS_TIM_MASTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
\r
9242 ((__INSTANCE__) == TIM2) || \
\r
9243 ((__INSTANCE__) == TIM3) || \
\r
9244 ((__INSTANCE__) == TIM4) || \
\r
9245 ((__INSTANCE__) == TIM5) || \
\r
9246 ((__INSTANCE__) == TIM6) || \
\r
9247 ((__INSTANCE__) == TIM7) || \
\r
9248 ((__INSTANCE__) == TIM8) || \
\r
9249 ((__INSTANCE__) == TIM13) || \
\r
9250 ((__INSTANCE__) == TIM14))
\r
9252 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
\r
9253 #define IS_TIM_SLAVE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
\r
9254 ((__INSTANCE__) == TIM2) || \
\r
9255 ((__INSTANCE__) == TIM3) || \
\r
9256 ((__INSTANCE__) == TIM4) || \
\r
9257 ((__INSTANCE__) == TIM5) || \
\r
9258 ((__INSTANCE__) == TIM8) || \
\r
9259 ((__INSTANCE__) == TIM9) || \
\r
9260 ((__INSTANCE__) == TIM12))
\r
9262 /********************** TIM Instances : 32 bit Counter ************************/
\r
9263 #define IS_TIM_32B_COUNTER_INSTANCE(__INSTANCE__)(((__INSTANCE__) == TIM2) || \
\r
9264 ((__INSTANCE__) == TIM5))
\r
9266 /***************** TIM Instances : external trigger input available ************/
\r
9267 #define IS_TIM_ETR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
\r
9268 ((__INSTANCE__) == TIM2) || \
\r
9269 ((__INSTANCE__) == TIM3) || \
\r
9270 ((__INSTANCE__) == TIM4) || \
\r
9271 ((__INSTANCE__) == TIM5) || \
\r
9272 ((__INSTANCE__) == TIM8))
\r
9274 /****************** TIM Instances : remapping capability **********************/
\r
9275 #define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2) || \
\r
9276 ((__INSTANCE__) == TIM5) || \
\r
9277 ((__INSTANCE__) == TIM11))
\r
9279 /******************* TIM Instances : output(s) available **********************/
\r
9280 #define IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \
\r
9281 ((((__INSTANCE__) == TIM1) && \
\r
9282 (((__CHANNEL__) == TIM_CHANNEL_1) || \
\r
9283 ((__CHANNEL__) == TIM_CHANNEL_2) || \
\r
9284 ((__CHANNEL__) == TIM_CHANNEL_3) || \
\r
9285 ((__CHANNEL__) == TIM_CHANNEL_4))) \
\r
9287 (((__INSTANCE__) == TIM2) && \
\r
9288 (((__CHANNEL__) == TIM_CHANNEL_1) || \
\r
9289 ((__CHANNEL__) == TIM_CHANNEL_2) || \
\r
9290 ((__CHANNEL__) == TIM_CHANNEL_3) || \
\r
9291 ((__CHANNEL__) == TIM_CHANNEL_4))) \
\r
9293 (((__INSTANCE__) == TIM3) && \
\r
9294 (((__CHANNEL__) == TIM_CHANNEL_1) || \
\r
9295 ((__CHANNEL__) == TIM_CHANNEL_2) || \
\r
9296 ((__CHANNEL__) == TIM_CHANNEL_3) || \
\r
9297 ((__CHANNEL__) == TIM_CHANNEL_4))) \
\r
9299 (((__INSTANCE__) == TIM4) && \
\r
9300 (((__CHANNEL__) == TIM_CHANNEL_1) || \
\r
9301 ((__CHANNEL__) == TIM_CHANNEL_2) || \
\r
9302 ((__CHANNEL__) == TIM_CHANNEL_3) || \
\r
9303 ((__CHANNEL__) == TIM_CHANNEL_4))) \
\r
9305 (((__INSTANCE__) == TIM5) && \
\r
9306 (((__CHANNEL__) == TIM_CHANNEL_1) || \
\r
9307 ((__CHANNEL__) == TIM_CHANNEL_2) || \
\r
9308 ((__CHANNEL__) == TIM_CHANNEL_3) || \
\r
9309 ((__CHANNEL__) == TIM_CHANNEL_4))) \
\r
9311 (((__INSTANCE__) == TIM8) && \
\r
9312 (((__CHANNEL__) == TIM_CHANNEL_1) || \
\r
9313 ((__CHANNEL__) == TIM_CHANNEL_2) || \
\r
9314 ((__CHANNEL__) == TIM_CHANNEL_3) || \
\r
9315 ((__CHANNEL__) == TIM_CHANNEL_4))) \
\r
9317 (((__INSTANCE__) == TIM9) && \
\r
9318 (((__CHANNEL__) == TIM_CHANNEL_1) || \
\r
9319 ((__CHANNEL__) == TIM_CHANNEL_2))) \
\r
9321 (((__INSTANCE__) == TIM10) && \
\r
9322 (((__CHANNEL__) == TIM_CHANNEL_1))) \
\r
9324 (((__INSTANCE__) == TIM11) && \
\r
9325 (((__CHANNEL__) == TIM_CHANNEL_1))) \
\r
9327 (((__INSTANCE__) == TIM12) && \
\r
9328 (((__CHANNEL__) == TIM_CHANNEL_1) || \
\r
9329 ((__CHANNEL__) == TIM_CHANNEL_2))) \
\r
9331 (((__INSTANCE__) == TIM13) && \
\r
9332 (((__CHANNEL__) == TIM_CHANNEL_1))) \
\r
9334 (((__INSTANCE__) == TIM14) && \
\r
9335 (((__CHANNEL__) == TIM_CHANNEL_1))))
\r
9337 /************ TIM Instances : complementary output(s) available ***************/
\r
9338 #define IS_TIM_CCXN_INSTANCE(__INSTANCE__, __CHANNEL__) \
\r
9339 ((((__INSTANCE__) == TIM1) && \
\r
9340 (((__CHANNEL__) == TIM_CHANNEL_1) || \
\r
9341 ((__CHANNEL__) == TIM_CHANNEL_2) || \
\r
9342 ((__CHANNEL__) == TIM_CHANNEL_3))) \
\r
9344 (((__INSTANCE__) == TIM8) && \
\r
9345 (((__CHANNEL__) == TIM_CHANNEL_1) || \
\r
9346 ((__CHANNEL__) == TIM_CHANNEL_2) || \
\r
9347 ((__CHANNEL__) == TIM_CHANNEL_3))))
\r
9349 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
\r
9350 #define IS_TIM_TRGO2_INSTANCE(__INSTANCE__)\
\r
9351 (((__INSTANCE__) == TIM1) || \
\r
9352 ((__INSTANCE__) == TIM8) )
\r
9354 /****************** TIM Instances : supporting synchronization ****************/
\r
9355 #define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
\r
9356 (((__INSTANCE__) == TIM1) || \
\r
9357 ((__INSTANCE__) == TIM2) || \
\r
9358 ((__INSTANCE__) == TIM3) || \
\r
9359 ((__INSTANCE__) == TIM4) || \
\r
9360 ((__INSTANCE__) == TIM5) || \
\r
9361 ((__INSTANCE__) == TIM6) || \
\r
9362 ((__INSTANCE__) == TIM7) || \
\r
9363 ((__INSTANCE__) == TIM8))
\r
9365 /******************** USART Instances : Synchronous mode **********************/
\r
9366 #define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
\r
9367 ((__INSTANCE__) == USART2) || \
\r
9368 ((__INSTANCE__) == USART3) || \
\r
9369 ((__INSTANCE__) == USART6))
\r
9371 /******************** UART Instances : Asynchronous mode **********************/
\r
9372 #define IS_UART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
\r
9373 ((__INSTANCE__) == USART2) || \
\r
9374 ((__INSTANCE__) == USART3) || \
\r
9375 ((__INSTANCE__) == UART4) || \
\r
9376 ((__INSTANCE__) == UART5) || \
\r
9377 ((__INSTANCE__) == USART6) || \
\r
9378 ((__INSTANCE__) == UART7) || \
\r
9379 ((__INSTANCE__) == UART8))
\r
9381 /****************** UART Instances : Hardware Flow control ********************/
\r
9382 #define IS_UART_HWFLOW_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
\r
9383 ((__INSTANCE__) == USART2) || \
\r
9384 ((__INSTANCE__) == USART3) || \
\r
9385 ((__INSTANCE__) == UART4) || \
\r
9386 ((__INSTANCE__) == UART5) || \
\r
9387 ((__INSTANCE__) == USART6) || \
\r
9388 ((__INSTANCE__) == UART7) || \
\r
9389 ((__INSTANCE__) == UART8))
\r
9391 /********************* UART Instances : Smart card mode ***********************/
\r
9392 #define IS_SMARTCARD_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
\r
9393 ((__INSTANCE__) == USART2) || \
\r
9394 ((__INSTANCE__) == USART3) || \
\r
9395 ((__INSTANCE__) == USART6))
\r
9397 /*********************** UART Instances : IRDA mode ***************************/
\r
9398 #define IS_IRDA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
\r
9399 ((__INSTANCE__) == USART2) || \
\r
9400 ((__INSTANCE__) == USART3) || \
\r
9401 ((__INSTANCE__) == UART4) || \
\r
9402 ((__INSTANCE__) == UART5) || \
\r
9403 ((__INSTANCE__) == USART6) || \
\r
9404 ((__INSTANCE__) == UART7) || \
\r
9405 ((__INSTANCE__) == UART8))
\r
9407 /****************************** IWDG Instances ********************************/
\r
9408 #define IS_IWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == IWDG)
\r
9410 /****************************** WWDG Instances ********************************/
\r
9411 #define IS_WWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == WWDG)
\r
9414 /******************************************************************************/
\r
9415 /* For a painless codes migration between the STM32F7xx device product */
\r
9416 /* lines, the aliases defined below are put in place to overcome the */
\r
9417 /* differences in the interrupt handlers and IRQn definitions. */
\r
9418 /* No need to update developed interrupt code when moving across */
\r
9419 /* product lines within the same STM32F7 Family */
\r
9420 /******************************************************************************/
\r
9422 /* Aliases for __IRQn */
\r
9423 #define HASH_RNG_IRQn RNG_IRQn
\r
9425 /* Aliases for __IRQHandler */
\r
9426 #define HASH_RNG_IRQHandler RNG_IRQHandler
\r
9440 #ifdef __cplusplus
\r
9442 #endif /* __cplusplus */
\r
9444 #endif /* __STM32F746xx_H */
\r
9447 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
\r
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