2 ******************************************************************************
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3 * @file stm32_hal_legacy.h
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4 * @author MCD Application Team
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6 * @date 06-March-2015
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7 * @brief This file contains aliases definition for the STM32Cube HAL constants
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8 * macros and functions maintained for legacy purpose.
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9 ******************************************************************************
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12 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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14 * Redistribution and use in source and binary forms, with or without modification,
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15 * are permitted provided that the following conditions are met:
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16 * 1. Redistributions of source code must retain the above copyright notice,
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17 * this list of conditions and the following disclaimer.
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18 * 2. Redistributions in binary form must reproduce the above copyright notice,
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19 * this list of conditions and the following disclaimer in the documentation
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20 * and/or other materials provided with the distribution.
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21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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22 * may be used to endorse or promote products derived from this software
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23 * without specific prior written permission.
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25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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36 ******************************************************************************
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39 /* Define to prevent recursive inclusion -------------------------------------*/
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40 #ifndef __STM32_HAL_LEGACY
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41 #define __STM32_HAL_LEGACY
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47 /* Includes ------------------------------------------------------------------*/
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48 /* Exported types ------------------------------------------------------------*/
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49 /* Exported constants --------------------------------------------------------*/
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51 /** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
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54 #define AES_FLAG_RDERR CRYP_FLAG_RDERR
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55 #define AES_FLAG_WRERR CRYP_FLAG_WRERR
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56 #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
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57 #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
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58 #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
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64 /** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
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67 #define ADC_RESOLUTION12b ADC_RESOLUTION_12B
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68 #define ADC_RESOLUTION10b ADC_RESOLUTION_10B
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69 #define ADC_RESOLUTION8b ADC_RESOLUTION_8B
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70 #define ADC_RESOLUTION6b ADC_RESOLUTION_6B
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71 #define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
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72 #define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
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73 #define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
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74 #define EOC_SEQ_CONV ADC_EOC_SEQ_CONV
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75 #define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
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76 #define REGULAR_GROUP ADC_REGULAR_GROUP
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77 #define INJECTED_GROUP ADC_INJECTED_GROUP
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78 #define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
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79 #define AWD_EVENT ADC_AWD_EVENT
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80 #define AWD1_EVENT ADC_AWD1_EVENT
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81 #define AWD2_EVENT ADC_AWD2_EVENT
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82 #define AWD3_EVENT ADC_AWD3_EVENT
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83 #define OVR_EVENT ADC_OVR_EVENT
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84 #define JQOVF_EVENT ADC_JQOVF_EVENT
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85 #define ALL_CHANNELS ADC_ALL_CHANNELS
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86 #define REGULAR_CHANNELS ADC_REGULAR_CHANNELS
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87 #define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
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88 #define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
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89 #define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
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90 #define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
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91 #define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
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92 #define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
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93 #define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
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94 #define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
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95 #define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
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96 #define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
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97 #define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
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98 #define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
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99 #define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
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100 #define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
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101 #define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
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106 /** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
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110 #define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
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116 /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
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120 #define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
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121 #define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
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122 #define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
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123 #define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
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129 /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
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133 #define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
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134 #define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
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140 /** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
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144 #define DAC1_CHANNEL_1 DAC_CHANNEL_1
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145 #define DAC1_CHANNEL_2 DAC_CHANNEL_2
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146 #define DAC2_CHANNEL_1 DAC_CHANNEL_1
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147 #define DAC_WAVE_NONE ((uint32_t)0x00000000)
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148 #define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)
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149 #define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
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150 #define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
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151 #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
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152 #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
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159 /** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
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163 #define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
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164 #define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
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165 #define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
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166 #define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
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167 #define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
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168 #define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES
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169 #define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
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170 #define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
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171 #define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE
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172 #define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE
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173 #define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
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174 #define OBEX_PCROP OPTIONBYTE_PCROP
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175 #define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
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176 #define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
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177 #define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
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178 #define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
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179 #define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
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180 #define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
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181 #define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
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182 #define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
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183 #define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
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184 #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
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185 #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
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186 #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
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187 #define PAGESIZE FLASH_PAGE_SIZE
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188 #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
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189 #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
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190 #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
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191 #define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
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192 #define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
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193 #define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
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194 #define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
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195 #define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
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196 #define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
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197 #define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
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198 #define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
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199 #define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
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200 #define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
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201 #define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
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202 #define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
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203 #define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
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204 #define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
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205 #define IS_NBSECTORS IS_FLASH_NBSECTORS
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206 #define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
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207 #define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
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208 #define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
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209 #define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
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210 #define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
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211 #define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
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212 #define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
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213 #define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
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214 #define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
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215 #define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
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216 #define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
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217 #define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
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218 #define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
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219 #define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
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220 #define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
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221 #define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
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222 #define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
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223 #define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
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224 #define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
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230 /** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
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234 #define SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
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235 #define SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
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236 #define SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
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237 #define SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
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238 #define SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
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239 #define SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
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240 #define SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
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247 /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
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250 #if defined(STM32L4) || defined(STM32F7)
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251 #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
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252 #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
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253 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
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254 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
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256 #define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
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257 #define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
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258 #define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
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259 #define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16
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265 /** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
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269 #define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
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270 #define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
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275 /** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
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278 #define GET_GPIO_SOURCE GPIO_GET_INDEX
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279 #define GET_GPIO_INDEX GPIO_GET_INDEX
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285 /** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
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288 #define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
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289 #define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
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290 #define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
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291 #define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
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292 #define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
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293 #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
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294 #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
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295 #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
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300 /** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
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303 #define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
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304 #define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
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310 /** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
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313 #define KR_KEY_RELOAD IWDG_KEY_RELOAD
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314 #define KR_KEY_ENABLE IWDG_KEY_ENABLE
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315 #define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
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316 #define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
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321 /** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
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325 #define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
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326 #define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
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327 #define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
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328 #define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
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330 #define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING
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331 #define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
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332 #define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
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334 #define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSISTIONS
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335 #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSISTIONS
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336 #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSISTIONS
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342 /** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
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345 #define NAND_AddressTypedef NAND_AddressTypeDef
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347 #define __ARRAY_ADDRESS ARRAY_ADDRESS
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348 #define __ADDR_1st_CYCLE ADDR_1ST_CYCLE
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349 #define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE
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350 #define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE
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351 #define __ADDR_4th_CYCLE ADDR_4TH_CYCLE
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356 /** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
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359 #define NOR_StatusTypedef HAL_NOR_StatusTypeDef
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360 #define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS
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361 #define NOR_ONGOING HAL_NOR_STATUS_ONGOING
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362 #define NOR_ERROR HAL_NOR_STATUS_ERROR
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363 #define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
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365 #define __NOR_WRITE NOR_WRITE
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366 #define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT
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371 /** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
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375 #define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
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376 #define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
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377 #define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
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378 #define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
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380 #define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
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381 #define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
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382 #define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
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383 #define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
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385 #define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
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386 #define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
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388 #define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
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389 #define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
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391 #define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
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392 #define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
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394 #define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
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396 #define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
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397 #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
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398 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
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404 /** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
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407 #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
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412 /** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
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416 /* Compact Flash-ATA registers description */
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417 #define CF_DATA ATA_DATA
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418 #define CF_SECTOR_COUNT ATA_SECTOR_COUNT
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419 #define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
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420 #define CF_CYLINDER_LOW ATA_CYLINDER_LOW
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421 #define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
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422 #define CF_CARD_HEAD ATA_CARD_HEAD
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423 #define CF_STATUS_CMD ATA_STATUS_CMD
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424 #define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
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425 #define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
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427 /* Compact Flash-ATA commands */
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428 #define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
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429 #define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
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430 #define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
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431 #define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
\r
433 #define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
\r
434 #define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
\r
435 #define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
\r
436 #define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
\r
437 #define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
\r
442 /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
\r
446 #define FORMAT_BIN RTC_FORMAT_BIN
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447 #define FORMAT_BCD RTC_FORMAT_BCD
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449 #define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
\r
450 #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
\r
451 #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
\r
452 #define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
\r
453 #define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
\r
455 #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
\r
456 #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
\r
457 #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
\r
458 #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
\r
459 #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
\r
460 #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
\r
461 #define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
\r
462 #define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
\r
469 /** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
\r
472 #define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
\r
473 #define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
\r
475 #define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
\r
476 #define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
\r
477 #define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
\r
478 #define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
\r
480 #define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
\r
481 #define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
\r
483 #define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
\r
484 #define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
\r
490 /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
\r
493 #define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
\r
494 #define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
\r
495 #define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
\r
496 #define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
\r
497 #define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
\r
498 #define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
\r
499 #define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
\r
500 #define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
\r
501 #define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
\r
506 /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
\r
509 #define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
\r
510 #define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
\r
512 #define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
\r
513 #define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
\r
515 #define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
\r
516 #define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
\r
522 /** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
\r
525 #define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
\r
526 #define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
\r
528 #define TIM_DMABase_CR1 TIM_DMABASE_CR1
\r
529 #define TIM_DMABase_CR2 TIM_DMABASE_CR2
\r
530 #define TIM_DMABase_SMCR TIM_DMABASE_SMCR
\r
531 #define TIM_DMABase_DIER TIM_DMABASE_DIER
\r
532 #define TIM_DMABase_SR TIM_DMABASE_SR
\r
533 #define TIM_DMABase_EGR TIM_DMABASE_EGR
\r
534 #define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
\r
535 #define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
\r
536 #define TIM_DMABase_CCER TIM_DMABASE_CCER
\r
537 #define TIM_DMABase_CNT TIM_DMABASE_CNT
\r
538 #define TIM_DMABase_PSC TIM_DMABASE_PSC
\r
539 #define TIM_DMABase_ARR TIM_DMABASE_ARR
\r
540 #define TIM_DMABase_RCR TIM_DMABASE_RCR
\r
541 #define TIM_DMABase_CCR1 TIM_DMABASE_CCR1
\r
542 #define TIM_DMABase_CCR2 TIM_DMABASE_CCR2
\r
543 #define TIM_DMABase_CCR3 TIM_DMABASE_CCR3
\r
544 #define TIM_DMABase_CCR4 TIM_DMABASE_CCR4
\r
545 #define TIM_DMABase_BDTR TIM_DMABASE_BDTR
\r
546 #define TIM_DMABase_DCR TIM_DMABASE_DCR
\r
547 #define TIM_DMABase_DMAR TIM_DMABASE_DMAR
\r
548 #define TIM_DMABase_OR1 TIM_DMABASE_OR1
\r
549 #define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
\r
550 #define TIM_DMABase_CCR5 TIM_DMABASE_CCR5
\r
551 #define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
\r
552 #define TIM_DMABase_OR2 TIM_DMABASE_OR2
\r
553 #define TIM_DMABase_OR3 TIM_DMABASE_OR3
\r
554 #define TIM_DMABase_OR TIM_DMABASE_OR
\r
556 #define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
\r
557 #define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
\r
558 #define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
\r
559 #define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
\r
560 #define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
\r
561 #define TIM_EventSource_COM TIM_EVENTSOURCE_COM
\r
562 #define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
\r
563 #define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
\r
564 #define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
\r
566 #define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
\r
567 #define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
\r
568 #define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
\r
569 #define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
\r
570 #define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
\r
571 #define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
\r
572 #define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
\r
573 #define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
\r
574 #define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
\r
575 #define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
\r
576 #define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
\r
577 #define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
\r
578 #define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
\r
579 #define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
\r
580 #define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
\r
581 #define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
\r
582 #define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
\r
583 #define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
\r
589 /** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
\r
592 #define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
\r
593 #define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
\r
598 /** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
\r
601 #define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
\r
602 #define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
\r
603 #define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
\r
604 #define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
\r
606 #define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
\r
607 #define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
\r
609 #define __DIV_SAMPLING16 UART_DIV_SAMPLING16
\r
610 #define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
\r
611 #define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
\r
612 #define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
\r
614 #define __DIV_SAMPLING8 UART_DIV_SAMPLING8
\r
615 #define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
\r
616 #define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
\r
617 #define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
\r
619 #define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
\r
620 #define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
\r
627 /** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
\r
631 #define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
\r
632 #define USART_CLOCK_ENABLED USART_CLOCK_ENABLE
\r
634 #define USARTNACK_ENABLED USART_NACK_ENABLE
\r
635 #define USARTNACK_DISABLED USART_NACK_DISABLE
\r
640 /** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
\r
643 #define CFR_BASE WWDG_CFR_BASE
\r
649 /** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
\r
652 #define CAN_FilterFIFO0 CAN_FILTER_FIFO0
\r
653 #define CAN_FilterFIFO1 CAN_FILTER_FIFO1
\r
654 #define CAN_IT_RQCP0 CAN_IT_TME
\r
655 #define CAN_IT_RQCP1 CAN_IT_TME
\r
656 #define CAN_IT_RQCP2 CAN_IT_TME
\r
657 #define INAK_TIMEOUT CAN_TIMEOUT_VALUE
\r
658 #define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
\r
659 #define CAN_TXSTATUS_FAILED ((uint8_t)0x00)
\r
660 #define CAN_TXSTATUS_OK ((uint8_t)0x01)
\r
661 #define CAN_TXSTATUS_PENDING ((uint8_t)0x02)
\r
667 /** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
\r
671 #define VLAN_TAG ETH_VLAN_TAG
\r
672 #define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
\r
673 #define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
\r
674 #define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
\r
675 #define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
\r
676 #define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
\r
677 #define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
\r
678 #define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
\r
680 #define ETH_MMCCR ((uint32_t)0x00000100)
\r
681 #define ETH_MMCRIR ((uint32_t)0x00000104)
\r
682 #define ETH_MMCTIR ((uint32_t)0x00000108)
\r
683 #define ETH_MMCRIMR ((uint32_t)0x0000010C)
\r
684 #define ETH_MMCTIMR ((uint32_t)0x00000110)
\r
685 #define ETH_MMCTGFSCCR ((uint32_t)0x0000014C)
\r
686 #define ETH_MMCTGFMSCCR ((uint32_t)0x00000150)
\r
687 #define ETH_MMCTGFCR ((uint32_t)0x00000168)
\r
688 #define ETH_MMCRFCECR ((uint32_t)0x00000194)
\r
689 #define ETH_MMCRFAECR ((uint32_t)0x00000198)
\r
690 #define ETH_MMCRGUFCR ((uint32_t)0x000001C4)
\r
696 /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
\r
704 /* Exported functions --------------------------------------------------------*/
\r
706 /** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
\r
709 #define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
\r
714 /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
\r
718 #define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
\r
719 #define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
\r
720 #define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
\r
721 #define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
\r
723 /*HASH Algorithm Selection*/
\r
725 #define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
\r
726 #define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
\r
727 #define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
\r
728 #define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
\r
730 #define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
\r
731 #define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
\r
733 #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
\r
734 #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
\r
739 /** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
\r
742 #define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
\r
743 #define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
\r
744 #define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
\r
745 #define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
\r
746 #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
\r
747 #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
\r
748 #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
\r
749 #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
\r
750 #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
\r
751 #define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
\r
752 #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
\r
753 #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
\r
758 /** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
\r
761 #define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
\r
762 #define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
\r
763 #define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
\r
764 #define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
\r
765 #define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
\r
766 #define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
\r
767 #define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
\r
773 /** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
\r
776 #define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
\r
777 #define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
\r
779 #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
\r
784 /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
\r
787 #define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
\r
788 #define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
\r
789 #define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
\r
790 #define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
\r
791 #define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
\r
792 #define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
\r
793 #define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
\r
794 #define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
\r
795 #define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
\r
796 #define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
\r
797 #define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
\r
798 #define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
\r
799 #define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
\r
800 #define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
\r
801 #define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
\r
802 #define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
\r
804 #define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
\r
805 #define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
\r
806 #define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
\r
807 #define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
\r
808 #define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
\r
809 #define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
\r
810 #define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
\r
812 #define CR_OFFSET_BB PWR_CR_OFFSET_BB
\r
813 #define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
\r
815 #define DBP_BitNumber DBP_BIT_NUMBER
\r
816 #define PVDE_BitNumber PVDE_BIT_NUMBER
\r
817 #define PMODE_BitNumber PMODE_BIT_NUMBER
\r
818 #define EWUP_BitNumber EWUP_BIT_NUMBER
\r
819 #define FPDS_BitNumber FPDS_BIT_NUMBER
\r
820 #define ODEN_BitNumber ODEN_BIT_NUMBER
\r
821 #define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
\r
822 #define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
\r
823 #define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
\r
824 #define BRE_BitNumber BRE_BIT_NUMBER
\r
826 #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
\r
832 /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
\r
835 #define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
\r
836 #define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
\r
837 #define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
\r
842 /** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
\r
845 #define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
\r
850 /** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
\r
853 #define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
\r
854 #define HAL_TIM_DMAError TIM_DMAError
\r
855 #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
\r
856 #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
\r
861 /** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
\r
864 #define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
\r
870 /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
\r
878 /* Exported macros ------------------------------------------------------------*/
\r
880 /** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
\r
883 #define AES_IT_CC CRYP_IT_CC
\r
884 #define AES_IT_ERR CRYP_IT_ERR
\r
885 #define AES_FLAG_CCF CRYP_FLAG_CCF
\r
890 /** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
\r
893 #define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
\r
894 #define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
\r
895 #define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
\r
896 #define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
\r
897 #define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
\r
898 #define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
\r
899 #define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC
\r
900 #define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI
\r
901 #define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
\r
902 #define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
\r
903 #define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
\r
904 #define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
\r
905 #define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
\r
907 #define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
\r
908 #define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
\r
909 #define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
\r
910 #define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
\r
911 #define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
\r
918 /** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
\r
921 #define __ADC_ENABLE __HAL_ADC_ENABLE
\r
922 #define __ADC_DISABLE __HAL_ADC_DISABLE
\r
923 #define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
\r
924 #define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
\r
925 #define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE
\r
926 #define __ADC_IS_ENABLED ADC_IS_ENABLE
\r
927 #define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
\r
928 #define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
\r
929 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
\r
930 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR
\r
931 #define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED
\r
932 #define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
\r
933 #define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
\r
935 #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
\r
936 #define __HAL_ADC_JSQR_RK ADC_JSQR_RK
\r
937 #define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
\r
938 #define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
\r
939 #define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
\r
940 #define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
\r
941 #define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
\r
942 #define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
\r
943 #define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
\r
944 #define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
\r
945 #define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
\r
946 #define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
\r
947 #define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
\r
948 #define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
\r
949 #define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
\r
950 #define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
\r
951 #define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
\r
952 #define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
\r
953 #define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
\r
954 #define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
\r
956 #define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
\r
957 #define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
\r
958 #define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
\r
959 #define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
\r
960 #define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
\r
961 #define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
\r
962 #define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
\r
963 #define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER
\r
964 #define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
\r
965 #define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
\r
967 #define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
\r
968 #define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
\r
969 #define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
\r
970 #define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
\r
971 #define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
\r
972 #define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
\r
973 #define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
\r
974 #define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
\r
976 #define __HAL_ADC_SQR1 ADC_SQR1
\r
977 #define __HAL_ADC_SMPR1 ADC_SMPR1
\r
978 #define __HAL_ADC_SMPR2 ADC_SMPR2
\r
979 #define __HAL_ADC_SQR3_RK ADC_SQR3_RK
\r
980 #define __HAL_ADC_SQR2_RK ADC_SQR2_RK
\r
981 #define __HAL_ADC_SQR1_RK ADC_SQR1_RK
\r
982 #define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
\r
983 #define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
\r
984 #define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
\r
985 #define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
\r
986 #define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
\r
987 #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
\r
988 #define __HAL_ADC_JSQR ADC_JSQR
\r
990 #define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
\r
991 #define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
\r
992 #define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
\r
993 #define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
\r
994 #define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
\r
995 #define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
\r
996 #define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
\r
997 #define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
\r
1003 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
\r
1006 #define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
\r
1007 #define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
\r
1008 #define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
\r
1009 #define IS_DAC_GENERATE_WAVE IS_DAC_WAVE
\r
1015 /** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
\r
1018 #define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
\r
1019 #define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
\r
1020 #define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
\r
1021 #define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
\r
1022 #define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
\r
1023 #define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
\r
1024 #define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
\r
1025 #define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
\r
1026 #define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
\r
1027 #define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
\r
1028 #define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
\r
1029 #define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
\r
1030 #define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
\r
1031 #define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
\r
1032 #define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
\r
1033 #define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
\r
1035 #define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
\r
1036 #define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
\r
1037 #define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
\r
1038 #define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
\r
1039 #define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
\r
1040 #define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
\r
1041 #define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
\r
1042 #define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
\r
1043 #define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
\r
1044 #define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
\r
1045 #define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
\r
1046 #define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
\r
1047 #define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
\r
1048 #define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
\r
1051 #define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
\r
1052 #define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
\r
1053 #define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
\r
1054 #define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
\r
1055 #define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
\r
1056 #define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
\r
1057 #define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
\r
1058 #define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
\r
1059 #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
\r
1060 #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
\r
1061 #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
\r
1062 #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
\r
1063 #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
\r
1064 #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
\r
1065 #define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
\r
1066 #define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
\r
1067 #define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
\r
1068 #define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
\r
1069 #define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
\r
1070 #define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
\r
1071 #define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
\r
1072 #define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
\r
1073 #define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
\r
1074 #define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
\r
1080 /** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
\r
1084 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
\r
1085 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
\r
1086 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
\r
1087 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
\r
1088 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
\r
1089 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
\r
1090 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
\r
1091 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
\r
1092 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
\r
1093 __HAL_COMP_COMP2_EXTI_ENABLE_IT())
\r
1094 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
\r
1095 __HAL_COMP_COMP2_EXTI_DISABLE_IT())
\r
1096 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
\r
1097 __HAL_COMP_COMP2_EXTI_GET_FLAG())
\r
1098 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
\r
1099 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
\r
1100 #define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
\r
1106 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
\r
1110 #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
\r
1111 ((WAVE) == DAC_WAVE_NOISE)|| \
\r
1112 ((WAVE) == DAC_WAVE_TRIANGLE))
\r
1118 /** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
\r
1122 #define IS_WRPAREA IS_OB_WRPAREA
\r
1123 #define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
\r
1124 #define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
\r
1125 #define IS_TYPEERASE IS_FLASH_TYPEERASE
\r
1131 /** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
\r
1135 #define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
\r
1136 #define __HAL_I2C_GENERATE_START I2C_GENERATE_START
\r
1137 #define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
\r
1138 #define __HAL_I2C_RISE_TIME I2C_RISE_TIME
\r
1139 #define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
\r
1140 #define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
\r
1141 #define __HAL_I2C_SPEED I2C_SPEED
\r
1142 #define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
\r
1143 #define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
\r
1144 #define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
\r
1145 #define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
\r
1146 #define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
\r
1147 #define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
\r
1148 #define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
\r
1149 #define __HAL_I2C_FREQRANGE I2C_FREQRANGE
\r
1154 /** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
\r
1158 #define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
\r
1159 #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
\r
1165 /** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
\r
1169 #define __IRDA_DISABLE __HAL_IRDA_DISABLE
\r
1170 #define __IRDA_ENABLE __HAL_IRDA_ENABLE
\r
1172 #define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
\r
1173 #define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
\r
1174 #define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
\r
1175 #define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
\r
1177 #define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
\r
1185 /** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
\r
1188 #define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
\r
1189 #define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
\r
1195 /** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
\r
1199 #define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
\r
1200 #define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
\r
1201 #define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
\r
1208 /** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
\r
1211 #define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD
\r
1212 #define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX
\r
1213 #define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX
\r
1214 #define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX
\r
1215 #define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX
\r
1216 #define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L
\r
1217 #define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H
\r
1218 #define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM
\r
1219 #define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES
\r
1220 #define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX
\r
1221 #define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT
\r
1222 #define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION
\r
1223 #define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET
\r
1230 /** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
\r
1233 #define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
\r
1234 #define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
\r
1235 #define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
\r
1236 #define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
\r
1237 #define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
\r
1238 #define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
\r
1239 #define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
\r
1240 #define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
\r
1241 #define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
\r
1242 #define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
\r
1243 #define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
\r
1244 #define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
\r
1245 #define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
\r
1246 #define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
\r
1247 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
\r
1248 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
\r
1249 #define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()
\r
1250 #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
\r
1251 #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
\r
1252 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
\r
1253 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
\r
1254 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
\r
1255 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
\r
1256 #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
\r
1257 #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
\r
1258 #define __HAL_PWR_PVM_DISABLE() HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4()
\r
1259 #define __HAL_PWR_PVM_ENABLE() HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4()
\r
1260 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
\r
1261 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
\r
1262 #define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
\r
1263 #define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
\r
1264 #define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
\r
1265 #define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
\r
1266 #define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
\r
1267 #define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
\r
1269 #if defined (STM32F4)
\r
1270 #define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
\r
1271 #define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
\r
1272 #define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
\r
1273 #define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
\r
1274 #define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
\r
1276 #define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
\r
1277 #define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
\r
1278 #define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
\r
1279 #define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
\r
1280 #define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
\r
1281 #endif /* STM32F4 */
\r
1287 /** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
\r
1291 #define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
\r
1292 #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
\r
1294 #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
\r
1295 #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
\r
1297 #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
\r
1298 #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
\r
1299 #define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
\r
1300 #define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
\r
1301 #define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
\r
1302 #define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
\r
1303 #define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
\r
1304 #define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
\r
1305 #define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
\r
1306 #define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
\r
1307 #define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
\r
1308 #define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
\r
1309 #define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
\r
1310 #define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
\r
1311 #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
\r
1312 #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
\r
1313 #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
\r
1314 #define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
\r
1315 #define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
\r
1316 #define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
\r
1317 #define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
\r
1318 #define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
\r
1319 #define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
\r
1320 #define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
\r
1321 #define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
\r
1322 #define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
\r
1323 #define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
\r
1324 #define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
\r
1325 #define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
\r
1326 #define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
\r
1327 #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
\r
1328 #define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
\r
1329 #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
\r
1330 #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
\r
1331 #define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
\r
1332 #define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
\r
1333 #define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
\r
1334 #define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
\r
1335 #define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
\r
1336 #define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
\r
1337 #define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
\r
1338 #define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
\r
1339 #define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
\r
1340 #define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
\r
1341 #define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
\r
1342 #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
\r
1343 #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
\r
1344 #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
\r
1345 #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
\r
1346 #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
\r
1347 #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
\r
1348 #define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
\r
1349 #define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
\r
1350 #define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
\r
1351 #define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
\r
1352 #define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
\r
1353 #define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
\r
1354 #define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
\r
1355 #define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
\r
1356 #define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
\r
1357 #define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
\r
1358 #define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
\r
1359 #define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
\r
1360 #define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
\r
1361 #define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
\r
1362 #define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
\r
1363 #define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
\r
1364 #define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
\r
1365 #define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE
\r
1366 #define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE
\r
1367 #define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET
\r
1368 #define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET
\r
1369 #define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE
\r
1370 #define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE
\r
1371 #define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
\r
1372 #define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
\r
1373 #define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
\r
1374 #define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
\r
1375 #define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
\r
1376 #define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
\r
1377 #define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
\r
1378 #define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
\r
1379 #define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
\r
1380 #define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
\r
1381 #define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
\r
1382 #define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
\r
1383 #define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
\r
1384 #define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
\r
1385 #define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
\r
1386 #define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
\r
1387 #define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
\r
1388 #define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
\r
1389 #define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE
\r
1390 #define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE
\r
1391 #define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET
\r
1392 #define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET
\r
1393 #define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
\r
1394 #define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
\r
1395 #define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
\r
1396 #define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
\r
1397 #define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
\r
1398 #define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
\r
1399 #define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
\r
1400 #define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
\r
1401 #define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
\r
1402 #define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
\r
1403 #define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
\r
1404 #define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
\r
1405 #define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
\r
1406 #define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
\r
1407 #define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
\r
1408 #define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
\r
1409 #define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
\r
1410 #define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
\r
1411 #define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
\r
1412 #define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
\r
1413 #define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
\r
1414 #define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
\r
1415 #define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
\r
1416 #define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
\r
1417 #define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
\r
1418 #define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
\r
1419 #define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
\r
1420 #define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
\r
1421 #define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
\r
1422 #define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
\r
1423 #define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
\r
1424 #define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
\r
1425 #define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
\r
1426 #define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
\r
1427 #define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
\r
1428 #define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
\r
1429 #define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET
\r
1430 #define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET
\r
1431 #define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
\r
1432 #define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
\r
1433 #define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
\r
1434 #define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
\r
1435 #define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
\r
1436 #define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
\r
1437 #define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
\r
1438 #define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
\r
1439 #define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
\r
1440 #define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
\r
1441 #define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
\r
1442 #define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
\r
1443 #define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
\r
1444 #define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
\r
1445 #define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
\r
1446 #define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
\r
1447 #define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
\r
1448 #define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
\r
1449 #define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
\r
1450 #define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
\r
1451 #define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
\r
1452 #define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
\r
1453 #define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
\r
1454 #define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
\r
1455 #define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
\r
1456 #define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
\r
1457 #define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
\r
1458 #define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
\r
1459 #define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
\r
1460 #define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
\r
1461 #define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
\r
1462 #define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
\r
1463 #define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
\r
1464 #define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
\r
1465 #define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
\r
1466 #define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
\r
1467 #define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
\r
1468 #define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
\r
1469 #define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
\r
1470 #define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
\r
1471 #define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
\r
1472 #define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
\r
1473 #define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
\r
1474 #define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
\r
1475 #define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
\r
1476 #define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
\r
1477 #define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
\r
1478 #define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
\r
1479 #define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
\r
1480 #define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
\r
1481 #define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
\r
1482 #define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
\r
1483 #define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
\r
1484 #define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
\r
1485 #define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
\r
1486 #define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
\r
1487 #define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
\r
1488 #define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
\r
1489 #define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
\r
1490 #define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
\r
1491 #define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
\r
1492 #define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
\r
1493 #define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
\r
1494 #define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
\r
1495 #define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
\r
1496 #define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
\r
1497 #define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
\r
1498 #define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
\r
1499 #define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
\r
1500 #define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
\r
1501 #define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
\r
1502 #define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
\r
1503 #define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
\r
1504 #define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
\r
1505 #define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
\r
1506 #define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
\r
1507 #define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
\r
1508 #define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
\r
1509 #define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
\r
1510 #define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
\r
1511 #define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
\r
1512 #define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
\r
1513 #define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
\r
1514 #define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
\r
1515 #define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
\r
1516 #define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
\r
1517 #define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
\r
1518 #define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
\r
1519 #define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
\r
1520 #define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
\r
1521 #define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
\r
1522 #define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
\r
1523 #define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
\r
1524 #define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
\r
1525 #define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
\r
1526 #define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
\r
1527 #define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
\r
1528 #define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
\r
1529 #define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
\r
1530 #define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
\r
1531 #define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
\r
1532 #define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
\r
1533 #define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
\r
1534 #define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
\r
1535 #define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
\r
1536 #define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
\r
1537 #define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
\r
1538 #define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
\r
1539 #define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
\r
1540 #define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
\r
1541 #define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
\r
1542 #define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
\r
1543 #define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
\r
1544 #define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
\r
1545 #define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
\r
1546 #define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
\r
1547 #define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
\r
1548 #define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
\r
1549 #define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
\r
1550 #define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
\r
1551 #define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
\r
1552 #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
\r
1553 #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
\r
1554 #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
\r
1555 #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
\r
1556 #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
\r
1557 #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
\r
1558 #define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
\r
1559 #define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
\r
1560 #define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
\r
1561 #define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
\r
1562 #define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
\r
1563 #define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
\r
1564 #define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
\r
1565 #define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
\r
1566 #define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
\r
1567 #define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
\r
1568 #define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
\r
1569 #define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
\r
1570 #define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
\r
1571 #define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
\r
1572 #define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
\r
1573 #define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
\r
1574 #define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
\r
1575 #define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
\r
1576 #define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
\r
1577 #define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
\r
1578 #define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
\r
1579 #define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
\r
1580 #define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
\r
1581 #define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
\r
1582 #define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
\r
1583 #define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
\r
1584 #define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
\r
1585 #define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
\r
1586 #define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
\r
1587 #define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
\r
1588 #define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
\r
1589 #define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
\r
1590 #define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
\r
1591 #define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
\r
1592 #define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
\r
1593 #define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
\r
1594 #define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
\r
1595 #define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
\r
1596 #define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
\r
1597 #define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
\r
1598 #define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
\r
1599 #define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
\r
1600 #define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
\r
1601 #define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
\r
1602 #define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
\r
1603 #define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
\r
1604 #define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
\r
1605 #define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
\r
1606 #define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
\r
1607 #define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
\r
1608 #define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
\r
1609 #define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
\r
1610 #define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
\r
1611 #define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
\r
1612 #define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
\r
1613 #define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
\r
1614 #define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
\r
1615 #define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
\r
1616 #define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
\r
1617 #define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
\r
1618 #define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
\r
1619 #define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
\r
1620 #define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
\r
1621 #define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
\r
1622 #define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
\r
1623 #define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
\r
1624 #define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
\r
1625 #define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
\r
1626 #define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
\r
1627 #define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
\r
1628 #define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
\r
1629 #define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
\r
1630 #define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
\r
1631 #define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
\r
1632 #define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
\r
1633 #define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
\r
1634 #define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
\r
1635 #define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
\r
1636 #define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
\r
1637 #define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
\r
1638 #define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
\r
1639 #define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
\r
1640 #define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
\r
1641 #define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
\r
1642 #define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
\r
1643 #define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
\r
1644 #define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
\r
1645 #define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
\r
1646 #define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
\r
1647 #define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
\r
1648 #define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
\r
1649 #define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
\r
1650 #define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
\r
1651 #define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
\r
1652 #define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
\r
1653 #define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
\r
1654 #define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
\r
1655 #define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
\r
1656 #define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
\r
1657 #define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
\r
1658 #define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
\r
1659 #define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
\r
1660 #define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
\r
1661 #define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
\r
1662 #define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
\r
1663 #define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
\r
1664 #define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
\r
1665 #define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
\r
1666 #define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
\r
1667 #define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
\r
1668 #define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
\r
1669 #define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
\r
1670 #define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
\r
1671 #define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
\r
1672 #define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
\r
1673 #define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
\r
1674 #define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
\r
1675 #define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
\r
1676 #define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
\r
1677 #define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
\r
1678 #define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
\r
1679 #define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
\r
1680 #define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
\r
1681 #define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
\r
1682 #define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
\r
1683 #define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
\r
1684 #define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
\r
1685 #define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
\r
1686 #define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
\r
1687 #define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
\r
1688 #define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
\r
1689 #define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
\r
1690 #define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
\r
1691 #define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
\r
1692 #define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
\r
1693 #define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
\r
1694 #define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
\r
1695 #define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
\r
1696 #define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
\r
1697 #define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
\r
1698 #define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
\r
1699 #define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
\r
1700 #define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
\r
1701 #define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
\r
1702 #define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
\r
1703 #define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
\r
1704 #define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
\r
1705 #define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
\r
1706 #define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
\r
1707 #define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
\r
1708 #define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
\r
1709 #define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
\r
1710 #define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
\r
1711 #define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
\r
1712 #define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
\r
1713 #define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
\r
1714 #define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
\r
1715 #define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
\r
1716 #define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
\r
1717 #define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
\r
1718 #define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
\r
1719 #define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
\r
1720 #define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
\r
1721 #define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
\r
1722 #define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
\r
1723 #define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
\r
1724 #define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
\r
1725 #define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
\r
1726 #define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
\r
1727 #define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
\r
1728 #define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
\r
1729 #define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
\r
1730 #define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
\r
1731 #define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
\r
1732 #define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
\r
1733 #define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
\r
1734 #define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
\r
1735 #define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
\r
1736 #define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
\r
1737 #define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
\r
1738 #define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
\r
1739 #define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
\r
1740 #define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
\r
1741 #define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
\r
1742 #define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
\r
1743 #define __USART4_CLK_DISABLE __HAL_RCC_USART4_CLK_DISABLE
\r
1744 #define __USART4_CLK_ENABLE __HAL_RCC_USART4_CLK_ENABLE
\r
1745 #define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_USART4_CLK_SLEEP_ENABLE
\r
1746 #define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE
\r
1747 #define __USART4_FORCE_RESET __HAL_RCC_USART4_FORCE_RESET
\r
1748 #define __USART4_RELEASE_RESET __HAL_RCC_USART4_RELEASE_RESET
\r
1749 #define __USART5_CLK_DISABLE __HAL_RCC_USART5_CLK_DISABLE
\r
1750 #define __USART5_CLK_ENABLE __HAL_RCC_USART5_CLK_ENABLE
\r
1751 #define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_USART5_CLK_SLEEP_ENABLE
\r
1752 #define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE
\r
1753 #define __USART5_FORCE_RESET __HAL_RCC_USART5_FORCE_RESET
\r
1754 #define __USART5_RELEASE_RESET __HAL_RCC_USART5_RELEASE_RESET
\r
1755 #define __USART7_CLK_DISABLE __HAL_RCC_USART7_CLK_DISABLE
\r
1756 #define __USART7_CLK_ENABLE __HAL_RCC_USART7_CLK_ENABLE
\r
1757 #define __USART7_FORCE_RESET __HAL_RCC_USART7_FORCE_RESET
\r
1758 #define __USART7_RELEASE_RESET __HAL_RCC_USART7_RELEASE_RESET
\r
1759 #define __USART8_CLK_DISABLE __HAL_RCC_USART8_CLK_DISABLE
\r
1760 #define __USART8_CLK_ENABLE __HAL_RCC_USART8_CLK_ENABLE
\r
1761 #define __USART8_FORCE_RESET __HAL_RCC_USART8_FORCE_RESET
\r
1762 #define __USART8_RELEASE_RESET __HAL_RCC_USART8_RELEASE_RESET
\r
1763 #define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
\r
1764 #define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
\r
1765 #define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
\r
1766 #define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE
\r
1767 #define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE
\r
1768 #define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
\r
1769 #define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
\r
1770 #define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
\r
1771 #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
\r
1772 #define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
\r
1773 #define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
\r
1774 #define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
\r
1775 #define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
\r
1776 #define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
\r
1777 #define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
\r
1778 #define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
\r
1779 #define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
\r
1780 #define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
\r
1781 #define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
\r
1782 #define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
\r
1783 #define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
\r
1784 #define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
\r
1785 #define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
\r
1786 #define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
\r
1787 #define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
\r
1788 #define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
\r
1789 #define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
\r
1790 #define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
\r
1791 #define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
\r
1792 #define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
\r
1793 #define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
\r
1794 #define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
\r
1795 #define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
\r
1796 #define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
\r
1798 #define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
\r
1799 #define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
\r
1800 #define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
\r
1801 #define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
\r
1802 #define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
\r
1803 #define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
\r
1804 #define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
\r
1805 #define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
\r
1806 #define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
\r
1807 #define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
\r
1808 #define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
\r
1809 #define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
\r
1810 #define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
\r
1811 #define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
\r
1812 #define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
\r
1813 #define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
\r
1814 #define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
\r
1815 #define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
\r
1816 #define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
\r
1817 #define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
\r
1818 #define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
\r
1819 #define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
\r
1820 #define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
\r
1821 #define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
\r
1822 #define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
\r
1823 #define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
\r
1824 #define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
\r
1825 #define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
\r
1826 #define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
\r
1827 #define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
\r
1828 #define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
\r
1829 #define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
\r
1830 #define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
\r
1831 #define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
\r
1832 #define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
\r
1833 #define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
\r
1834 #define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
\r
1835 #define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
\r
1836 #define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
\r
1837 #define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
\r
1838 #define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
\r
1839 #define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
\r
1840 #define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
\r
1841 #define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
\r
1842 #define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
\r
1843 #define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
\r
1844 #define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
\r
1845 #define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
\r
1846 #define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
\r
1847 #define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
\r
1848 #define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
\r
1849 #define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
\r
1850 #define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
\r
1851 #define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
\r
1852 #define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
\r
1853 #define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
\r
1854 #define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
\r
1855 #define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
\r
1856 #define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
\r
1857 #define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
\r
1858 #define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
\r
1859 #define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
\r
1860 #define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
\r
1861 #define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
\r
1862 #define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
\r
1863 #define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
\r
1864 #define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
\r
1865 #define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
\r
1866 #define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
\r
1867 #define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
\r
1868 #define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
\r
1869 #define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
\r
1870 #define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
\r
1871 #define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
\r
1872 #define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
\r
1873 #define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
\r
1874 #define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
\r
1875 #define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
\r
1876 #define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
\r
1877 #define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
\r
1878 #define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
\r
1879 #define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
\r
1880 #define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
\r
1881 #define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
\r
1882 #define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
\r
1883 #define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
\r
1884 #define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
\r
1885 #define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
\r
1886 #define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
\r
1887 #define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
\r
1888 #define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
\r
1889 #define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
\r
1890 #define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
\r
1891 #define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
\r
1892 #define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
\r
1893 #define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
\r
1894 #define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
\r
1895 #define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
\r
1896 #define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
\r
1897 #define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
\r
1898 #define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
\r
1899 #define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
\r
1900 #define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
\r
1901 #define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
\r
1902 #define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
\r
1903 #define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
\r
1904 #define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
\r
1905 #define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
\r
1906 #define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
\r
1907 #define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
\r
1908 #define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
\r
1909 #define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
\r
1910 #define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
\r
1911 #define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
\r
1912 #define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
\r
1913 #define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
\r
1914 #define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
\r
1915 #define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
\r
1916 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
\r
1917 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
\r
1918 #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
\r
1919 #define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
\r
1920 #define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
\r
1921 #define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
\r
1922 #define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
\r
1923 #define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
\r
1924 #define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
\r
1925 #define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
\r
1926 #define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
\r
1927 #define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
\r
1928 #define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
\r
1929 #define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
\r
1930 #define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
\r
1931 #define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
\r
1932 #define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
\r
1933 #define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
\r
1934 #define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
\r
1935 #define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
\r
1936 #define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
\r
1937 #define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
\r
1938 #define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
\r
1939 #define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
\r
1940 #define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
\r
1941 #define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
\r
1943 /* alias define maintained for legacy */
\r
1944 #define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
\r
1945 #define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
\r
1947 #define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
\r
1948 #define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
\r
1950 #define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
\r
1952 #define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
\r
1953 #define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
\r
1954 #define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
\r
1955 #define IS_RCC_HCLK_DIV IS_RCC_PCLK
\r
1957 #define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
\r
1958 #define RCC_MCO_NODIV RCC_MCODIV_1
\r
1959 #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
\r
1961 #define HSION_BitNumber RCC_HSION_BIT_NUMBER
\r
1962 #define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
\r
1963 #define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
\r
1964 #define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
\r
1965 #define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
\r
1966 #define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
\r
1967 #define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
\r
1968 #define LSION_BitNumber RCC_LSION_BIT_NUMBER
\r
1969 #define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
\r
1970 #define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
\r
1972 #define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
\r
1973 #define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
\r
1974 #define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
\r
1975 #define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
\r
1976 #define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
\r
1977 #define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
\r
1979 #define CR_HSION_BB RCC_CR_HSION_BB
\r
1980 #define CR_CSSON_BB RCC_CR_CSSON_BB
\r
1981 #define CR_PLLON_BB RCC_CR_PLLON_BB
\r
1982 #define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
\r
1983 #define CR_MSION_BB RCC_CR_MSION_BB
\r
1984 #define CSR_LSION_BB RCC_CSR_LSION_BB
\r
1985 #define CSR_LSEON_BB RCC_CSR_LSEON_BB
\r
1986 #define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB
\r
1987 #define CSR_RTCEN_BB RCC_CSR_RTCEN_BB
\r
1988 #define CSR_RTCRST_BB RCC_CSR_RTCRST_BB
\r
1989 #define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
\r
1990 #define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
\r
1991 #define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
\r
1992 #define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
\r
1993 #define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
\r
1999 /** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
\r
2002 #define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
\r
2008 /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
\r
2012 #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
\r
2013 #define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
\r
2014 #define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
\r
2016 #if defined (STM32F1)
\r
2017 #define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
\r
2019 #define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
\r
2021 #define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()
\r
2023 #define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()
\r
2025 #define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
\r
2027 #define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
\r
2028 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
\r
2029 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
\r
2030 #define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
\r
2031 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
\r
2032 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
\r
2033 #define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
\r
2034 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
\r
2035 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
\r
2036 #define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
\r
2037 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
\r
2038 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
\r
2039 #define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
\r
2040 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
\r
2041 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
\r
2042 #endif /* STM32F1 */
\r
2044 #define IS_ALARM IS_RTC_ALARM
\r
2045 #define IS_ALARM_MASK IS_RTC_ALARM_MASK
\r
2046 #define IS_TAMPER IS_RTC_TAMPER
\r
2047 #define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
\r
2048 #define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
\r
2049 #define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
\r
2050 #define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
\r
2051 #define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
\r
2052 #define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
\r
2053 #define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
\r
2054 #define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
\r
2055 #define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
\r
2056 #define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
\r
2057 #define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
\r
2059 #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
\r
2060 #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
\r
2066 /** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
\r
2070 #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
\r
2071 #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
\r
2077 /** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
\r
2081 #define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
\r
2082 #define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
\r
2083 #define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
\r
2084 #define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
\r
2085 #define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
\r
2086 #define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
\r
2088 #define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
\r
2089 #define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
\r
2091 #define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
\r
2097 /** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
\r
2100 #define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
\r
2101 #define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
\r
2102 #define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
\r
2103 #define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
\r
2104 #define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR
\r
2105 #define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
\r
2106 #define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
\r
2107 #define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
\r
2112 /** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
\r
2116 #define __HAL_SPI_1LINE_TX SPI_1LINE_TX
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2117 #define __HAL_SPI_1LINE_RX SPI_1LINE_RX
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2118 #define __HAL_SPI_RESET_CRC SPI_RESET_CRC
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2124 /** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
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2128 #define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
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2129 #define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
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2130 #define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
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2131 #define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
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2133 #define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
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2135 #define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
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2136 #define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
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2143 /** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
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2147 #define __USART_ENABLE_IT __HAL_USART_ENABLE_IT
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2148 #define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
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2149 #define __USART_ENABLE __HAL_USART_ENABLE
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2150 #define __USART_DISABLE __HAL_USART_DISABLE
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2152 #define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
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2153 #define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
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2159 /** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
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2162 #define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
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2164 #define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
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2165 #define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
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2166 #define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
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2167 #define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
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2169 #define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
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2170 #define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
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2171 #define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
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2172 #define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
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2174 #define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
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2175 #define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
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2176 #define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
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2177 #define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
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2178 #define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
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2179 #define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
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2180 #define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
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2182 #define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
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2183 #define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
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2184 #define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
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2185 #define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
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2186 #define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
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2187 #define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
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2188 #define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
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2189 #define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
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2191 #define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
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2192 #define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
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2193 #define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
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2194 #define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
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2195 #define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
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2196 #define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
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2197 #define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
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2198 #define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
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2200 #define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
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2201 #define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
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2203 #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
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2204 #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
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2209 /** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
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2212 #define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
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2213 #define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
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2215 #define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
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2216 #define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
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2218 #define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
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2220 #define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
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2221 #define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
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2222 #define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
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2223 #define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
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2224 #define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
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2225 #define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
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2226 #define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
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2227 #define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
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2228 #define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
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2229 #define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
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2230 #define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
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2231 #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
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2233 #define TIM_TS_ITR0 ((uint32_t)0x0000)
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2234 #define TIM_TS_ITR1 ((uint32_t)0x0010)
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2235 #define TIM_TS_ITR2 ((uint32_t)0x0020)
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2236 #define TIM_TS_ITR3 ((uint32_t)0x0030)
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2237 #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
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2238 ((SELECTION) == TIM_TS_ITR1) || \
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2239 ((SELECTION) == TIM_TS_ITR2) || \
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2240 ((SELECTION) == TIM_TS_ITR3))
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2242 #define TIM_CHANNEL_1 ((uint32_t)0x0000)
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2243 #define TIM_CHANNEL_2 ((uint32_t)0x0004)
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2244 #define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
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2245 ((CHANNEL) == TIM_CHANNEL_2))
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2247 #define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
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2248 #define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
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2250 #define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \
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2251 ((STATE) == TIM_OUTPUTNSTATE_ENABLE))
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2253 #define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
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2254 #define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
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2256 #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \
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2257 ((STATE) == TIM_OUTPUTSTATE_ENABLE))
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2262 /** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
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2266 #define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
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2267 #define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
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2268 #define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
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2269 #define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
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2270 #define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
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2271 #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
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2272 #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
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2274 #define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
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2275 #define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
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2276 #define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
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2281 /** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
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2284 #define __HAL_LTDC_LAYER LTDC_LAYER
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2289 /** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
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2292 #define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
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2293 #define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
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2294 #define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
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2295 #define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
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2296 #define SAI_STREOMODE SAI_STEREOMODE
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2297 #define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
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2298 #define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
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2299 #define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
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2300 #define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
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2301 #define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
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2302 #define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
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2303 #define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
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2310 /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
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2318 #ifdef __cplusplus
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2322 #endif /* ___STM32_HAL_LEGACY */
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2324 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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