2 ******************************************************************************
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3 * @file stm32f7xx_hal_dma.h
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4 * @author MCD Application Team
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6 * @date 06-March-2015
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7 * @brief Header file of DMA HAL module.
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8 ******************************************************************************
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11 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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13 * Redistribution and use in source and binary forms, with or without modification,
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14 * are permitted provided that the following conditions are met:
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15 * 1. Redistributions of source code must retain the above copyright notice,
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16 * this list of conditions and the following disclaimer.
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17 * 2. Redistributions in binary form must reproduce the above copyright notice,
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18 * this list of conditions and the following disclaimer in the documentation
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19 * and/or other materials provided with the distribution.
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20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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21 * may be used to endorse or promote products derived from this software
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22 * without specific prior written permission.
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24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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35 ******************************************************************************
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38 /* Define to prevent recursive inclusion -------------------------------------*/
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39 #ifndef __STM32F7xx_HAL_DMA_H
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40 #define __STM32F7xx_HAL_DMA_H
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46 /* Includes ------------------------------------------------------------------*/
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47 #include "stm32f7xx_hal_def.h"
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49 /** @addtogroup STM32F7xx_HAL_Driver
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57 /* Exported types ------------------------------------------------------------*/
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59 /** @defgroup DMA_Exported_Types DMA Exported Types
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60 * @brief DMA Exported Types
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65 * @brief DMA Configuration Structure definition
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69 uint32_t Channel; /*!< Specifies the channel used for the specified stream.
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70 This parameter can be a value of @ref DMA_Channel_selection */
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72 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
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73 from memory to memory or from peripheral to memory.
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74 This parameter can be a value of @ref DMA_Data_transfer_direction */
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76 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
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77 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
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79 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
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80 This parameter can be a value of @ref DMA_Memory_incremented_mode */
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82 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
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83 This parameter can be a value of @ref DMA_Peripheral_data_size */
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85 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
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86 This parameter can be a value of @ref DMA_Memory_data_size */
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88 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx.
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89 This parameter can be a value of @ref DMA_mode
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90 @note The circular buffer mode cannot be used if the memory-to-memory
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91 data transfer is configured on the selected Stream */
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93 uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx.
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94 This parameter can be a value of @ref DMA_Priority_level */
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96 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
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97 This parameter can be a value of @ref DMA_FIFO_direct_mode
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98 @note The Direct mode (FIFO mode disabled) cannot be used if the
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99 memory-to-memory data transfer is configured on the selected stream */
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101 uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
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102 This parameter can be a value of @ref DMA_FIFO_threshold_level */
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104 uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
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105 It specifies the amount of data to be transferred in a single non interruptible
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107 This parameter can be a value of @ref DMA_Memory_burst
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108 @note The burst mode is possible only if the address Increment mode is enabled. */
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110 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
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111 It specifies the amount of data to be transferred in a single non interruptible
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113 This parameter can be a value of @ref DMA_Peripheral_burst
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114 @note The burst mode is possible only if the address Increment mode is enabled. */
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118 * @brief HAL DMA State structures definition
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122 HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
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123 HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */
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124 HAL_DMA_STATE_READY_MEM0 = 0x11, /*!< DMA Mem0 process success */
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125 HAL_DMA_STATE_READY_MEM1 = 0x21, /*!< DMA Mem1 process success */
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126 HAL_DMA_STATE_READY_HALF_MEM0 = 0x31, /*!< DMA Mem0 Half process success */
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127 HAL_DMA_STATE_READY_HALF_MEM1 = 0x41, /*!< DMA Mem1 Half process success */
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128 HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
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129 HAL_DMA_STATE_BUSY_MEM0 = 0x12, /*!< DMA Mem0 process is ongoing */
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130 HAL_DMA_STATE_BUSY_MEM1 = 0x22, /*!< DMA Mem1 process is ongoing */
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131 HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
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132 HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
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133 }HAL_DMA_StateTypeDef;
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136 * @brief HAL DMA Error Code structure definition
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140 HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
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141 HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
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142 }HAL_DMA_LevelCompleteTypeDef;
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145 * @brief DMA handle Structure definition
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147 typedef struct __DMA_HandleTypeDef
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149 DMA_Stream_TypeDef *Instance; /*!< Register base address */
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151 DMA_InitTypeDef Init; /*!< DMA communication parameters */
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153 HAL_LockTypeDef Lock; /*!< DMA locking object */
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155 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
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157 void *Parent; /*!< Parent object state */
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159 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
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161 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
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163 void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */
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165 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
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167 __IO uint32_t ErrorCode; /*!< DMA Error code */
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168 }DMA_HandleTypeDef;
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175 /* Exported constants --------------------------------------------------------*/
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177 /** @defgroup DMA_Exported_Constants DMA Exported Constants
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178 * @brief DMA Exported constants
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182 /** @defgroup DMA_Error_Code DMA Error Code
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183 * @brief DMA Error Code
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186 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
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187 #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
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188 #define HAL_DMA_ERROR_FE ((uint32_t)0x00000002) /*!< FIFO error */
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189 #define HAL_DMA_ERROR_DME ((uint32_t)0x00000004) /*!< Direct Mode error */
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190 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
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195 /** @defgroup DMA_Channel_selection DMA Channel selection
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196 * @brief DMA channel selection
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199 #define DMA_CHANNEL_0 ((uint32_t)0x00000000) /*!< DMA Channel 0 */
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200 #define DMA_CHANNEL_1 ((uint32_t)0x02000000) /*!< DMA Channel 1 */
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201 #define DMA_CHANNEL_2 ((uint32_t)0x04000000) /*!< DMA Channel 2 */
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202 #define DMA_CHANNEL_3 ((uint32_t)0x06000000) /*!< DMA Channel 3 */
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203 #define DMA_CHANNEL_4 ((uint32_t)0x08000000) /*!< DMA Channel 4 */
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204 #define DMA_CHANNEL_5 ((uint32_t)0x0A000000) /*!< DMA Channel 5 */
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205 #define DMA_CHANNEL_6 ((uint32_t)0x0C000000) /*!< DMA Channel 6 */
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206 #define DMA_CHANNEL_7 ((uint32_t)0x0E000000) /*!< DMA Channel 7 */
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211 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
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212 * @brief DMA data transfer direction
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215 #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
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216 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */
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217 #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */
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222 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
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223 * @brief DMA peripheral incremented mode
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226 #define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */
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227 #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode disable */
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232 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
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233 * @brief DMA memory incremented mode
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236 #define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */
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237 #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode disable */
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243 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
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244 * @brief DMA peripheral data size
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247 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment: Byte */
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248 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
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249 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */
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255 /** @defgroup DMA_Memory_data_size DMA Memory data size
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256 * @brief DMA memory data size
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259 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment: Byte */
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260 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
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261 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */
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266 /** @defgroup DMA_mode DMA mode
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270 #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */
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271 #define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */
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272 #define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */
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278 /** @defgroup DMA_Priority_level DMA Priority level
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279 * @brief DMA priority levels
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282 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level: Low */
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283 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */
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284 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */
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285 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */
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291 /** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
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292 * @brief DMA FIFO direct mode
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295 #define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000) /*!< FIFO mode disable */
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296 #define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */
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301 /** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
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302 * @brief DMA FIFO level
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305 #define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000) /*!< FIFO threshold 1 quart full configuration */
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306 #define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */
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307 #define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */
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308 #define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */
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313 /** @defgroup DMA_Memory_burst DMA Memory burst
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314 * @brief DMA memory burst
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317 #define DMA_MBURST_SINGLE ((uint32_t)0x00000000)
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318 #define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
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319 #define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
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320 #define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
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326 /** @defgroup DMA_Peripheral_burst DMA Peripheral burst
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327 * @brief DMA peripheral burst
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330 #define DMA_PBURST_SINGLE ((uint32_t)0x00000000)
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331 #define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
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332 #define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
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333 #define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
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338 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
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339 * @brief DMA interrupts definition
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342 #define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
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343 #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
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344 #define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
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345 #define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
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346 #define DMA_IT_FE ((uint32_t)0x00000080)
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351 /** @defgroup DMA_flag_definitions DMA flag definitions
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352 * @brief DMA flag definitions
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355 #define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001)
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356 #define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004)
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357 #define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008)
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358 #define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010)
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359 #define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020)
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360 #define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040)
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361 #define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100)
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362 #define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200)
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363 #define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400)
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364 #define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800)
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365 #define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000)
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366 #define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000)
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367 #define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000)
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368 #define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000)
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369 #define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000)
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370 #define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000)
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371 #define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000)
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372 #define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000)
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373 #define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000)
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374 #define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000)
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383 /* Exported macro ------------------------------------------------------------*/
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385 /** @brief Reset DMA handle state
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386 * @param __HANDLE__: specifies the DMA handle.
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389 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
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392 * @brief Return the current DMA Stream FIFO filled level.
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393 * @param __HANDLE__: DMA handle
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394 * @retval The FIFO filling state.
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395 * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
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397 * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
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398 * - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
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399 * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
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400 * - DMA_FIFOStatus_Empty: when FIFO is empty
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401 * - DMA_FIFOStatus_Full: when FIFO is full
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403 #define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
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406 * @brief Enable the specified DMA Stream.
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407 * @param __HANDLE__: DMA handle
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410 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)
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413 * @brief Disable the specified DMA Stream.
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414 * @param __HANDLE__: DMA handle
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417 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)
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419 /* Interrupt & Flag management */
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422 * @brief Return the current DMA Stream transfer complete flag.
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423 * @param __HANDLE__: DMA handle
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424 * @retval The specified transfer complete flag index.
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426 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
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427 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
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428 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
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429 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
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430 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
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431 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
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432 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
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433 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
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434 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
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435 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
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436 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
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437 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
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438 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
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442 * @brief Return the current DMA Stream half transfer complete flag.
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443 * @param __HANDLE__: DMA handle
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444 * @retval The specified half transfer complete flag index.
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446 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
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447 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
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448 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
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449 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
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450 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
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451 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
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452 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
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453 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
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454 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
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455 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
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456 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
\r
457 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
\r
458 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
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462 * @brief Return the current DMA Stream transfer error flag.
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463 * @param __HANDLE__: DMA handle
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464 * @retval The specified transfer error flag index.
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466 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
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467 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
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468 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
\r
469 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
\r
470 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
\r
471 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
\r
472 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
\r
473 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
\r
474 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
\r
475 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
\r
476 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
\r
477 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
\r
478 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
\r
482 * @brief Return the current DMA Stream FIFO error flag.
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483 * @param __HANDLE__: DMA handle
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484 * @retval The specified FIFO error flag index.
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486 #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
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487 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
\r
488 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
\r
489 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
\r
490 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
\r
491 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
\r
492 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
\r
493 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
\r
494 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
\r
495 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
\r
496 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
\r
497 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
\r
498 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
\r
502 * @brief Return the current DMA Stream direct mode error flag.
\r
503 * @param __HANDLE__: DMA handle
\r
504 * @retval The specified direct mode error flag index.
\r
506 #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
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507 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
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508 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
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509 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
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510 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
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511 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
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512 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
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513 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
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514 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
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515 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
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516 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
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517 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
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518 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
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522 * @brief Get the DMA Stream pending flags.
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523 * @param __HANDLE__: DMA handle
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524 * @param __FLAG__: Get the specified flag.
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525 * This parameter can be any combination of the following values:
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526 * @arg DMA_FLAG_TCIFx: Transfer complete flag.
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527 * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
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528 * @arg DMA_FLAG_TEIFx: Transfer error flag.
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529 * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
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530 * @arg DMA_FLAG_FEIFx: FIFO error flag.
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531 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
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532 * @retval The state of FLAG (SET or RESET).
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534 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
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535 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
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536 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
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537 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
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540 * @brief Clear the DMA Stream pending flags.
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541 * @param __HANDLE__: DMA handle
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542 * @param __FLAG__: specifies the flag to clear.
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543 * This parameter can be any combination of the following values:
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544 * @arg DMA_FLAG_TCIFx: Transfer complete flag.
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545 * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
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546 * @arg DMA_FLAG_TEIFx: Transfer error flag.
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547 * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
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548 * @arg DMA_FLAG_FEIFx: FIFO error flag.
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549 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
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552 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
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553 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
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554 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
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555 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
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558 * @brief Enable the specified DMA Stream interrupts.
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559 * @param __HANDLE__: DMA handle
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560 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
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561 * This parameter can be any combination of the following values:
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562 * @arg DMA_IT_TC: Transfer complete interrupt mask.
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563 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
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564 * @arg DMA_IT_TE: Transfer error interrupt mask.
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565 * @arg DMA_IT_FE: FIFO error interrupt mask.
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566 * @arg DMA_IT_DME: Direct mode error interrupt.
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569 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
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570 ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
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573 * @brief Disable the specified DMA Stream interrupts.
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574 * @param __HANDLE__: DMA handle
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575 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
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576 * This parameter can be any combination of the following values:
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577 * @arg DMA_IT_TC: Transfer complete interrupt mask.
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578 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
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579 * @arg DMA_IT_TE: Transfer error interrupt mask.
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580 * @arg DMA_IT_FE: FIFO error interrupt mask.
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581 * @arg DMA_IT_DME: Direct mode error interrupt.
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584 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
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585 ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
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588 * @brief Check whether the specified DMA Stream interrupt has occurred or not.
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589 * @param __HANDLE__: DMA handle
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590 * @param __INTERRUPT__: specifies the DMA interrupt source to check.
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591 * This parameter can be one of the following values:
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592 * @arg DMA_IT_TC: Transfer complete interrupt mask.
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593 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
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594 * @arg DMA_IT_TE: Transfer error interrupt mask.
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595 * @arg DMA_IT_FE: FIFO error interrupt mask.
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596 * @arg DMA_IT_DME: Direct mode error interrupt.
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597 * @retval The state of DMA_IT.
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599 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
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600 ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
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601 ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
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604 * @brief Writes the number of data units to be transferred on the DMA Stream.
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605 * @param __HANDLE__: DMA handle
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606 * @param __COUNTER__: Number of data units to be transferred (from 0 to 65535)
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607 * Number of data items depends only on the Peripheral data format.
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609 * @note If Peripheral data format is Bytes: number of data units is equal
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610 * to total number of bytes to be transferred.
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612 * @note If Peripheral data format is Half-Word: number of data units is
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613 * equal to total number of bytes to be transferred / 2.
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615 * @note If Peripheral data format is Word: number of data units is equal
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616 * to total number of bytes to be transferred / 4.
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618 * @retval The number of remaining data units in the current DMAy Streamx transfer.
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620 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
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623 * @brief Returns the number of remaining data units in the current DMAy Streamx transfer.
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624 * @param __HANDLE__: DMA handle
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626 * @retval The number of remaining data units in the current DMA Stream transfer.
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628 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
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631 /* Include DMA HAL Extension module */
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632 #include "stm32f7xx_hal_dma_ex.h"
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634 /* Exported functions --------------------------------------------------------*/
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636 /** @defgroup DMA_Exported_Functions DMA Exported Functions
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637 * @brief DMA Exported functions
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641 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
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642 * @brief Initialization and de-initialization functions
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645 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
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646 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
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651 /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
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652 * @brief I/O operation functions
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655 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
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656 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
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657 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
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658 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
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659 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
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664 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
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665 * @brief Peripheral State functions
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668 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
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669 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
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676 /* Private Constants -------------------------------------------------------------*/
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677 /** @defgroup DMA_Private_Constants DMA Private Constants
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678 * @brief DMA private defines and constants
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685 /* Private macros ------------------------------------------------------------*/
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686 /** @defgroup DMA_Private_Macros DMA Private Macros
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687 * @brief DMA private macros
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690 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
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691 ((CHANNEL) == DMA_CHANNEL_1) || \
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692 ((CHANNEL) == DMA_CHANNEL_2) || \
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693 ((CHANNEL) == DMA_CHANNEL_3) || \
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694 ((CHANNEL) == DMA_CHANNEL_4) || \
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695 ((CHANNEL) == DMA_CHANNEL_5) || \
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696 ((CHANNEL) == DMA_CHANNEL_6) || \
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697 ((CHANNEL) == DMA_CHANNEL_7))
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699 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
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700 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
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701 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
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703 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
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705 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
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706 ((STATE) == DMA_PINC_DISABLE))
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708 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
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709 ((STATE) == DMA_MINC_DISABLE))
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711 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
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712 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
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713 ((SIZE) == DMA_PDATAALIGN_WORD))
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715 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
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716 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
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717 ((SIZE) == DMA_MDATAALIGN_WORD ))
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719 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
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720 ((MODE) == DMA_CIRCULAR) || \
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721 ((MODE) == DMA_PFCTRL))
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723 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
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724 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
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725 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
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726 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
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728 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
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729 ((STATE) == DMA_FIFOMODE_ENABLE))
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731 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
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732 ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \
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733 ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
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734 ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
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736 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
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737 ((BURST) == DMA_MBURST_INC4) || \
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738 ((BURST) == DMA_MBURST_INC8) || \
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739 ((BURST) == DMA_MBURST_INC16))
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741 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
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742 ((BURST) == DMA_PBURST_INC4) || \
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743 ((BURST) == DMA_PBURST_INC8) || \
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744 ((BURST) == DMA_PBURST_INC16))
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749 /* Private functions ---------------------------------------------------------*/
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750 /** @defgroup DMA_Private_Functions DMA Private Functions
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751 * @brief DMA private functions
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770 #endif /* __STM32F7xx_HAL_DMA_H */
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772 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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