2 ******************************************************************************
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3 * @file stm32f7xx_hal_nand.h
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4 * @author MCD Application Team
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6 * @date 06-March-2015
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7 * @brief Header file of NAND HAL module.
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8 ******************************************************************************
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11 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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13 * Redistribution and use in source and binary forms, with or without modification,
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14 * are permitted provided that the following conditions are met:
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15 * 1. Redistributions of source code must retain the above copyright notice,
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16 * this list of conditions and the following disclaimer.
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17 * 2. Redistributions in binary form must reproduce the above copyright notice,
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18 * this list of conditions and the following disclaimer in the documentation
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19 * and/or other materials provided with the distribution.
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20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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21 * may be used to endorse or promote products derived from this software
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22 * without specific prior written permission.
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24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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35 ******************************************************************************
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38 /* Define to prevent recursive inclusion -------------------------------------*/
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39 #ifndef __STM32F7xx_HAL_NAND_H
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40 #define __STM32F7xx_HAL_NAND_H
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46 /* Includes ------------------------------------------------------------------*/
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47 #include "stm32f7xx_ll_fmc.h"
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49 /** @addtogroup STM32F7xx_HAL_Driver
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53 /** @addtogroup NAND
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57 #if defined(STM32F756xx) || defined(STM32F746xx)
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58 /* Exported typedef ----------------------------------------------------------*/
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59 /* Exported types ------------------------------------------------------------*/
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60 /** @defgroup NAND_Exported_Types NAND Exported Types
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65 * @brief HAL NAND State structures definition
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69 HAL_NAND_STATE_RESET = 0x00, /*!< NAND not yet initialized or disabled */
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70 HAL_NAND_STATE_READY = 0x01, /*!< NAND initialized and ready for use */
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71 HAL_NAND_STATE_BUSY = 0x02, /*!< NAND internal process is ongoing */
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72 HAL_NAND_STATE_ERROR = 0x03 /*!< NAND error state */
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73 }HAL_NAND_StateTypeDef;
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76 * @brief NAND Memory electronic signature Structure definition
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80 /*<! NAND memory electronic signature maker and device IDs */
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92 * @brief NAND Memory address Structure definition
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96 uint16_t Page; /*!< NAND memory Page address */
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98 uint16_t Zone; /*!< NAND memory Zone address */
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100 uint16_t Block; /*!< NAND memory Block address */
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102 }NAND_AddressTypeDef;
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105 * @brief NAND Memory info Structure definition
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109 uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in K. bytes */
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111 uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in K. bytes */
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113 uint32_t BlockSize; /*!< NAND memory block size number of pages */
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115 uint32_t BlockNbr; /*!< NAND memory number of blocks */
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117 uint32_t ZoneSize; /*!< NAND memory zone size measured in number of blocks */
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121 * @brief NAND handle Structure definition
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125 FMC_NAND_TypeDef *Instance; /*!< Register base address */
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127 FMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */
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129 HAL_LockTypeDef Lock; /*!< NAND locking object */
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131 __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */
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133 NAND_InfoTypeDef Info; /*!< NAND characteristic information structure */
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134 }NAND_HandleTypeDef;
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139 /* Exported constants --------------------------------------------------------*/
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140 /* Exported macro ------------------------------------------------------------*/
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141 /** @defgroup NAND_Exported_Macros NAND Exported Macros
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145 /** @brief Reset NAND handle state
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146 * @param __HANDLE__: specifies the NAND handle.
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149 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
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155 /* Exported functions --------------------------------------------------------*/
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156 /** @addtogroup NAND_Exported_Functions NAND Exported Functions
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160 /** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
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164 /* Initialization/de-initialization functions ********************************/
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165 HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
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166 HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
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167 void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
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168 void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
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169 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
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170 void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
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176 /** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
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180 /* IO operation functions ****************************************************/
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181 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
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182 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
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183 HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
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184 HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
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185 HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
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186 HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
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187 HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
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188 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
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189 uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
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195 /** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
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199 /* NAND Control functions ****************************************************/
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200 HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
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201 HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
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202 HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
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208 /** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
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211 /* NAND State functions *******************************************************/
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212 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
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213 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
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221 /* Private types -------------------------------------------------------------*/
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222 /* Private variables ---------------------------------------------------------*/
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223 /* Private constants ---------------------------------------------------------*/
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224 /** @defgroup NAND_Private_Constants NAND Private Constants
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227 #define NAND_DEVICE ((uint32_t)0x80000000)
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228 #define NAND_WRITE_TIMEOUT ((uint32_t)0x01000000)
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230 #define CMD_AREA ((uint32_t)(1<<16)) /* A16 = CLE high */
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231 #define ADDR_AREA ((uint32_t)(1<<17)) /* A17 = ALE high */
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233 #define NAND_CMD_AREA_A ((uint8_t)0x00)
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234 #define NAND_CMD_AREA_B ((uint8_t)0x01)
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235 #define NAND_CMD_AREA_C ((uint8_t)0x50)
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236 #define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)
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238 #define NAND_CMD_WRITE0 ((uint8_t)0x80)
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239 #define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
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240 #define NAND_CMD_ERASE0 ((uint8_t)0x60)
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241 #define NAND_CMD_ERASE1 ((uint8_t)0xD0)
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242 #define NAND_CMD_READID ((uint8_t)0x90)
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243 #define NAND_CMD_STATUS ((uint8_t)0x70)
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244 #define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
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245 #define NAND_CMD_RESET ((uint8_t)0xFF)
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247 /* NAND memory status */
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248 #define NAND_VALID_ADDRESS ((uint32_t)0x00000100)
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249 #define NAND_INVALID_ADDRESS ((uint32_t)0x00000200)
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250 #define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400)
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251 #define NAND_BUSY ((uint32_t)0x00000000)
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252 #define NAND_ERROR ((uint32_t)0x00000001)
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253 #define NAND_READY ((uint32_t)0x00000040)
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258 /* Private macros ------------------------------------------------------------*/
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259 /** @defgroup NAND_Private_Macros NAND Private Macros
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264 * @brief NAND memory address computation.
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265 * @param __ADDRESS__: NAND memory address.
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266 * @param __HANDLE__ : NAND handle.
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267 * @retval NAND Raw address value
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269 #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
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270 (((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.ZoneSize)))* ((__HANDLE__)->Info.BlockSize)))
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273 * @brief NAND memory address cycling.
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274 * @param __ADDRESS__: NAND memory address.
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275 * @retval NAND address cycling value.
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277 #define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
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278 #define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */
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279 #define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */
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280 #define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */
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284 #endif /* STM32F756xx || STM32F746xx */
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301 #endif /* __STM32F7xx_HAL_NAND_H */
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303 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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