2 ******************************************************************************
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3 * @file stm32f7xx_hal_tim.h
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4 * @author MCD Application Team
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6 * @date 06-March-2015
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7 * @brief Header file of TIM HAL module.
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8 ******************************************************************************
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11 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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13 * Redistribution and use in source and binary forms, with or without modification,
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14 * are permitted provided that the following conditions are met:
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15 * 1. Redistributions of source code must retain the above copyright notice,
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16 * this list of conditions and the following disclaimer.
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17 * 2. Redistributions in binary form must reproduce the above copyright notice,
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18 * this list of conditions and the following disclaimer in the documentation
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19 * and/or other materials provided with the distribution.
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20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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21 * may be used to endorse or promote products derived from this software
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22 * without specific prior written permission.
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24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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35 ******************************************************************************
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38 /* Define to prevent recursive inclusion -------------------------------------*/
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39 #ifndef __STM32F7xx_HAL_TIM_H
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40 #define __STM32F7xx_HAL_TIM_H
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46 /* Includes ------------------------------------------------------------------*/
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47 #include "stm32f7xx_hal_def.h"
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49 /** @addtogroup STM32F7xx_HAL_Driver
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57 /* Exported types ------------------------------------------------------------*/
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58 /** @defgroup TIM_Exported_Types TIM Exported Types
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63 * @brief TIM Time base Configuration Structure definition
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67 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
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68 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
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70 uint32_t CounterMode; /*!< Specifies the counter mode.
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71 This parameter can be a value of @ref TIM_Counter_Mode */
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73 uint32_t Period; /*!< Specifies the period value to be loaded into the active
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74 Auto-Reload Register at the next update event.
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75 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
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77 uint32_t ClockDivision; /*!< Specifies the clock division.
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78 This parameter can be a value of @ref TIM_ClockDivision */
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80 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
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81 reaches zero, an update event is generated and counting restarts
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82 from the RCR value (N).
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83 This means in PWM mode that (N+1) corresponds to:
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84 - the number of PWM periods in edge-aligned mode
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85 - the number of half PWM period in center-aligned mode
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86 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
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87 @note This parameter is valid only for TIM1 and TIM8. */
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88 } TIM_Base_InitTypeDef;
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91 * @brief TIM Output Compare Configuration Structure definition
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96 uint32_t OCMode; /*!< Specifies the TIM mode.
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97 This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */
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99 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
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100 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
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102 uint32_t OCPolarity; /*!< Specifies the output polarity.
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103 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
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105 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
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106 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
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107 @note This parameter is valid only for TIM1 and TIM8. */
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109 uint32_t OCFastMode; /*!< Specifies the Fast mode state.
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110 This parameter can be a value of @ref TIM_Output_Fast_State
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111 @note This parameter is valid only in PWM1 and PWM2 mode. */
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114 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
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115 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
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116 @note This parameter is valid only for TIM1 and TIM8. */
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118 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
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119 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
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120 @note This parameter is valid only for TIM1 and TIM8. */
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121 } TIM_OC_InitTypeDef;
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124 * @brief TIM One Pulse Mode Configuration Structure definition
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128 uint32_t OCMode; /*!< Specifies the TIM mode.
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129 This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */
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131 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
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132 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
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134 uint32_t OCPolarity; /*!< Specifies the output polarity.
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135 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
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137 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
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138 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
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139 @note This parameter is valid only for TIM1 and TIM8. */
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141 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
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142 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
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143 @note This parameter is valid only for TIM1 and TIM8. */
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145 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
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146 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
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147 @note This parameter is valid only for TIM1 and TIM8. */
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149 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
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150 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
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152 uint32_t ICSelection; /*!< Specifies the input.
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153 This parameter can be a value of @ref TIM_Input_Capture_Selection */
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155 uint32_t ICFilter; /*!< Specifies the input capture filter.
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156 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
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157 } TIM_OnePulse_InitTypeDef;
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161 * @brief TIM Input Capture Configuration Structure definition
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166 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
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167 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
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169 uint32_t ICSelection; /*!< Specifies the input.
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170 This parameter can be a value of @ref TIM_Input_Capture_Selection */
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172 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
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173 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
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175 uint32_t ICFilter; /*!< Specifies the input capture filter.
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176 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
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177 } TIM_IC_InitTypeDef;
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180 * @brief TIM Encoder Configuration Structure definition
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185 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
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186 This parameter can be a value of @ref TIM_Encoder_Mode */
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188 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
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189 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
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191 uint32_t IC1Selection; /*!< Specifies the input.
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192 This parameter can be a value of @ref TIM_Input_Capture_Selection */
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194 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
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195 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
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197 uint32_t IC1Filter; /*!< Specifies the input capture filter.
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198 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
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200 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
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201 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
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203 uint32_t IC2Selection; /*!< Specifies the input.
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204 This parameter can be a value of @ref TIM_Input_Capture_Selection */
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206 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
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207 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
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209 uint32_t IC2Filter; /*!< Specifies the input capture filter.
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210 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
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211 } TIM_Encoder_InitTypeDef;
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214 * @brief Clock Configuration Handle Structure definition
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218 uint32_t ClockSource; /*!< TIM clock sources.
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219 This parameter can be a value of @ref TIM_Clock_Source */
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220 uint32_t ClockPolarity; /*!< TIM clock polarity.
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221 This parameter can be a value of @ref TIM_Clock_Polarity */
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222 uint32_t ClockPrescaler; /*!< TIM clock prescaler.
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223 This parameter can be a value of @ref TIM_Clock_Prescaler */
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224 uint32_t ClockFilter; /*!< TIM clock filter.
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225 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
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226 }TIM_ClockConfigTypeDef;
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229 * @brief Clear Input Configuration Handle Structure definition
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233 uint32_t ClearInputState; /*!< TIM clear Input state.
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234 This parameter can be ENABLE or DISABLE */
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235 uint32_t ClearInputSource; /*!< TIM clear Input sources.
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236 This parameter can be a value of @ref TIMEx_ClearInput_Source */
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237 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity.
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238 This parameter can be a value of @ref TIM_ClearInput_Polarity */
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239 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler.
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240 This parameter can be a value of @ref TIM_ClearInput_Prescaler */
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241 uint32_t ClearInputFilter; /*!< TIM Clear Input filter.
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242 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
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243 }TIM_ClearInputConfigTypeDef;
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246 * @brief TIM Slave configuration Structure definition
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249 uint32_t SlaveMode; /*!< Slave mode selection
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250 This parameter can be a value of @ref TIMEx_Slave_Mode */
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251 uint32_t InputTrigger; /*!< Input Trigger source
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252 This parameter can be a value of @ref TIM_Trigger_Selection */
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253 uint32_t TriggerPolarity; /*!< Input Trigger polarity
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254 This parameter can be a value of @ref TIM_Trigger_Polarity */
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255 uint32_t TriggerPrescaler; /*!< Input trigger prescaler
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256 This parameter can be a value of @ref TIM_Trigger_Prescaler */
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257 uint32_t TriggerFilter; /*!< Input trigger filter
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258 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
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260 }TIM_SlaveConfigTypeDef;
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263 * @brief HAL State structures definition
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267 HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */
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268 HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
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269 HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
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270 HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */
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271 HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
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272 }HAL_TIM_StateTypeDef;
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275 * @brief HAL Active channel structures definition
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279 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */
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280 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */
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281 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */
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282 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */
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283 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */
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284 }HAL_TIM_ActiveChannel;
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287 * @brief TIM Time Base Handle Structure definition
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291 TIM_TypeDef *Instance; /*!< Register base address */
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292 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
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293 HAL_TIM_ActiveChannel Channel; /*!< Active channel */
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294 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
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295 This array is accessed by a @ref DMA_Handle_index */
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296 HAL_LockTypeDef Lock; /*!< Locking object */
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297 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
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298 }TIM_HandleTypeDef;
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303 /* Exported constants --------------------------------------------------------*/
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304 /** @defgroup TIM_Exported_Constants TIM Exported Constants
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308 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
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311 #define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */
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312 #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */
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313 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
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318 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity
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321 #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
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322 #define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */
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327 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
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330 #define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */
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331 #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */
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332 #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */
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333 #define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */
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338 /** @defgroup TIM_Counter_Mode TIM Counter Mode
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341 #define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
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342 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
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343 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
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344 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
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345 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
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350 /** @defgroup TIM_ClockDivision TIM Clock Division
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353 #define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
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354 #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
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355 #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
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360 /** @defgroup TIM_Output_Compare_State TIM Output Compare State
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363 #define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
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364 #define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
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370 /** @defgroup TIM_Output_Fast_State TIM Output Fast State
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373 #define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
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374 #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
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379 /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
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382 #define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
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383 #define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
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388 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
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391 #define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
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392 #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
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397 /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
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400 #define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)
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401 #define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
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406 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
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409 #define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
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410 #define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)
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415 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Output Compare N Idle State
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418 #define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
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419 #define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)
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424 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
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427 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
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428 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
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429 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
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434 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
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437 #define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
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438 connected to IC1, IC2, IC3 or IC4, respectively */
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439 #define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
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440 connected to IC2, IC1, IC4 or IC3, respectively */
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441 #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
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447 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
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450 #define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */
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451 #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */
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452 #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */
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453 #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */
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458 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
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461 #define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
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462 #define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
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467 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode
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470 #define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
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471 #define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
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472 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
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478 /** @defgroup TIM_Interrupt_definition TIM Interrupt definition
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481 #define TIM_IT_UPDATE (TIM_DIER_UIE)
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482 #define TIM_IT_CC1 (TIM_DIER_CC1IE)
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483 #define TIM_IT_CC2 (TIM_DIER_CC2IE)
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484 #define TIM_IT_CC3 (TIM_DIER_CC3IE)
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485 #define TIM_IT_CC4 (TIM_DIER_CC4IE)
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486 #define TIM_IT_COM (TIM_DIER_COMIE)
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487 #define TIM_IT_TRIGGER (TIM_DIER_TIE)
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488 #define TIM_IT_BREAK (TIM_DIER_BIE)
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493 /** @defgroup TIM_Commutation_Source TIM Commutation Source
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496 #define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
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497 #define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)
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502 /** @defgroup TIM_DMA_sources TIM DMA sources
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505 #define TIM_DMA_UPDATE (TIM_DIER_UDE)
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506 #define TIM_DMA_CC1 (TIM_DIER_CC1DE)
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507 #define TIM_DMA_CC2 (TIM_DIER_CC2DE)
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508 #define TIM_DMA_CC3 (TIM_DIER_CC3DE)
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509 #define TIM_DMA_CC4 (TIM_DIER_CC4DE)
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510 #define TIM_DMA_COM (TIM_DIER_COMDE)
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511 #define TIM_DMA_TRIGGER (TIM_DIER_TDE)
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516 /** @defgroup TIM_Event_Source TIM Event Source
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519 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
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520 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
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521 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
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522 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
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523 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
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524 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG
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525 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
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526 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG
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527 #define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G
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532 /** @defgroup TIM_Flag_definition TIM Flag definition
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535 #define TIM_FLAG_UPDATE (TIM_SR_UIF)
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536 #define TIM_FLAG_CC1 (TIM_SR_CC1IF)
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537 #define TIM_FLAG_CC2 (TIM_SR_CC2IF)
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538 #define TIM_FLAG_CC3 (TIM_SR_CC3IF)
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539 #define TIM_FLAG_CC4 (TIM_SR_CC4IF)
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540 #define TIM_FLAG_COM (TIM_SR_COMIF)
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541 #define TIM_FLAG_TRIGGER (TIM_SR_TIF)
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542 #define TIM_FLAG_BREAK (TIM_SR_BIF)
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543 #define TIM_FLAG_BREAK2 (TIM_SR_B2IF)
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544 #define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
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545 #define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
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546 #define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
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547 #define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
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552 /** @defgroup TIM_Clock_Source TIM Clock Source
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555 #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
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556 #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
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557 #define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
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558 #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
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559 #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
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560 #define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
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561 #define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
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562 #define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
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563 #define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
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564 #define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
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569 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity
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572 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
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573 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
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574 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
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575 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
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576 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
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581 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
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584 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
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585 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
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586 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
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587 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
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592 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
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595 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
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596 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
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601 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
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604 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
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605 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
\r
606 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
\r
607 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
\r
612 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
\r
615 #define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
\r
616 #define TIM_OSSR_DISABLE ((uint32_t)0x0000)
\r
621 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
\r
624 #define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
\r
625 #define TIM_OSSI_DISABLE ((uint32_t)0x0000)
\r
630 /** @defgroup TIM_Lock_level TIM Lock level
\r
633 #define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
\r
634 #define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
\r
635 #define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
\r
636 #define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
\r
640 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input State
\r
643 #define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
\r
644 #define TIM_BREAK_DISABLE ((uint32_t)0x0000)
\r
649 /** @defgroup TIM_Break_Polarity TIM Break Polarity
\r
652 #define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
\r
653 #define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
\r
658 /** @defgroup TIM_AOE_Bit_Set_Reset TIM AOE Bit State
\r
661 #define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
\r
662 #define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
\r
667 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
\r
670 #define TIM_TRGO_RESET ((uint32_t)0x0000)
\r
671 #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
\r
672 #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
\r
673 #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
\r
674 #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
\r
675 #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
\r
676 #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
\r
677 #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
\r
682 /** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
\r
685 #define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
\r
686 #define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
\r
691 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection
\r
694 #define TIM_TS_ITR0 ((uint32_t)0x0000)
\r
695 #define TIM_TS_ITR1 ((uint32_t)0x0010)
\r
696 #define TIM_TS_ITR2 ((uint32_t)0x0020)
\r
697 #define TIM_TS_ITR3 ((uint32_t)0x0030)
\r
698 #define TIM_TS_TI1F_ED ((uint32_t)0x0040)
\r
699 #define TIM_TS_TI1FP1 ((uint32_t)0x0050)
\r
700 #define TIM_TS_TI2FP2 ((uint32_t)0x0060)
\r
701 #define TIM_TS_ETRF ((uint32_t)0x0070)
\r
702 #define TIM_TS_NONE ((uint32_t)0xFFFF)
\r
707 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
\r
710 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
\r
711 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
\r
712 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
\r
713 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
\r
714 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
\r
719 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
\r
722 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
\r
723 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
\r
724 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
\r
725 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
\r
731 /** @defgroup TIM_TI1_Selection TIM TI1 Selection
\r
734 #define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
\r
735 #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
\r
740 /** @defgroup TIM_DMA_Base_address TIM DMA Base address
\r
743 #define TIM_DMABASE_CR1 (0x00000000)
\r
744 #define TIM_DMABASE_CR2 (0x00000001)
\r
745 #define TIM_DMABASE_SMCR (0x00000002)
\r
746 #define TIM_DMABASE_DIER (0x00000003)
\r
747 #define TIM_DMABASE_SR (0x00000004)
\r
748 #define TIM_DMABASE_EGR (0x00000005)
\r
749 #define TIM_DMABASE_CCMR1 (0x00000006)
\r
750 #define TIM_DMABASE_CCMR2 (0x00000007)
\r
751 #define TIM_DMABASE_CCER (0x00000008)
\r
752 #define TIM_DMABASE_CNT (0x00000009)
\r
753 #define TIM_DMABASE_PSC (0x0000000A)
\r
754 #define TIM_DMABASE_ARR (0x0000000B)
\r
755 #define TIM_DMABASE_RCR (0x0000000C)
\r
756 #define TIM_DMABASE_CCR1 (0x0000000D)
\r
757 #define TIM_DMABASE_CCR2 (0x0000000E)
\r
758 #define TIM_DMABASE_CCR3 (0x0000000F)
\r
759 #define TIM_DMABASE_CCR4 (0x00000010)
\r
760 #define TIM_DMABASE_BDTR (0x00000011)
\r
761 #define TIM_DMABASE_DCR (0x00000012)
\r
762 #define TIM_DMABASE_OR (0x00000013)
\r
767 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
\r
770 #define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000)
\r
771 #define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100)
\r
772 #define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200)
\r
773 #define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300)
\r
774 #define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400)
\r
775 #define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500)
\r
776 #define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600)
\r
777 #define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700)
\r
778 #define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800)
\r
779 #define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900)
\r
780 #define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00)
\r
781 #define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00)
\r
782 #define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00)
\r
783 #define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00)
\r
784 #define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00)
\r
785 #define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00)
\r
786 #define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000)
\r
787 #define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100)
\r
792 /** @defgroup DMA_Handle_index DMA Handle index
\r
795 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */
\r
796 #define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
\r
797 #define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
\r
798 #define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
\r
799 #define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
\r
800 #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /*!< Index of the DMA handle used for Commutation DMA requests */
\r
801 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /*!< Index of the DMA handle used for Trigger DMA requests */
\r
806 /** @defgroup Channel_CC_State Channel CC State
\r
809 #define TIM_CCx_ENABLE ((uint32_t)0x0001)
\r
810 #define TIM_CCx_DISABLE ((uint32_t)0x0000)
\r
811 #define TIM_CCxN_ENABLE ((uint32_t)0x0004)
\r
812 #define TIM_CCxN_DISABLE ((uint32_t)0x0000)
\r
821 /* Exported macro ------------------------------------------------------------*/
\r
822 /** @defgroup TIM_Exported_Macros TIM Exported Macros
\r
825 /** @brief Reset TIM handle state
\r
826 * @param __HANDLE__: TIM handle
\r
829 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
\r
832 * @brief Enable the TIM peripheral.
\r
833 * @param __HANDLE__: TIM handle
\r
836 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
\r
839 * @brief Enable the TIM update source request.
\r
840 * @param __HANDLE__: TIM handle
\r
843 #define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_URS))
\r
846 * @brief Enable the TIM main Output.
\r
847 * @param __HANDLE__: TIM handle
\r
850 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
\r
853 /* The counter of a timer instance is disabled only if all the CCx and CCxN
\r
854 channels have been disabled */
\r
855 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
\r
856 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
\r
859 * @brief Disable the TIM peripheral.
\r
860 * @param __HANDLE__: TIM handle
\r
863 #define __HAL_TIM_DISABLE(__HANDLE__) \
\r
865 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
\r
867 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
\r
869 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
\r
875 * @brief Disable the TIM update source request.
\r
876 * @param __HANDLE__: TIM handle
\r
879 #define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
\r
882 /* The Main Output of a timer instance is disabled only if all the CCx and CCxN
\r
883 channels have been disabled */
\r
885 * @brief Disable the TIM main Output.
\r
886 * @param __HANDLE__: TIM handle
\r
889 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
\r
891 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
\r
893 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
\r
895 (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
\r
900 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
\r
901 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
\r
902 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
\r
903 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
\r
904 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
\r
905 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
\r
907 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
\r
908 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
\r
910 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
\r
911 #define __HAL_TIM_SET_PRESCALER (__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
\r
913 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
\r
914 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
\r
915 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\
\r
916 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
\r
917 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))
\r
919 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
\r
920 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
\r
921 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
\r
922 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
\r
923 ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
\r
925 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
\r
926 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
\r
927 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\
\r
928 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\
\r
929 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12) & TIM_CCER_CC4P)))
\r
931 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
\r
932 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
\r
933 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
\r
934 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
\r
935 ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
\r
938 * @brief Sets the TIM Counter Register value on runtime.
\r
939 * @param __HANDLE__: TIM handle.
\r
940 * @param __COUNTER__: specifies the Counter register new value.
\r
943 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
\r
946 * @brief Gets the TIM Counter Register value on runtime.
\r
947 * @param __HANDLE__: TIM handle.
\r
950 #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
\r
953 * @brief Sets the TIM Autoreload Register value on runtime without calling
\r
954 * another time any Init function.
\r
955 * @param __HANDLE__: TIM handle.
\r
956 * @param __AUTORELOAD__: specifies the Counter register new value.
\r
959 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
\r
961 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
\r
962 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
\r
965 * @brief Gets the TIM Autoreload Register value on runtime
\r
966 * @param __HANDLE__: TIM handle.
\r
969 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
\r
972 * @brief Sets the TIM Clock Division value on runtime without calling
\r
973 * another time any Init function.
\r
974 * @param __HANDLE__: TIM handle.
\r
975 * @param __CKD__: specifies the clock division value.
\r
976 * This parameter can be one of the following value:
\r
977 * @arg TIM_CLOCKDIVISION_DIV1
\r
978 * @arg TIM_CLOCKDIVISION_DIV2
\r
979 * @arg TIM_CLOCKDIVISION_DIV4
\r
982 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
\r
984 (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
\r
985 (__HANDLE__)->Instance->CR1 |= (__CKD__); \
\r
986 (__HANDLE__)->Init.ClockDivision = (__CKD__); \
\r
989 * @brief Gets the TIM Clock Division value on runtime
\r
990 * @param __HANDLE__: TIM handle.
\r
993 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
\r
996 * @brief Sets the TIM Input Capture prescaler on runtime without calling
\r
997 * another time HAL_TIM_IC_ConfigChannel() function.
\r
998 * @param __HANDLE__: TIM handle.
\r
999 * @param __CHANNEL__ : TIM Channels to be configured.
\r
1000 * This parameter can be one of the following values:
\r
1001 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
1002 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
1003 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
\r
1004 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
\r
1005 * @param __ICPSC__: specifies the Input Capture4 prescaler new value.
\r
1006 * This parameter can be one of the following values:
\r
1007 * @arg TIM_ICPSC_DIV1: no prescaler
\r
1008 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
\r
1009 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
\r
1010 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
\r
1013 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
\r
1015 TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
\r
1016 TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
\r
1020 * @brief Gets the TIM Input Capture prescaler on runtime
\r
1021 * @param __HANDLE__: TIM handle.
\r
1022 * @param __CHANNEL__ : TIM Channels to be configured.
\r
1023 * This parameter can be one of the following values:
\r
1024 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
\r
1025 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
\r
1026 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
\r
1027 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
\r
1030 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
\r
1031 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
\r
1032 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
\r
1033 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
\r
1034 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
\r
1037 * @brief Sets the TIM Capture x input polarity on runtime.
\r
1038 * @param __HANDLE__: TIM handle.
\r
1039 * @param __CHANNEL__: TIM Channels to be configured.
\r
1040 * This parameter can be one of the following values:
\r
1041 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
1042 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
1043 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
\r
1044 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
\r
1045 * @param __POLARITY__: Polarity for TIx source
\r
1046 * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
\r
1047 * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
\r
1048 * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
\r
1049 * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4.
\r
1052 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
\r
1054 TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
\r
1055 TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
\r
1062 /* Include TIM HAL Extension module */
\r
1063 #include "stm32f7xx_hal_tim_ex.h"
\r
1065 /* Exported functions --------------------------------------------------------*/
\r
1066 /** @addtogroup TIM_Exported_Functions
\r
1070 /** @addtogroup TIM_Exported_Functions_Group1
\r
1074 /* Time Base functions ********************************************************/
\r
1075 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
\r
1076 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
\r
1077 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
\r
1078 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
\r
1079 /* Blocking mode: Polling */
\r
1080 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
\r
1081 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
\r
1082 /* Non-Blocking mode: Interrupt */
\r
1083 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
\r
1084 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
\r
1085 /* Non-Blocking mode: DMA */
\r
1086 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
\r
1087 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
\r
1092 /** @addtogroup TIM_Exported_Functions_Group2
\r
1095 /* Timer Output Compare functions **********************************************/
\r
1096 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
\r
1097 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
\r
1098 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
\r
1099 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
\r
1100 /* Blocking mode: Polling */
\r
1101 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1102 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1103 /* Non-Blocking mode: Interrupt */
\r
1104 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1105 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1106 /* Non-Blocking mode: DMA */
\r
1107 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
\r
1108 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1114 /** @addtogroup TIM_Exported_Functions_Group3
\r
1117 /* Timer PWM functions *********************************************************/
\r
1118 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
\r
1119 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
\r
1120 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
\r
1121 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
\r
1122 /* Blocking mode: Polling */
\r
1123 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1124 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1125 /* Non-Blocking mode: Interrupt */
\r
1126 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1127 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1128 /* Non-Blocking mode: DMA */
\r
1129 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
\r
1130 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1136 /** @addtogroup TIM_Exported_Functions_Group4
\r
1139 /* Timer Input Capture functions ***********************************************/
\r
1140 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
\r
1141 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
\r
1142 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
\r
1143 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
\r
1144 /* Blocking mode: Polling */
\r
1145 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1146 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1147 /* Non-Blocking mode: Interrupt */
\r
1148 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1149 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1150 /* Non-Blocking mode: DMA */
\r
1151 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
\r
1152 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1158 /** @addtogroup TIM_Exported_Functions_Group5
\r
1161 /* Timer One Pulse functions ***************************************************/
\r
1162 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
\r
1163 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
\r
1164 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
\r
1165 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
\r
1166 /* Blocking mode: Polling */
\r
1167 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
\r
1168 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
\r
1170 /* Non-Blocking mode: Interrupt */
\r
1171 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
\r
1172 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
\r
1178 /** @addtogroup TIM_Exported_Functions_Group6
\r
1181 /* Timer Encoder functions *****************************************************/
\r
1182 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig);
\r
1183 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
\r
1184 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
\r
1185 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
\r
1186 /* Blocking mode: Polling */
\r
1187 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1188 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1189 /* Non-Blocking mode: Interrupt */
\r
1190 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1191 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1192 /* Non-Blocking mode: DMA */
\r
1193 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
\r
1194 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1200 /** @addtogroup TIM_Exported_Functions_Group7
\r
1203 /* Interrupt Handler functions **********************************************/
\r
1204 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
\r
1210 /** @addtogroup TIM_Exported_Functions_Group8
\r
1213 /* Control functions *********************************************************/
\r
1214 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
\r
1215 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
\r
1216 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
\r
1217 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel);
\r
1218 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
\r
1219 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
\r
1220 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
\r
1221 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
\r
1222 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
\r
1223 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
\r
1224 uint32_t *BurstBuffer, uint32_t BurstLength);
\r
1225 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
\r
1226 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
\r
1227 uint32_t *BurstBuffer, uint32_t BurstLength);
\r
1228 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
\r
1229 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
\r
1230 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1236 /** @addtogroup TIM_Exported_Functions_Group9
\r
1239 /* Callback in non blocking modes (Interrupt and DMA) *************************/
\r
1240 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
\r
1241 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
\r
1242 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
\r
1243 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
\r
1244 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
\r
1245 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
\r
1251 /** @addtogroup TIM_Exported_Functions_Group10
\r
1254 /* Peripheral State functions **************************************************/
\r
1255 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
\r
1256 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
\r
1257 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
\r
1258 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
\r
1259 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
\r
1260 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
\r
1270 /* Private macros ------------------------------------------------------------*/
\r
1271 /** @defgroup TIM_Private_Macros TIM Private Macros
\r
1275 /** @defgroup TIM_IS_TIM_Definitions TIM Private macros to check input parameters
\r
1278 #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \
\r
1279 ((__MODE__) == TIM_COUNTERMODE_DOWN) || \
\r
1280 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \
\r
1281 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \
\r
1282 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
\r
1284 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
\r
1285 ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
\r
1286 ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
\r
1288 #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \
\r
1289 ((__STATE__) == TIM_OCFAST_ENABLE))
\r
1291 #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \
\r
1292 ((STATE) == TIM_OUTPUTSTATE_ENABLE))
\r
1294 #define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \
\r
1295 ((STATE) == TIM_OUTPUTNSTATE_ENABLE))
\r
1297 #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
\r
1298 ((__POLARITY__) == TIM_OCPOLARITY_LOW))
\r
1300 #define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
\r
1301 ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
\r
1303 #define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \
\r
1304 ((__STATE__) == TIM_OCIDLESTATE_RESET))
\r
1306 #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
\r
1307 ((__STATE__) == TIM_OCNIDLESTATE_RESET))
\r
1309 #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
\r
1310 ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
\r
1311 ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
\r
1313 #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
\r
1314 ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
\r
1315 ((__SELECTION__) == TIM_ICSELECTION_TRC))
\r
1317 #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
\r
1318 ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
\r
1319 ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
\r
1320 ((__PRESCALER__) == TIM_ICPSC_DIV8))
\r
1322 #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \
\r
1323 ((__MODE__) == TIM_OPMODE_REPETITIVE))
\r
1325 #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \
\r
1326 ((__MODE__) == TIM_ENCODERMODE_TI2) || \
\r
1327 ((__MODE__) == TIM_ENCODERMODE_TI12))
\r
1329 #define IS_TIM_IT(__IT__) ((((__IT__) & 0xFFFFFF00) == 0x00000000) && ((__IT__) != 0x00000000))
\r
1332 #define IS_TIM_GET_IT(__IT__) (((__IT__) == TIM_IT_UPDATE) || \
\r
1333 ((__IT__) == TIM_IT_CC1) || \
\r
1334 ((__IT__) == TIM_IT_CC2) || \
\r
1335 ((__IT__) == TIM_IT_CC3) || \
\r
1336 ((__IT__) == TIM_IT_CC4) || \
\r
1337 ((__IT__) == TIM_IT_COM) || \
\r
1338 ((__IT__) == TIM_IT_TRIGGER) || \
\r
1339 ((__IT__) == TIM_IT_BREAK))
\r
1341 #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FF) == 0x00000000) && ((__SOURCE__) != 0x00000000))
\r
1343 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00) == 0x00000000) && ((__SOURCE__) != 0x00000000))
\r
1345 #define IS_TIM_FLAG(__FLAG__) (((__FLAG__) == TIM_FLAG_UPDATE) || \
\r
1346 ((__FLAG__) == TIM_FLAG_CC1) || \
\r
1347 ((__FLAG__) == TIM_FLAG_CC2) || \
\r
1348 ((__FLAG__) == TIM_FLAG_CC3) || \
\r
1349 ((__FLAG__) == TIM_FLAG_CC4) || \
\r
1350 ((__FLAG__) == TIM_FLAG_COM) || \
\r
1351 ((__FLAG__) == TIM_FLAG_TRIGGER) || \
\r
1352 ((__FLAG__) == TIM_FLAG_BREAK) || \
\r
1353 ((__FLAG__) == TIM_FLAG_BREAK2) || \
\r
1354 ((__FLAG__) == TIM_FLAG_CC1OF) || \
\r
1355 ((__FLAG__) == TIM_FLAG_CC2OF) || \
\r
1356 ((__FLAG__) == TIM_FLAG_CC3OF) || \
\r
1357 ((__FLAG__) == TIM_FLAG_CC4OF))
\r
1359 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
\r
1360 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
\r
1361 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
\r
1362 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
\r
1363 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
\r
1364 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
\r
1365 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
\r
1366 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
\r
1367 ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
\r
1368 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
\r
1370 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \
\r
1371 ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
\r
1372 ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \
\r
1373 ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \
\r
1374 ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
\r
1376 #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
\r
1377 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
\r
1378 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
\r
1379 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
\r
1381 #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
\r
1383 #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
\r
1384 ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
\r
1386 #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
\r
1387 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
\r
1388 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
\r
1389 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
\r
1391 #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
\r
1393 #define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \
\r
1394 ((__STATE__) == TIM_OSSR_DISABLE))
\r
1396 #define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \
\r
1397 ((__STATE__) == TIM_OSSI_DISABLE))
\r
1399 #define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
\r
1400 ((__LEVEL__) == TIM_LOCKLEVEL_1) || \
\r
1401 ((__LEVEL__) == TIM_LOCKLEVEL_2) || \
\r
1402 ((__LEVEL__) == TIM_LOCKLEVEL_3))
\r
1404 #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \
\r
1405 ((__STATE__) == TIM_BREAK_DISABLE))
\r
1407 #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
\r
1408 ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
\r
1410 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
\r
1411 ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
\r
1413 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \
\r
1414 ((__SOURCE__) == TIM_TRGO_ENABLE) || \
\r
1415 ((__SOURCE__) == TIM_TRGO_UPDATE) || \
\r
1416 ((__SOURCE__) == TIM_TRGO_OC1) || \
\r
1417 ((__SOURCE__) == TIM_TRGO_OC1REF) || \
\r
1418 ((__SOURCE__) == TIM_TRGO_OC2REF) || \
\r
1419 ((__SOURCE__) == TIM_TRGO_OC3REF) || \
\r
1420 ((__SOURCE__) == TIM_TRGO_OC4REF))
\r
1422 #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
\r
1423 ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
\r
1425 #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
\r
1426 ((__SELECTION__) == TIM_TS_ITR1) || \
\r
1427 ((__SELECTION__) == TIM_TS_ITR2) || \
\r
1428 ((__SELECTION__) == TIM_TS_ITR3) || \
\r
1429 ((__SELECTION__) == TIM_TS_TI1F_ED) || \
\r
1430 ((__SELECTION__) == TIM_TS_TI1FP1) || \
\r
1431 ((__SELECTION__) == TIM_TS_TI2FP2) || \
\r
1432 ((__SELECTION__) == TIM_TS_ETRF))
\r
1434 #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
\r
1435 ((SELECTION) == TIM_TS_ITR1) || \
\r
1436 ((SELECTION) == TIM_TS_ITR2) || \
\r
1437 ((SELECTION) == TIM_TS_ITR3))
\r
1439 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
\r
1440 ((__SELECTION__) == TIM_TS_ITR1) || \
\r
1441 ((__SELECTION__) == TIM_TS_ITR2) || \
\r
1442 ((__SELECTION__) == TIM_TS_ITR3) || \
\r
1443 ((__SELECTION__) == TIM_TS_NONE))
\r
1445 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \
\r
1446 ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
\r
1447 ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \
\r
1448 ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \
\r
1449 ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
\r
1451 #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
\r
1452 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
\r
1453 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
\r
1454 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
\r
1456 #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
\r
1458 #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
\r
1459 ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
\r
1461 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \
\r
1462 ((__BASE__) == TIM_DMABASE_CR2) || \
\r
1463 ((__BASE__) == TIM_DMABASE_SMCR) || \
\r
1464 ((__BASE__) == TIM_DMABASE_DIER) || \
\r
1465 ((__BASE__) == TIM_DMABASE_SR) || \
\r
1466 ((__BASE__) == TIM_DMABASE_EGR) || \
\r
1467 ((__BASE__) == TIM_DMABASE_CCMR1) || \
\r
1468 ((__BASE__) == TIM_DMABASE_CCMR2) || \
\r
1469 ((__BASE__) == TIM_DMABASE_CCER) || \
\r
1470 ((__BASE__) == TIM_DMABASE_CNT) || \
\r
1471 ((__BASE__) == TIM_DMABASE_PSC) || \
\r
1472 ((__BASE__) == TIM_DMABASE_ARR) || \
\r
1473 ((__BASE__) == TIM_DMABASE_RCR) || \
\r
1474 ((__BASE__) == TIM_DMABASE_CCR1) || \
\r
1475 ((__BASE__) == TIM_DMABASE_CCR2) || \
\r
1476 ((__BASE__) == TIM_DMABASE_CCR3) || \
\r
1477 ((__BASE__) == TIM_DMABASE_CCR4) || \
\r
1478 ((__BASE__) == TIM_DMABASE_BDTR) || \
\r
1479 ((__BASE__) == TIM_DMABASE_DCR) || \
\r
1480 ((__BASE__) == TIM_DMABASE_OR))
\r
1482 #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
\r
1483 ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
\r
1484 ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
\r
1485 ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
\r
1486 ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
\r
1487 ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
\r
1488 ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
\r
1489 ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
\r
1490 ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
\r
1491 ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
\r
1492 ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
\r
1493 ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
\r
1494 ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
\r
1495 ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
\r
1496 ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
\r
1497 ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
\r
1498 ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
\r
1499 ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
\r
1501 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
\r
1512 /* Private functions ---------------------------------------------------------*/
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1513 /** @defgroup TIM_Private_Functions TIM Private Functions
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1516 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
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1517 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
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1518 void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
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1519 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
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1520 void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
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1521 void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
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1522 void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
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1524 void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
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1525 void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma);
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1526 void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
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1527 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
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1540 #ifdef __cplusplus
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1544 #endif /* __STM32F7xx_HAL_TIM_H */
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1546 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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