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   1 /**\r
   2   ******************************************************************************\r
   3   * @file    stm32f7xx_ll_sdmmc.h\r
   4   * @author  MCD Application Team\r
   5   * @version V0.3.0\r
   6   * @date    06-March-2015\r
   7   * @brief   Header file of SDMMC HAL module.\r
   8   ******************************************************************************\r
   9   * @attention\r
  10   *\r
  11   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
  12   *\r
  13   * Redistribution and use in source and binary forms, with or without modification,\r
  14   * are permitted provided that the following conditions are met:\r
  15   *   1. Redistributions of source code must retain the above copyright notice,\r
  16   *      this list of conditions and the following disclaimer.\r
  17   *   2. Redistributions in binary form must reproduce the above copyright notice,\r
  18   *      this list of conditions and the following disclaimer in the documentation\r
  19   *      and/or other materials provided with the distribution.\r
  20   *   3. Neither the name of STMicroelectronics nor the names of its contributors\r
  21   *      may be used to endorse or promote products derived from this software\r
  22   *      without specific prior written permission.\r
  23   *\r
  24   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
  25   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
  26   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
  27   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
  28   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
  29   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
  30   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
  31   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
  32   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
  33   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
  34   *\r
  35   ******************************************************************************\r
  36   */ \r
  37 \r
  38 /* Define to prevent recursive inclusion -------------------------------------*/\r
  39 #ifndef __STM32F7xx_LL_SDMMC_H\r
  40 #define __STM32F7xx_LL_SDMMC_H\r
  41 \r
  42 #ifdef __cplusplus\r
  43  extern "C" {\r
  44 #endif\r
  45 \r
  46 /* Includes ------------------------------------------------------------------*/\r
  47 #include "stm32f7xx_hal_def.h"\r
  48 \r
  49 /** @addtogroup STM32F7xx_Driver\r
  50   * @{\r
  51   */\r
  52 \r
  53 /** @addtogroup SDMMC_LL\r
  54   * @{\r
  55   */ \r
  56 \r
  57 /* Exported types ------------------------------------------------------------*/ \r
  58 /** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types\r
  59   * @{\r
  60   */\r
  61   \r
  62 /** \r
  63   * @brief  SDMMC Configuration Structure definition  \r
  64   */\r
  65 typedef struct\r
  66 {\r
  67   uint32_t ClockEdge;            /*!< Specifies the clock transition on which the bit capture is made.\r
  68                                       This parameter can be a value of @ref SDMMC_LL_Clock_Edge                 */\r
  69 \r
  70   uint32_t ClockBypass;          /*!< Specifies whether the SDMMC Clock divider bypass is\r
  71                                       enabled or disabled.\r
  72                                       This parameter can be a value of @ref SDMMC_LL_Clock_Bypass               */\r
  73 \r
  74   uint32_t ClockPowerSave;       /*!< Specifies whether SDMMC Clock output is enabled or\r
  75                                       disabled when the bus is idle.\r
  76                                       This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save           */\r
  77 \r
  78   uint32_t BusWide;              /*!< Specifies the SDMMC bus width.\r
  79                                       This parameter can be a value of @ref SDMMC_LL_Bus_Wide                   */\r
  80 \r
  81   uint32_t HardwareFlowControl;  /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled.\r
  82                                       This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control      */\r
  83 \r
  84   uint32_t ClockDiv;             /*!< Specifies the clock frequency of the SDMMC controller.\r
  85                                       This parameter can be a value between Min_Data = 0 and Max_Data = 255 */  \r
  86   \r
  87 }SDMMC_InitTypeDef;\r
  88   \r
  89 \r
  90 /** \r
  91   * @brief  SDMMC Command Control structure \r
  92   */\r
  93 typedef struct                                                                                            \r
  94 {\r
  95   uint32_t Argument;            /*!< Specifies the SDMMC command argument which is sent\r
  96                                      to a card as part of a command message. If a command\r
  97                                      contains an argument, it must be loaded into this register\r
  98                                      before writing the command to the command register.              */\r
  99 \r
 100   uint32_t CmdIndex;            /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and \r
 101                                      Max_Data = 64                                                    */\r
 102 \r
 103   uint32_t Response;            /*!< Specifies the SDMMC response type.\r
 104                                      This parameter can be a value of @ref SDMMC_LL_Response_Type         */\r
 105 \r
 106   uint32_t WaitForInterrupt;    /*!< Specifies whether SDMMC wait for interrupt request is \r
 107                                      enabled or disabled.\r
 108                                      This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State  */\r
 109 \r
 110   uint32_t CPSM;                /*!< Specifies whether SDMMC Command path state machine (CPSM)\r
 111                                      is enabled or disabled.\r
 112                                      This parameter can be a value of @ref SDMMC_LL_CPSM_State            */\r
 113 }SDMMC_CmdInitTypeDef;\r
 114 \r
 115 \r
 116 /** \r
 117   * @brief  SDMMC Data Control structure \r
 118   */\r
 119 typedef struct\r
 120 {\r
 121   uint32_t DataTimeOut;         /*!< Specifies the data timeout period in card bus clock periods.  */\r
 122 \r
 123   uint32_t DataLength;          /*!< Specifies the number of data bytes to be transferred.         */\r
 124  \r
 125   uint32_t DataBlockSize;       /*!< Specifies the data block size for block transfer.\r
 126                                      This parameter can be a value of @ref SDMMC_LL_Data_Block_Size    */\r
 127  \r
 128   uint32_t TransferDir;         /*!< Specifies the data transfer direction, whether the transfer\r
 129                                      is a read or write.\r
 130                                      This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */\r
 131  \r
 132   uint32_t TransferMode;        /*!< Specifies whether data transfer is in stream or block mode.\r
 133                                      This parameter can be a value of @ref SDMMC_LL_Transfer_Type      */\r
 134  \r
 135   uint32_t DPSM;                /*!< Specifies whether SDMMC Data path state machine (DPSM)\r
 136                                      is enabled or disabled.\r
 137                                      This parameter can be a value of @ref SDMMC_LL_DPSM_State         */\r
 138 }SDMMC_DataInitTypeDef;\r
 139 \r
 140 /**\r
 141   * @}\r
 142   */\r
 143   \r
 144 /* Exported constants --------------------------------------------------------*/\r
 145 /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants\r
 146   * @{\r
 147   */\r
 148 \r
 149 /** @defgroup SDMMC_LL_Clock_Edge Clock Edge\r
 150   * @{\r
 151   */\r
 152 #define SDMMC_CLOCK_EDGE_RISING               ((uint32_t)0x00000000)\r
 153 #define SDMMC_CLOCK_EDGE_FALLING              SDMMC_CLKCR_NEGEDGE\r
 154 \r
 155 #define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \\r
 156                                   ((EDGE) == SDMMC_CLOCK_EDGE_FALLING))\r
 157 /**\r
 158   * @}\r
 159   */\r
 160 \r
 161 /** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass\r
 162   * @{\r
 163   */\r
 164 #define SDMMC_CLOCK_BYPASS_DISABLE             ((uint32_t)0x00000000)\r
 165 #define SDMMC_CLOCK_BYPASS_ENABLE              SDMMC_CLKCR_BYPASS   \r
 166 \r
 167 #define IS_SDMMC_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDMMC_CLOCK_BYPASS_DISABLE) || \\r
 168                                       ((BYPASS) == SDMMC_CLOCK_BYPASS_ENABLE))\r
 169 /**\r
 170   * @}\r
 171   */ \r
 172 \r
 173 /** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving\r
 174   * @{\r
 175   */\r
 176 #define SDMMC_CLOCK_POWER_SAVE_DISABLE         ((uint32_t)0x00000000)\r
 177 #define SDMMC_CLOCK_POWER_SAVE_ENABLE          SDMMC_CLKCR_PWRSAV\r
 178 \r
 179 #define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \\r
 180                                         ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE))\r
 181 /**\r
 182   * @}\r
 183   */\r
 184 \r
 185 /** @defgroup SDMMC_LL_Bus_Wide Bus Width\r
 186   * @{\r
 187   */\r
 188 #define SDMMC_BUS_WIDE_1B                      ((uint32_t)0x00000000)\r
 189 #define SDMMC_BUS_WIDE_4B                      SDMMC_CLKCR_WIDBUS_0\r
 190 #define SDMMC_BUS_WIDE_8B                      SDMMC_CLKCR_WIDBUS_1\r
 191 \r
 192 #define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || \\r
 193                                 ((WIDE) == SDMMC_BUS_WIDE_4B) || \\r
 194                                 ((WIDE) == SDMMC_BUS_WIDE_8B))\r
 195 /**\r
 196   * @}\r
 197   */\r
 198 \r
 199 /** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control\r
 200   * @{\r
 201   */\r
 202 #define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE    ((uint32_t)0x00000000)\r
 203 #define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE     SDMMC_CLKCR_HWFC_EN\r
 204 \r
 205 #define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \\r
 206                                                 ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE))\r
 207 /**\r
 208   * @}\r
 209   */\r
 210   \r
 211 /** @defgroup SDMMC_LL_Clock_Division Clock Division\r
 212   * @{\r
 213   */\r
 214 #define IS_SDMMC_CLKDIV(DIV)   ((DIV) <= 0xFF)\r
 215 /**\r
 216   * @}\r
 217   */  \r
 218     \r
 219 /** @defgroup SDMMC_LL_Command_Index Command Index\r
 220   * @{\r
 221   */\r
 222 #define IS_SDMMC_CMD_INDEX(INDEX)            ((INDEX) < 0x40)\r
 223 /**\r
 224   * @}\r
 225   */\r
 226 \r
 227 /** @defgroup SDMMC_LL_Response_Type Response Type\r
 228   * @{\r
 229   */\r
 230 #define SDMMC_RESPONSE_NO                    ((uint32_t)0x00000000)\r
 231 #define SDMMC_RESPONSE_SHORT                 SDMMC_CMD_WAITRESP_0\r
 232 #define SDMMC_RESPONSE_LONG                  SDMMC_CMD_WAITRESP\r
 233 \r
 234 #define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO)    || \\r
 235                                     ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \\r
 236                                     ((RESPONSE) == SDMMC_RESPONSE_LONG))\r
 237 /**\r
 238   * @}\r
 239   */\r
 240 \r
 241 /** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt\r
 242   * @{\r
 243   */\r
 244 #define SDMMC_WAIT_NO                        ((uint32_t)0x00000000)\r
 245 #define SDMMC_WAIT_IT                        SDMMC_CMD_WAITINT \r
 246 #define SDMMC_WAIT_PEND                      SDMMC_CMD_WAITPEND\r
 247 \r
 248 #define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \\r
 249                             ((WAIT) == SDMMC_WAIT_IT) || \\r
 250                             ((WAIT) == SDMMC_WAIT_PEND))\r
 251 /**\r
 252   * @}\r
 253   */\r
 254 \r
 255 /** @defgroup SDMMC_LL_CPSM_State CPSM State\r
 256   * @{\r
 257   */\r
 258 #define SDMMC_CPSM_DISABLE                   ((uint32_t)0x00000000)\r
 259 #define SDMMC_CPSM_ENABLE                    SDMMC_CMD_CPSMEN\r
 260 \r
 261 #define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \\r
 262                             ((CPSM) == SDMMC_CPSM_ENABLE))\r
 263 /**\r
 264   * @}\r
 265   */  \r
 266 \r
 267 /** @defgroup SDMMC_LL_Response_Registers Response Register\r
 268   * @{\r
 269   */\r
 270 #define SDMMC_RESP1                          ((uint32_t)0x00000000)\r
 271 #define SDMMC_RESP2                          ((uint32_t)0x00000004)\r
 272 #define SDMMC_RESP3                          ((uint32_t)0x00000008)\r
 273 #define SDMMC_RESP4                          ((uint32_t)0x0000000C)\r
 274 \r
 275 #define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \\r
 276                             ((RESP) == SDMMC_RESP2) || \\r
 277                             ((RESP) == SDMMC_RESP3) || \\r
 278                             ((RESP) == SDMMC_RESP4))\r
 279 /**\r
 280   * @}\r
 281   */\r
 282 \r
 283 /** @defgroup SDMMC_LL_Data_Length Data Lenght\r
 284   * @{\r
 285   */\r
 286 #define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)\r
 287 /**\r
 288   * @}\r
 289   */\r
 290 \r
 291 /** @defgroup SDMMC_LL_Data_Block_Size  Data Block Size\r
 292   * @{\r
 293   */\r
 294 #define SDMMC_DATABLOCK_SIZE_1B               ((uint32_t)0x00000000)\r
 295 #define SDMMC_DATABLOCK_SIZE_2B               SDMMC_DCTRL_DBLOCKSIZE_0\r
 296 #define SDMMC_DATABLOCK_SIZE_4B               SDMMC_DCTRL_DBLOCKSIZE_1\r
 297 #define SDMMC_DATABLOCK_SIZE_8B               (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1)\r
 298 #define SDMMC_DATABLOCK_SIZE_16B              SDMMC_DCTRL_DBLOCKSIZE_2\r
 299 #define SDMMC_DATABLOCK_SIZE_32B              (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2)\r
 300 #define SDMMC_DATABLOCK_SIZE_64B              (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)\r
 301 #define SDMMC_DATABLOCK_SIZE_128B             (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)\r
 302 #define SDMMC_DATABLOCK_SIZE_256B             SDMMC_DCTRL_DBLOCKSIZE_3\r
 303 #define SDMMC_DATABLOCK_SIZE_512B             (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_3)\r
 304 #define SDMMC_DATABLOCK_SIZE_1024B            (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)\r
 305 #define SDMMC_DATABLOCK_SIZE_2048B            (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) \r
 306 #define SDMMC_DATABLOCK_SIZE_4096B            (SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)\r
 307 #define SDMMC_DATABLOCK_SIZE_8192B            (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)\r
 308 #define SDMMC_DATABLOCK_SIZE_16384B           (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)\r
 309 \r
 310 #define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B)    || \\r
 311                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_2B)    || \\r
 312                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_4B)    || \\r
 313                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_8B)    || \\r
 314                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_16B)   || \\r
 315                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_32B)   || \\r
 316                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_64B)   || \\r
 317                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_128B)  || \\r
 318                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_256B)  || \\r
 319                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_512B)  || \\r
 320                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \\r
 321                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \\r
 322                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \\r
 323                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \\r
 324                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B)) \r
 325 /**\r
 326   * @}\r
 327   */\r
 328 \r
 329 /** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction\r
 330   * @{\r
 331   */\r
 332 #define SDMMC_TRANSFER_DIR_TO_CARD            ((uint32_t)0x00000000)\r
 333 #define SDMMC_TRANSFER_DIR_TO_SDMMC            SDMMC_DCTRL_DTDIR\r
 334 \r
 335 #define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \\r
 336                                    ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC))\r
 337 /**\r
 338   * @}\r
 339   */\r
 340 \r
 341 /** @defgroup SDMMC_LL_Transfer_Type Transfer Type\r
 342   * @{\r
 343   */\r
 344 #define SDMMC_TRANSFER_MODE_BLOCK             ((uint32_t)0x00000000)\r
 345 #define SDMMC_TRANSFER_MODE_STREAM            SDMMC_DCTRL_DTMODE\r
 346 \r
 347 #define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \\r
 348                                      ((MODE) == SDMMC_TRANSFER_MODE_STREAM))\r
 349 /**\r
 350   * @}\r
 351   */\r
 352 \r
 353 /** @defgroup SDMMC_LL_DPSM_State DPSM State\r
 354   * @{\r
 355   */\r
 356 #define SDMMC_DPSM_DISABLE                    ((uint32_t)0x00000000)\r
 357 #define SDMMC_DPSM_ENABLE                     SDMMC_DCTRL_DTEN\r
 358 \r
 359 #define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\\r
 360                             ((DPSM) == SDMMC_DPSM_ENABLE))\r
 361 /**\r
 362   * @}\r
 363   */\r
 364   \r
 365 /** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode\r
 366   * @{\r
 367   */\r
 368 #define SDMMC_READ_WAIT_MODE_DATA2                ((uint32_t)0x00000000)\r
 369 #define SDMMC_READ_WAIT_MODE_CLK                  (SDMMC_DCTRL_RWMOD)\r
 370 \r
 371 #define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || \\r
 372                                      ((MODE) == SDMMC_READ_WAIT_MODE_DATA2))\r
 373 /**\r
 374   * @}\r
 375   */  \r
 376 \r
 377 /** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources\r
 378   * @{\r
 379   */\r
 380 #define SDMMC_IT_CCRCFAIL                    SDMMC_STA_CCRCFAIL\r
 381 #define SDMMC_IT_DCRCFAIL                    SDMMC_STA_DCRCFAIL\r
 382 #define SDMMC_IT_CTIMEOUT                    SDMMC_STA_CTIMEOUT\r
 383 #define SDMMC_IT_DTIMEOUT                    SDMMC_STA_DTIMEOUT\r
 384 #define SDMMC_IT_TXUNDERR                    SDMMC_STA_TXUNDERR\r
 385 #define SDMMC_IT_RXOVERR                     SDMMC_STA_RXOVERR\r
 386 #define SDMMC_IT_CMDREND                     SDMMC_STA_CMDREND\r
 387 #define SDMMC_IT_CMDSENT                     SDMMC_STA_CMDSENT\r
 388 #define SDMMC_IT_DATAEND                     SDMMC_STA_DATAEND\r
 389 #define SDMMC_IT_DBCKEND                     SDMMC_STA_DBCKEND\r
 390 #define SDMMC_IT_CMDACT                      SDMMC_STA_CMDACT\r
 391 #define SDMMC_IT_TXACT                       SDMMC_STA_TXACT\r
 392 #define SDMMC_IT_RXACT                       SDMMC_STA_RXACT\r
 393 #define SDMMC_IT_TXFIFOHE                    SDMMC_STA_TXFIFOHE\r
 394 #define SDMMC_IT_RXFIFOHF                    SDMMC_STA_RXFIFOHF\r
 395 #define SDMMC_IT_TXFIFOF                     SDMMC_STA_TXFIFOF\r
 396 #define SDMMC_IT_RXFIFOF                     SDMMC_STA_RXFIFOF\r
 397 #define SDMMC_IT_TXFIFOE                     SDMMC_STA_TXFIFOE\r
 398 #define SDMMC_IT_RXFIFOE                     SDMMC_STA_RXFIFOE\r
 399 #define SDMMC_IT_TXDAVL                      SDMMC_STA_TXDAVL\r
 400 #define SDMMC_IT_RXDAVL                      SDMMC_STA_RXDAVL\r
 401 #define SDMMC_IT_SDIOIT                      SDMMC_STA_SDIOIT\r
 402 /**\r
 403   * @}\r
 404   */ \r
 405 \r
 406 /** @defgroup SDMMC_LL_Flags Flags\r
 407   * @{\r
 408   */\r
 409 #define SDMMC_FLAG_CCRCFAIL                  SDMMC_STA_CCRCFAIL\r
 410 #define SDMMC_FLAG_DCRCFAIL                  SDMMC_STA_DCRCFAIL\r
 411 #define SDMMC_FLAG_CTIMEOUT                  SDMMC_STA_CTIMEOUT\r
 412 #define SDMMC_FLAG_DTIMEOUT                  SDMMC_STA_DTIMEOUT\r
 413 #define SDMMC_FLAG_TXUNDERR                  SDMMC_STA_TXUNDERR\r
 414 #define SDMMC_FLAG_RXOVERR                   SDMMC_STA_RXOVERR\r
 415 #define SDMMC_FLAG_CMDREND                   SDMMC_STA_CMDREND\r
 416 #define SDMMC_FLAG_CMDSENT                   SDMMC_STA_CMDSENT\r
 417 #define SDMMC_FLAG_DATAEND                   SDMMC_STA_DATAEND\r
 418 #define SDMMC_FLAG_DBCKEND                   SDMMC_STA_DBCKEND\r
 419 #define SDMMC_FLAG_CMDACT                    SDMMC_STA_CMDACT\r
 420 #define SDMMC_FLAG_TXACT                     SDMMC_STA_TXACT\r
 421 #define SDMMC_FLAG_RXACT                     SDMMC_STA_RXACT\r
 422 #define SDMMC_FLAG_TXFIFOHE                  SDMMC_STA_TXFIFOHE\r
 423 #define SDMMC_FLAG_RXFIFOHF                  SDMMC_STA_RXFIFOHF\r
 424 #define SDMMC_FLAG_TXFIFOF                   SDMMC_STA_TXFIFOF\r
 425 #define SDMMC_FLAG_RXFIFOF                   SDMMC_STA_RXFIFOF\r
 426 #define SDMMC_FLAG_TXFIFOE                   SDMMC_STA_TXFIFOE\r
 427 #define SDMMC_FLAG_RXFIFOE                   SDMMC_STA_RXFIFOE\r
 428 #define SDMMC_FLAG_TXDAVL                    SDMMC_STA_TXDAVL\r
 429 #define SDMMC_FLAG_RXDAVL                    SDMMC_STA_RXDAVL\r
 430 #define SDMMC_FLAG_SDIOIT                    SDMMC_STA_SDIOIT\r
 431 /**\r
 432   * @}\r
 433   */\r
 434 \r
 435 /**\r
 436   * @}\r
 437   */\r
 438   \r
 439 /* Exported macro ------------------------------------------------------------*/\r
 440 /** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros\r
 441   * @{\r
 442   */\r
 443   \r
 444 /** @defgroup SDMMC_LL_Register Bits And Addresses Definitions\r
 445   * @brief SDMMC_LL registers bit address in the alias region\r
 446   * @{\r
 447   */\r
 448 /* ---------------------- SDMMC registers bit mask --------------------------- */\r
 449 /* --- CLKCR Register ---*/\r
 450 /* CLKCR register clear mask */ \r
 451 #define CLKCR_CLEAR_MASK         ((uint32_t)(SDMMC_CLKCR_CLKDIV  | SDMMC_CLKCR_PWRSAV |\\r
 452                                              SDMMC_CLKCR_BYPASS  | SDMMC_CLKCR_WIDBUS |\\r
 453                                              SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN))\r
 454 \r
 455 /* --- DCTRL Register ---*/\r
 456 /* SDMMC DCTRL Clear Mask */\r
 457 #define DCTRL_CLEAR_MASK         ((uint32_t)(SDMMC_DCTRL_DTEN    | SDMMC_DCTRL_DTDIR |\\r
 458                                              SDMMC_DCTRL_DTMODE  | SDMMC_DCTRL_DBLOCKSIZE))\r
 459 \r
 460 /* --- CMD Register ---*/\r
 461 /* CMD Register clear mask */\r
 462 #define CMD_CLEAR_MASK           ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\\r
 463                                              SDMMC_CMD_WAITINT  | SDMMC_CMD_WAITPEND |\\r
 464                                              SDMMC_CMD_CPSMEN   | SDMMC_CMD_SDIOSUSPEND))\r
 465 \r
 466 /* SDMMC Initialization Frequency (400KHz max) */\r
 467 #define SDMMC_INIT_CLK_DIV ((uint8_t)0x76)\r
 468 \r
 469 /* SDMMC Data Transfer Frequency (25MHz max) */\r
 470 #define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x0)\r
 471 \r
 472 /**\r
 473   * @}\r
 474   */\r
 475 \r
 476 /** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration\r
 477  *  @brief macros to handle interrupts and specific clock configurations\r
 478  * @{\r
 479  */\r
 480  \r
 481 /**\r
 482   * @brief  Enable the SDMMC device.\r
 483   * @param  __INSTANCE__: SDMMC Instance  \r
 484   * @retval None\r
 485   */ \r
 486 #define __SDMMC_ENABLE(__INSTANCE__)  ((__INSTANCE__)->CLKCR |= SDMMC_CLKCR_CLKEN)\r
 487 \r
 488 /**\r
 489   * @brief  Disable the SDMMC device.\r
 490   * @param  __INSTANCE__: SDMMC Instance  \r
 491   * @retval None\r
 492   */\r
 493 #define __SDMMC_DISABLE(__INSTANCE__)  ((__INSTANCE__)->CLKCR &= ~SDMMC_CLKCR_CLKEN)\r
 494 \r
 495 /**\r
 496   * @brief  Enable the SDMMC DMA transfer.\r
 497   * @param  __INSTANCE__: SDMMC Instance  \r
 498   * @retval None\r
 499   */ \r
 500 #define __SDMMC_DMA_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_DMAEN)\r
 501 /**\r
 502   * @brief  Disable the SDMMC DMA transfer.\r
 503   * @param  __INSTANCE__: SDMMC Instance   \r
 504   * @retval None\r
 505   */\r
 506 #define __SDMMC_DMA_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_DMAEN)\r
 507  \r
 508 /**\r
 509   * @brief  Enable the SDMMC device interrupt.\r
 510   * @param  __INSTANCE__ : Pointer to SDMMC register base  \r
 511   * @param  __INTERRUPT__ : specifies the SDMMC interrupt sources to be enabled.\r
 512   *         This parameter can be one or a combination of the following values:\r
 513   *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\r
 514   *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\r
 515   *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt\r
 516   *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt\r
 517   *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt\r
 518   *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt\r
 519   *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt\r
 520   *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt\r
 521   *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt\r
 522   *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt\r
 523   *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt\r
 524   *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt\r
 525   *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt\r
 526   *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt\r
 527   *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt\r
 528   *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt\r
 529   *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt\r
 530   *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt\r
 531   *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt\r
 532   *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt\r
 533   *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt\r
 534   *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt   \r
 535   * @retval None\r
 536   */\r
 537 #define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK |= (__INTERRUPT__))\r
 538 \r
 539 /**\r
 540   * @brief  Disable the SDMMC device interrupt.\r
 541   * @param  __INSTANCE__ : Pointer to SDMMC register base   \r
 542   * @param  __INTERRUPT__ : specifies the SDMMC interrupt sources to be disabled.\r
 543   *          This parameter can be one or a combination of the following values:\r
 544   *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\r
 545   *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\r
 546   *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt\r
 547   *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt\r
 548   *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt\r
 549   *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt\r
 550   *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt\r
 551   *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt\r
 552   *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt\r
 553   *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt\r
 554   *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt\r
 555   *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt\r
 556   *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt\r
 557   *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt\r
 558   *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt\r
 559   *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt\r
 560   *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt\r
 561   *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt\r
 562   *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt\r
 563   *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt\r
 564   *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt\r
 565   *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt   \r
 566   * @retval None\r
 567   */\r
 568 #define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))\r
 569 \r
 570 /**\r
 571   * @brief  Checks whether the specified SDMMC flag is set or not. \r
 572   * @param  __INSTANCE__ : Pointer to SDMMC register base   \r
 573   * @param  __FLAG__: specifies the flag to check. \r
 574   *          This parameter can be one of the following values:\r
 575   *            @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)\r
 576   *            @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)\r
 577   *            @arg SDMMC_FLAG_CTIMEOUT: Command response timeout\r
 578   *            @arg SDMMC_FLAG_DTIMEOUT: Data timeout\r
 579   *            @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error\r
 580   *            @arg SDMMC_FLAG_RXOVERR:  Received FIFO overrun error\r
 581   *            @arg SDMMC_FLAG_CMDREND:  Command response received (CRC check passed)\r
 582   *            @arg SDMMC_FLAG_CMDSENT:  Command sent (no response required)\r
 583   *            @arg SDMMC_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)\r
 584   *            @arg SDMMC_FLAG_DBCKEND:  Data block sent/received (CRC check passed)\r
 585   *            @arg SDMMC_FLAG_CMDACT:   Command transfer in progress\r
 586   *            @arg SDMMC_FLAG_TXACT:    Data transmit in progress\r
 587   *            @arg SDMMC_FLAG_RXACT:    Data receive in progress\r
 588   *            @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty\r
 589   *            @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full\r
 590   *            @arg SDMMC_FLAG_TXFIFOF:  Transmit FIFO full\r
 591   *            @arg SDMMC_FLAG_RXFIFOF:  Receive FIFO full\r
 592   *            @arg SDMMC_FLAG_TXFIFOE:  Transmit FIFO empty\r
 593   *            @arg SDMMC_FLAG_RXFIFOE:  Receive FIFO empty\r
 594   *            @arg SDMMC_FLAG_TXDAVL:   Data available in transmit FIFO\r
 595   *            @arg SDMMC_FLAG_RXDAVL:   Data available in receive FIFO\r
 596   *            @arg SDMMC_FLAG_SDMMCIT:   SD I/O interrupt received\r
 597   * @retval The new state of SDMMC_FLAG (SET or RESET).\r
 598   */\r
 599 #define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__)  (((__INSTANCE__)->STA &(__FLAG__)) != RESET)\r
 600 \r
 601 \r
 602 /**\r
 603   * @brief  Clears the SDMMC pending flags.\r
 604   * @param  __INSTANCE__ : Pointer to SDMMC register base  \r
 605   * @param  __FLAG__: specifies the flag to clear.  \r
 606   *          This parameter can be one or a combination of the following values:\r
 607   *            @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)\r
 608   *            @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)\r
 609   *            @arg SDMMC_FLAG_CTIMEOUT: Command response timeout\r
 610   *            @arg SDMMC_FLAG_DTIMEOUT: Data timeout\r
 611   *            @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error\r
 612   *            @arg SDMMC_FLAG_RXOVERR:  Received FIFO overrun error\r
 613   *            @arg SDMMC_FLAG_CMDREND:  Command response received (CRC check passed)\r
 614   *            @arg SDMMC_FLAG_CMDSENT:  Command sent (no response required)\r
 615   *            @arg SDMMC_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)\r
 616   *            @arg SDMMC_FLAG_DBCKEND:  Data block sent/received (CRC check passed)\r
 617   *            @arg SDMMC_FLAG_SDMMCIT:   SD I/O interrupt received\r
 618   * @retval None\r
 619   */\r
 620 #define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__)  ((__INSTANCE__)->ICR = (__FLAG__))\r
 621 \r
 622 /**\r
 623   * @brief  Checks whether the specified SDMMC interrupt has occurred or not.\r
 624   * @param  __INSTANCE__ : Pointer to SDMMC register base   \r
 625   * @param  __INTERRUPT__: specifies the SDMMC interrupt source to check. \r
 626   *          This parameter can be one of the following values:\r
 627   *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\r
 628   *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\r
 629   *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt\r
 630   *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt\r
 631   *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt\r
 632   *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt\r
 633   *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt\r
 634   *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt\r
 635   *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt\r
 636   *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt\r
 637   *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt\r
 638   *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt\r
 639   *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt\r
 640   *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt\r
 641   *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt\r
 642   *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt\r
 643   *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt\r
 644   *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt\r
 645   *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt\r
 646   *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt\r
 647   *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt\r
 648   *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt\r
 649   * @retval The new state of SDMMC_IT (SET or RESET).\r
 650   */\r
 651 #define __SDMMC_GET_IT  (__INSTANCE__, __INTERRUPT__)  (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))\r
 652 \r
 653 /**\r
 654   * @brief  Clears the SDMMC's interrupt pending bits.\r
 655   * @param  __INSTANCE__ : Pointer to SDMMC register base \r
 656   * @param  __INTERRUPT__: specifies the interrupt pending bit to clear. \r
 657   *          This parameter can be one or a combination of the following values:\r
 658   *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\r
 659   *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\r
 660   *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt\r
 661   *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt\r
 662   *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt\r
 663   *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt\r
 664   *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt\r
 665   *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt\r
 666   *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDMMC_DCOUNT, is zero) interrupt\r
 667   *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt\r
 668   * @retval None\r
 669   */\r
 670 #define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->ICR = (__INTERRUPT__))\r
 671 \r
 672 /**\r
 673   * @brief  Enable Start the SD I/O Read Wait operation.\r
 674   * @param  __INSTANCE__ : Pointer to SDMMC register base  \r
 675   * @retval None\r
 676   */  \r
 677 #define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART)\r
 678 \r
 679 /**\r
 680   * @brief  Disable Start the SD I/O Read Wait operations.\r
 681   * @param  __INSTANCE__ : Pointer to SDMMC register base   \r
 682   * @retval None\r
 683   */  \r
 684 #define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART)\r
 685 \r
 686 /**\r
 687   * @brief  Enable Start the SD I/O Read Wait operation.\r
 688   * @param  __INSTANCE__ : Pointer to SDMMC register base   \r
 689   * @retval None\r
 690   */  \r
 691 #define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP)\r
 692 \r
 693 /**\r
 694   * @brief  Disable Stop the SD I/O Read Wait operations.\r
 695   * @param  __INSTANCE__ : Pointer to SDMMC register base  \r
 696   * @retval None\r
 697   */  \r
 698 #define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP)\r
 699 \r
 700 /**\r
 701   * @brief  Enable the SD I/O Mode Operation.\r
 702   * @param  __INSTANCE__ : Pointer to SDMMC register base   \r
 703   * @retval None\r
 704   */  \r
 705 #define __SDMMC_OPERATION_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN) \r
 706 \r
 707 /**\r
 708   * @brief  Disable the SD I/O Mode Operation.\r
 709   * @param  __INSTANCE__ : Pointer to SDMMC register base \r
 710   * @retval None\r
 711   */  \r
 712 #define __SDMMC_OPERATION_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN) \r
 713 \r
 714 /**\r
 715   * @brief  Enable the SD I/O Suspend command sending.\r
 716   * @param  __INSTANCE__ : Pointer to SDMMC register base  \r
 717   * @retval None\r
 718   */  \r
 719 #define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__)  ((__INSTANCE__)->CMD |= SDMMC_CMD_SDIOSUSPEND) \r
 720 \r
 721 /**\r
 722   * @brief  Disable the SD I/O Suspend command sending.\r
 723   * @param  __INSTANCE__ : Pointer to SDMMC register base  \r
 724   * @retval None\r
 725   */  \r
 726 #define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__)  ((__INSTANCE__)->CMD &= ~SDMMC_CMD_SDIOSUSPEND) \r
 727       \r
 728 /**\r
 729   * @}\r
 730   */\r
 731 \r
 732 /**\r
 733   * @}\r
 734   */  \r
 735 \r
 736 /* Exported functions --------------------------------------------------------*/\r
 737 /** @addtogroup SDMMC_LL_Exported_Functions\r
 738   * @{\r
 739   */\r
 740   \r
 741 /* Initialization/de-initialization functions  **********************************/\r
 742 /** @addtogroup HAL_SDMMC_LL_Group1\r
 743   * @{\r
 744   */\r
 745 HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init);\r
 746 /**\r
 747   * @}\r
 748   */\r
 749   \r
 750 /* I/O operation functions  *****************************************************/\r
 751 /** @addtogroup HAL_SDMMC_LL_Group2\r
 752   * @{\r
 753   */\r
 754 /* Blocking mode: Polling */\r
 755 uint32_t          SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx);\r
 756 HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData);\r
 757 /**\r
 758   * @}\r
 759   */\r
 760   \r
 761 /* Peripheral Control functions  ************************************************/\r
 762 /** @addtogroup HAL_SDMMC_LL_Group3\r
 763   * @{\r
 764   */\r
 765 HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx);\r
 766 HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx);\r
 767 uint32_t          SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx);\r
 768 \r
 769 /* Command path state machine (CPSM) management functions */\r
 770 HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command);\r
 771 uint8_t           SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx);\r
 772 uint32_t          SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response);\r
 773 \r
 774 /* Data path state machine (DPSM) management functions */\r
 775 HAL_StatusTypeDef SDMMC_DataConfig(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data);\r
 776 uint32_t          SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx);\r
 777 uint32_t          SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx);\r
 778 \r
 779 /* SDMMC Cards mode management functions */\r
 780 HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode);\r
 781 \r
 782 /**\r
 783   * @}\r
 784   */\r
 785   \r
 786 /**\r
 787   * @}\r
 788   */\r
 789   \r
 790 /**\r
 791   * @}\r
 792   */ \r
 793 \r
 794 /**\r
 795   * @}\r
 796   */\r
 797 \r
 798 #ifdef __cplusplus\r
 799 }\r
 800 #endif\r
 801 \r
 802 #endif /* __STM32F7xx_LL_SDMMC_H */\r
 803 \r
 804 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r