2 ******************************************************************************
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3 * @file stm32f7xx_hal_rcc.c
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4 * @author MCD Application Team
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6 * @date 06-March-2015
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7 * @brief RCC HAL module driver.
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8 * This file provides firmware functions to manage the following
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9 * functionalities of the Reset and Clock Control (RCC) peripheral:
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10 * + Initialization and de-initialization functions
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11 * + Peripheral Control functions
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14 ==============================================================================
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15 ##### RCC specific features #####
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16 ==============================================================================
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18 After reset the device is running from Internal High Speed oscillator
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19 (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
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20 and I-Cache are disabled, and all peripherals are off except internal
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21 SRAM, Flash and JTAG.
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22 (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
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23 all peripherals mapped on these busses are running at HSI speed.
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24 (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
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25 (+) All GPIOs are in input floating state, except the JTAG pins which
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26 are assigned to be used for debug purpose.
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29 Once the device started from reset, the user application has to:
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30 (+) Configure the clock source to be used to drive the System clock
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31 (if the application needs higher frequency/performance)
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32 (+) Configure the System clock frequency and Flash settings
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33 (+) Configure the AHB and APB busses prescalers
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34 (+) Enable the clock for the peripheral(s) to be used
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35 (+) Configure the clock source(s) for peripherals which clocks are not
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36 derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
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38 ##### RCC Limitations #####
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39 ==============================================================================
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41 A delay between an RCC peripheral clock enable and the effective peripheral
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42 enabling should be taken into account in order to manage the peripheral read/write
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44 (+) This delay depends on the peripheral mapping.
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45 (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
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46 after the clock enable bit is set on the hardware register
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47 (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
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48 after the clock enable bit is set on the hardware register
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52 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
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53 inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
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56 ******************************************************************************
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59 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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61 * Redistribution and use in source and binary forms, with or without modification,
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62 * are permitted provided that the following conditions are met:
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63 * 1. Redistributions of source code must retain the above copyright notice,
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64 * this list of conditions and the following disclaimer.
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65 * 2. Redistributions in binary form must reproduce the above copyright notice,
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66 * this list of conditions and the following disclaimer in the documentation
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67 * and/or other materials provided with the distribution.
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68 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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69 * may be used to endorse or promote products derived from this software
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70 * without specific prior written permission.
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72 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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73 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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74 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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75 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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76 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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77 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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78 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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79 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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80 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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81 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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83 ******************************************************************************
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86 /* Includes ------------------------------------------------------------------*/
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87 #include "stm32f7xx_hal.h"
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89 /** @addtogroup STM32F7xx_HAL_Driver
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93 /** @defgroup RCC RCC
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94 * @brief RCC HAL module driver
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98 #ifdef HAL_RCC_MODULE_ENABLED
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100 /* Private typedef -----------------------------------------------------------*/
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101 /* Private define ------------------------------------------------------------*/
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102 /* Private macro -------------------------------------------------------------*/
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103 /** @defgroup RCC_Private_Macros RCC Private Macros
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107 #define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
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108 #define MCO1_GPIO_PORT GPIOA
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109 #define MCO1_PIN GPIO_PIN_8
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111 #define MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
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112 #define MCO2_GPIO_PORT GPIOC
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113 #define MCO2_PIN GPIO_PIN_9
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118 /* Private variables ---------------------------------------------------------*/
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119 /** @defgroup RCC_Private_Variables RCC Private Variables
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122 const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
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128 /* Private function prototypes -----------------------------------------------*/
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129 /* Exported functions ---------------------------------------------------------*/
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131 /** @defgroup RCC_Exported_Functions RCC Exported Functions
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135 /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
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136 * @brief Initialization and Configuration functions
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139 ===============================================================================
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140 ##### Initialization and de-initialization functions #####
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141 ===============================================================================
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143 This section provides functions allowing to configure the internal/external oscillators
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144 (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1
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147 [..] Internal/external clock and PLL configuration
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148 (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
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149 the PLL as System clock source.
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151 (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
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154 (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
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155 through the PLL as System clock source. Can be used also as RTC clock source.
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157 (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
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159 (#) PLL (clocked by HSI or HSE), featuring two different output clocks:
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160 (++) The first output is used to generate the high speed system clock (up to 200 MHz)
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161 (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
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162 the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
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164 (#) CSS (Clock security system), once enable using the function HAL_RCC_EnableCSS()
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165 and if a HSE clock failure occurs(HSE used directly or through PLL as System
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166 clock source), the System clock is automatically switched to HSI and an interrupt
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167 is generated if enabled. The interrupt is linked to the Cortex-M7 NMI
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168 (Non-Maskable Interrupt) exception vector.
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170 (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
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171 clock (through a configurable prescaler) on PA8 pin.
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173 (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
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174 clock (through a configurable prescaler) on PC9 pin.
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176 [..] System, AHB and APB busses clocks configuration
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177 (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
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179 The AHB clock (HCLK) is derived from System clock through configurable
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180 prescaler and used to clock the CPU, memory and peripherals mapped
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181 on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
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182 from AHB clock through configurable prescalers and used to clock
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183 the peripherals mapped on these busses. You can use
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184 "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
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186 -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
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187 (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or
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188 from an external clock mapped on the I2S_CKIN pin.
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189 You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.
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190 (+@) SAI: the SAI clock can be derived either from a specific PLL (PLLI2S) or (PLLSAI) or
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191 from an external clock mapped on the I2S_CKIN pin.
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192 You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.
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193 (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
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194 divided by 2 to 31. You have to use __HAL_RCC_RTC_CONFIG() and __HAL_RCC_RTC_ENABLE()
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195 macros to configure this clock.
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196 (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz
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197 to work correctly, while the SDIO require a frequency equal or lower than
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198 to 48. This clock is derived of the main PLL through PLLQ divider.
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199 (+@) IWDG clock which is always the LSI clock.
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205 * @brief Resets the RCC clock configuration to the default reset state.
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206 * @note The default reset state of the clock configuration is given below:
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207 * - HSI ON and used as system clock source
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208 * - HSE, PLL and PLLI2S OFF
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209 * - AHB, APB1 and APB2 prescaler set to 1.
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210 * - CSS, MCO1 and MCO2 OFF
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211 * - All interrupts disabled
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212 * @note This function doesn't modify the configuration of the
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213 * - Peripheral clocks
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214 * - LSI, LSE and RTC clocks
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217 void HAL_RCC_DeInit(void)
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219 /* Set HSION bit */
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220 SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4);
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222 /* Reset CFGR register */
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223 CLEAR_REG(RCC->CFGR);
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225 /* Reset HSEON, CSSON, PLLON, PLLI2S */
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226 CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON| RCC_CR_PLLI2SON);
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228 /* Reset PLLCFGR register */
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229 CLEAR_REG(RCC->PLLCFGR);
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230 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2);
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232 /* Reset PLLI2SCFGR register */
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233 CLEAR_REG(RCC->PLLI2SCFGR);
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234 SET_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1);
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236 /* Reset HSEBYP bit */
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237 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
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239 /* Disable all interrupts */
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240 CLEAR_REG(RCC->CIR);
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244 * @brief Initializes the RCC Oscillators according to the specified parameters in the
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245 * RCC_OscInitTypeDef.
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246 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
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247 * contains the configuration information for the RCC Oscillators.
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248 * @note The PLL is not disabled when used as system clock.
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249 * @retval HAL status
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251 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
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253 uint32_t tickstart = 0;
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255 /* Check the parameters */
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256 assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
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258 /*------------------------------- HSE Configuration ------------------------*/
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259 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
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261 /* Check the parameters */
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262 assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
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263 /* When the HSE is used as system clock or clock source for PLL, It can not be disabled */
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264 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
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265 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
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267 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
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274 /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
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275 __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
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277 /* Get Start Tick*/
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278 tickstart = HAL_GetTick();
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280 /* Wait till HSE is disabled */
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281 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
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283 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
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285 return HAL_TIMEOUT;
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289 /* Set the new HSE configuration ---------------------------------------*/
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290 __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
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292 /* Check the HSE State */
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293 if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
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295 /* Get Start Tick*/
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296 tickstart = HAL_GetTick();
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298 /* Wait till HSE is ready */
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299 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
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301 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
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303 return HAL_TIMEOUT;
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309 /* Get Start Tick*/
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310 tickstart = HAL_GetTick();
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312 /* Wait till HSE is bypassed or disabled */
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313 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
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315 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
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317 return HAL_TIMEOUT;
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323 /*----------------------------- HSI Configuration --------------------------*/
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324 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
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326 /* Check the parameters */
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327 assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
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328 assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
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330 /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
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331 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
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332 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
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334 /* When HSI is used as system clock it will not disabled */
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335 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
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339 /* Otherwise, just the calibration is allowed */
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342 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
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343 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
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348 /* Check the HSI State */
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349 if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
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351 /* Enable the Internal High Speed oscillator (HSI). */
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352 __HAL_RCC_HSI_ENABLE();
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354 /* Get Start Tick*/
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355 tickstart = HAL_GetTick();
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357 /* Wait till HSI is ready */
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358 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
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360 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
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362 return HAL_TIMEOUT;
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366 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
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367 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
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371 /* Disable the Internal High Speed oscillator (HSI). */
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372 __HAL_RCC_HSI_DISABLE();
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374 /* Get Start Tick*/
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375 tickstart = HAL_GetTick();
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377 /* Wait till HSI is ready */
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378 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
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380 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
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382 return HAL_TIMEOUT;
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388 /*------------------------------ LSI Configuration -------------------------*/
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389 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
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391 /* Check the parameters */
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392 assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
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394 /* Check the LSI State */
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395 if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
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397 /* Enable the Internal Low Speed oscillator (LSI). */
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398 __HAL_RCC_LSI_ENABLE();
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400 /* Get Start Tick*/
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401 tickstart = HAL_GetTick();
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403 /* Wait till LSI is ready */
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404 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
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406 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
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408 return HAL_TIMEOUT;
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414 /* Disable the Internal Low Speed oscillator (LSI). */
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415 __HAL_RCC_LSI_DISABLE();
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417 /* Get Start Tick*/
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418 tickstart = HAL_GetTick();
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420 /* Wait till LSI is ready */
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421 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
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423 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
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425 return HAL_TIMEOUT;
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430 /*------------------------------ LSE Configuration -------------------------*/
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431 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
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433 /* Check the parameters */
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434 assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
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436 /* Enable Power Clock*/
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437 __HAL_RCC_PWR_CLK_ENABLE();
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439 /* Enable write access to Backup domain */
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440 PWR->CR1 |= PWR_CR1_DBP;
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442 /* Wait for Backup domain Write protection disable */
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443 tickstart = HAL_GetTick();
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445 while((PWR->CR1 & PWR_CR1_DBP) == RESET)
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447 if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
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449 return HAL_TIMEOUT;
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453 /* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
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454 __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
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456 /* Get Start Tick*/
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457 tickstart = HAL_GetTick();
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459 /* Wait till LSE is ready */
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460 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
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462 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
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464 return HAL_TIMEOUT;
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468 /* Set the new LSE configuration -----------------------------------------*/
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469 __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
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470 /* Check the LSE State */
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471 if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
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473 /* Get Start Tick*/
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474 tickstart = HAL_GetTick();
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476 /* Wait till LSE is ready */
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477 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
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479 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
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481 return HAL_TIMEOUT;
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487 /* Get Start Tick*/
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488 tickstart = HAL_GetTick();
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490 /* Wait till LSE is ready */
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491 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
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493 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
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495 return HAL_TIMEOUT;
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500 /*-------------------------------- PLL Configuration -----------------------*/
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501 /* Check the parameters */
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502 assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
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503 if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
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505 /* Check if the PLL is used as system clock or not */
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506 if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
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508 if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
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510 /* Check the parameters */
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511 assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
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512 assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
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513 assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
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514 assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
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515 assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
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517 /* Disable the main PLL. */
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518 __HAL_RCC_PLL_DISABLE();
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520 /* Get Start Tick*/
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521 tickstart = HAL_GetTick();
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523 /* Wait till PLL is ready */
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524 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
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526 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
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528 return HAL_TIMEOUT;
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532 /* Configure the main PLL clock source, multiplication and division factors. */
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533 __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
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534 RCC_OscInitStruct->PLL.PLLM,
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535 RCC_OscInitStruct->PLL.PLLN,
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536 RCC_OscInitStruct->PLL.PLLP,
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537 RCC_OscInitStruct->PLL.PLLQ);
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538 /* Enable the main PLL. */
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539 __HAL_RCC_PLL_ENABLE();
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541 /* Get Start Tick*/
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542 tickstart = HAL_GetTick();
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544 /* Wait till PLL is ready */
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545 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
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547 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
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549 return HAL_TIMEOUT;
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555 /* Disable the main PLL. */
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556 __HAL_RCC_PLL_DISABLE();
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558 /* Get Start Tick*/
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559 tickstart = HAL_GetTick();
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561 /* Wait till PLL is ready */
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562 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
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564 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
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566 return HAL_TIMEOUT;
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580 * @brief Initializes the CPU, AHB and APB busses clocks according to the specified
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581 * parameters in the RCC_ClkInitStruct.
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582 * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
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583 * contains the configuration information for the RCC peripheral.
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584 * @param FLatency: FLASH Latency, this parameter depend on device selected
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586 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
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587 * and updated by HAL_RCC_GetHCLKFreq() function called within this function
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589 * @note The HSI is used (enabled by hardware) as system clock source after
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590 * startup from Reset, wake-up from STOP and STANDBY mode, or in case
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591 * of failure of the HSE used directly or indirectly as system clock
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592 * (if the Clock Security System CSS is enabled).
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594 * @note A switch from one clock source to another occurs only if the target
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595 * clock source is ready (clock stable after startup delay or PLL locked).
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596 * If a clock source which is not yet ready is selected, the switch will
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597 * occur when the clock source will be ready.
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598 * You can use HAL_RCC_GetClockConfig() function to know which clock is
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599 * currently used as system clock source.
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600 * @note Depending on the device voltage range, the software has to set correctly
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601 * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
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602 * (for more details refer to section above "Initialization/de-initialization functions")
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605 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
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607 uint32_t tickstart = 0;
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609 /* Check the parameters */
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610 assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
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611 assert_param(IS_FLASH_LATENCY(FLatency));
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613 /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
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614 must be correctly programmed according to the frequency of the CPU clock
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615 (HCLK) and the supply voltage of the device. */
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617 /* Increasing the CPU frequency */
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618 if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
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620 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
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621 __HAL_FLASH_SET_LATENCY(FLatency);
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623 /* Check that the new number of wait states is taken into account to access the Flash
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624 memory by reading the FLASH_ACR register */
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625 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
\r
630 /*-------------------------- HCLK Configuration --------------------------*/
\r
631 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
\r
633 assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
\r
634 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
\r
637 /*------------------------- SYSCLK Configuration ---------------------------*/
\r
638 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
\r
640 assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
\r
642 /* HSE is selected as System Clock Source */
\r
643 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
\r
645 /* Check the HSE ready flag */
\r
646 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
\r
651 /* PLL is selected as System Clock Source */
\r
652 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
\r
654 /* Check the PLL ready flag */
\r
655 if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
\r
660 /* HSI is selected as System Clock Source */
\r
663 /* Check the HSI ready flag */
\r
664 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
\r
670 __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
\r
671 /* Get Start Tick*/
\r
672 tickstart = HAL_GetTick();
\r
674 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
\r
676 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
\r
678 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
\r
680 return HAL_TIMEOUT;
\r
684 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
\r
686 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
\r
688 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
\r
690 return HAL_TIMEOUT;
\r
696 while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
\r
698 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
\r
700 return HAL_TIMEOUT;
\r
706 /* Decreasing the CPU frequency */
\r
709 /*-------------------------- HCLK Configuration --------------------------*/
\r
710 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
\r
712 assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
\r
713 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
\r
716 /*------------------------- SYSCLK Configuration -------------------------*/
\r
717 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
\r
719 assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
\r
721 /* HSE is selected as System Clock Source */
\r
722 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
\r
724 /* Check the HSE ready flag */
\r
725 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
\r
730 /* PLL is selected as System Clock Source */
\r
731 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
\r
733 /* Check the PLL ready flag */
\r
734 if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
\r
739 /* HSI is selected as System Clock Source */
\r
742 /* Check the HSI ready flag */
\r
743 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
\r
748 __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
\r
749 /* Get Start Tick*/
\r
750 tickstart = HAL_GetTick();
\r
752 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
\r
754 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
\r
756 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
\r
758 return HAL_TIMEOUT;
\r
762 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
\r
764 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
\r
766 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
\r
768 return HAL_TIMEOUT;
\r
774 while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
\r
776 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
\r
778 return HAL_TIMEOUT;
\r
784 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
\r
785 __HAL_FLASH_SET_LATENCY(FLatency);
\r
787 /* Check that the new number of wait states is taken into account to access the Flash
\r
788 memory by reading the FLASH_ACR register */
\r
789 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
\r
795 /*-------------------------- PCLK1 Configuration ---------------------------*/
\r
796 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
\r
798 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
\r
799 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
\r
802 /*-------------------------- PCLK2 Configuration ---------------------------*/
\r
803 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
\r
805 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
\r
806 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
\r
809 /* Configure the source of time base considering new system clocks settings*/
\r
810 HAL_InitTick (TICK_INT_PRIORITY);
\r
819 /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
\r
820 * @brief RCC clocks control functions
\r
823 ===============================================================================
\r
824 ##### Peripheral Control functions #####
\r
825 ===============================================================================
\r
827 This subsection provides a set of functions allowing to control the RCC Clocks
\r
835 * @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
\r
836 * @note PA8/PC9 should be configured in alternate function mode.
\r
837 * @param RCC_MCOx: specifies the output direction for the clock source.
\r
838 * This parameter can be one of the following values:
\r
839 * @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).
\r
840 * @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).
\r
841 * @param RCC_MCOSource: specifies the clock source to output.
\r
842 * This parameter can be one of the following values:
\r
843 * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
\r
844 * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
\r
845 * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
\r
846 * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
\r
847 * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
\r
848 * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source
\r
849 * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
\r
850 * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
\r
851 * @param RCC_MCODiv: specifies the MCOx prescaler.
\r
852 * This parameter can be one of the following values:
\r
853 * @arg RCC_MCODIV_1: no division applied to MCOx clock
\r
854 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
\r
855 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
\r
856 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
\r
857 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
\r
860 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
\r
862 GPIO_InitTypeDef GPIO_InitStruct;
\r
863 /* Check the parameters */
\r
864 assert_param(IS_RCC_MCO(RCC_MCOx));
\r
865 assert_param(IS_RCC_MCODIV(RCC_MCODiv));
\r
867 if(RCC_MCOx == RCC_MCO1)
\r
869 assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
\r
871 /* MCO1 Clock Enable */
\r
874 /* Configure the MCO1 pin in alternate function mode */
\r
875 GPIO_InitStruct.Pin = MCO1_PIN;
\r
876 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
\r
877 GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
\r
878 GPIO_InitStruct.Pull = GPIO_NOPULL;
\r
879 GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
\r
880 HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
\r
882 /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */
\r
883 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));
\r
887 assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
\r
889 /* MCO2 Clock Enable */
\r
892 /* Configure the MCO2 pin in alternate function mode */
\r
893 GPIO_InitStruct.Pin = MCO2_PIN;
\r
894 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
\r
895 GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
\r
896 GPIO_InitStruct.Pull = GPIO_NOPULL;
\r
897 GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
\r
898 HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
\r
900 /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */
\r
901 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3)));
\r
906 * @brief Enables the Clock Security System.
\r
907 * @note If a failure is detected on the HSE oscillator clock, this oscillator
\r
908 * is automatically disabled and an interrupt is generated to inform the
\r
909 * software about the failure (Clock Security System Interrupt, CSSI),
\r
910 * allowing the MCU to perform rescue operations. The CSSI is linked to
\r
911 * the Cortex-M7 NMI (Non-Maskable Interrupt) exception vector.
\r
914 void HAL_RCC_EnableCSS(void)
\r
916 SET_BIT(RCC->CR, RCC_CR_CSSON);
\r
920 * @brief Disables the Clock Security System.
\r
923 void HAL_RCC_DisableCSS(void)
\r
925 CLEAR_BIT(RCC->CR, RCC_CR_CSSON);
\r
929 * @brief Returns the SYSCLK frequency
\r
931 * @note The system frequency computed by this function is not the real
\r
932 * frequency in the chip. It is calculated based on the predefined
\r
933 * constant and the selected clock source:
\r
934 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
\r
935 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
\r
936 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
\r
937 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
\r
938 * @note (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value
\r
939 * 16 MHz) but the real value may vary depending on the variations
\r
940 * in voltage and temperature.
\r
941 * @note (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value
\r
942 * 25 MHz), user has to ensure that HSE_VALUE is same as the real
\r
943 * frequency of the crystal used. Otherwise, this function may
\r
944 * have wrong result.
\r
946 * @note The result of this function could be not correct when using fractional
\r
947 * value for HSE crystal.
\r
949 * @note This function can be used by the user application to compute the
\r
950 * baudrate for the communication peripherals or configure other parameters.
\r
952 * @note Each time SYSCLK changes, this function must be called to update the
\r
953 * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
\r
956 * @retval SYSCLK frequency
\r
958 uint32_t HAL_RCC_GetSysClockFreq(void)
\r
960 uint32_t pllm = 0, pllvco = 0, pllp = 0;
\r
961 uint32_t sysclockfreq = 0;
\r
963 /* Get SYSCLK source -------------------------------------------------------*/
\r
964 switch (RCC->CFGR & RCC_CFGR_SWS)
\r
966 case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
\r
968 sysclockfreq = HSI_VALUE;
\r
971 case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
\r
973 sysclockfreq = HSE_VALUE;
\r
976 case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */
\r
978 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
\r
979 SYSCLK = PLL_VCO / PLLP */
\r
980 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
\r
981 if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI)
\r
983 /* HSE used as PLL clock source */
\r
984 pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
\r
988 /* HSI used as PLL clock source */
\r
989 pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
\r
991 pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> POSITION_VAL(RCC_PLLCFGR_PLLP)) + 1 ) *2);
\r
993 sysclockfreq = pllvco/pllp;
\r
998 sysclockfreq = HSI_VALUE;
\r
1002 return sysclockfreq;
\r
1006 * @brief Returns the HCLK frequency
\r
1007 * @note Each time HCLK changes, this function must be called to update the
\r
1008 * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
\r
1010 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
\r
1011 * and updated within this function
\r
1012 * @retval HCLK frequency
\r
1014 uint32_t HAL_RCC_GetHCLKFreq(void)
\r
1016 SystemCoreClock = HAL_RCC_GetSysClockFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
\r
1017 return SystemCoreClock;
\r
1021 * @brief Returns the PCLK1 frequency
\r
1022 * @note Each time PCLK1 changes, this function must be called to update the
\r
1023 * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
\r
1024 * @retval PCLK1 frequency
\r
1026 uint32_t HAL_RCC_GetPCLK1Freq(void)
\r
1028 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
\r
1029 return (HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
\r
1033 * @brief Returns the PCLK2 frequency
\r
1034 * @note Each time PCLK2 changes, this function must be called to update the
\r
1035 * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
\r
1036 * @retval PCLK2 frequency
\r
1038 uint32_t HAL_RCC_GetPCLK2Freq(void)
\r
1040 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
\r
1041 return (HAL_RCC_GetHCLKFreq()>> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
\r
1045 * @brief Configures the RCC_OscInitStruct according to the internal
\r
1046 * RCC configuration registers.
\r
1047 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
\r
1048 * will be configured.
\r
1051 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
\r
1053 /* Set all possible values for the Oscillator type parameter ---------------*/
\r
1054 RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
\r
1056 /* Get the HSE configuration -----------------------------------------------*/
\r
1057 if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
\r
1059 RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
\r
1061 else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
\r
1063 RCC_OscInitStruct->HSEState = RCC_HSE_ON;
\r
1067 RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
\r
1070 /* Get the HSI configuration -----------------------------------------------*/
\r
1071 if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
\r
1073 RCC_OscInitStruct->HSIState = RCC_HSI_ON;
\r
1077 RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
\r
1080 RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
\r
1082 /* Get the LSE configuration -----------------------------------------------*/
\r
1083 if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
\r
1085 RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
\r
1087 else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
\r
1089 RCC_OscInitStruct->LSEState = RCC_LSE_ON;
\r
1093 RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
\r
1096 /* Get the LSI configuration -----------------------------------------------*/
\r
1097 if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
\r
1099 RCC_OscInitStruct->LSIState = RCC_LSI_ON;
\r
1103 RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
\r
1106 /* Get the PLL configuration -----------------------------------------------*/
\r
1107 if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
\r
1109 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
\r
1113 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
\r
1115 RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
\r
1116 RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
\r
1117 RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
\r
1118 RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1) >> POSITION_VAL(RCC_PLLCFGR_PLLP));
\r
1119 RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ));
\r
1123 * @brief Configures the RCC_ClkInitStruct according to the internal
\r
1124 * RCC configuration registers.
\r
1125 * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
\r
1126 * will be configured.
\r
1127 * @param pFLatency: Pointer on the Flash Latency.
\r
1130 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
\r
1132 /* Set all possible values for the Clock type parameter --------------------*/
\r
1133 RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
\r
1135 /* Get the SYSCLK configuration --------------------------------------------*/
\r
1136 RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
\r
1138 /* Get the HCLK configuration ----------------------------------------------*/
\r
1139 RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
\r
1141 /* Get the APB1 configuration ----------------------------------------------*/
\r
1142 RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
\r
1144 /* Get the APB2 configuration ----------------------------------------------*/
\r
1145 RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
\r
1147 /* Get the Flash Wait State (Latency) configuration ------------------------*/
\r
1148 *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
\r
1152 * @brief This function handles the RCC CSS interrupt request.
\r
1153 * @note This API should be called under the NMI_Handler().
\r
1156 void HAL_RCC_NMI_IRQHandler(void)
\r
1158 /* Check RCC CSSF flag */
\r
1159 if(__HAL_RCC_GET_IT(RCC_IT_CSS))
\r
1161 /* RCC Clock Security System interrupt user callback */
\r
1162 HAL_RCC_CSSCallback();
\r
1164 /* Clear RCC CSS pending bit */
\r
1165 __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
\r
1170 * @brief RCC Clock Security System interrupt callback
\r
1173 __weak void HAL_RCC_CSSCallback(void)
\r
1175 /* NOTE : This function Should not be modified, when the callback is needed,
\r
1176 the HAL_RCC_CSSCallback could be implemented in the user file
\r
1188 #endif /* HAL_RCC_MODULE_ENABLED */
\r
1197 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
\r