2 ******************************************************************************
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3 * @file stm32f7xx_hal_spi.c
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4 * @author MCD Application Team
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6 * @date 06-March-2015
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7 * @brief SPI HAL module driver.
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9 * This file provides firmware functions to manage the following
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10 * functionalities of the Serial Peripheral Interface (SPI) peripheral:
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11 * + Initialization and de-initialization functions
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12 * + IO operation functions
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13 * + Peripheral Control functions
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14 * + Peripheral State functions
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16 ==============================================================================
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17 ##### How to use this driver #####
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18 ==============================================================================
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20 The SPI HAL driver can be used as follows:
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22 (#) Declare a SPI_HandleTypeDef handle structure, for example:
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23 SPI_HandleTypeDef hspi;
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25 (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit ()API:
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26 (##) Enable the SPIx interface clock
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27 (##) SPI pins configuration
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28 (+++) Enable the clock for the SPI GPIOs
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29 (+++) Configure these SPI pins as alternate function push-pull
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30 (##) NVIC configuration if you need to use interrupt process
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31 (+++) Configure the SPIx interrupt priority
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32 (+++) Enable the NVIC SPI IRQ handle
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33 (##) DMA Configuration if you need to use DMA process
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34 (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
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35 (+++) Enable the DMAx clock
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36 (+++) Configure the DMA handle parameters
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37 (+++) Configure the DMA Tx or Rx channel
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38 (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
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39 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx channel
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41 (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
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42 management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
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44 (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
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45 (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
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46 by calling the customed HAL_SPI_MspInit() API.
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48 Circular mode restriction:
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49 (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
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50 (##) Master 2Lines RxOnly
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51 (##) Master 1Line Rx
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52 (#) The CRC feature is not managed when the DMA circular mode is enabled
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53 (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
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54 the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
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57 ******************************************************************************
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60 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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62 * Redistribution and use in source and binary forms, with or without modification,
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63 * are permitted provided that the following conditions are met:
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64 * 1. Redistributions of source code must retain the above copyright notice,
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65 * this list of conditions and the following disclaimer.
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66 * 2. Redistributions in binary form must reproduce the above copyright notice,
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67 * this list of conditions and the following disclaimer in the documentation
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68 * and/or other materials provided with the distribution.
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69 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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70 * may be used to endorse or promote products derived from this software
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71 * without specific prior written permission.
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73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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76 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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79 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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80 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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81 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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82 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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84 ******************************************************************************
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87 /* Includes ------------------------------------------------------------------*/
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88 #include "stm32f7xx_hal.h"
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90 /** @addtogroup STM32F7xx_HAL_Driver
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94 /** @defgroup SPI SPI
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95 * @brief SPI HAL module driver
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98 #ifdef HAL_SPI_MODULE_ENABLED
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100 /* Private typedef -----------------------------------------------------------*/
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101 /* Private defines -----------------------------------------------------------*/
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102 /** @defgroup SPI_Private_Constants SPI Private Constants
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105 #define SPI_DEFAULT_TIMEOUT 50
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110 /* Private macro -------------------------------------------------------------*/
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111 /* Private variables ---------------------------------------------------------*/
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112 /* Private function prototypes -----------------------------------------------*/
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113 /** @defgroup SPI_Private_Functions SPI Private Functions
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116 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
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117 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
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118 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
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119 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
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120 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
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121 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
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122 static void SPI_DMAError(DMA_HandleTypeDef *hdma);
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123 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout);
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124 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout);
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125 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
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126 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
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127 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
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128 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
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129 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
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130 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
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131 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
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132 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
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133 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
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134 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
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135 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
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136 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
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137 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
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138 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
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139 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
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140 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
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141 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
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146 /* Exported functions ---------------------------------------------------------*/
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148 /** @defgroup SPI_Exported_Functions SPI Exported Functions
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152 /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
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153 * @brief Initialization and Configuration functions
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156 ===============================================================================
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157 ##### Initialization and de-initialization functions #####
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158 ===============================================================================
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159 [..] This subsection provides a set of functions allowing to initialize and
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160 de-initialize the SPIx peripheral:
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162 (+) User must implement HAL_SPI_MspInit() function in which he configures
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163 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
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165 (+) Call the function HAL_SPI_Init() to configure the selected device with
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166 the selected configuration:
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170 (++) Clock Polarity and Phase
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171 (++) NSS Management
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172 (++) BaudRate Prescaler
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175 (++) CRC Calculation
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176 (++) CRC Polynomial if CRC enabled
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177 (++) CRC Length, used only with Data8 and Data16
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178 (++) FIFO reception threshold
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180 (+) Call the function HAL_SPI_DeInit() to restore the default configuration
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181 of the selected SPIx peripheral.
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188 * @brief Initializes the SPI according to the specified parameters
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189 * in the SPI_InitTypeDef and create the associated handle.
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190 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
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191 * the configuration information for SPI module.
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192 * @retval HAL status
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194 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
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198 /* Check the SPI handle allocation */
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204 /* Check the parameters */
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205 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
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206 assert_param(IS_SPI_MODE(hspi->Init.Mode));
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207 assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
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208 assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
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209 assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
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210 assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
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211 assert_param(IS_SPI_NSS(hspi->Init.NSS));
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212 assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
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213 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
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214 assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
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215 assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
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216 assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
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217 assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
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218 assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
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220 if(hspi->State == HAL_SPI_STATE_RESET)
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222 /* Allocate lock resource and initialize it */
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223 hspi->Lock = HAL_UNLOCKED;
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225 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
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226 HAL_SPI_MspInit(hspi);
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229 hspi->State = HAL_SPI_STATE_BUSY;
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231 /* Disable the selected SPI peripheral */
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232 __HAL_SPI_DISABLE(hspi);
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234 /* Align by default the rs fifo threshold on the data size */
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235 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
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237 frxth = SPI_RXFIFO_THRESHOLD_HF;
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241 frxth = SPI_RXFIFO_THRESHOLD_QF;
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244 /* CRC calculation is valid only for 16Bit and 8 Bit */
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245 if(( hspi->Init.DataSize != SPI_DATASIZE_16BIT ) && ( hspi->Init.DataSize != SPI_DATASIZE_8BIT ))
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247 /* CRC must be disabled */
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248 hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
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251 /* Align the CRC Length on the data size */
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252 if( hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
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254 /* CRC Length aligned on the data size : value set by default */
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255 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
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257 hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
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261 hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
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265 /*---------------------------- SPIx CR1 & CR2 Configuration ------------------------*/
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266 /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
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267 Communication speed, First bit, CRC calculation state, CRC Length */
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268 hspi->Instance->CR1 = (hspi->Init.Mode | hspi->Init.Direction |
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269 hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
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270 hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation);
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272 if( hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
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274 hspi->Instance->CR1|= SPI_CR1_CRCL;
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277 /* Configure : NSS management */
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278 /* Configure : Rx Fifo Threshold */
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279 hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode | hspi->Init.NSSPMode |
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280 hspi->Init.DataSize ) | frxth;
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282 /*---------------------------- SPIx CRCPOLY Configuration --------------------*/
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283 /* Configure : CRC Polynomial */
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284 hspi->Instance->CRCPR = hspi->Init.CRCPolynomial;
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286 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
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287 hspi->State= HAL_SPI_STATE_READY;
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293 * @brief DeInitializes the SPI peripheral
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294 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
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295 * the configuration information for SPI module.
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296 * @retval HAL status
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298 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
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300 /* Check the SPI handle allocation */
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306 /* Check the parameters */
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307 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
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309 hspi->State = HAL_SPI_STATE_BUSY;
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311 /* check flag before the SPI disable */
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312 SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, SPI_DEFAULT_TIMEOUT);
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313 SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT);
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314 SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT);
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316 /* Disable the SPI Peripheral Clock */
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317 __HAL_SPI_DISABLE(hspi);
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319 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
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320 HAL_SPI_MspDeInit(hspi);
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322 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
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323 hspi->State = HAL_SPI_STATE_RESET;
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325 __HAL_UNLOCK(hspi);
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331 * @brief SPI MSP Init
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332 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
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333 * the configuration information for SPI module.
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336 __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
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338 /* NOTE : This function should not be modified, when the callback is needed,
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339 the HAL_SPI_MspInit should be implemented in the user file
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344 * @brief SPI MSP DeInit
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345 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
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346 * the configuration information for SPI module.
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349 __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
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351 /* NOTE : This function should not be modified, when the callback is needed,
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352 the HAL_SPI_MspDeInit should be implemented in the user file
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360 /** @defgroup SPI_Exported_Functions_Group2 IO operation functions
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361 * @brief Data transfers functions
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364 ==============================================================================
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365 ##### IO operation functions #####
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366 ===============================================================================
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367 This subsection provides a set of functions allowing to manage the SPI
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370 [..] The SPI supports master and slave mode :
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372 (#) There are two modes of transfer:
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373 (++) Blocking mode: The communication is performed in polling mode.
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374 The HAL status of all data processing is returned by the same function
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375 after finishing transfer.
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376 (++) No-Blocking mode: The communication is performed using Interrupts
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377 or DMA, These APIs return the HAL status.
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378 The end of the data processing will be indicated through the
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379 dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
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381 The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
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382 will be executed respectively at the end of the transmit or Receive process
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383 The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
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385 (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
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386 exist for 1Line (simplex) and 2Lines (full duplex) modes.
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393 * @brief Transmit an amount of data in blocking mode
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394 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
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395 * the configuration information for SPI module.
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396 * @param pData: pointer to data buffer
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397 * @param Size: amount of data to be sent
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398 * @param Timeout: Timeout duration
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399 * @retval HAL status
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401 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
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403 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
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405 /* Process Locked */
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408 if(hspi->State != HAL_SPI_STATE_READY)
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410 hspi->State = HAL_SPI_STATE_READY;
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411 /* Process Unlocked */
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412 __HAL_UNLOCK(hspi);
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416 if((pData == NULL ) || (Size == 0))
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418 hspi->State = HAL_SPI_STATE_READY;
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419 /* Process Unlocked */
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420 __HAL_UNLOCK(hspi);
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424 /* Set the transaction information */
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425 hspi->State = HAL_SPI_STATE_BUSY_TX;
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426 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
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427 hspi->pTxBuffPtr = pData;
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428 hspi->TxXferSize = Size;
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429 hspi->TxXferCount = Size;
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430 hspi->pRxBuffPtr = (uint8_t *)NULL;
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431 hspi->RxXferSize = 0;
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432 hspi->RxXferCount = 0;
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434 /* Configure communication direction : 1Line */
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435 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
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437 SPI_1LINE_TX(hspi);
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440 /* Reset CRC Calculation */
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441 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
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443 SPI_RESET_CRC(hspi);
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446 /* Check if the SPI is already enabled */
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447 if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
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449 /* Enable SPI peripheral */
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450 __HAL_SPI_ENABLE(hspi);
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453 /* Transmit data in 16 Bit mode */
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454 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
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456 /* Transmit data in 16 Bit mode */
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457 while (hspi->TxXferCount > 0)
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459 /* Wait until TXE flag is set to send data */
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460 if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK)
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462 hspi->State = HAL_SPI_STATE_READY;
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463 /* Process Unlocked */
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464 __HAL_UNLOCK(hspi);
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465 return HAL_TIMEOUT;
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467 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
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468 hspi->pTxBuffPtr += sizeof(uint16_t);
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469 hspi->TxXferCount--;
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472 /* Transmit data in 8 Bit mode */
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475 while (hspi->TxXferCount > 0)
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477 if(hspi->TxXferCount != 0x1)
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479 /* Wait until TXE flag is set to send data */
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480 if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK)
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482 hspi->State = HAL_SPI_STATE_READY;
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483 /* Process Unlocked */
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484 __HAL_UNLOCK(hspi);
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485 return HAL_TIMEOUT;
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487 hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
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488 hspi->pTxBuffPtr += sizeof(uint16_t);
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489 hspi->TxXferCount -= 2;
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493 /* Wait until TXE flag is set to send data */
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494 if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK)
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496 return HAL_TIMEOUT;
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498 *((__IO uint8_t*)&hspi->Instance->DR) = (*hspi->pTxBuffPtr++);
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499 hspi->TxXferCount--;
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504 /* Enable CRC Transmission */
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505 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
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507 hspi->Instance->CR1|= SPI_CR1_CRCNEXT;
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510 /* Check the end of the transaction */
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511 if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)
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513 return HAL_TIMEOUT;
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516 /* Clear OVERUN flag in 2 Lines communication mode because received is not read */
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517 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
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519 __HAL_SPI_CLEAR_OVRFLAG(hspi);
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522 hspi->State = HAL_SPI_STATE_READY;
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524 /* Process Unlocked */
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525 __HAL_UNLOCK(hspi);
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527 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
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538 * @brief Receive an amount of data in blocking mode
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539 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
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540 * the configuration information for SPI module.
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541 * @param pData: pointer to data buffer
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542 * @param Size: amount of data to be received
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543 * @param Timeout: Timeout duration
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544 * @retval HAL status
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546 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
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548 __IO uint16_t tmpreg;
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550 if(hspi->State != HAL_SPI_STATE_READY)
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555 if((pData == NULL ) || (Size == 0))
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560 if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
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562 /* the receive process is not supported in 2Lines direction master mode */
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563 /* in this case we call the transmitReceive process */
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564 return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout);
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567 /* Process Locked */
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570 hspi->State = HAL_SPI_STATE_BUSY_RX;
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571 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
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572 hspi->pRxBuffPtr = pData;
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573 hspi->RxXferSize = Size;
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574 hspi->RxXferCount = Size;
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575 hspi->pTxBuffPtr = (uint8_t *)NULL;
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576 hspi->TxXferSize = 0;
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577 hspi->TxXferCount = 0;
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579 /* Reset CRC Calculation */
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580 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
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582 SPI_RESET_CRC(hspi);
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583 /* this is done to handle the CRCNEXT before the latest data */
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584 hspi->RxXferCount--;
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587 /* Set the Rx Fido thresold */
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588 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
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590 /* set fiforxthresold according the reception data length: 16bit */
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591 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
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595 /* set fiforxthresold according the reception data length: 8bit */
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596 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
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599 /* Configure communication direction 1Line and enabled SPI if needed */
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600 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
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602 SPI_1LINE_RX(hspi);
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605 /* Check if the SPI is already enabled */
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606 if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
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608 /* Enable SPI peripheral */
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609 __HAL_SPI_ENABLE(hspi);
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612 /* Receive data in 8 Bit mode */
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613 if(hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
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615 while(hspi->RxXferCount > 1)
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617 /* Wait until the RXNE flag */
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618 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
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620 return HAL_TIMEOUT;
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622 (*hspi->pRxBuffPtr++)= *(__IO uint8_t *)&hspi->Instance->DR;
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623 hspi->RxXferCount--;
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626 else /* Receive data in 16 Bit mode */
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628 while(hspi->RxXferCount > 1 )
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630 /* Wait until RXNE flag is reset to read data */
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631 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
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633 return HAL_TIMEOUT;
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635 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
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636 hspi->pRxBuffPtr += sizeof(uint16_t);
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637 hspi->RxXferCount--;
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641 /* Enable CRC Transmission */
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642 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
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644 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
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647 /* Wait until RXNE flag is set */
\r
648 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
\r
650 return HAL_TIMEOUT;
\r
653 /* Receive last data in 16 Bit mode */
\r
654 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
\r
656 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
\r
657 hspi->pRxBuffPtr += sizeof(uint16_t);
\r
659 /* Receive last data in 8 Bit mode */
\r
662 (*hspi->pRxBuffPtr++) = *(__IO uint8_t *)&hspi->Instance->DR;
\r
664 hspi->RxXferCount--;
\r
666 /* Read CRC from DR to close CRC calculation process */
\r
667 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
\r
669 /* Wait until TXE flag */
\r
670 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
\r
672 /* Erreur on the CRC reception */
\r
673 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
\r
675 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
\r
677 tmpreg = hspi->Instance->DR;
\r
678 UNUSED(tmpreg); /* To avoid GCC warning */
\r
682 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
\r
683 UNUSED(tmpreg); /* To avoid GCC warning */
\r
685 if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
\r
687 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
\r
689 /* Erreur on the CRC reception */
\r
690 hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
\r
692 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
\r
693 UNUSED(tmpreg); /* To avoid GCC warning */
\r
698 /* Check the end of the transaction */
\r
699 if(SPI_EndRxTransaction(hspi,Timeout) != HAL_OK)
\r
701 return HAL_TIMEOUT;
\r
704 hspi->State = HAL_SPI_STATE_READY;
\r
706 /* Check if CRC error occurred */
\r
707 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
\r
709 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
\r
710 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
\r
712 /* Process Unlocked */
\r
713 __HAL_UNLOCK(hspi);
\r
717 /* Process Unlocked */
\r
718 __HAL_UNLOCK(hspi);
\r
720 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
\r
731 * @brief Transmit and Receive an amount of data in blocking mode
\r
732 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
\r
733 * the configuration information for SPI module.
\r
734 * @param pTxData: pointer to transmission data buffer
\r
735 * @param pRxData: pointer to reception data buffer
\r
736 * @param Size: amount of data to be sent and received
\r
737 * @param Timeout: Timeout duration
\r
738 * @retval HAL status
\r
740 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
\r
742 __IO uint16_t tmpreg = 0;
\r
743 uint32_t tickstart = HAL_GetTick();
\r
745 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
\r
747 if(hspi->State != HAL_SPI_STATE_READY)
\r
752 if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
\r
758 /* Process Locked */
\r
761 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
\r
762 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
\r
763 hspi->pRxBuffPtr = pRxData;
\r
764 hspi->RxXferCount = Size;
\r
765 hspi->RxXferSize = Size;
\r
766 hspi->pTxBuffPtr = pTxData;
\r
767 hspi->TxXferCount = Size;
\r
768 hspi->TxXferSize = Size;
\r
770 /* Reset CRC Calculation */
\r
771 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
\r
773 SPI_RESET_CRC(hspi);
\r
776 /* Set the Rx Fido threshold */
\r
777 if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1))
\r
779 /* set fiforxthreshold according the reception data length: 16bit */
\r
780 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
\r
784 /* set fiforxthreshold according the reception data length: 8bit */
\r
785 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
\r
788 /* Check if the SPI is already enabled */
\r
789 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
\r
791 /* Enable SPI peripheral */
\r
792 __HAL_SPI_ENABLE(hspi);
\r
795 /* Transmit and Receive data in 16 Bit mode */
\r
796 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
\r
798 while ((hspi->TxXferCount > 0 ) || (hspi->RxXferCount > 0))
\r
800 /* Check TXE flag */
\r
801 if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))
\r
803 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
\r
804 hspi->pTxBuffPtr += sizeof(uint16_t);
\r
805 hspi->TxXferCount--;
\r
807 /* Enable CRC Transmission */
\r
808 if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
\r
810 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
\r
814 /* Check RXNE flag */
\r
815 if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
\r
817 *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
\r
818 hspi->pRxBuffPtr += sizeof(uint16_t);
\r
819 hspi->RxXferCount--;
\r
821 if(Timeout != HAL_MAX_DELAY)
\r
823 if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
\r
825 hspi->State = HAL_SPI_STATE_READY;
\r
826 __HAL_UNLOCK(hspi);
\r
827 return HAL_TIMEOUT;
\r
832 /* Transmit and Receive data in 8 Bit mode */
\r
835 while((hspi->TxXferCount > 0) || (hspi->RxXferCount > 0))
\r
837 /* check TXE flag */
\r
838 if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))
\r
840 if(hspi->TxXferCount > 1)
\r
842 hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
\r
843 hspi->pTxBuffPtr += sizeof(uint16_t);
\r
844 hspi->TxXferCount -= 2;
\r
848 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
\r
849 hspi->TxXferCount--;
\r
852 /* Enable CRC Transmission */
\r
853 if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
\r
855 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
\r
859 /* Wait until RXNE flag is reset */
\r
860 if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
\r
862 if(hspi->RxXferCount > 1)
\r
864 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
\r
865 hspi->pRxBuffPtr += sizeof(uint16_t);
\r
866 hspi->RxXferCount -= 2;
\r
867 if(hspi->RxXferCount <= 1)
\r
869 /* set fiforxthresold before to switch on 8 bit data size */
\r
870 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
\r
875 (*hspi->pRxBuffPtr++) = *(__IO uint8_t *)&hspi->Instance->DR;
\r
876 hspi->RxXferCount--;
\r
879 if(Timeout != HAL_MAX_DELAY)
\r
881 if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
\r
883 hspi->State = HAL_SPI_STATE_READY;
\r
884 __HAL_UNLOCK(hspi);
\r
885 return HAL_TIMEOUT;
\r
891 /* Read CRC from DR to close CRC calculation process */
\r
892 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
\r
894 /* Wait until TXE flag */
\r
895 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
\r
897 /* Erreur on the CRC reception */
\r
898 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
\r
901 if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
\r
903 tmpreg = hspi->Instance->DR;
\r
904 UNUSED(tmpreg); /* To avoid GCC warning */
\r
908 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
\r
909 UNUSED(tmpreg); /* To avoid GCC warning */
\r
911 if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
\r
913 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
\r
915 /* Erreur on the CRC reception */
\r
916 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
\r
918 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
\r
919 UNUSED(tmpreg); /* To avoid GCC warning */
\r
924 /* Check the end of the transaction */
\r
925 if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)
\r
927 return HAL_TIMEOUT;
\r
930 hspi->State = HAL_SPI_STATE_READY;
\r
932 /* Check if CRC error occurred */
\r
933 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
\r
935 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
\r
936 /* Clear CRC Flag */
\r
937 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
\r
939 /* Process Unlocked */
\r
940 __HAL_UNLOCK(hspi);
\r
945 /* Process Unlocked */
\r
946 __HAL_UNLOCK(hspi);
\r
948 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
\r
959 * @brief Transmit an amount of data in no-blocking mode with Interrupt
\r
960 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
\r
961 * the configuration information for SPI module.
\r
962 * @param pData: pointer to data buffer
\r
963 * @param Size: amount of data to be sent
\r
964 * @retval HAL status
\r
966 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
\r
968 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
\r
970 if(hspi->State == HAL_SPI_STATE_READY)
\r
972 if((pData == NULL) || (Size == 0))
\r
977 /* Process Locked */
\r
980 hspi->State = HAL_SPI_STATE_BUSY_TX;
\r
981 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
\r
982 hspi->pTxBuffPtr = pData;
\r
983 hspi->TxXferSize = Size;
\r
984 hspi->TxXferCount = Size;
\r
985 hspi->pRxBuffPtr = NULL;
\r
986 hspi->RxXferSize = 0;
\r
987 hspi->RxXferCount = 0;
\r
989 /* Set the function for IT treatement */
\r
990 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
\r
992 hspi->RxISR = NULL;
\r
993 hspi->TxISR = SPI_TxISR_16BIT;
\r
997 hspi->RxISR = NULL;
\r
998 hspi->TxISR = SPI_TxISR_8BIT;
\r
1001 /* Configure communication direction : 1Line */
\r
1002 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
\r
1004 SPI_1LINE_TX(hspi);
\r
1007 /* Reset CRC Calculation */
\r
1008 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
\r
1010 SPI_RESET_CRC(hspi);
\r
1013 /* Enable TXE and ERR interrupt */
\r
1014 __HAL_SPI_ENABLE_IT(hspi,(SPI_IT_TXE));
\r
1016 /* Process Unlocked */
\r
1017 __HAL_UNLOCK(hspi);
\r
1019 /* Note : The SPI must be enabled after unlocking current process
\r
1020 to avoid the risk of SPI interrupt handle execution before current
\r
1023 /* Check if the SPI is already enabled */
\r
1024 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
\r
1026 /* Enable SPI peripheral */
\r
1027 __HAL_SPI_ENABLE(hspi);
\r
1039 * @brief Receive an amount of data in no-blocking mode with Interrupt
\r
1040 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
\r
1041 * the configuration information for SPI module.
\r
1042 * @param pData: pointer to data buffer
\r
1043 * @param Size: amount of data to be sent
\r
1044 * @retval HAL status
\r
1046 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
\r
1048 if(hspi->State == HAL_SPI_STATE_READY)
\r
1050 if((pData == NULL) || (Size == 0))
\r
1052 return HAL_ERROR;
\r
1055 /* Process Locked */
\r
1058 /* Configure communication */
\r
1059 hspi->State = HAL_SPI_STATE_BUSY_RX;
\r
1060 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
\r
1061 hspi->pRxBuffPtr = pData;
\r
1062 hspi->RxXferSize = Size;
\r
1063 hspi->RxXferCount = Size;
\r
1064 hspi->pTxBuffPtr = NULL;
\r
1065 hspi->TxXferSize = 0;
\r
1066 hspi->TxXferCount = 0;
\r
1068 if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
\r
1070 /* Process Unlocked */
\r
1071 __HAL_UNLOCK(hspi);
\r
1072 /* the receive process is not supported in 2Lines direction master mode */
\r
1073 /* in this we call the transmitReceive process */
\r
1074 return HAL_SPI_TransmitReceive_IT(hspi,pData,pData,Size);
\r
1077 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
\r
1079 hspi->CRCSize = 1;
\r
1080 if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
\r
1082 hspi->CRCSize = 2;
\r
1087 hspi->CRCSize = 0;
\r
1090 /* check the data size to adapt Rx threshold and the set the function for IT treatment */
\r
1091 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
\r
1093 /* set fiforxthresold according the reception data length: 16 bit */
\r
1094 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
\r
1095 hspi->RxISR = SPI_RxISR_16BIT;
\r
1096 hspi->TxISR = NULL;
\r
1100 /* set fiforxthresold according the reception data length: 8 bit */
\r
1101 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
\r
1102 hspi->RxISR = SPI_RxISR_8BIT;
\r
1103 hspi->TxISR = NULL;
\r
1106 /* Configure communication direction : 1Line */
\r
1107 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
\r
1109 SPI_1LINE_RX(hspi);
\r
1112 /* Reset CRC Calculation */
\r
1113 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
\r
1115 SPI_RESET_CRC(hspi);
\r
1118 /* Enable TXE and ERR interrupt */
\r
1119 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
\r
1121 /* Process Unlocked */
\r
1122 __HAL_UNLOCK(hspi);
\r
1124 /* Note : The SPI must be enabled after unlocking current process
\r
1125 to avoid the risk of SPI interrupt handle execution before current
\r
1128 /* Check if the SPI is already enabled */
\r
1129 if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
\r
1131 /* Enable SPI peripheral */
\r
1132 __HAL_SPI_ENABLE(hspi);
\r
1144 * @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt
\r
1145 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
\r
1146 * the configuration information for SPI module.
\r
1147 * @param pTxData: pointer to transmission data buffer
\r
1148 * @param pRxData: pointer to reception data buffer
\r
1149 * @param Size: amount of data to be sent and received
\r
1150 * @retval HAL status
\r
1152 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
\r
1154 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
\r
1156 if((hspi->State == HAL_SPI_STATE_READY) || \
\r
1157 ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
\r
1159 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
\r
1161 return HAL_ERROR;
\r
1164 /* Process locked */
\r
1167 hspi->CRCSize = 0;
\r
1168 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
\r
1170 hspi->CRCSize = 1;
\r
1171 if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
\r
1173 hspi->CRCSize = 2;
\r
1177 if(hspi->State != HAL_SPI_STATE_BUSY_RX)
\r
1179 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
\r
1182 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
\r
1183 hspi->pTxBuffPtr = pTxData;
\r
1184 hspi->TxXferSize = Size;
\r
1185 hspi->TxXferCount = Size;
\r
1186 hspi->pRxBuffPtr = pRxData;
\r
1187 hspi->RxXferSize = Size;
\r
1188 hspi->RxXferCount = Size;
\r
1190 /* Set the function for IT treatement */
\r
1191 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
\r
1193 hspi->RxISR = SPI_2linesRxISR_16BIT;
\r
1194 hspi->TxISR = SPI_2linesTxISR_16BIT;
\r
1198 hspi->RxISR = SPI_2linesRxISR_8BIT;
\r
1199 hspi->TxISR = SPI_2linesTxISR_8BIT;
\r
1202 /* Reset CRC Calculation */
\r
1203 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
\r
1205 SPI_RESET_CRC(hspi);
\r
1208 /* check if packing mode is enabled and if there is more than 2 data to receive */
\r
1209 if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2))
\r
1211 /* set fiforxthresold according the reception data length: 16 bit */
\r
1212 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
\r
1216 /* set fiforxthresold according the reception data length: 8 bit */
\r
1217 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
\r
1220 /* Enable TXE, RXNE and ERR interrupt */
\r
1221 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
\r
1223 /* Process Unlocked */
\r
1224 __HAL_UNLOCK(hspi);
\r
1226 /* Check if the SPI is already enabled */
\r
1227 if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
\r
1229 /* Enable SPI peripheral */
\r
1230 __HAL_SPI_ENABLE(hspi);
\r
1242 * @brief Transmit an amount of data in no-blocking mode with DMA
\r
1243 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
\r
1244 * the configuration information for SPI module.
\r
1245 * @param pData: pointer to data buffer
\r
1246 * @param Size: amount of data to be sent
\r
1247 * @retval HAL status
\r
1249 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
\r
1251 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
\r
1253 if(hspi->State != HAL_SPI_STATE_READY)
\r
1258 if((pData == NULL) || (Size == 0))
\r
1263 /* Process Locked */
\r
1266 hspi->State = HAL_SPI_STATE_BUSY_TX;
\r
1267 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
\r
1268 hspi->pTxBuffPtr = pData;
\r
1269 hspi->TxXferSize = Size;
\r
1270 hspi->TxXferCount = Size;
\r
1271 hspi->pRxBuffPtr = (uint8_t *)NULL;
\r
1272 hspi->RxXferSize = 0;
\r
1273 hspi->RxXferCount = 0;
\r
1275 /* Configure communication direction : 1Line */
\r
1276 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
\r
1278 SPI_1LINE_TX(hspi);
\r
1281 /* Reset CRC Calculation */
\r
1282 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
\r
1284 SPI_RESET_CRC(hspi);
\r
1287 /* Set the SPI TxDMA Half transfer complete callback */
\r
1288 hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
\r
1290 /* Set the SPI TxDMA transfer complete callback */
\r
1291 hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
\r
1293 /* Set the DMA error callback */
\r
1294 hspi->hdmatx->XferErrorCallback = SPI_DMAError;
\r
1296 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
\r
1297 /* packing mode is enabled only if the DMA setting is HALWORD */
\r
1298 if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
\r
1300 /* Check the even/odd of the data size + crc if enabled */
\r
1301 if((hspi->TxXferCount & 0x1) == 0)
\r
1303 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
\r
1304 hspi->TxXferCount = (hspi->TxXferCount >> 1);
\r
1308 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
\r
1309 hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
\r
1313 /* Enable the Tx DMA channel */
\r
1314 HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
\r
1316 /* Check if the SPI is already enabled */
\r
1317 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
\r
1319 /* Enable SPI peripheral */
\r
1320 __HAL_SPI_ENABLE(hspi);
\r
1323 /* Enable Tx DMA Request */
\r
1324 hspi->Instance->CR2 |= SPI_CR2_TXDMAEN;
\r
1326 /* Process Unlocked */
\r
1327 __HAL_UNLOCK(hspi);
\r
1333 * @brief Receive an amount of data in no-blocking mode with DMA
\r
1334 * @param hspi: SPI handle
\r
1335 * @param pData: pointer to data buffer
\r
1336 * @param Size: amount of data to be sent
\r
1337 * @retval HAL status
\r
1339 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
\r
1341 if(hspi->State != HAL_SPI_STATE_READY)
\r
1346 if((pData == NULL) || (Size == 0))
\r
1351 /* Process Locked */
\r
1354 hspi->State = HAL_SPI_STATE_BUSY_RX;
\r
1355 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
\r
1356 hspi->pRxBuffPtr = pData;
\r
1357 hspi->RxXferSize = Size;
\r
1358 hspi->RxXferCount = Size;
\r
1359 hspi->pTxBuffPtr = (uint8_t *)NULL;
\r
1360 hspi->TxXferSize = 0;
\r
1361 hspi->TxXferCount = 0;
\r
1363 if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
\r
1365 /* Process Unlocked */
\r
1366 __HAL_UNLOCK(hspi);
\r
1367 /* the receive process is not supported in 2Lines direction master mode */
\r
1368 /* in this case we call the transmitReceive process */
\r
1369 return HAL_SPI_TransmitReceive_DMA(hspi,pData,pData,Size);
\r
1372 /* Configure communication direction : 1Line */
\r
1373 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
\r
1375 SPI_1LINE_RX(hspi);
\r
1378 /* Reset CRC Calculation */
\r
1379 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
\r
1381 SPI_RESET_CRC(hspi);
\r
1384 /* packing mode management is enabled by the DMA settings */
\r
1385 if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
\r
1387 /* Process Locked */
\r
1388 __HAL_UNLOCK(hspi);
\r
1389 /* Restriction the DMA data received is not allowed in this mode */
\r
1393 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
\r
1394 if( hspi->Init.DataSize > SPI_DATASIZE_8BIT)
\r
1396 /* set fiforxthresold according the reception data length: 16bit */
\r
1397 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
\r
1401 /* set fiforxthresold according the reception data length: 8bit */
\r
1402 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
\r
1405 /* Set the SPI RxDMA Half transfer complete callback */
\r
1406 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
\r
1408 /* Set the SPI Rx DMA transfer complete callback */
\r
1409 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
\r
1411 /* Set the DMA error callback */
\r
1412 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
\r
1414 /* Enable Rx DMA Request */
\r
1415 hspi->Instance->CR2 |= SPI_CR2_RXDMAEN;
\r
1417 /* Enable the Rx DMA channel */
\r
1418 HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
\r
1420 /* Process Unlocked */
\r
1421 __HAL_UNLOCK(hspi);
\r
1423 /* Check if the SPI is already enabled */
\r
1424 if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
\r
1426 /* Enable SPI peripheral */
\r
1427 __HAL_SPI_ENABLE(hspi);
\r
1434 * @brief Transmit and Receive an amount of data in no-blocking mode with DMA
\r
1435 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
\r
1436 * the configuration information for SPI module.
\r
1437 * @param pTxData: pointer to transmission data buffer
\r
1438 * @param pRxData: pointer to reception data buffer
\r
1439 * @note When the CRC feature is enabled the pRxData Length must be Size + 1
\r
1440 * @param Size: amount of data to be sent
\r
1441 * @retval HAL status
\r
1443 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
\r
1445 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
\r
1447 if((hspi->State == HAL_SPI_STATE_READY) ||
\r
1448 ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
\r
1450 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
\r
1452 return HAL_ERROR;
\r
1455 /* Process locked */
\r
1458 /* check if the transmit Receive function is not called by a receive master */
\r
1459 if(hspi->State != HAL_SPI_STATE_BUSY_RX)
\r
1461 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
\r
1464 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
\r
1465 hspi->pTxBuffPtr = (uint8_t *)pTxData;
\r
1466 hspi->TxXferSize = Size;
\r
1467 hspi->TxXferCount = Size;
\r
1468 hspi->pRxBuffPtr = (uint8_t *)pRxData;
\r
1469 hspi->RxXferSize = Size;
\r
1470 hspi->RxXferCount = Size;
\r
1472 /* Reset CRC Calculation + increase the rxsize */
\r
1473 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
\r
1475 SPI_RESET_CRC(hspi);
\r
1478 /* Reset the threshold bit */
\r
1479 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
\r
1480 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
\r
1482 /* the packing mode management is enabled by the DMA settings according the spi data size */
\r
1483 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
\r
1485 /* set fiforxthreshold according the reception data length: 16bit */
\r
1486 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
\r
1490 /* set fiforxthresold according the reception data length: 8bit */
\r
1491 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
\r
1493 if(hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
\r
1495 if((hspi->TxXferSize & 0x1) == 0x0 )
\r
1497 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
\r
1498 hspi->TxXferCount = hspi->TxXferCount >> 1;
\r
1502 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
\r
1503 hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
\r
1507 if(hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
\r
1509 /* set fiforxthresold according the reception data length: 16bit */
\r
1510 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
\r
1512 /* Size must include the CRC length */
\r
1513 if((hspi->RxXferCount & 0x1) == 0x0 )
\r
1515 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
\r
1516 hspi->RxXferCount = hspi->RxXferCount >> 1;
\r
1520 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
\r
1521 hspi->RxXferCount = (hspi->RxXferCount >> 1) + 1;
\r
1526 /* Set the SPI Rx DMA transfer complete callback because the last generated transfer request is
\r
1527 the reception request (RXNE) */
\r
1528 if(hspi->State == HAL_SPI_STATE_BUSY_RX)
\r
1530 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
\r
1531 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
\r
1535 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
\r
1536 hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
\r
1538 /* Set the DMA error callback */
\r
1539 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
\r
1541 /* Enable Rx DMA Request */
\r
1542 hspi->Instance->CR2 |= SPI_CR2_RXDMAEN;
\r
1544 /* Enable the Rx DMA channel */
\r
1545 HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t) hspi->pRxBuffPtr, hspi->RxXferCount);
\r
1547 /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
\r
1548 is performed in DMA reception complete callback */
\r
1549 hspi->hdmatx->XferHalfCpltCallback = NULL;
\r
1550 hspi->hdmatx->XferCpltCallback = NULL;
\r
1552 /* Set the DMA error callback */
\r
1553 hspi->hdmatx->XferErrorCallback = SPI_DMAError;
\r
1555 /* Enable the Tx DMA channel */
\r
1556 HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
\r
1558 /* Check if the SPI is already enabled */
\r
1559 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
\r
1561 /* Enable SPI peripheral */
\r
1562 __HAL_SPI_ENABLE(hspi);
\r
1565 /* Enable Tx DMA Request */
\r
1566 hspi->Instance->CR2 |= SPI_CR2_TXDMAEN;
\r
1568 /* Process Unlocked */
\r
1569 __HAL_UNLOCK(hspi);
\r
1580 * @brief Pauses the DMA Transfer.
\r
1581 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
\r
1582 * the configuration information for the specified SPI module.
\r
1583 * @retval HAL status
\r
1585 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
\r
1587 /* Process Locked */
\r
1590 /* Disable the SPI DMA Tx & Rx requests */
\r
1591 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
\r
1593 /* Process Unlocked */
\r
1594 __HAL_UNLOCK(hspi);
\r
1600 * @brief Resumes the DMA Transfer.
\r
1601 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
\r
1602 * the configuration information for the specified SPI module.
\r
1603 * @retval HAL status
\r
1605 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
\r
1607 /* Process Locked */
\r
1610 /* Enable the SPI DMA Tx & Rx requests */
\r
1611 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
\r
1613 /* Process Unlocked */
\r
1614 __HAL_UNLOCK(hspi);
\r
1620 * @brief Stops the DMA Transfer.
\r
1621 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
\r
1622 * the configuration information for the specified SPI module.
\r
1623 * @retval HAL status
\r
1625 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
\r
1627 /* The Lock is not implemented on this API to allow the user application
\r
1628 to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
\r
1629 when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
\r
1630 and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
\r
1633 /* Abort the SPI DMA tx Stream */
\r
1634 if(hspi->hdmatx != NULL)
\r
1636 HAL_DMA_Abort(hspi->hdmatx);
\r
1638 /* Abort the SPI DMA rx Stream */
\r
1639 if(hspi->hdmarx != NULL)
\r
1641 HAL_DMA_Abort(hspi->hdmarx);
\r
1644 /* Disable the SPI DMA Tx & Rx requests */
\r
1645 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
\r
1646 hspi->State = HAL_SPI_STATE_READY;
\r
1651 * @brief This function handles SPI interrupt request.
\r
1652 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
\r
1653 * the configuration information for the specified SPI module.
\r
1656 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
\r
1658 /* SPI in mode Receiver ----------------------------------------------------*/
\r
1659 if((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) == RESET) &&
\r
1660 (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE) != RESET) && (__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) != RESET))
\r
1662 hspi->RxISR(hspi);
\r
1666 /* SPI in mode Tramitter ---------------------------------------------------*/
\r
1667 if((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE) != RESET) && (__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) != RESET))
\r
1669 hspi->TxISR(hspi);
\r
1673 /* SPI in Erreur Treatment ---------------------------------------------------*/
\r
1674 if((hspi->Instance->SR & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET)
\r
1676 /* SPI Overrun error interrupt occured -------------------------------------*/
\r
1677 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET)
\r
1679 if(hspi->State != HAL_SPI_STATE_BUSY_TX)
\r
1681 hspi->ErrorCode |= HAL_SPI_ERROR_OVR;
\r
1682 __HAL_SPI_CLEAR_OVRFLAG(hspi);
\r
1690 /* SPI Mode Fault error interrupt occured -------------------------------------*/
\r
1691 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET)
\r
1693 hspi->ErrorCode |= HAL_SPI_ERROR_MODF;
\r
1694 __HAL_SPI_CLEAR_MODFFLAG(hspi);
\r
1697 /* SPI Frame error interrupt occured ----------------------------------------*/
\r
1698 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_FRE) != RESET)
\r
1700 hspi->ErrorCode |= HAL_SPI_ERROR_FRE;
\r
1701 __HAL_SPI_CLEAR_FREFLAG(hspi);
\r
1704 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
\r
1705 hspi->State = HAL_SPI_STATE_READY;
\r
1706 HAL_SPI_ErrorCallback(hspi);
\r
1713 * @brief Tx Transfer completed callback
\r
1714 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
\r
1715 * the configuration information for SPI module.
\r
1718 __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
\r
1720 /* NOTE : This function should not be modified, when the callback is needed,
\r
1721 the HAL_SPI_TxCpltCallback should be implemented in the user file
\r
1726 * @brief Rx Transfer completed callbacks
\r
1727 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
\r
1728 * the configuration information for SPI module.
\r
1731 __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
\r
1733 /* NOTE : This function should not be modified, when the callback is needed,
\r
1734 the HAL_SPI_RxCpltCallback should be implemented in the user file
\r
1739 * @brief Tx and Rx Transfer completed callback
\r
1740 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
\r
1741 * the configuration information for SPI module.
\r
1744 __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
\r
1746 /* NOTE : This function should not be modified, when the callback is needed,
\r
1747 the HAL_SPI_TxRxCpltCallback should be implemented in the user file
\r
1752 * @brief Tx Half Transfer completed callback
\r
1753 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
\r
1754 * the configuration information for SPI module.
\r
1757 __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
\r
1759 /* NOTE : This function should not be modified, when the callback is needed,
\r
1760 the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
\r
1765 * @brief Rx Half Transfer completed callback
\r
1766 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
\r
1767 * the configuration information for SPI module.
\r
1770 __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
\r
1772 /* NOTE : This function should not be modified, when the callback is needed,
\r
1773 the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
\r
1778 * @brief Tx and Rx Half Transfer callback
\r
1779 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
\r
1780 * the configuration information for SPI module.
\r
1783 __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
\r
1785 /* NOTE : This function should not be modified, when the callback is needed,
\r
1786 the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
\r
1791 * @brief SPI error callback
\r
1792 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
\r
1793 * the configuration information for SPI module.
\r
1796 __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
\r
1798 /* NOTE : This function should not be modified, when the callback is needed,
\r
1799 the HAL_SPI_ErrorCallback should be implemented in the user file
\r
1801 /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
\r
1802 and user can use HAL_SPI_GetError() API to check the latest error occurred
\r
1822 /** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
\r
1823 * @brief SPI control functions
\r
1826 ===============================================================================
\r
1827 ##### Peripheral State and Errors functions #####
\r
1828 ===============================================================================
\r
1830 This subsection provides a set of functions allowing to control the SPI.
\r
1831 (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
\r
1832 (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
\r
1838 * @brief Return the SPI state
\r
1839 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
\r
1840 * the configuration information for SPI module.
\r
1841 * @retval SPI state
\r
1843 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
\r
1845 return hspi->State;
\r
1849 * @brief Return the SPI error code
\r
1850 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
\r
1851 * the configuration information for SPI module.
\r
1852 * @retval SPI error code in bitmap format
\r
1854 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
\r
1856 return hspi->ErrorCode;
\r
1867 /** @addtogroup SPI_Private_Functions
\r
1868 * @brief Private functions
\r
1872 * @brief DMA SPI transmit process complete callback
\r
1873 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
\r
1874 * the configuration information for the specified DMA module.
\r
1877 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
\r
1879 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
\r
1881 /* DMA Normal Mode */
\r
1882 if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
\r
1884 /* Disable Tx DMA Request */
\r
1885 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
\r
1887 /* Clear OVERUN flag in 2 Lines communication mode because received data is not read */
\r
1888 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
\r
1890 __HAL_SPI_CLEAR_OVRFLAG(hspi);
\r
1893 hspi->TxXferCount = 0;
\r
1894 hspi->State = HAL_SPI_STATE_READY;
\r
1896 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
\r
1898 HAL_SPI_ErrorCallback(hspi);
\r
1902 HAL_SPI_TxCpltCallback(hspi);
\r
1906 * @brief DMA SPI receive process complete callback
\r
1907 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
\r
1908 * the configuration information for the specified DMA module.
\r
1911 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
\r
1913 __IO uint16_t tmpreg;
\r
1914 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
\r
1916 /* CRC handling */
\r
1917 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
\r
1919 /* Wait until TXE flag */
\r
1920 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
\r
1922 /* Erreur on the CRC reception */
\r
1923 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
\r
1925 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
\r
1927 tmpreg = hspi->Instance->DR;
\r
1928 UNUSED(tmpreg); /* To avoid GCC warning */
\r
1932 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
\r
1933 UNUSED(tmpreg); /* To avoid GCC warning */
\r
1935 if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
\r
1937 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
\r
1939 /* Erreur on the CRC reception */
\r
1940 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
\r
1942 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
\r
1943 UNUSED(tmpreg); /* To avoid GCC warning */
\r
1948 /* Disable Rx DMA Request */
\r
1949 hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
\r
1950 /* Disable Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
\r
1951 hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
\r
1953 /* Check the end of the transaction */
\r
1954 SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
\r
1956 hspi->RxXferCount = 0;
\r
1957 hspi->State = HAL_SPI_STATE_READY;
\r
1959 /* Check if CRC error occurred */
\r
1960 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
\r
1962 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
\r
1963 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
\r
1964 HAL_SPI_RxCpltCallback(hspi);
\r
1968 if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
\r
1970 HAL_SPI_RxCpltCallback(hspi);
\r
1974 HAL_SPI_ErrorCallback(hspi);
\r
1980 * @brief DMA SPI transmit receive process complete callback
\r
1981 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
\r
1982 * the configuration information for the specified DMA module.
\r
1985 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
\r
1987 __IO int16_t tmpreg;
\r
1988 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
\r
1990 /* CRC handling */
\r
1991 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
\r
1993 if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
\r
1995 if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
\r
1997 /* Error on the CRC reception */
\r
1998 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
\r
2000 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
\r
2001 UNUSED(tmpreg); /* To avoid GCC warning */
\r
2005 if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
\r
2007 /* Erreur on the CRC reception */
\r
2008 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
\r
2010 tmpreg = hspi->Instance->DR;
\r
2011 UNUSED(tmpreg); /* To avoid GCC warning */
\r
2015 /* Check the end of the transaction */
\r
2016 SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
\r
2018 /* Disable Tx DMA Request */
\r
2019 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
\r
2021 /* Disable Rx DMA Request */
\r
2022 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
\r
2024 hspi->TxXferCount = 0;
\r
2025 hspi->RxXferCount = 0;
\r
2026 hspi->State = HAL_SPI_STATE_READY;
\r
2028 /* Check if CRC error occurred */
\r
2029 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
\r
2031 hspi->ErrorCode = HAL_SPI_ERROR_CRC;
\r
2032 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
\r
2033 HAL_SPI_ErrorCallback(hspi);
\r
2037 if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
\r
2039 HAL_SPI_TxRxCpltCallback(hspi);
\r
2043 HAL_SPI_ErrorCallback(hspi);
\r
2049 * @brief DMA SPI half transmit process complete callback
\r
2050 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
\r
2051 * the configuration information for the specified DMA module.
\r
2054 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
\r
2056 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
\r
2058 HAL_SPI_TxHalfCpltCallback(hspi);
\r
2062 * @brief DMA SPI half receive process complete callback
\r
2063 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
\r
2064 * the configuration information for the specified DMA module.
\r
2067 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
\r
2069 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
\r
2071 HAL_SPI_RxHalfCpltCallback(hspi);
\r
2075 * @brief DMA SPI Half transmit receive process complete callback
\r
2076 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
\r
2077 * the configuration information for the specified DMA module.
\r
2080 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
\r
2082 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
\r
2084 HAL_SPI_TxRxHalfCpltCallback(hspi);
\r
2088 * @brief DMA SPI communication error callback
\r
2089 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
\r
2090 * the configuration information for the specified DMA module.
\r
2093 static void SPI_DMAError(DMA_HandleTypeDef *hdma)
\r
2095 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
\r
2097 /* Stop the disable DMA transfer on SPI side */
\r
2098 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
\r
2100 hspi->ErrorCode|= HAL_SPI_ERROR_DMA;
\r
2101 hspi->State = HAL_SPI_STATE_READY;
\r
2102 HAL_SPI_ErrorCallback(hspi);
\r
2106 * @brief Rx Handler for Transmit and Receive in Interrupt mode
\r
2107 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
\r
2108 * the configuration information for SPI module.
\r
2111 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
\r
2113 /* Receive data in packing mode */
\r
2114 if(hspi->RxXferCount > 1)
\r
2116 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
\r
2117 hspi->pRxBuffPtr += sizeof(uint16_t);
\r
2118 hspi->RxXferCount -= 2;
\r
2119 if(hspi->RxXferCount == 1)
\r
2121 /* set fiforxthresold according the reception data length: 8bit */
\r
2122 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
\r
2125 /* Receive data in 8 Bit mode */
\r
2128 *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR);
\r
2129 hspi->RxXferCount--;
\r
2132 /* check end of the reception */
\r
2133 if(hspi->RxXferCount == 0)
\r
2135 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
\r
2137 hspi->RxISR = SPI_2linesRxISR_8BITCRC;
\r
2141 /* Disable RXNE interrupt */
\r
2142 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
\r
2144 if(hspi->TxXferCount == 0)
\r
2146 SPI_CloseRxTx_ISR(hspi);
\r
2152 * @brief Rx Handler for Transmit and Receive in Interrupt mode
\r
2153 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
\r
2154 * the configuration information for SPI module.
\r
2157 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
\r
2159 __IO uint8_t tmpreg;
\r
2161 tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
\r
2162 UNUSED(tmpreg); /* To avoid GCC warning */
\r
2166 /* check end of the reception */
\r
2167 if(hspi->CRCSize == 0)
\r
2169 /* Disable RXNE interrupt */
\r
2170 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
\r
2172 if(hspi->TxXferCount == 0)
\r
2174 SPI_CloseRxTx_ISR(hspi);
\r
2180 * @brief Tx Handler for Transmit and Receive in Interrupt mode
\r
2181 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
\r
2182 * the configuration information for SPI module.
\r
2185 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
\r
2187 /* Transmit data in packing Bit mode */
\r
2188 if(hspi->TxXferCount >= 2)
\r
2190 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
\r
2191 hspi->pTxBuffPtr += sizeof(uint16_t);
\r
2192 hspi->TxXferCount -= 2;
\r
2194 /* Transmit data in 8 Bit mode */
\r
2197 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
\r
2198 hspi->TxXferCount--;
\r
2201 /* check the end of the transmission */
\r
2202 if(hspi->TxXferCount == 0)
\r
2204 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
\r
2206 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
\r
2208 /* Disable TXE interrupt */
\r
2209 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
\r
2211 if(hspi->RxXferCount == 0)
\r
2213 SPI_CloseRxTx_ISR(hspi);
\r
2219 * @brief Rx 16Bit Handler for Transmit and Receive in Interrupt mode
\r
2220 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
\r
2221 * the configuration information for SPI module.
\r
2224 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
\r
2226 /* Receive data in 16 Bit mode */
\r
2227 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
\r
2228 hspi->pRxBuffPtr += sizeof(uint16_t);
\r
2229 hspi->RxXferCount--;
\r
2231 if(hspi->RxXferCount == 0)
\r
2233 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
\r
2235 hspi->RxISR = SPI_2linesRxISR_16BITCRC;
\r
2239 /* Disable RXNE interrupt */
\r
2240 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
\r
2242 if(hspi->TxXferCount == 0)
\r
2244 SPI_CloseRxTx_ISR(hspi);
\r
2250 * @brief Manage the CRC 16bit receive for Transmit and Receive in Interrupt mode
\r
2251 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
\r
2252 * the configuration information for SPI module.
\r
2255 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
\r
2257 /* Receive data in 16 Bit mode */
\r
2258 __IO uint16_t tmpreg = hspi->Instance->DR;
\r
2259 UNUSED(tmpreg); /* To avoid GCC warning */
\r
2261 /* Disable RXNE interrupt */
\r
2262 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
\r
2264 SPI_CloseRxTx_ISR(hspi);
\r
2268 * @brief Tx Handler for Transmit and Receive in Interrupt mode
\r
2269 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
\r
2270 * the configuration information for SPI module.
\r
2273 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
\r
2275 /* Transmit data in 16 Bit mode */
\r
2276 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
\r
2277 hspi->pTxBuffPtr += sizeof(uint16_t);
\r
2278 hspi->TxXferCount--;
\r
2280 /* Enable CRC Transmission */
\r
2281 if(hspi->TxXferCount == 0)
\r
2283 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
\r
2285 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
\r
2287 /* Disable TXE interrupt */
\r
2288 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
\r
2290 if(hspi->RxXferCount == 0)
\r
2292 SPI_CloseRxTx_ISR(hspi);
\r
2298 * @brief Manage the CRC receive in Interrupt context
\r
2299 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
\r
2300 * the configuration information for SPI module.
\r
2303 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
\r
2305 __IO uint8_t tmpreg;
\r
2306 tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);
\r
2307 UNUSED(tmpreg); /* To avoid GCC warning */
\r
2311 if(hspi->CRCSize == 0)
\r
2313 SPI_CloseRx_ISR(hspi);
\r
2318 * @brief Manage the receive in Interrupt context
\r
2319 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
\r
2320 * the configuration information for SPI module.
\r
2323 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
\r
2325 *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR);
\r
2326 hspi->RxXferCount--;
\r
2328 /* Enable CRC Transmission */
\r
2329 if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
\r
2331 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
\r
2334 if(hspi->RxXferCount == 0)
\r
2336 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
\r
2338 hspi->RxISR = SPI_RxISR_8BITCRC;
\r
2341 SPI_CloseRx_ISR(hspi);
\r
2346 * @brief Manage the CRC 16bit receive in Interrupt context
\r
2347 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
\r
2348 * the configuration information for SPI module.
\r
2351 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
\r
2353 __IO uint16_t tmpreg;
\r
2355 tmpreg = hspi->Instance->DR;
\r
2356 UNUSED(tmpreg); /* To avoid GCC warning */
\r
2358 /* Disable RXNE and ERR interrupt */
\r
2359 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
\r
2361 SPI_CloseRx_ISR(hspi);
\r
2365 * @brief Manage the 16Bit receive in Interrupt context
\r
2366 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
\r
2367 * the configuration information for SPI module.
\r
2370 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
\r
2372 *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
\r
2373 hspi->pRxBuffPtr += sizeof(uint16_t);
\r
2374 hspi->RxXferCount--;
\r
2376 /* Enable CRC Transmission */
\r
2377 if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
\r
2379 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
\r
2382 if(hspi->RxXferCount == 0)
\r
2384 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
\r
2386 hspi->RxISR = SPI_RxISR_16BITCRC;
\r
2389 SPI_CloseRx_ISR(hspi);
\r
2394 * @brief Handle the data 8Bit transmit in Interrupt mode
\r
2395 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
\r
2396 * the configuration information for SPI module.
\r
2399 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
\r
2401 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
\r
2402 hspi->TxXferCount--;
\r
2404 if(hspi->TxXferCount == 0)
\r
2406 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
\r
2408 /* Enable CRC Transmission */
\r
2409 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
\r
2411 SPI_CloseTx_ISR(hspi);
\r
2416 * @brief Handle the data 16Bit transmit in Interrupt mode
\r
2417 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
\r
2418 * the configuration information for SPI module.
\r
2421 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
\r
2423 /* Transmit data in 16 Bit mode */
\r
2424 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
\r
2425 hspi->pTxBuffPtr += sizeof(uint16_t);
\r
2426 hspi->TxXferCount--;
\r
2428 if(hspi->TxXferCount == 0)
\r
2430 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
\r
2432 /* Enable CRC Transmission */
\r
2433 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
\r
2435 SPI_CloseTx_ISR(hspi);
\r
2440 * @brief This function handles SPI Communication Timeout.
\r
2441 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
\r
2442 * the configuration information for SPI module.
\r
2443 * @param Flag : SPI flag to check
\r
2444 * @param State : flag state to check
\r
2445 * @param Timeout : Timeout duration
\r
2446 * @retval HAL status
\r
2448 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout)
\r
2450 uint32_t tickstart = HAL_GetTick();
\r
2452 while((hspi->Instance->SR & Flag) != State)
\r
2454 if(Timeout != HAL_MAX_DELAY)
\r
2456 if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout))
\r
2458 /* Disable the SPI and reset the CRC: the CRC value should be cleared
\r
2459 on both master and slave sides in order to resynchronize the master
\r
2460 and slave for their respective CRC calculation */
\r
2462 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
\r
2463 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
\r
2465 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
\r
2467 /* Disable SPI peripheral */
\r
2468 __HAL_SPI_DISABLE(hspi);
\r
2471 /* Reset CRC Calculation */
\r
2472 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
\r
2474 SPI_RESET_CRC(hspi);
\r
2477 hspi->State= HAL_SPI_STATE_READY;
\r
2479 /* Process Unlocked */
\r
2480 __HAL_UNLOCK(hspi);
\r
2482 return HAL_TIMEOUT;
\r
2491 * @brief This function handles SPI Communication Timeout.
\r
2492 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
\r
2493 * the configuration information for SPI module.
\r
2494 * @param Fifo : Fifo to check
\r
2495 * @param State : Fifo state to check
\r
2496 * @param Timeout : Timeout duration
\r
2497 * @retval HAL status
\r
2499 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout)
\r
2501 __IO uint8_t tmpreg;
\r
2502 uint32_t tickstart = HAL_GetTick();
\r
2504 while((hspi->Instance->SR & Fifo) != State)
\r
2506 if((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
\r
2508 tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);
\r
2509 UNUSED(tmpreg); /* To avoid GCC warning */
\r
2512 if(Timeout != HAL_MAX_DELAY)
\r
2514 if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout))
\r
2516 /* Disable the SPI and reset the CRC: the CRC value should be cleared
\r
2517 on both master and slave sides in order to resynchronize the master
\r
2518 and slave for their respective CRC calculation */
\r
2520 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
\r
2521 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
\r
2523 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
\r
2525 /* Disable SPI peripheral */
\r
2526 __HAL_SPI_DISABLE(hspi);
\r
2529 /* Reset CRC Calculation */
\r
2530 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
\r
2532 SPI_RESET_CRC(hspi);
\r
2535 hspi->State = HAL_SPI_STATE_READY;
\r
2537 /* Process Unlocked */
\r
2538 __HAL_UNLOCK(hspi);
\r
2540 return HAL_TIMEOUT;
\r
2549 * @brief This function handles the check of the RX transaction complete.
\r
2550 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
\r
2551 * the configuration information for SPI module.
\r
2552 * @param Timeout : Timeout duration
\r
2555 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)
\r
2557 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
\r
2559 /* Disable SPI peripheral */
\r
2560 __HAL_SPI_DISABLE(hspi);
\r
2562 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
\r
2564 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
\r
2565 return HAL_TIMEOUT;
\r
2567 if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK)
\r
2569 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
\r
2570 return HAL_TIMEOUT;
\r
2577 * @brief This function handles the check of the RXTX or TX transaction complete.
\r
2578 * @param hspi: SPI handle
\r
2579 * @param Timeout : Timeout duration
\r
2581 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)
\r
2583 /* Procedure to check the transaction complete */
\r
2584 if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout) != HAL_OK)
\r
2586 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
\r
2587 return HAL_TIMEOUT;
\r
2589 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
\r
2591 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
\r
2592 return HAL_TIMEOUT;
\r
2594 if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK)
\r
2596 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
\r
2597 return HAL_TIMEOUT;
\r
2603 * @brief This function handles the close of the RXTX transaction.
\r
2604 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
\r
2605 * the configuration information for SPI module.
\r
2608 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
\r
2610 /* Disable ERR interrupt */
\r
2611 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
\r
2613 /* Check if CRC error occurred */
\r
2614 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
\r
2616 hspi->State = HAL_SPI_STATE_READY;
\r
2617 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
\r
2618 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
\r
2619 HAL_SPI_ErrorCallback(hspi);
\r
2623 if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
\r
2625 if(hspi->State == HAL_SPI_STATE_BUSY_RX)
\r
2627 hspi->State = HAL_SPI_STATE_READY;
\r
2628 HAL_SPI_RxCpltCallback(hspi);
\r
2632 hspi->State = HAL_SPI_STATE_READY;
\r
2633 HAL_SPI_TxRxCpltCallback(hspi);
\r
2638 hspi->State = HAL_SPI_STATE_READY;
\r
2639 HAL_SPI_ErrorCallback(hspi);
\r
2645 * @brief This function handles the close of the RX transaction.
\r
2646 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
\r
2647 * the configuration information for SPI module.
\r
2650 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
\r
2652 /* Disable RXNE and ERR interrupt */
\r
2653 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
\r
2655 /* Check the end of the transaction */
\r
2656 SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
\r
2658 hspi->State = HAL_SPI_STATE_READY;
\r
2660 /* Check if CRC error occurred */
\r
2661 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
\r
2663 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
\r
2664 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
\r
2665 HAL_SPI_ErrorCallback(hspi);
\r
2669 if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
\r
2671 HAL_SPI_RxCpltCallback(hspi);
\r
2675 HAL_SPI_ErrorCallback(hspi);
\r
2681 * @brief This function handles the close of the TX transaction.
\r
2682 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
\r
2683 * the configuration information for SPI module.
\r
2686 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
\r
2688 /* Disable TXE and ERR interrupt */
\r
2689 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
\r
2691 /* Clear OVERUN flag in 2 Lines communication mode because received is not read */
\r
2692 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
\r
2694 __HAL_SPI_CLEAR_OVRFLAG(hspi);
\r
2697 hspi->State = HAL_SPI_STATE_READY;
\r
2698 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
\r
2700 HAL_SPI_ErrorCallback(hspi);
\r
2704 HAL_SPI_TxCpltCallback(hspi);
\r
2712 #endif /* HAL_SPI_MODULE_ENABLED */
\r
2721 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
\r