2 ******************************************************************************
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3 * @file stm32f7xx_hal_sram.c
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4 * @author MCD Application Team
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6 * @date 06-March-2015
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7 * @brief SRAM HAL module driver.
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8 * This file provides a generic firmware to drive SRAM memories
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9 * mounted as external device.
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12 ==============================================================================
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13 ##### How to use this driver #####
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14 ==============================================================================
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16 This driver is a generic layered driver which contains a set of APIs used to
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17 control SRAM memories. It uses the FMC layer functions to interface
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19 The following sequence should be followed to configure the FMC to interface
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20 with SRAM/PSRAM memories:
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22 (#) Declare a SRAM_HandleTypeDef handle structure, for example:
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23 SRAM_HandleTypeDef hsram; and:
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25 (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
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26 values of the structure member.
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28 (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
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29 base register instance for NOR or SRAM device
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31 (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
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32 base register instance for NOR or SRAM extended mode
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34 (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
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35 mode timings; for example:
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36 FMC_NORSRAM_TimingTypeDef Timing and FMC_NORSRAM_TimingTypeDef ExTiming;
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37 and fill its fields with the allowed values of the structure member.
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39 (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
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40 performs the following sequence:
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42 (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
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43 (##) Control register configuration using the FMC NORSRAM interface function
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45 (##) Timing register configuration using the FMC NORSRAM interface function
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46 FMC_NORSRAM_Timing_Init()
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47 (##) Extended mode Timing register configuration using the FMC NORSRAM interface function
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48 FMC_NORSRAM_Extended_Timing_Init()
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49 (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()
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51 (#) At this stage you can perform read/write accesses from/to the memory connected
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52 to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
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54 (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
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55 (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
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57 (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
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58 HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
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60 (#) You can continuously monitor the SRAM device HAL state by calling the function
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61 HAL_SRAM_GetState()
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64 ******************************************************************************
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67 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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69 * Redistribution and use in source and binary forms, with or without modification,
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70 * are permitted provided that the following conditions are met:
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71 * 1. Redistributions of source code must retain the above copyright notice,
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72 * this list of conditions and the following disclaimer.
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73 * 2. Redistributions in binary form must reproduce the above copyright notice,
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74 * this list of conditions and the following disclaimer in the documentation
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75 * and/or other materials provided with the distribution.
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76 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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77 * may be used to endorse or promote products derived from this software
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78 * without specific prior written permission.
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80 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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81 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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82 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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83 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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84 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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85 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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86 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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87 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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88 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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89 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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91 ******************************************************************************
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94 /* Includes ------------------------------------------------------------------*/
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95 #include "stm32f7xx_hal.h"
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97 /** @addtogroup STM32F7xx_HAL_Driver
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101 /** @defgroup SRAM SRAM
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102 * @brief SRAM driver modules
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105 #ifdef HAL_SRAM_MODULE_ENABLED
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106 /* Private typedef -----------------------------------------------------------*/
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107 /* Private define ------------------------------------------------------------*/
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108 /* Private macro -------------------------------------------------------------*/
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109 /* Private variables ---------------------------------------------------------*/
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110 /* Private function prototypes -----------------------------------------------*/
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111 /* Exported functions --------------------------------------------------------*/
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113 /** @defgroup SRAM_Exported_Functions SRAM Exported Functions
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117 /** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
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118 * @brief Initialization and Configuration functions.
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121 ==============================================================================
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122 ##### SRAM Initialization and de_initialization functions #####
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123 ==============================================================================
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124 [..] This section provides functions allowing to initialize/de-initialize
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132 * @brief Performs the SRAM device initialization sequence
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133 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
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134 * the configuration information for SRAM module.
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135 * @param Timing: Pointer to SRAM control timing structure
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136 * @param ExtTiming: Pointer to SRAM extended mode timing structure
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137 * @retval HAL status
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139 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
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141 /* Check the SRAM handle parameter */
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147 if(hsram->State == HAL_SRAM_STATE_RESET)
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149 /* Initialize the low level hardware (MSP) */
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150 HAL_SRAM_MspInit(hsram);
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153 /* Initialize SRAM control Interface */
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154 FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
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156 /* Initialize SRAM timing Interface */
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157 FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
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159 /* Initialize SRAM extended mode timing Interface */
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160 FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode);
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162 /* Enable the NORSRAM device */
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163 __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
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169 * @brief Performs the SRAM device De-initialization sequence.
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170 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
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171 * the configuration information for SRAM module.
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172 * @retval HAL status
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174 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
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176 /* De-Initialize the low level hardware (MSP) */
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177 HAL_SRAM_MspDeInit(hsram);
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179 /* Configure the SRAM registers with their reset values */
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180 FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
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182 hsram->State = HAL_SRAM_STATE_RESET;
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185 __HAL_UNLOCK(hsram);
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191 * @brief SRAM MSP Init.
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192 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
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193 * the configuration information for SRAM module.
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196 __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
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198 /* NOTE : This function Should not be modified, when the callback is needed,
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199 the HAL_SRAM_MspInit could be implemented in the user file
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204 * @brief SRAM MSP DeInit.
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205 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
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206 * the configuration information for SRAM module.
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209 __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
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211 /* NOTE : This function Should not be modified, when the callback is needed,
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212 the HAL_SRAM_MspDeInit could be implemented in the user file
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217 * @brief DMA transfer complete callback.
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218 * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
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219 * the configuration information for SRAM module.
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222 __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
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224 /* NOTE : This function Should not be modified, when the callback is needed,
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225 the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
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230 * @brief DMA transfer complete error callback.
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231 * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
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232 * the configuration information for SRAM module.
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235 __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
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237 /* NOTE : This function Should not be modified, when the callback is needed,
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238 the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
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246 /** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
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247 * @brief Input Output and memory control functions
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250 ==============================================================================
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251 ##### SRAM Input and Output functions #####
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252 ==============================================================================
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254 This section provides functions allowing to use and control the SRAM memory
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261 * @brief Reads 8-bit buffer from SRAM memory.
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262 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
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263 * the configuration information for SRAM module.
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264 * @param pAddress: Pointer to read start address
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265 * @param pDstBuffer: Pointer to destination buffer
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266 * @param BufferSize: Size of the buffer to read from memory
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267 * @retval HAL status
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269 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
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271 __IO uint8_t * psramaddress = (uint8_t *)pAddress;
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273 /* Process Locked */
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276 /* Update the SRAM controller state */
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277 hsram->State = HAL_SRAM_STATE_BUSY;
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279 /* Read data from memory */
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280 for(; BufferSize != 0; BufferSize--)
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282 *pDstBuffer = *(__IO uint8_t *)psramaddress;
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287 /* Update the SRAM controller state */
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288 hsram->State = HAL_SRAM_STATE_READY;
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290 /* Process unlocked */
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291 __HAL_UNLOCK(hsram);
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297 * @brief Writes 8-bit buffer to SRAM memory.
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298 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
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299 * the configuration information for SRAM module.
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300 * @param pAddress: Pointer to write start address
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301 * @param pSrcBuffer: Pointer to source buffer to write
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302 * @param BufferSize: Size of the buffer to write to memory
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303 * @retval HAL status
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305 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
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307 __IO uint8_t * psramaddress = (uint8_t *)pAddress;
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309 /* Check the SRAM controller state */
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310 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
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315 /* Process Locked */
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318 /* Update the SRAM controller state */
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319 hsram->State = HAL_SRAM_STATE_BUSY;
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321 /* Write data to memory */
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322 for(; BufferSize != 0; BufferSize--)
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324 *(__IO uint8_t *)psramaddress = *pSrcBuffer;
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329 /* Update the SRAM controller state */
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330 hsram->State = HAL_SRAM_STATE_READY;
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332 /* Process unlocked */
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333 __HAL_UNLOCK(hsram);
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339 * @brief Reads 16-bit buffer from SRAM memory.
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340 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
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341 * the configuration information for SRAM module.
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342 * @param pAddress: Pointer to read start address
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343 * @param pDstBuffer: Pointer to destination buffer
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344 * @param BufferSize: Size of the buffer to read from memory
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345 * @retval HAL status
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347 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
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349 __IO uint16_t * psramaddress = (uint16_t *)pAddress;
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351 /* Process Locked */
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354 /* Update the SRAM controller state */
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355 hsram->State = HAL_SRAM_STATE_BUSY;
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357 /* Read data from memory */
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358 for(; BufferSize != 0; BufferSize--)
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360 *pDstBuffer = *(__IO uint16_t *)psramaddress;
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365 /* Update the SRAM controller state */
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366 hsram->State = HAL_SRAM_STATE_READY;
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368 /* Process unlocked */
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369 __HAL_UNLOCK(hsram);
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375 * @brief Writes 16-bit buffer to SRAM memory.
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376 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
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377 * the configuration information for SRAM module.
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378 * @param pAddress: Pointer to write start address
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379 * @param pSrcBuffer: Pointer to source buffer to write
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380 * @param BufferSize: Size of the buffer to write to memory
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381 * @retval HAL status
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383 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
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385 __IO uint16_t * psramaddress = (uint16_t *)pAddress;
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387 /* Check the SRAM controller state */
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388 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
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393 /* Process Locked */
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396 /* Update the SRAM controller state */
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397 hsram->State = HAL_SRAM_STATE_BUSY;
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399 /* Write data to memory */
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400 for(; BufferSize != 0; BufferSize--)
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402 *(__IO uint16_t *)psramaddress = *pSrcBuffer;
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407 /* Update the SRAM controller state */
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408 hsram->State = HAL_SRAM_STATE_READY;
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410 /* Process unlocked */
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411 __HAL_UNLOCK(hsram);
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417 * @brief Reads 32-bit buffer from SRAM memory.
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418 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
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419 * the configuration information for SRAM module.
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420 * @param pAddress: Pointer to read start address
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421 * @param pDstBuffer: Pointer to destination buffer
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422 * @param BufferSize: Size of the buffer to read from memory
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423 * @retval HAL status
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425 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
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427 /* Process Locked */
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430 /* Update the SRAM controller state */
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431 hsram->State = HAL_SRAM_STATE_BUSY;
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433 /* Read data from memory */
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434 for(; BufferSize != 0; BufferSize--)
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436 *pDstBuffer = *(__IO uint32_t *)pAddress;
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441 /* Update the SRAM controller state */
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442 hsram->State = HAL_SRAM_STATE_READY;
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444 /* Process unlocked */
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445 __HAL_UNLOCK(hsram);
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451 * @brief Writes 32-bit buffer to SRAM memory.
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452 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
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453 * the configuration information for SRAM module.
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454 * @param pAddress: Pointer to write start address
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455 * @param pSrcBuffer: Pointer to source buffer to write
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456 * @param BufferSize: Size of the buffer to write to memory
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457 * @retval HAL status
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459 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
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461 /* Check the SRAM controller state */
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462 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
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467 /* Process Locked */
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470 /* Update the SRAM controller state */
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471 hsram->State = HAL_SRAM_STATE_BUSY;
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473 /* Write data to memory */
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474 for(; BufferSize != 0; BufferSize--)
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476 *(__IO uint32_t *)pAddress = *pSrcBuffer;
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481 /* Update the SRAM controller state */
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482 hsram->State = HAL_SRAM_STATE_READY;
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484 /* Process unlocked */
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485 __HAL_UNLOCK(hsram);
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491 * @brief Reads a Words data from the SRAM memory using DMA transfer.
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492 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
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493 * the configuration information for SRAM module.
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494 * @param pAddress: Pointer to read start address
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495 * @param pDstBuffer: Pointer to destination buffer
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496 * @param BufferSize: Size of the buffer to read from memory
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497 * @retval HAL status
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499 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
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501 /* Process Locked */
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502 __HAL_LOCK(hsram);
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504 /* Update the SRAM controller state */
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505 hsram->State = HAL_SRAM_STATE_BUSY;
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507 /* Configure DMA user callbacks */
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508 hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
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509 hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
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511 /* Enable the DMA Stream */
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512 HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
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514 /* Update the SRAM controller state */
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515 hsram->State = HAL_SRAM_STATE_READY;
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517 /* Process unlocked */
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518 __HAL_UNLOCK(hsram);
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524 * @brief Writes a Words data buffer to SRAM memory using DMA transfer.
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525 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
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526 * the configuration information for SRAM module.
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527 * @param pAddress: Pointer to write start address
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528 * @param pSrcBuffer: Pointer to source buffer to write
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529 * @param BufferSize: Size of the buffer to write to memory
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530 * @retval HAL status
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532 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
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534 /* Check the SRAM controller state */
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535 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
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540 /* Process Locked */
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543 /* Update the SRAM controller state */
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544 hsram->State = HAL_SRAM_STATE_BUSY;
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546 /* Configure DMA user callbacks */
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547 hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
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548 hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
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550 /* Enable the DMA Stream */
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551 HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
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553 /* Update the SRAM controller state */
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554 hsram->State = HAL_SRAM_STATE_READY;
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556 /* Process unlocked */
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557 __HAL_UNLOCK(hsram);
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566 /** @defgroup SRAM_Exported_Functions_Group3 Control functions
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567 * @brief Control functions
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570 ==============================================================================
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571 ##### SRAM Control functions #####
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572 ==============================================================================
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574 This subsection provides a set of functions allowing to control dynamically
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575 the SRAM interface.
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582 * @brief Enables dynamically SRAM write operation.
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583 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
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584 * the configuration information for SRAM module.
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585 * @retval HAL status
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587 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
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589 /* Process Locked */
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592 /* Enable write operation */
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593 FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
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595 /* Update the SRAM controller state */
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596 hsram->State = HAL_SRAM_STATE_READY;
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598 /* Process unlocked */
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599 __HAL_UNLOCK(hsram);
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605 * @brief Disables dynamically SRAM write operation.
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606 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
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607 * the configuration information for SRAM module.
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608 * @retval HAL status
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610 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
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612 /* Process Locked */
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615 /* Update the SRAM controller state */
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616 hsram->State = HAL_SRAM_STATE_BUSY;
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618 /* Disable write operation */
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619 FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
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621 /* Update the SRAM controller state */
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622 hsram->State = HAL_SRAM_STATE_PROTECTED;
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624 /* Process unlocked */
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625 __HAL_UNLOCK(hsram);
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634 /** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
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635 * @brief Peripheral State functions
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638 ==============================================================================
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639 ##### SRAM State functions #####
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640 ==============================================================================
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642 This subsection permits to get in run-time the status of the SRAM controller
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650 * @brief Returns the SRAM controller state
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651 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
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652 * the configuration information for SRAM module.
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653 * @retval HAL state
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655 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
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657 return hsram->State;
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667 #endif /* HAL_SRAM_MODULE_ENABLED */
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676 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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