2 ******************************************************************************
\r
3 * @file stm32f7xx_hal_tim.c
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4 * @author MCD Application Team
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6 * @date 06-March-2015
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7 * @brief TIM HAL module driver.
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8 * This file provides firmware functions to manage the following
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9 * functionalities of the Timer (TIM) peripheral:
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10 * + Time Base Initialization
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12 * + Time Base Start Interruption
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13 * + Time Base Start DMA
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14 * + Time Output Compare/PWM Initialization
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15 * + Time Output Compare/PWM Channel Configuration
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16 * + Time Output Compare/PWM Start
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17 * + Time Output Compare/PWM Start Interruption
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18 * + Time Output Compare/PWM Start DMA
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19 * + Time Input Capture Initialization
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20 * + Time Input Capture Channel Configuration
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21 * + Time Input Capture Start
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22 * + Time Input Capture Start Interruption
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23 * + Time Input Capture Start DMA
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24 * + Time One Pulse Initialization
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25 * + Time One Pulse Channel Configuration
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26 * + Time One Pulse Start
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27 * + Time Encoder Interface Initialization
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28 * + Time Encoder Interface Start
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29 * + Time Encoder Interface Start Interruption
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30 * + Time Encoder Interface Start DMA
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31 * + Commutation Event configuration with Interruption and DMA
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32 * + Time OCRef clear configuration
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33 * + Time External Clock configuration
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35 ==============================================================================
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36 ##### TIMER Generic features #####
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37 ==============================================================================
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38 [..] The Timer features include:
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39 (#) 16-bit up, down, up/down auto-reload counter.
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40 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
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41 counter clock frequency either by any factor between 1 and 65536.
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42 (#) Up to 4 independent channels for:
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45 (++) PWM generation (Edge and Center-aligned Mode)
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46 (++) One-pulse mode output
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48 ##### How to use this driver #####
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49 ==============================================================================
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51 (#) Initialize the TIM low level resources by implementing the following functions
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52 depending from feature used :
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53 (++) Time Base : HAL_TIM_Base_MspInit()
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54 (++) Input Capture : HAL_TIM_IC_MspInit()
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55 (++) Output Compare : HAL_TIM_OC_MspInit()
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56 (++) PWM generation : HAL_TIM_PWM_MspInit()
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57 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
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58 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
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60 (#) Initialize the TIM low level resources :
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61 (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
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62 (##) TIM pins configuration
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63 (+++) Enable the clock for the TIM GPIOs using the following function:
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64 __GPIOx_CLK_ENABLE();
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65 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
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67 (#) The external Clock can be configured, if needed (the default clock is the
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68 internal clock from the APBx), using the following function:
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69 HAL_TIM_ConfigClockSource, the clock configuration should be done before
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72 (#) Configure the TIM in the desired functioning mode using one of the
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73 initialization function of this driver:
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74 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
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75 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
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76 Output Compare signal.
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77 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
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79 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
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81 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
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83 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
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85 (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
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86 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
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87 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
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88 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
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89 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
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90 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
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91 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
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93 (#) The DMA Burst is managed with the two following functions:
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94 HAL_TIM_DMABurst_WriteStart()
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95 HAL_TIM_DMABurst_ReadStart()
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98 ******************************************************************************
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101 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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103 * Redistribution and use in source and binary forms, with or without modification,
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104 * are permitted provided that the following conditions are met:
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105 * 1. Redistributions of source code must retain the above copyright notice,
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106 * this list of conditions and the following disclaimer.
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107 * 2. Redistributions in binary form must reproduce the above copyright notice,
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108 * this list of conditions and the following disclaimer in the documentation
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109 * and/or other materials provided with the distribution.
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110 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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111 * may be used to endorse or promote products derived from this software
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112 * without specific prior written permission.
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114 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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115 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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116 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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117 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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118 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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119 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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120 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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121 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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122 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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123 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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125 ******************************************************************************
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128 /* Includes ------------------------------------------------------------------*/
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129 #include "stm32f7xx_hal.h"
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131 /** @addtogroup STM32F7xx_HAL_Driver
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135 /** @defgroup TIM TIM
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136 * @brief TIM HAL module driver
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140 #ifdef HAL_TIM_MODULE_ENABLED
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142 /* Private typedef -----------------------------------------------------------*/
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143 /* Private define ------------------------------------------------------------*/
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144 /* Private macro -------------------------------------------------------------*/
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145 /* Private variables ---------------------------------------------------------*/
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146 /** @addtogroup TIM_Private_Functions
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149 /* Private function prototypes -----------------------------------------------*/
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150 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
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151 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
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152 uint32_t TIM_ICFilter);
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153 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
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154 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
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155 uint32_t TIM_ICFilter);
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156 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
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157 uint32_t TIM_ICFilter);
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159 static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t TIM_ITRx);
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160 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
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161 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
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162 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
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163 TIM_SlaveConfigTypeDef * sSlaveConfig);
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168 /* Exported functions --------------------------------------------------------*/
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169 /** @defgroup TIM_Exported_Functions TIM Exported Functions
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173 /** @defgroup TIM_Exported_Functions_Group1 Time Base functions
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174 * @brief Time Base functions
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177 ==============================================================================
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178 ##### Time Base functions #####
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179 ==============================================================================
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181 This section provides functions allowing to:
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182 (+) Initialize and configure the TIM base.
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183 (+) De-initialize the TIM base.
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184 (+) Start the Time Base.
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185 (+) Stop the Time Base.
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186 (+) Start the Time Base and enable interrupt.
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187 (+) Stop the Time Base and disable interrupt.
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188 (+) Start the Time Base and enable DMA transfer.
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189 (+) Stop the Time Base and disable DMA transfer.
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195 * @brief Initializes the TIM Time base Unit according to the specified
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196 * parameters in the TIM_HandleTypeDef and create the associated handle.
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197 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
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198 * the configuration information for TIM module.
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199 * @retval HAL status
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201 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
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203 /* Check the TIM handle allocation */
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209 /* Check the parameters */
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210 assert_param(IS_TIM_INSTANCE(htim->Instance));
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211 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
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212 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
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214 if(htim->State == HAL_TIM_STATE_RESET)
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216 /* Init the low level hardware : GPIO, CLOCK, NVIC */
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217 HAL_TIM_Base_MspInit(htim);
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220 /* Set the TIM state */
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221 htim->State= HAL_TIM_STATE_BUSY;
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223 /* Set the Time Base configuration */
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224 TIM_Base_SetConfig(htim->Instance, &htim->Init);
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226 /* Initialize the TIM state*/
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227 htim->State= HAL_TIM_STATE_READY;
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233 * @brief DeInitializes the TIM Base peripheral
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234 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
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235 * the configuration information for TIM module.
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236 * @retval HAL status
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238 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
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240 /* Check the parameters */
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241 assert_param(IS_TIM_INSTANCE(htim->Instance));
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243 htim->State = HAL_TIM_STATE_BUSY;
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245 /* Disable the TIM Peripheral Clock */
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246 __HAL_TIM_DISABLE(htim);
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248 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
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249 HAL_TIM_Base_MspDeInit(htim);
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251 /* Change TIM state */
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252 htim->State = HAL_TIM_STATE_RESET;
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255 __HAL_UNLOCK(htim);
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261 * @brief Initializes the TIM Base MSP.
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262 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
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263 * the configuration information for TIM module.
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266 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
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268 /* NOTE : This function Should not be modified, when the callback is needed,
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269 the HAL_TIM_Base_MspInit could be implemented in the user file
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274 * @brief DeInitializes TIM Base MSP.
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275 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
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276 * the configuration information for TIM module.
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279 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
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281 /* NOTE : This function Should not be modified, when the callback is needed,
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282 the HAL_TIM_Base_MspDeInit could be implemented in the user file
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287 * @brief Starts the TIM Base generation.
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288 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
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289 * the configuration information for TIM module.
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290 * @retval HAL status
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292 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
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294 /* Check the parameters */
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295 assert_param(IS_TIM_INSTANCE(htim->Instance));
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297 /* Set the TIM state */
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298 htim->State= HAL_TIM_STATE_BUSY;
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300 /* Enable the Peripheral */
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301 __HAL_TIM_ENABLE(htim);
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303 /* Change the TIM state*/
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304 htim->State= HAL_TIM_STATE_READY;
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306 /* Return function status */
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311 * @brief Stops the TIM Base generation.
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312 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
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313 * the configuration information for TIM module.
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314 * @retval HAL status
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316 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
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318 /* Check the parameters */
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319 assert_param(IS_TIM_INSTANCE(htim->Instance));
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321 /* Set the TIM state */
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322 htim->State= HAL_TIM_STATE_BUSY;
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324 /* Disable the Peripheral */
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325 __HAL_TIM_DISABLE(htim);
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327 /* Change the TIM state*/
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328 htim->State= HAL_TIM_STATE_READY;
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330 /* Return function status */
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335 * @brief Starts the TIM Base generation in interrupt mode.
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336 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
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337 * the configuration information for TIM module.
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338 * @retval HAL status
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340 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
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342 /* Check the parameters */
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343 assert_param(IS_TIM_INSTANCE(htim->Instance));
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345 /* Enable the TIM Update interrupt */
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346 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
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348 /* Enable the Peripheral */
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349 __HAL_TIM_ENABLE(htim);
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351 /* Return function status */
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356 * @brief Stops the TIM Base generation in interrupt mode.
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357 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
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358 * the configuration information for TIM module.
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359 * @retval HAL status
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361 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
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363 /* Check the parameters */
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364 assert_param(IS_TIM_INSTANCE(htim->Instance));
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365 /* Disable the TIM Update interrupt */
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366 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
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368 /* Disable the Peripheral */
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369 __HAL_TIM_DISABLE(htim);
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371 /* Return function status */
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376 * @brief Starts the TIM Base generation in DMA mode.
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377 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
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378 * the configuration information for TIM module.
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379 * @param pData: The source Buffer address.
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380 * @param Length: The length of data to be transferred from memory to peripheral.
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381 * @retval HAL status
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383 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
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385 /* Check the parameters */
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386 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
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388 if((htim->State == HAL_TIM_STATE_BUSY))
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392 else if((htim->State == HAL_TIM_STATE_READY))
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394 if((pData == 0 ) && (Length > 0))
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400 htim->State = HAL_TIM_STATE_BUSY;
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403 /* Set the DMA Period elapsed callback */
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404 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
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406 /* Set the DMA error callback */
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407 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
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409 /* Enable the DMA Stream */
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410 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
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412 /* Enable the TIM Update DMA request */
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413 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
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415 /* Enable the Peripheral */
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416 __HAL_TIM_ENABLE(htim);
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418 /* Return function status */
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423 * @brief Stops the TIM Base generation in DMA mode.
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424 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
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425 * the configuration information for TIM module.
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426 * @retval HAL status
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428 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
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430 /* Check the parameters */
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431 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
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433 /* Disable the TIM Update DMA request */
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434 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
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436 /* Disable the Peripheral */
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437 __HAL_TIM_DISABLE(htim);
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439 /* Change the htim state */
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440 htim->State = HAL_TIM_STATE_READY;
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442 /* Return function status */
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450 /** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
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451 * @brief Time Output Compare functions
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454 ==============================================================================
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455 ##### Time Output Compare functions #####
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456 ==============================================================================
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458 This section provides functions allowing to:
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459 (+) Initialize and configure the TIM Output Compare.
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460 (+) De-initialize the TIM Output Compare.
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461 (+) Start the Time Output Compare.
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462 (+) Stop the Time Output Compare.
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463 (+) Start the Time Output Compare and enable interrupt.
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464 (+) Stop the Time Output Compare and disable interrupt.
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465 (+) Start the Time Output Compare and enable DMA transfer.
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466 (+) Stop the Time Output Compare and disable DMA transfer.
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472 * @brief Initializes the TIM Output Compare according to the specified
\r
473 * parameters in the TIM_HandleTypeDef and create the associated handle.
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474 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
475 * the configuration information for TIM module.
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476 * @retval HAL status
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478 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
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480 /* Check the TIM handle allocation */
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486 /* Check the parameters */
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487 assert_param(IS_TIM_INSTANCE(htim->Instance));
\r
488 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
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489 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
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491 if(htim->State == HAL_TIM_STATE_RESET)
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493 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
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494 HAL_TIM_OC_MspInit(htim);
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497 /* Set the TIM state */
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498 htim->State= HAL_TIM_STATE_BUSY;
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500 /* Init the base time for the Output Compare */
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501 TIM_Base_SetConfig(htim->Instance, &htim->Init);
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503 /* Initialize the TIM state*/
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504 htim->State= HAL_TIM_STATE_READY;
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510 * @brief DeInitializes the TIM peripheral
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511 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
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512 * the configuration information for TIM module.
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513 * @retval HAL status
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515 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
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517 /* Check the parameters */
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518 assert_param(IS_TIM_INSTANCE(htim->Instance));
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520 htim->State = HAL_TIM_STATE_BUSY;
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522 /* Disable the TIM Peripheral Clock */
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523 __HAL_TIM_DISABLE(htim);
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525 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
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526 HAL_TIM_OC_MspDeInit(htim);
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528 /* Change TIM state */
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529 htim->State = HAL_TIM_STATE_RESET;
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532 __HAL_UNLOCK(htim);
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538 * @brief Initializes the TIM Output Compare MSP.
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539 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
540 * the configuration information for TIM module.
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543 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
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545 /* NOTE : This function Should not be modified, when the callback is needed,
\r
546 the HAL_TIM_OC_MspInit could be implemented in the user file
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551 * @brief DeInitializes TIM Output Compare MSP.
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552 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
553 * the configuration information for TIM module.
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556 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
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558 /* NOTE : This function Should not be modified, when the callback is needed,
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559 the HAL_TIM_OC_MspDeInit could be implemented in the user file
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564 * @brief Starts the TIM Output Compare signal generation.
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565 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
566 * the configuration information for TIM module.
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567 * @param Channel: TIM Channel to be enabled.
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568 * This parameter can be one of the following values:
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569 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
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570 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
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571 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
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572 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
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573 * @retval HAL status
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575 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
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577 /* Check the parameters */
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578 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
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580 /* Enable the Output compare channel */
\r
581 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
\r
583 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
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585 /* Enable the main output */
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586 __HAL_TIM_MOE_ENABLE(htim);
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589 /* Enable the Peripheral */
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590 __HAL_TIM_ENABLE(htim);
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592 /* Return function status */
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597 * @brief Stops the TIM Output Compare signal generation.
\r
598 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
599 * the configuration information for TIM module.
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600 * @param Channel: TIM Channel to be disabled.
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601 * This parameter can be one of the following values:
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602 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
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603 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
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604 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
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605 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
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606 * @retval HAL status
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608 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
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610 /* Check the parameters */
\r
611 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
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613 /* Disable the Output compare channel */
\r
614 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
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616 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
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618 /* Disable the Main Output */
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619 __HAL_TIM_MOE_DISABLE(htim);
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622 /* Disable the Peripheral */
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623 __HAL_TIM_DISABLE(htim);
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625 /* Return function status */
\r
630 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
\r
631 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
632 * the configuration information for TIM module.
\r
633 * @param Channel: TIM Channel to be enabled.
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634 * This parameter can be one of the following values:
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635 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
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636 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
637 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
\r
638 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
\r
639 * @retval HAL status
\r
641 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
\r
643 /* Check the parameters */
\r
644 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
\r
648 case TIM_CHANNEL_1:
\r
650 /* Enable the TIM Capture/Compare 1 interrupt */
\r
651 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
\r
655 case TIM_CHANNEL_2:
\r
657 /* Enable the TIM Capture/Compare 2 interrupt */
\r
658 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
\r
662 case TIM_CHANNEL_3:
\r
664 /* Enable the TIM Capture/Compare 3 interrupt */
\r
665 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
\r
669 case TIM_CHANNEL_4:
\r
671 /* Enable the TIM Capture/Compare 4 interrupt */
\r
672 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
\r
680 /* Enable the Output compare channel */
\r
681 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
\r
683 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
\r
685 /* Enable the main output */
\r
686 __HAL_TIM_MOE_ENABLE(htim);
\r
689 /* Enable the Peripheral */
\r
690 __HAL_TIM_ENABLE(htim);
\r
692 /* Return function status */
\r
697 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
\r
698 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
699 * the configuration information for TIM module.
\r
700 * @param Channel: TIM Channel to be disabled.
\r
701 * This parameter can be one of the following values:
\r
702 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
703 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
704 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
\r
705 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
\r
706 * @retval HAL status
\r
708 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
\r
710 /* Check the parameters */
\r
711 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
\r
715 case TIM_CHANNEL_1:
\r
717 /* Disable the TIM Capture/Compare 1 interrupt */
\r
718 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
\r
722 case TIM_CHANNEL_2:
\r
724 /* Disable the TIM Capture/Compare 2 interrupt */
\r
725 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
\r
729 case TIM_CHANNEL_3:
\r
731 /* Disable the TIM Capture/Compare 3 interrupt */
\r
732 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
\r
736 case TIM_CHANNEL_4:
\r
738 /* Disable the TIM Capture/Compare 4 interrupt */
\r
739 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
\r
747 /* Disable the Output compare channel */
\r
748 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
\r
750 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
\r
752 /* Disable the Main Output */
\r
753 __HAL_TIM_MOE_DISABLE(htim);
\r
756 /* Disable the Peripheral */
\r
757 __HAL_TIM_DISABLE(htim);
\r
759 /* Return function status */
\r
764 * @brief Starts the TIM Output Compare signal generation in DMA mode.
\r
765 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
766 * the configuration information for TIM module.
\r
767 * @param Channel: TIM Channel to be enabled.
\r
768 * This parameter can be one of the following values:
\r
769 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
770 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
771 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
\r
772 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
\r
773 * @param pData: The source Buffer address.
\r
774 * @param Length: The length of data to be transferred from memory to TIM peripheral
\r
775 * @retval HAL status
\r
777 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
\r
779 /* Check the parameters */
\r
780 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
\r
782 if((htim->State == HAL_TIM_STATE_BUSY))
\r
786 else if((htim->State == HAL_TIM_STATE_READY))
\r
788 if(((uint32_t)pData == 0 ) && (Length > 0))
\r
794 htim->State = HAL_TIM_STATE_BUSY;
\r
799 case TIM_CHANNEL_1:
\r
801 /* Set the DMA Period elapsed callback */
\r
802 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
\r
804 /* Set the DMA error callback */
\r
805 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
\r
807 /* Enable the DMA Stream */
\r
808 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
\r
810 /* Enable the TIM Capture/Compare 1 DMA request */
\r
811 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
\r
815 case TIM_CHANNEL_2:
\r
817 /* Set the DMA Period elapsed callback */
\r
818 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
\r
820 /* Set the DMA error callback */
\r
821 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
\r
823 /* Enable the DMA Stream */
\r
824 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
\r
826 /* Enable the TIM Capture/Compare 2 DMA request */
\r
827 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
\r
831 case TIM_CHANNEL_3:
\r
833 /* Set the DMA Period elapsed callback */
\r
834 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
\r
836 /* Set the DMA error callback */
\r
837 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
\r
839 /* Enable the DMA Stream */
\r
840 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
\r
842 /* Enable the TIM Capture/Compare 3 DMA request */
\r
843 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
\r
847 case TIM_CHANNEL_4:
\r
849 /* Set the DMA Period elapsed callback */
\r
850 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
\r
852 /* Set the DMA error callback */
\r
853 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
\r
855 /* Enable the DMA Stream */
\r
856 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
\r
858 /* Enable the TIM Capture/Compare 4 DMA request */
\r
859 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
\r
867 /* Enable the Output compare channel */
\r
868 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
\r
870 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
\r
872 /* Enable the main output */
\r
873 __HAL_TIM_MOE_ENABLE(htim);
\r
876 /* Enable the Peripheral */
\r
877 __HAL_TIM_ENABLE(htim);
\r
879 /* Return function status */
\r
884 * @brief Stops the TIM Output Compare signal generation in DMA mode.
\r
885 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
886 * the configuration information for TIM module.
\r
887 * @param Channel: TIM Channel to be disabled.
\r
888 * This parameter can be one of the following values:
\r
889 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
890 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
891 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
\r
892 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
\r
893 * @retval HAL status
\r
895 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
\r
897 /* Check the parameters */
\r
898 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
\r
902 case TIM_CHANNEL_1:
\r
904 /* Disable the TIM Capture/Compare 1 DMA request */
\r
905 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
\r
909 case TIM_CHANNEL_2:
\r
911 /* Disable the TIM Capture/Compare 2 DMA request */
\r
912 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
\r
916 case TIM_CHANNEL_3:
\r
918 /* Disable the TIM Capture/Compare 3 DMA request */
\r
919 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
\r
923 case TIM_CHANNEL_4:
\r
925 /* Disable the TIM Capture/Compare 4 interrupt */
\r
926 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
\r
934 /* Disable the Output compare channel */
\r
935 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
\r
937 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
\r
939 /* Disable the Main Output */
\r
940 __HAL_TIM_MOE_DISABLE(htim);
\r
943 /* Disable the Peripheral */
\r
944 __HAL_TIM_DISABLE(htim);
\r
946 /* Change the htim state */
\r
947 htim->State = HAL_TIM_STATE_READY;
\r
949 /* Return function status */
\r
957 /** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
\r
958 * @brief Time PWM functions
\r
961 ==============================================================================
\r
962 ##### Time PWM functions #####
\r
963 ==============================================================================
\r
965 This section provides functions allowing to:
\r
966 (+) Initialize and configure the TIM OPWM.
\r
967 (+) De-initialize the TIM PWM.
\r
968 (+) Start the Time PWM.
\r
969 (+) Stop the Time PWM.
\r
970 (+) Start the Time PWM and enable interrupt.
\r
971 (+) Stop the Time PWM and disable interrupt.
\r
972 (+) Start the Time PWM and enable DMA transfer.
\r
973 (+) Stop the Time PWM and disable DMA transfer.
\r
979 * @brief Initializes the TIM PWM Time Base according to the specified
\r
980 * parameters in the TIM_HandleTypeDef and create the associated handle.
\r
981 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
982 * the configuration information for TIM module.
\r
983 * @retval HAL status
\r
985 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
\r
987 /* Check the TIM handle allocation */
\r
993 /* Check the parameters */
\r
994 assert_param(IS_TIM_INSTANCE(htim->Instance));
\r
995 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
\r
996 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
\r
998 if(htim->State == HAL_TIM_STATE_RESET)
\r
1000 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
\r
1001 HAL_TIM_PWM_MspInit(htim);
\r
1004 /* Set the TIM state */
\r
1005 htim->State= HAL_TIM_STATE_BUSY;
\r
1007 /* Init the base time for the PWM */
\r
1008 TIM_Base_SetConfig(htim->Instance, &htim->Init);
\r
1010 /* Initialize the TIM state*/
\r
1011 htim->State= HAL_TIM_STATE_READY;
\r
1017 * @brief DeInitializes the TIM peripheral
\r
1018 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
1019 * the configuration information for TIM module.
\r
1020 * @retval HAL status
\r
1022 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
\r
1024 /* Check the parameters */
\r
1025 assert_param(IS_TIM_INSTANCE(htim->Instance));
\r
1027 htim->State = HAL_TIM_STATE_BUSY;
\r
1029 /* Disable the TIM Peripheral Clock */
\r
1030 __HAL_TIM_DISABLE(htim);
\r
1032 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
\r
1033 HAL_TIM_PWM_MspDeInit(htim);
\r
1035 /* Change TIM state */
\r
1036 htim->State = HAL_TIM_STATE_RESET;
\r
1038 /* Release Lock */
\r
1039 __HAL_UNLOCK(htim);
\r
1045 * @brief Initializes the TIM PWM MSP.
\r
1046 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
1047 * the configuration information for TIM module.
\r
1050 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
\r
1052 /* NOTE : This function Should not be modified, when the callback is needed,
\r
1053 the HAL_TIM_PWM_MspInit could be implemented in the user file
\r
1058 * @brief DeInitializes TIM PWM MSP.
\r
1059 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
1060 * the configuration information for TIM module.
\r
1063 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
\r
1065 /* NOTE : This function Should not be modified, when the callback is needed,
\r
1066 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
\r
1071 * @brief Starts the PWM signal generation.
\r
1072 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
1073 * the configuration information for TIM module.
\r
1074 * @param Channel: TIM Channels to be enabled.
\r
1075 * This parameter can be one of the following values:
\r
1076 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
1077 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
1078 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
\r
1079 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
\r
1080 * @retval HAL status
\r
1082 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
\r
1084 /* Check the parameters */
\r
1085 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
\r
1087 /* Enable the Capture compare channel */
\r
1088 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
\r
1090 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
\r
1092 /* Enable the main output */
\r
1093 __HAL_TIM_MOE_ENABLE(htim);
\r
1096 /* Enable the Peripheral */
\r
1097 __HAL_TIM_ENABLE(htim);
\r
1099 /* Return function status */
\r
1104 * @brief Stops the PWM signal generation.
\r
1105 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
1106 * the configuration information for TIM module.
\r
1107 * @param Channel: TIM Channels to be disabled.
\r
1108 * This parameter can be one of the following values:
\r
1109 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
1110 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
1111 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
\r
1112 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
\r
1113 * @retval HAL status
\r
1115 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
\r
1117 /* Check the parameters */
\r
1118 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
\r
1120 /* Disable the Capture compare channel */
\r
1121 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
\r
1123 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
\r
1125 /* Disable the Main Output */
\r
1126 __HAL_TIM_MOE_DISABLE(htim);
\r
1129 /* Disable the Peripheral */
\r
1130 __HAL_TIM_DISABLE(htim);
\r
1132 /* Change the htim state */
\r
1133 htim->State = HAL_TIM_STATE_READY;
\r
1135 /* Return function status */
\r
1140 * @brief Starts the PWM signal generation in interrupt mode.
\r
1141 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
1142 * the configuration information for TIM module.
\r
1143 * @param Channel: TIM Channel to be disabled.
\r
1144 * This parameter can be one of the following values:
\r
1145 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
1146 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
1147 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
\r
1148 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
\r
1149 * @retval HAL status
\r
1151 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
\r
1153 /* Check the parameters */
\r
1154 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
\r
1158 case TIM_CHANNEL_1:
\r
1160 /* Enable the TIM Capture/Compare 1 interrupt */
\r
1161 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
\r
1165 case TIM_CHANNEL_2:
\r
1167 /* Enable the TIM Capture/Compare 2 interrupt */
\r
1168 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
\r
1172 case TIM_CHANNEL_3:
\r
1174 /* Enable the TIM Capture/Compare 3 interrupt */
\r
1175 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
\r
1179 case TIM_CHANNEL_4:
\r
1181 /* Enable the TIM Capture/Compare 4 interrupt */
\r
1182 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
\r
1190 /* Enable the Capture compare channel */
\r
1191 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
\r
1193 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
\r
1195 /* Enable the main output */
\r
1196 __HAL_TIM_MOE_ENABLE(htim);
\r
1199 /* Enable the Peripheral */
\r
1200 __HAL_TIM_ENABLE(htim);
\r
1202 /* Return function status */
\r
1207 * @brief Stops the PWM signal generation in interrupt mode.
\r
1208 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
1209 * the configuration information for TIM module.
\r
1210 * @param Channel: TIM Channels to be disabled.
\r
1211 * This parameter can be one of the following values:
\r
1212 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
1213 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
1214 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
\r
1215 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
\r
1216 * @retval HAL status
\r
1218 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
\r
1220 /* Check the parameters */
\r
1221 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
\r
1225 case TIM_CHANNEL_1:
\r
1227 /* Disable the TIM Capture/Compare 1 interrupt */
\r
1228 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
\r
1232 case TIM_CHANNEL_2:
\r
1234 /* Disable the TIM Capture/Compare 2 interrupt */
\r
1235 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
\r
1239 case TIM_CHANNEL_3:
\r
1241 /* Disable the TIM Capture/Compare 3 interrupt */
\r
1242 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
\r
1246 case TIM_CHANNEL_4:
\r
1248 /* Disable the TIM Capture/Compare 4 interrupt */
\r
1249 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
\r
1257 /* Disable the Capture compare channel */
\r
1258 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
\r
1260 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
\r
1262 /* Disable the Main Output */
\r
1263 __HAL_TIM_MOE_DISABLE(htim);
\r
1266 /* Disable the Peripheral */
\r
1267 __HAL_TIM_DISABLE(htim);
\r
1269 /* Return function status */
\r
1274 * @brief Starts the TIM PWM signal generation in DMA mode.
\r
1275 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
1276 * the configuration information for TIM module.
\r
1277 * @param Channel: TIM Channels to be enabled.
\r
1278 * This parameter can be one of the following values:
\r
1279 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
1280 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
1281 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
\r
1282 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
\r
1283 * @param pData: The source Buffer address.
\r
1284 * @param Length: The length of data to be transferred from memory to TIM peripheral
\r
1285 * @retval HAL status
\r
1287 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
\r
1289 /* Check the parameters */
\r
1290 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
\r
1292 if((htim->State == HAL_TIM_STATE_BUSY))
\r
1296 else if((htim->State == HAL_TIM_STATE_READY))
\r
1298 if(((uint32_t)pData == 0 ) && (Length > 0))
\r
1300 return HAL_ERROR;
\r
1304 htim->State = HAL_TIM_STATE_BUSY;
\r
1309 case TIM_CHANNEL_1:
\r
1311 /* Set the DMA Period elapsed callback */
\r
1312 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
\r
1314 /* Set the DMA error callback */
\r
1315 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
\r
1317 /* Enable the DMA Stream */
\r
1318 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
\r
1320 /* Enable the TIM Capture/Compare 1 DMA request */
\r
1321 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
\r
1325 case TIM_CHANNEL_2:
\r
1327 /* Set the DMA Period elapsed callback */
\r
1328 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
\r
1330 /* Set the DMA error callback */
\r
1331 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
\r
1333 /* Enable the DMA Stream */
\r
1334 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
\r
1336 /* Enable the TIM Capture/Compare 2 DMA request */
\r
1337 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
\r
1341 case TIM_CHANNEL_3:
\r
1343 /* Set the DMA Period elapsed callback */
\r
1344 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
\r
1346 /* Set the DMA error callback */
\r
1347 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
\r
1349 /* Enable the DMA Stream */
\r
1350 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
\r
1352 /* Enable the TIM Output Capture/Compare 3 request */
\r
1353 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
\r
1357 case TIM_CHANNEL_4:
\r
1359 /* Set the DMA Period elapsed callback */
\r
1360 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
\r
1362 /* Set the DMA error callback */
\r
1363 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
\r
1365 /* Enable the DMA Stream */
\r
1366 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
\r
1368 /* Enable the TIM Capture/Compare 4 DMA request */
\r
1369 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
\r
1377 /* Enable the Capture compare channel */
\r
1378 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
\r
1380 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
\r
1382 /* Enable the main output */
\r
1383 __HAL_TIM_MOE_ENABLE(htim);
\r
1386 /* Enable the Peripheral */
\r
1387 __HAL_TIM_ENABLE(htim);
\r
1389 /* Return function status */
\r
1394 * @brief Stops the TIM PWM signal generation in DMA mode.
\r
1395 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
1396 * the configuration information for TIM module.
\r
1397 * @param Channel: TIM Channels to be disabled.
\r
1398 * This parameter can be one of the following values:
\r
1399 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
1400 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
1401 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
\r
1402 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
\r
1403 * @retval HAL status
\r
1405 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
\r
1407 /* Check the parameters */
\r
1408 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
\r
1412 case TIM_CHANNEL_1:
\r
1414 /* Disable the TIM Capture/Compare 1 DMA request */
\r
1415 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
\r
1419 case TIM_CHANNEL_2:
\r
1421 /* Disable the TIM Capture/Compare 2 DMA request */
\r
1422 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
\r
1426 case TIM_CHANNEL_3:
\r
1428 /* Disable the TIM Capture/Compare 3 DMA request */
\r
1429 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
\r
1433 case TIM_CHANNEL_4:
\r
1435 /* Disable the TIM Capture/Compare 4 interrupt */
\r
1436 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
\r
1444 /* Disable the Capture compare channel */
\r
1445 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
\r
1447 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
\r
1449 /* Disable the Main Output */
\r
1450 __HAL_TIM_MOE_DISABLE(htim);
\r
1453 /* Disable the Peripheral */
\r
1454 __HAL_TIM_DISABLE(htim);
\r
1456 /* Change the htim state */
\r
1457 htim->State = HAL_TIM_STATE_READY;
\r
1459 /* Return function status */
\r
1467 /** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
\r
1468 * @brief Time Input Capture functions
\r
1471 ==============================================================================
\r
1472 ##### Time Input Capture functions #####
\r
1473 ==============================================================================
\r
1475 This section provides functions allowing to:
\r
1476 (+) Initialize and configure the TIM Input Capture.
\r
1477 (+) De-initialize the TIM Input Capture.
\r
1478 (+) Start the Time Input Capture.
\r
1479 (+) Stop the Time Input Capture.
\r
1480 (+) Start the Time Input Capture and enable interrupt.
\r
1481 (+) Stop the Time Input Capture and disable interrupt.
\r
1482 (+) Start the Time Input Capture and enable DMA transfer.
\r
1483 (+) Stop the Time Input Capture and disable DMA transfer.
\r
1489 * @brief Initializes the TIM Input Capture Time base according to the specified
\r
1490 * parameters in the TIM_HandleTypeDef and create the associated handle.
\r
1491 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
1492 * the configuration information for TIM module.
\r
1493 * @retval HAL status
\r
1495 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
\r
1497 /* Check the TIM handle allocation */
\r
1503 /* Check the parameters */
\r
1504 assert_param(IS_TIM_INSTANCE(htim->Instance));
\r
1505 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
\r
1506 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
\r
1508 if(htim->State == HAL_TIM_STATE_RESET)
\r
1510 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
\r
1511 HAL_TIM_IC_MspInit(htim);
\r
1514 /* Set the TIM state */
\r
1515 htim->State= HAL_TIM_STATE_BUSY;
\r
1517 /* Init the base time for the input capture */
\r
1518 TIM_Base_SetConfig(htim->Instance, &htim->Init);
\r
1520 /* Initialize the TIM state*/
\r
1521 htim->State= HAL_TIM_STATE_READY;
\r
1527 * @brief DeInitializes the TIM peripheral
\r
1528 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
1529 * the configuration information for TIM module.
\r
1530 * @retval HAL status
\r
1532 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
\r
1534 /* Check the parameters */
\r
1535 assert_param(IS_TIM_INSTANCE(htim->Instance));
\r
1537 htim->State = HAL_TIM_STATE_BUSY;
\r
1539 /* Disable the TIM Peripheral Clock */
\r
1540 __HAL_TIM_DISABLE(htim);
\r
1542 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
\r
1543 HAL_TIM_IC_MspDeInit(htim);
\r
1545 /* Change TIM state */
\r
1546 htim->State = HAL_TIM_STATE_RESET;
\r
1548 /* Release Lock */
\r
1549 __HAL_UNLOCK(htim);
\r
1555 * @brief Initializes the TIM INput Capture MSP.
\r
1556 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
1557 * the configuration information for TIM module.
\r
1560 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
\r
1562 /* NOTE : This function Should not be modified, when the callback is needed,
\r
1563 the HAL_TIM_IC_MspInit could be implemented in the user file
\r
1568 * @brief DeInitializes TIM Input Capture MSP.
\r
1569 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
1570 * the configuration information for TIM module.
\r
1573 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
\r
1575 /* NOTE : This function Should not be modified, when the callback is needed,
\r
1576 the HAL_TIM_IC_MspDeInit could be implemented in the user file
\r
1581 * @brief Starts the TIM Input Capture measurement.
\r
1582 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
1583 * the configuration information for TIM module.
\r
1584 * @param Channel: TIM Channels to be enabled.
\r
1585 * This parameter can be one of the following values:
\r
1586 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
1587 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
1588 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
\r
1589 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
\r
1590 * @retval HAL status
\r
1592 HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
\r
1594 /* Check the parameters */
\r
1595 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
\r
1597 /* Enable the Input Capture channel */
\r
1598 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
\r
1600 /* Enable the Peripheral */
\r
1601 __HAL_TIM_ENABLE(htim);
\r
1603 /* Return function status */
\r
1608 * @brief Stops the TIM Input Capture measurement.
\r
1609 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
1610 * the configuration information for TIM module.
\r
1611 * @param Channel: TIM Channels to be disabled.
\r
1612 * This parameter can be one of the following values:
\r
1613 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
1614 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
1615 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
\r
1616 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
\r
1617 * @retval HAL status
\r
1619 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
\r
1621 /* Check the parameters */
\r
1622 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
\r
1624 /* Disable the Input Capture channel */
\r
1625 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
\r
1627 /* Disable the Peripheral */
\r
1628 __HAL_TIM_DISABLE(htim);
\r
1630 /* Return function status */
\r
1635 * @brief Starts the TIM Input Capture measurement in interrupt mode.
\r
1636 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
1637 * the configuration information for TIM module.
\r
1638 * @param Channel: TIM Channels to be enabled.
\r
1639 * This parameter can be one of the following values:
\r
1640 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
1641 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
1642 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
\r
1643 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
\r
1644 * @retval HAL status
\r
1646 HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
\r
1648 /* Check the parameters */
\r
1649 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
\r
1653 case TIM_CHANNEL_1:
\r
1655 /* Enable the TIM Capture/Compare 1 interrupt */
\r
1656 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
\r
1660 case TIM_CHANNEL_2:
\r
1662 /* Enable the TIM Capture/Compare 2 interrupt */
\r
1663 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
\r
1667 case TIM_CHANNEL_3:
\r
1669 /* Enable the TIM Capture/Compare 3 interrupt */
\r
1670 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
\r
1674 case TIM_CHANNEL_4:
\r
1676 /* Enable the TIM Capture/Compare 4 interrupt */
\r
1677 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
\r
1684 /* Enable the Input Capture channel */
\r
1685 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
\r
1687 /* Enable the Peripheral */
\r
1688 __HAL_TIM_ENABLE(htim);
\r
1690 /* Return function status */
\r
1695 * @brief Stops the TIM Input Capture measurement in interrupt mode.
\r
1696 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
1697 * the configuration information for TIM module.
\r
1698 * @param Channel: TIM Channels to be disabled.
\r
1699 * This parameter can be one of the following values:
\r
1700 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
1701 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
1702 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
\r
1703 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
\r
1704 * @retval HAL status
\r
1706 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
\r
1708 /* Check the parameters */
\r
1709 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
\r
1713 case TIM_CHANNEL_1:
\r
1715 /* Disable the TIM Capture/Compare 1 interrupt */
\r
1716 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
\r
1720 case TIM_CHANNEL_2:
\r
1722 /* Disable the TIM Capture/Compare 2 interrupt */
\r
1723 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
\r
1727 case TIM_CHANNEL_3:
\r
1729 /* Disable the TIM Capture/Compare 3 interrupt */
\r
1730 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
\r
1734 case TIM_CHANNEL_4:
\r
1736 /* Disable the TIM Capture/Compare 4 interrupt */
\r
1737 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
\r
1745 /* Disable the Input Capture channel */
\r
1746 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
\r
1748 /* Disable the Peripheral */
\r
1749 __HAL_TIM_DISABLE(htim);
\r
1751 /* Return function status */
\r
1756 * @brief Starts the TIM Input Capture measurement on in DMA mode.
\r
1757 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
1758 * the configuration information for TIM module.
\r
1759 * @param Channel: TIM Channels to be enabled.
\r
1760 * This parameter can be one of the following values:
\r
1761 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
1762 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
1763 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
\r
1764 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
\r
1765 * @param pData: The destination Buffer address.
\r
1766 * @param Length: The length of data to be transferred from TIM peripheral to memory.
\r
1767 * @retval HAL status
\r
1769 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
\r
1771 /* Check the parameters */
\r
1772 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
\r
1773 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
\r
1775 if((htim->State == HAL_TIM_STATE_BUSY))
\r
1779 else if((htim->State == HAL_TIM_STATE_READY))
\r
1781 if((pData == 0 ) && (Length > 0))
\r
1783 return HAL_ERROR;
\r
1787 htim->State = HAL_TIM_STATE_BUSY;
\r
1793 case TIM_CHANNEL_1:
\r
1795 /* Set the DMA Period elapsed callback */
\r
1796 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
\r
1798 /* Set the DMA error callback */
\r
1799 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
\r
1801 /* Enable the DMA Stream */
\r
1802 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
\r
1804 /* Enable the TIM Capture/Compare 1 DMA request */
\r
1805 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
\r
1809 case TIM_CHANNEL_2:
\r
1811 /* Set the DMA Period elapsed callback */
\r
1812 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
\r
1814 /* Set the DMA error callback */
\r
1815 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
\r
1817 /* Enable the DMA Stream */
\r
1818 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
\r
1820 /* Enable the TIM Capture/Compare 2 DMA request */
\r
1821 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
\r
1825 case TIM_CHANNEL_3:
\r
1827 /* Set the DMA Period elapsed callback */
\r
1828 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
\r
1830 /* Set the DMA error callback */
\r
1831 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
\r
1833 /* Enable the DMA Stream */
\r
1834 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
\r
1836 /* Enable the TIM Capture/Compare 3 DMA request */
\r
1837 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
\r
1841 case TIM_CHANNEL_4:
\r
1843 /* Set the DMA Period elapsed callback */
\r
1844 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
\r
1846 /* Set the DMA error callback */
\r
1847 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
\r
1849 /* Enable the DMA Stream */
\r
1850 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
\r
1852 /* Enable the TIM Capture/Compare 4 DMA request */
\r
1853 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
\r
1861 /* Enable the Input Capture channel */
\r
1862 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
\r
1864 /* Enable the Peripheral */
\r
1865 __HAL_TIM_ENABLE(htim);
\r
1867 /* Return function status */
\r
1872 * @brief Stops the TIM Input Capture measurement on in DMA mode.
\r
1873 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
1874 * the configuration information for TIM module.
\r
1875 * @param Channel: TIM Channels to be disabled.
\r
1876 * This parameter can be one of the following values:
\r
1877 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
1878 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
1879 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
\r
1880 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
\r
1881 * @retval HAL status
\r
1883 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
\r
1885 /* Check the parameters */
\r
1886 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
\r
1887 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
\r
1891 case TIM_CHANNEL_1:
\r
1893 /* Disable the TIM Capture/Compare 1 DMA request */
\r
1894 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
\r
1898 case TIM_CHANNEL_2:
\r
1900 /* Disable the TIM Capture/Compare 2 DMA request */
\r
1901 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
\r
1905 case TIM_CHANNEL_3:
\r
1907 /* Disable the TIM Capture/Compare 3 DMA request */
\r
1908 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
\r
1912 case TIM_CHANNEL_4:
\r
1914 /* Disable the TIM Capture/Compare 4 DMA request */
\r
1915 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
\r
1923 /* Disable the Input Capture channel */
\r
1924 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
\r
1926 /* Disable the Peripheral */
\r
1927 __HAL_TIM_DISABLE(htim);
\r
1929 /* Change the htim state */
\r
1930 htim->State = HAL_TIM_STATE_READY;
\r
1932 /* Return function status */
\r
1939 /** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
\r
1940 * @brief Time One Pulse functions
\r
1943 ==============================================================================
\r
1944 ##### Time One Pulse functions #####
\r
1945 ==============================================================================
\r
1947 This section provides functions allowing to:
\r
1948 (+) Initialize and configure the TIM One Pulse.
\r
1949 (+) De-initialize the TIM One Pulse.
\r
1950 (+) Start the Time One Pulse.
\r
1951 (+) Stop the Time One Pulse.
\r
1952 (+) Start the Time One Pulse and enable interrupt.
\r
1953 (+) Stop the Time One Pulse and disable interrupt.
\r
1954 (+) Start the Time One Pulse and enable DMA transfer.
\r
1955 (+) Stop the Time One Pulse and disable DMA transfer.
\r
1961 * @brief Initializes the TIM One Pulse Time Base according to the specified
\r
1962 * parameters in the TIM_HandleTypeDef and create the associated handle.
\r
1963 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
1964 * the configuration information for TIM module.
\r
1965 * @param OnePulseMode: Select the One pulse mode.
\r
1966 * This parameter can be one of the following values:
\r
1967 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
\r
1968 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
\r
1969 * @retval HAL status
\r
1971 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
\r
1973 /* Check the TIM handle allocation */
\r
1979 /* Check the parameters */
\r
1980 assert_param(IS_TIM_INSTANCE(htim->Instance));
\r
1981 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
\r
1982 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
\r
1983 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
\r
1985 if(htim->State == HAL_TIM_STATE_RESET)
\r
1987 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
\r
1988 HAL_TIM_OnePulse_MspInit(htim);
\r
1991 /* Set the TIM state */
\r
1992 htim->State= HAL_TIM_STATE_BUSY;
\r
1994 /* Configure the Time base in the One Pulse Mode */
\r
1995 TIM_Base_SetConfig(htim->Instance, &htim->Init);
\r
1997 /* Reset the OPM Bit */
\r
1998 htim->Instance->CR1 &= ~TIM_CR1_OPM;
\r
2000 /* Configure the OPM Mode */
\r
2001 htim->Instance->CR1 |= OnePulseMode;
\r
2003 /* Initialize the TIM state*/
\r
2004 htim->State= HAL_TIM_STATE_READY;
\r
2010 * @brief DeInitializes the TIM One Pulse
\r
2011 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
2012 * the configuration information for TIM module.
\r
2013 * @retval HAL status
\r
2015 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
\r
2017 /* Check the parameters */
\r
2018 assert_param(IS_TIM_INSTANCE(htim->Instance));
\r
2020 htim->State = HAL_TIM_STATE_BUSY;
\r
2022 /* Disable the TIM Peripheral Clock */
\r
2023 __HAL_TIM_DISABLE(htim);
\r
2025 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
\r
2026 HAL_TIM_OnePulse_MspDeInit(htim);
\r
2028 /* Change TIM state */
\r
2029 htim->State = HAL_TIM_STATE_RESET;
\r
2031 /* Release Lock */
\r
2032 __HAL_UNLOCK(htim);
\r
2038 * @brief Initializes the TIM One Pulse MSP.
\r
2039 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
2040 * the configuration information for TIM module.
\r
2043 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
\r
2045 /* NOTE : This function Should not be modified, when the callback is needed,
\r
2046 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
\r
2051 * @brief DeInitializes TIM One Pulse MSP.
\r
2052 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
2053 * the configuration information for TIM module.
\r
2056 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
\r
2058 /* NOTE : This function Should not be modified, when the callback is needed,
\r
2059 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
\r
2064 * @brief Starts the TIM One Pulse signal generation.
\r
2065 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
2066 * the configuration information for TIM module.
\r
2067 * @param OutputChannel : TIM Channels to be enabled.
\r
2068 * This parameter can be one of the following values:
\r
2069 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
2070 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
2071 * @retval HAL status
\r
2073 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
\r
2075 /* Enable the Capture compare and the Input Capture channels
\r
2076 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
\r
2077 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
\r
2078 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
\r
2079 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
\r
2081 No need to enable the counter, it's enabled automatically by hardware
\r
2082 (the counter starts in response to a stimulus and generate a pulse */
\r
2084 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
\r
2085 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
\r
2087 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
\r
2089 /* Enable the main output */
\r
2090 __HAL_TIM_MOE_ENABLE(htim);
\r
2093 /* Return function status */
\r
2098 * @brief Stops the TIM One Pulse signal generation.
\r
2099 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
2100 * the configuration information for TIM module.
\r
2101 * @param OutputChannel : TIM Channels to be disable.
\r
2102 * This parameter can be one of the following values:
\r
2103 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
2104 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
2105 * @retval HAL status
\r
2107 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
\r
2109 /* Disable the Capture compare and the Input Capture channels
\r
2110 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
\r
2111 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
\r
2112 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
\r
2113 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
\r
2115 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
\r
2116 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
\r
2118 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
\r
2120 /* Disable the Main Output */
\r
2121 __HAL_TIM_MOE_DISABLE(htim);
\r
2124 /* Disable the Peripheral */
\r
2125 __HAL_TIM_DISABLE(htim);
\r
2127 /* Return function status */
\r
2132 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
\r
2133 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
2134 * the configuration information for TIM module.
\r
2135 * @param OutputChannel : TIM Channels to be enabled.
\r
2136 * This parameter can be one of the following values:
\r
2137 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
2138 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
2139 * @retval HAL status
\r
2141 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
\r
2143 /* Enable the Capture compare and the Input Capture channels
\r
2144 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
\r
2145 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
\r
2146 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
\r
2147 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
\r
2149 No need to enable the counter, it's enabled automatically by hardware
\r
2150 (the counter starts in response to a stimulus and generate a pulse */
\r
2152 /* Enable the TIM Capture/Compare 1 interrupt */
\r
2153 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
\r
2155 /* Enable the TIM Capture/Compare 2 interrupt */
\r
2156 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
\r
2158 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
\r
2159 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
\r
2161 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
\r
2163 /* Enable the main output */
\r
2164 __HAL_TIM_MOE_ENABLE(htim);
\r
2167 /* Return function status */
\r
2172 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
\r
2173 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
2174 * the configuration information for TIM module.
\r
2175 * @param OutputChannel : TIM Channels to be enabled.
\r
2176 * This parameter can be one of the following values:
\r
2177 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
2178 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
2179 * @retval HAL status
\r
2181 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
\r
2183 /* Disable the TIM Capture/Compare 1 interrupt */
\r
2184 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
\r
2186 /* Disable the TIM Capture/Compare 2 interrupt */
\r
2187 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
\r
2189 /* Disable the Capture compare and the Input Capture channels
\r
2190 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
\r
2191 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
\r
2192 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
\r
2193 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
\r
2194 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
\r
2195 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
\r
2197 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
\r
2199 /* Disable the Main Output */
\r
2200 __HAL_TIM_MOE_DISABLE(htim);
\r
2203 /* Disable the Peripheral */
\r
2204 __HAL_TIM_DISABLE(htim);
\r
2206 /* Return function status */
\r
2214 /** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
\r
2215 * @brief Time Encoder functions
\r
2218 ==============================================================================
\r
2219 ##### Time Encoder functions #####
\r
2220 ==============================================================================
\r
2222 This section provides functions allowing to:
\r
2223 (+) Initialize and configure the TIM Encoder.
\r
2224 (+) De-initialize the TIM Encoder.
\r
2225 (+) Start the Time Encoder.
\r
2226 (+) Stop the Time Encoder.
\r
2227 (+) Start the Time Encoder and enable interrupt.
\r
2228 (+) Stop the Time Encoder and disable interrupt.
\r
2229 (+) Start the Time Encoder and enable DMA transfer.
\r
2230 (+) Stop the Time Encoder and disable DMA transfer.
\r
2236 * @brief Initializes the TIM Encoder Interface and create the associated handle.
\r
2237 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
2238 * the configuration information for TIM module.
\r
2239 * @param sConfig: TIM Encoder Interface configuration structure
\r
2240 * @retval HAL status
\r
2242 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig)
\r
2244 uint32_t tmpsmcr = 0;
\r
2245 uint32_t tmpccmr1 = 0;
\r
2246 uint32_t tmpccer = 0;
\r
2248 /* Check the TIM handle allocation */
\r
2254 /* Check the parameters */
\r
2255 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
\r
2256 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
\r
2257 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
\r
2258 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
\r
2259 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
\r
2260 assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
\r
2261 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
\r
2262 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
\r
2263 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
\r
2264 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
\r
2266 if(htim->State == HAL_TIM_STATE_RESET)
\r
2268 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
\r
2269 HAL_TIM_Encoder_MspInit(htim);
\r
2272 /* Set the TIM state */
\r
2273 htim->State= HAL_TIM_STATE_BUSY;
\r
2275 /* Reset the SMS bits */
\r
2276 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
\r
2278 /* Configure the Time base in the Encoder Mode */
\r
2279 TIM_Base_SetConfig(htim->Instance, &htim->Init);
\r
2281 /* Get the TIMx SMCR register value */
\r
2282 tmpsmcr = htim->Instance->SMCR;
\r
2284 /* Get the TIMx CCMR1 register value */
\r
2285 tmpccmr1 = htim->Instance->CCMR1;
\r
2287 /* Get the TIMx CCER register value */
\r
2288 tmpccer = htim->Instance->CCER;
\r
2290 /* Set the encoder Mode */
\r
2291 tmpsmcr |= sConfig->EncoderMode;
\r
2293 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
\r
2294 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
\r
2295 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8));
\r
2297 /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
\r
2298 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
\r
2299 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
\r
2300 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8);
\r
2301 tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12);
\r
2303 /* Set the TI1 and the TI2 Polarities */
\r
2304 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
\r
2305 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
\r
2306 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4);
\r
2308 /* Write to TIMx SMCR */
\r
2309 htim->Instance->SMCR = tmpsmcr;
\r
2311 /* Write to TIMx CCMR1 */
\r
2312 htim->Instance->CCMR1 = tmpccmr1;
\r
2314 /* Write to TIMx CCER */
\r
2315 htim->Instance->CCER = tmpccer;
\r
2317 /* Initialize the TIM state*/
\r
2318 htim->State= HAL_TIM_STATE_READY;
\r
2324 * @brief DeInitializes the TIM Encoder interface
\r
2325 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
2326 * the configuration information for TIM module.
\r
2327 * @retval HAL status
\r
2329 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
\r
2331 /* Check the parameters */
\r
2332 assert_param(IS_TIM_INSTANCE(htim->Instance));
\r
2334 htim->State = HAL_TIM_STATE_BUSY;
\r
2336 /* Disable the TIM Peripheral Clock */
\r
2337 __HAL_TIM_DISABLE(htim);
\r
2339 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
\r
2340 HAL_TIM_Encoder_MspDeInit(htim);
\r
2342 /* Change TIM state */
\r
2343 htim->State = HAL_TIM_STATE_RESET;
\r
2345 /* Release Lock */
\r
2346 __HAL_UNLOCK(htim);
\r
2352 * @brief Initializes the TIM Encoder Interface MSP.
\r
2353 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
2354 * the configuration information for TIM module.
\r
2357 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
\r
2359 /* NOTE : This function Should not be modified, when the callback is needed,
\r
2360 the HAL_TIM_Encoder_MspInit could be implemented in the user file
\r
2365 * @brief DeInitializes TIM Encoder Interface MSP.
\r
2366 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
2367 * the configuration information for TIM module.
\r
2370 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
\r
2372 /* NOTE : This function Should not be modified, when the callback is needed,
\r
2373 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
\r
2378 * @brief Starts the TIM Encoder Interface.
\r
2379 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
2380 * the configuration information for TIM module.
\r
2381 * @param Channel: TIM Channels to be enabled.
\r
2382 * This parameter can be one of the following values:
\r
2383 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
2384 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
2385 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
\r
2386 * @retval HAL status
\r
2388 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
\r
2390 /* Check the parameters */
\r
2391 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
\r
2393 /* Enable the encoder interface channels */
\r
2396 case TIM_CHANNEL_1:
\r
2398 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
\r
2401 case TIM_CHANNEL_2:
\r
2403 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
\r
2408 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
\r
2409 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
\r
2413 /* Enable the Peripheral */
\r
2414 __HAL_TIM_ENABLE(htim);
\r
2416 /* Return function status */
\r
2421 * @brief Stops the TIM Encoder Interface.
\r
2422 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
2423 * the configuration information for TIM module.
\r
2424 * @param Channel: TIM Channels to be disabled.
\r
2425 * This parameter can be one of the following values:
\r
2426 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
2427 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
2428 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
\r
2429 * @retval HAL status
\r
2431 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
\r
2433 /* Check the parameters */
\r
2434 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
\r
2436 /* Disable the Input Capture channels 1 and 2
\r
2437 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
\r
2440 case TIM_CHANNEL_1:
\r
2442 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
\r
2445 case TIM_CHANNEL_2:
\r
2447 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
\r
2452 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
\r
2453 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
\r
2457 /* Disable the Peripheral */
\r
2458 __HAL_TIM_DISABLE(htim);
\r
2460 /* Return function status */
\r
2465 * @brief Starts the TIM Encoder Interface in interrupt mode.
\r
2466 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
2467 * the configuration information for TIM module.
\r
2468 * @param Channel: TIM Channels to be enabled.
\r
2469 * This parameter can be one of the following values:
\r
2470 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
2471 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
2472 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
\r
2473 * @retval HAL status
\r
2475 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
\r
2477 /* Check the parameters */
\r
2478 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
\r
2480 /* Enable the encoder interface channels */
\r
2481 /* Enable the capture compare Interrupts 1 and/or 2 */
\r
2484 case TIM_CHANNEL_1:
\r
2486 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
\r
2487 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
\r
2490 case TIM_CHANNEL_2:
\r
2492 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
\r
2493 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
\r
2498 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
\r
2499 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
\r
2500 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
\r
2501 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
\r
2506 /* Enable the Peripheral */
\r
2507 __HAL_TIM_ENABLE(htim);
\r
2509 /* Return function status */
\r
2514 * @brief Stops the TIM Encoder Interface in interrupt mode.
\r
2515 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
2516 * the configuration information for TIM module.
\r
2517 * @param Channel: TIM Channels to be disabled.
\r
2518 * This parameter can be one of the following values:
\r
2519 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
2520 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
2521 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
\r
2522 * @retval HAL status
\r
2524 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
\r
2526 /* Check the parameters */
\r
2527 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
\r
2529 /* Disable the Input Capture channels 1 and 2
\r
2530 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
\r
2531 if(Channel == TIM_CHANNEL_1)
\r
2533 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
\r
2535 /* Disable the capture compare Interrupts 1 */
\r
2536 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
\r
2538 else if(Channel == TIM_CHANNEL_2)
\r
2540 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
\r
2542 /* Disable the capture compare Interrupts 2 */
\r
2543 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
\r
2547 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
\r
2548 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
\r
2550 /* Disable the capture compare Interrupts 1 and 2 */
\r
2551 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
\r
2552 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
\r
2555 /* Disable the Peripheral */
\r
2556 __HAL_TIM_DISABLE(htim);
\r
2558 /* Change the htim state */
\r
2559 htim->State = HAL_TIM_STATE_READY;
\r
2561 /* Return function status */
\r
2566 * @brief Starts the TIM Encoder Interface in DMA mode.
\r
2567 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
2568 * the configuration information for TIM module.
\r
2569 * @param Channel: TIM Channels to be enabled.
\r
2570 * This parameter can be one of the following values:
\r
2571 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
2572 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
2573 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
\r
2574 * @param pData1: The destination Buffer address for IC1.
\r
2575 * @param pData2: The destination Buffer address for IC2.
\r
2576 * @param Length: The length of data to be transferred from TIM peripheral to memory.
\r
2577 * @retval HAL status
\r
2579 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
\r
2581 /* Check the parameters */
\r
2582 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
\r
2584 if((htim->State == HAL_TIM_STATE_BUSY))
\r
2588 else if((htim->State == HAL_TIM_STATE_READY))
\r
2590 if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0))
\r
2592 return HAL_ERROR;
\r
2596 htim->State = HAL_TIM_STATE_BUSY;
\r
2602 case TIM_CHANNEL_1:
\r
2604 /* Set the DMA Period elapsed callback */
\r
2605 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
\r
2607 /* Set the DMA error callback */
\r
2608 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
\r
2610 /* Enable the DMA Stream */
\r
2611 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
\r
2613 /* Enable the TIM Input Capture DMA request */
\r
2614 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
\r
2616 /* Enable the Peripheral */
\r
2617 __HAL_TIM_ENABLE(htim);
\r
2619 /* Enable the Capture compare channel */
\r
2620 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
\r
2624 case TIM_CHANNEL_2:
\r
2626 /* Set the DMA Period elapsed callback */
\r
2627 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
\r
2629 /* Set the DMA error callback */
\r
2630 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError;
\r
2631 /* Enable the DMA Stream */
\r
2632 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
\r
2634 /* Enable the TIM Input Capture DMA request */
\r
2635 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
\r
2637 /* Enable the Peripheral */
\r
2638 __HAL_TIM_ENABLE(htim);
\r
2640 /* Enable the Capture compare channel */
\r
2641 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
\r
2645 case TIM_CHANNEL_ALL:
\r
2647 /* Set the DMA Period elapsed callback */
\r
2648 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
\r
2650 /* Set the DMA error callback */
\r
2651 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
\r
2653 /* Enable the DMA Stream */
\r
2654 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
\r
2656 /* Set the DMA Period elapsed callback */
\r
2657 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
\r
2659 /* Set the DMA error callback */
\r
2660 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
\r
2662 /* Enable the DMA Stream */
\r
2663 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
\r
2665 /* Enable the Peripheral */
\r
2666 __HAL_TIM_ENABLE(htim);
\r
2668 /* Enable the Capture compare channel */
\r
2669 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
\r
2670 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
\r
2672 /* Enable the TIM Input Capture DMA request */
\r
2673 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
\r
2674 /* Enable the TIM Input Capture DMA request */
\r
2675 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
\r
2682 /* Return function status */
\r
2687 * @brief Stops the TIM Encoder Interface in DMA mode.
\r
2688 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
2689 * the configuration information for TIM module.
\r
2690 * @param Channel: TIM Channels to be enabled.
\r
2691 * This parameter can be one of the following values:
\r
2692 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
2693 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
2694 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
\r
2695 * @retval HAL status
\r
2697 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
\r
2699 /* Check the parameters */
\r
2700 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
\r
2702 /* Disable the Input Capture channels 1 and 2
\r
2703 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
\r
2704 if(Channel == TIM_CHANNEL_1)
\r
2706 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
\r
2708 /* Disable the capture compare DMA Request 1 */
\r
2709 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
\r
2711 else if(Channel == TIM_CHANNEL_2)
\r
2713 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
\r
2715 /* Disable the capture compare DMA Request 2 */
\r
2716 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
\r
2720 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
\r
2721 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
\r
2723 /* Disable the capture compare DMA Request 1 and 2 */
\r
2724 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
\r
2725 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
\r
2728 /* Disable the Peripheral */
\r
2729 __HAL_TIM_DISABLE(htim);
\r
2731 /* Change the htim state */
\r
2732 htim->State = HAL_TIM_STATE_READY;
\r
2734 /* Return function status */
\r
2741 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
\r
2742 * @brief IRQ handler management
\r
2745 ==============================================================================
\r
2746 ##### IRQ handler management #####
\r
2747 ==============================================================================
\r
2749 This section provides Timer IRQ handler function.
\r
2755 * @brief This function handles TIM interrupts requests.
\r
2756 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
2757 * the configuration information for TIM module.
\r
2760 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
\r
2762 /* Capture compare 1 event */
\r
2763 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
\r
2765 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
\r
2768 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
\r
2769 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
\r
2771 /* Input capture event */
\r
2772 if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
\r
2774 HAL_TIM_IC_CaptureCallback(htim);
\r
2776 /* Output compare event */
\r
2779 HAL_TIM_OC_DelayElapsedCallback(htim);
\r
2780 HAL_TIM_PWM_PulseFinishedCallback(htim);
\r
2782 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
\r
2786 /* Capture compare 2 event */
\r
2787 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
\r
2789 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
\r
2791 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
\r
2792 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
\r
2793 /* Input capture event */
\r
2794 if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
\r
2796 HAL_TIM_IC_CaptureCallback(htim);
\r
2798 /* Output compare event */
\r
2801 HAL_TIM_OC_DelayElapsedCallback(htim);
\r
2802 HAL_TIM_PWM_PulseFinishedCallback(htim);
\r
2804 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
\r
2807 /* Capture compare 3 event */
\r
2808 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
\r
2810 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
\r
2812 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
\r
2813 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
\r
2814 /* Input capture event */
\r
2815 if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
\r
2817 HAL_TIM_IC_CaptureCallback(htim);
\r
2819 /* Output compare event */
\r
2822 HAL_TIM_OC_DelayElapsedCallback(htim);
\r
2823 HAL_TIM_PWM_PulseFinishedCallback(htim);
\r
2825 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
\r
2828 /* Capture compare 4 event */
\r
2829 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
\r
2831 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
\r
2833 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
\r
2834 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
\r
2835 /* Input capture event */
\r
2836 if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
\r
2838 HAL_TIM_IC_CaptureCallback(htim);
\r
2840 /* Output compare event */
\r
2843 HAL_TIM_OC_DelayElapsedCallback(htim);
\r
2844 HAL_TIM_PWM_PulseFinishedCallback(htim);
\r
2846 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
\r
2849 /* TIM Update event */
\r
2850 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
\r
2852 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
\r
2854 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
\r
2855 HAL_TIM_PeriodElapsedCallback(htim);
\r
2858 /* TIM Break input event */
\r
2859 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
\r
2861 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
\r
2863 __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
\r
2864 HAL_TIMEx_BreakCallback(htim);
\r
2868 /* TIM Break input event */
\r
2869 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
\r
2871 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
\r
2873 __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
\r
2874 HAL_TIMEx_BreakCallback(htim);
\r
2878 /* TIM Trigger detection event */
\r
2879 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
\r
2881 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
\r
2883 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
\r
2884 HAL_TIM_TriggerCallback(htim);
\r
2887 /* TIM commutation event */
\r
2888 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
\r
2890 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
\r
2892 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
\r
2893 HAL_TIMEx_CommutationCallback(htim);
\r
2902 /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
\r
2903 * @brief Peripheral Control functions
\r
2906 ==============================================================================
\r
2907 ##### Peripheral Control functions #####
\r
2908 ==============================================================================
\r
2910 This section provides functions allowing to:
\r
2911 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
\r
2912 (+) Configure External Clock source.
\r
2913 (+) Configure Complementary channels, break features and dead time.
\r
2914 (+) Configure Master and the Slave synchronization.
\r
2915 (+) Configure the DMA Burst Mode.
\r
2922 * @brief Initializes the TIM Output Compare Channels according to the specified
\r
2923 * parameters in the TIM_OC_InitTypeDef.
\r
2924 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
2925 * the configuration information for TIM module.
\r
2926 * @param sConfig: TIM Output Compare configuration structure
\r
2927 * @param Channel: TIM Channels to be enabled.
\r
2928 * This parameter can be one of the following values:
\r
2929 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
2930 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
2931 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
\r
2932 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
\r
2933 * @retval HAL status
\r
2935 __weak HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
\r
2937 /* Check the parameters */
\r
2938 assert_param(IS_TIM_CHANNELS(Channel));
\r
2939 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
\r
2940 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
\r
2941 assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
\r
2942 assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
\r
2943 assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
\r
2945 /* Check input state */
\r
2946 __HAL_LOCK(htim);
\r
2948 htim->State = HAL_TIM_STATE_BUSY;
\r
2952 case TIM_CHANNEL_1:
\r
2954 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
\r
2955 /* Configure the TIM Channel 1 in Output Compare */
\r
2956 TIM_OC1_SetConfig(htim->Instance, sConfig);
\r
2960 case TIM_CHANNEL_2:
\r
2962 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
\r
2963 /* Configure the TIM Channel 2 in Output Compare */
\r
2964 TIM_OC2_SetConfig(htim->Instance, sConfig);
\r
2968 case TIM_CHANNEL_3:
\r
2970 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
\r
2971 /* Configure the TIM Channel 3 in Output Compare */
\r
2972 TIM_OC3_SetConfig(htim->Instance, sConfig);
\r
2976 case TIM_CHANNEL_4:
\r
2978 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
\r
2979 /* Configure the TIM Channel 4 in Output Compare */
\r
2980 TIM_OC4_SetConfig(htim->Instance, sConfig);
\r
2987 htim->State = HAL_TIM_STATE_READY;
\r
2989 __HAL_UNLOCK(htim);
\r
2995 * @brief Initializes the TIM Input Capture Channels according to the specified
\r
2996 * parameters in the TIM_IC_InitTypeDef.
\r
2997 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
2998 * the configuration information for TIM module.
\r
2999 * @param sConfig: TIM Input Capture configuration structure
\r
3000 * @param Channel: TIM Channels to be enabled.
\r
3001 * This parameter can be one of the following values:
\r
3002 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
3003 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
3004 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
\r
3005 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
\r
3006 * @retval HAL status
\r
3008 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
\r
3010 /* Check the parameters */
\r
3011 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
\r
3012 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
\r
3013 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
\r
3014 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
\r
3015 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
\r
3019 htim->State = HAL_TIM_STATE_BUSY;
\r
3021 if (Channel == TIM_CHANNEL_1)
\r
3023 /* TI1 Configuration */
\r
3024 TIM_TI1_SetConfig(htim->Instance,
\r
3025 sConfig->ICPolarity,
\r
3026 sConfig->ICSelection,
\r
3027 sConfig->ICFilter);
\r
3029 /* Reset the IC1PSC Bits */
\r
3030 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
\r
3032 /* Set the IC1PSC value */
\r
3033 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
\r
3035 else if (Channel == TIM_CHANNEL_2)
\r
3037 /* TI2 Configuration */
\r
3038 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
\r
3040 TIM_TI2_SetConfig(htim->Instance,
\r
3041 sConfig->ICPolarity,
\r
3042 sConfig->ICSelection,
\r
3043 sConfig->ICFilter);
\r
3045 /* Reset the IC2PSC Bits */
\r
3046 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
\r
3048 /* Set the IC2PSC value */
\r
3049 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8);
\r
3051 else if (Channel == TIM_CHANNEL_3)
\r
3053 /* TI3 Configuration */
\r
3054 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
\r
3056 TIM_TI3_SetConfig(htim->Instance,
\r
3057 sConfig->ICPolarity,
\r
3058 sConfig->ICSelection,
\r
3059 sConfig->ICFilter);
\r
3061 /* Reset the IC3PSC Bits */
\r
3062 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
\r
3064 /* Set the IC3PSC value */
\r
3065 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
\r
3069 /* TI4 Configuration */
\r
3070 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
\r
3072 TIM_TI4_SetConfig(htim->Instance,
\r
3073 sConfig->ICPolarity,
\r
3074 sConfig->ICSelection,
\r
3075 sConfig->ICFilter);
\r
3077 /* Reset the IC4PSC Bits */
\r
3078 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
\r
3080 /* Set the IC4PSC value */
\r
3081 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8);
\r
3084 htim->State = HAL_TIM_STATE_READY;
\r
3086 __HAL_UNLOCK(htim);
\r
3092 * @brief Initializes the TIM PWM channels according to the specified
\r
3093 * parameters in the TIM_OC_InitTypeDef.
\r
3094 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
3095 * the configuration information for TIM module.
\r
3096 * @param sConfig: TIM PWM configuration structure
\r
3097 * @param Channel: TIM Channels to be enabled.
\r
3098 * This parameter can be one of the following values:
\r
3099 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
3100 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
3101 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
\r
3102 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
\r
3103 * @retval HAL status
\r
3105 __weak HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
\r
3109 /* Check the parameters */
\r
3110 assert_param(IS_TIM_CHANNELS(Channel));
\r
3111 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
\r
3112 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
\r
3113 assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
\r
3114 assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
\r
3115 assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
\r
3116 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
\r
3118 htim->State = HAL_TIM_STATE_BUSY;
\r
3122 case TIM_CHANNEL_1:
\r
3124 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
\r
3125 /* Configure the Channel 1 in PWM mode */
\r
3126 TIM_OC1_SetConfig(htim->Instance, sConfig);
\r
3128 /* Set the Preload enable bit for channel1 */
\r
3129 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
\r
3131 /* Configure the Output Fast mode */
\r
3132 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
\r
3133 htim->Instance->CCMR1 |= sConfig->OCFastMode;
\r
3137 case TIM_CHANNEL_2:
\r
3139 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
\r
3140 /* Configure the Channel 2 in PWM mode */
\r
3141 TIM_OC2_SetConfig(htim->Instance, sConfig);
\r
3143 /* Set the Preload enable bit for channel2 */
\r
3144 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
\r
3146 /* Configure the Output Fast mode */
\r
3147 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
\r
3148 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
\r
3152 case TIM_CHANNEL_3:
\r
3154 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
\r
3155 /* Configure the Channel 3 in PWM mode */
\r
3156 TIM_OC3_SetConfig(htim->Instance, sConfig);
\r
3158 /* Set the Preload enable bit for channel3 */
\r
3159 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
\r
3161 /* Configure the Output Fast mode */
\r
3162 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
\r
3163 htim->Instance->CCMR2 |= sConfig->OCFastMode;
\r
3167 case TIM_CHANNEL_4:
\r
3169 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
\r
3170 /* Configure the Channel 4 in PWM mode */
\r
3171 TIM_OC4_SetConfig(htim->Instance, sConfig);
\r
3173 /* Set the Preload enable bit for channel4 */
\r
3174 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
\r
3176 /* Configure the Output Fast mode */
\r
3177 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
\r
3178 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
\r
3186 htim->State = HAL_TIM_STATE_READY;
\r
3188 __HAL_UNLOCK(htim);
\r
3194 * @brief Initializes the TIM One Pulse Channels according to the specified
\r
3195 * parameters in the TIM_OnePulse_InitTypeDef.
\r
3196 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
3197 * the configuration information for TIM module.
\r
3198 * @param sConfig: TIM One Pulse configuration structure
\r
3199 * @param OutputChannel: TIM Channels to be enabled.
\r
3200 * This parameter can be one of the following values:
\r
3201 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
3202 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
3203 * @param InputChannel: TIM Channels to be enabled.
\r
3204 * This parameter can be one of the following values:
\r
3205 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
3206 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
3207 * @retval HAL status
\r
3209 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel)
\r
3211 TIM_OC_InitTypeDef temp1;
\r
3213 /* Check the parameters */
\r
3214 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
\r
3215 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
\r
3217 if(OutputChannel != InputChannel)
\r
3221 htim->State = HAL_TIM_STATE_BUSY;
\r
3223 /* Extract the Output compare configuration from sConfig structure */
\r
3224 temp1.OCMode = sConfig->OCMode;
\r
3225 temp1.Pulse = sConfig->Pulse;
\r
3226 temp1.OCPolarity = sConfig->OCPolarity;
\r
3227 temp1.OCNPolarity = sConfig->OCNPolarity;
\r
3228 temp1.OCIdleState = sConfig->OCIdleState;
\r
3229 temp1.OCNIdleState = sConfig->OCNIdleState;
\r
3231 switch (OutputChannel)
\r
3233 case TIM_CHANNEL_1:
\r
3235 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
\r
3237 TIM_OC1_SetConfig(htim->Instance, &temp1);
\r
3240 case TIM_CHANNEL_2:
\r
3242 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
\r
3244 TIM_OC2_SetConfig(htim->Instance, &temp1);
\r
3250 switch (InputChannel)
\r
3252 case TIM_CHANNEL_1:
\r
3254 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
\r
3256 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
\r
3257 sConfig->ICSelection, sConfig->ICFilter);
\r
3259 /* Reset the IC1PSC Bits */
\r
3260 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
\r
3262 /* Select the Trigger source */
\r
3263 htim->Instance->SMCR &= ~TIM_SMCR_TS;
\r
3264 htim->Instance->SMCR |= TIM_TS_TI1FP1;
\r
3266 /* Select the Slave Mode */
\r
3267 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
\r
3268 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
\r
3271 case TIM_CHANNEL_2:
\r
3273 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
\r
3275 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
\r
3276 sConfig->ICSelection, sConfig->ICFilter);
\r
3278 /* Reset the IC2PSC Bits */
\r
3279 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
\r
3281 /* Select the Trigger source */
\r
3282 htim->Instance->SMCR &= ~TIM_SMCR_TS;
\r
3283 htim->Instance->SMCR |= TIM_TS_TI2FP2;
\r
3285 /* Select the Slave Mode */
\r
3286 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
\r
3287 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
\r
3295 htim->State = HAL_TIM_STATE_READY;
\r
3297 __HAL_UNLOCK(htim);
\r
3308 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
\r
3309 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
3310 * the configuration information for TIM module.
\r
3311 * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write.
\r
3312 * This parameters can be on of the following values:
\r
3313 * @arg TIM_DMABASE_CR1
\r
3314 * @arg TIM_DMABASE_CR2
\r
3315 * @arg TIM_DMABASE_SMCR
\r
3316 * @arg TIM_DMABASE_DIER
\r
3317 * @arg TIM_DMABASE_SR
\r
3318 * @arg TIM_DMABASE_EGR
\r
3319 * @arg TIM_DMABASE_CCMR1
\r
3320 * @arg TIM_DMABASE_CCMR2
\r
3321 * @arg TIM_DMABASE_CCER
\r
3322 * @arg TIM_DMABASE_CNT
\r
3323 * @arg TIM_DMABASE_PSC
\r
3324 * @arg TIM_DMABASE_ARR
\r
3325 * @arg TIM_DMABASE_RCR
\r
3326 * @arg TIM_DMABASE_CCR1
\r
3327 * @arg TIM_DMABASE_CCR2
\r
3328 * @arg TIM_DMABASE_CCR3
\r
3329 * @arg TIM_DMABASE_CCR4
\r
3330 * @arg TIM_DMABASE_BDTR
\r
3331 * @arg TIM_DMABASE_DCR
\r
3332 * @param BurstRequestSrc: TIM DMA Request sources.
\r
3333 * This parameters can be on of the following values:
\r
3334 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
\r
3335 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
\r
3336 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
\r
3337 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
\r
3338 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
\r
3339 * @arg TIM_DMA_COM: TIM Commutation DMA source
\r
3340 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
\r
3341 * @param BurstBuffer: The Buffer address.
\r
3342 * @param BurstLength: DMA Burst length. This parameter can be one value
\r
3343 * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
\r
3344 * @retval HAL status
\r
3346 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
\r
3347 uint32_t* BurstBuffer, uint32_t BurstLength)
\r
3349 /* Check the parameters */
\r
3350 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
\r
3351 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
\r
3352 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
\r
3353 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
\r
3355 if((htim->State == HAL_TIM_STATE_BUSY))
\r
3359 else if((htim->State == HAL_TIM_STATE_READY))
\r
3361 if((BurstBuffer == 0 ) && (BurstLength > 0))
\r
3363 return HAL_ERROR;
\r
3367 htim->State = HAL_TIM_STATE_BUSY;
\r
3370 switch(BurstRequestSrc)
\r
3372 case TIM_DMA_UPDATE:
\r
3374 /* Set the DMA Period elapsed callback */
\r
3375 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
\r
3377 /* Set the DMA error callback */
\r
3378 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
\r
3380 /* Enable the DMA Stream */
\r
3381 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
\r
3386 /* Set the DMA Period elapsed callback */
\r
3387 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
\r
3389 /* Set the DMA error callback */
\r
3390 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
\r
3392 /* Enable the DMA Stream */
\r
3393 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
\r
3398 /* Set the DMA Period elapsed callback */
\r
3399 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
\r
3401 /* Set the DMA error callback */
\r
3402 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
\r
3404 /* Enable the DMA Stream */
\r
3405 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
\r
3410 /* Set the DMA Period elapsed callback */
\r
3411 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
\r
3413 /* Set the DMA error callback */
\r
3414 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
\r
3416 /* Enable the DMA Stream */
\r
3417 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
\r
3422 /* Set the DMA Period elapsed callback */
\r
3423 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
\r
3425 /* Set the DMA error callback */
\r
3426 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
\r
3428 /* Enable the DMA Stream */
\r
3429 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
\r
3434 /* Set the DMA Period elapsed callback */
\r
3435 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
\r
3437 /* Set the DMA error callback */
\r
3438 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
\r
3440 /* Enable the DMA Stream */
\r
3441 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
\r
3444 case TIM_DMA_TRIGGER:
\r
3446 /* Set the DMA Period elapsed callback */
\r
3447 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
\r
3449 /* Set the DMA error callback */
\r
3450 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
\r
3452 /* Enable the DMA Stream */
\r
3453 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
\r
3459 /* configure the DMA Burst Mode */
\r
3460 htim->Instance->DCR = BurstBaseAddress | BurstLength;
\r
3462 /* Enable the TIM DMA Request */
\r
3463 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
\r
3465 htim->State = HAL_TIM_STATE_READY;
\r
3467 /* Return function status */
\r
3472 * @brief Stops the TIM DMA Burst mode
\r
3473 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
3474 * the configuration information for TIM module.
\r
3475 * @param BurstRequestSrc: TIM DMA Request sources to disable
\r
3476 * @retval HAL status
\r
3478 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
\r
3480 /* Check the parameters */
\r
3481 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
\r
3483 /* Abort the DMA transfer (at least disable the DMA channel) */
\r
3484 switch(BurstRequestSrc)
\r
3486 case TIM_DMA_UPDATE:
\r
3488 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
\r
3493 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
\r
3498 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
\r
3503 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
\r
3508 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
\r
3513 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
\r
3516 case TIM_DMA_TRIGGER:
\r
3518 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
\r
3525 /* Disable the TIM Update DMA request */
\r
3526 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
\r
3528 /* Return function status */
\r
3533 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
\r
3534 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
3535 * the configuration information for TIM module.
\r
3536 * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read.
\r
3537 * This parameters can be on of the following values:
\r
3538 * @arg TIM_DMABASE_CR1
\r
3539 * @arg TIM_DMABASE_CR2
\r
3540 * @arg TIM_DMABASE_SMCR
\r
3541 * @arg TIM_DMABASE_DIER
\r
3542 * @arg TIM_DMABASE_SR
\r
3543 * @arg TIM_DMABASE_EGR
\r
3544 * @arg TIM_DMABASE_CCMR1
\r
3545 * @arg TIM_DMABASE_CCMR2
\r
3546 * @arg TIM_DMABASE_CCER
\r
3547 * @arg TIM_DMABASE_CNT
\r
3548 * @arg TIM_DMABASE_PSC
\r
3549 * @arg TIM_DMABASE_ARR
\r
3550 * @arg TIM_DMABASE_RCR
\r
3551 * @arg TIM_DMABASE_CCR1
\r
3552 * @arg TIM_DMABASE_CCR2
\r
3553 * @arg TIM_DMABASE_CCR3
\r
3554 * @arg TIM_DMABASE_CCR4
\r
3555 * @arg TIM_DMABASE_BDTR
\r
3556 * @arg TIM_DMABASE_DCR
\r
3557 * @param BurstRequestSrc: TIM DMA Request sources.
\r
3558 * This parameters can be on of the following values:
\r
3559 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
\r
3560 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
\r
3561 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
\r
3562 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
\r
3563 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
\r
3564 * @arg TIM_DMA_COM: TIM Commutation DMA source
\r
3565 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
\r
3566 * @param BurstBuffer: The Buffer address.
\r
3567 * @param BurstLength: DMA Burst length. This parameter can be one value
\r
3568 * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
\r
3569 * @retval HAL status
\r
3571 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
\r
3572 uint32_t *BurstBuffer, uint32_t BurstLength)
\r
3574 /* Check the parameters */
\r
3575 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
\r
3576 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
\r
3577 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
\r
3578 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
\r
3580 if((htim->State == HAL_TIM_STATE_BUSY))
\r
3584 else if((htim->State == HAL_TIM_STATE_READY))
\r
3586 if((BurstBuffer == 0 ) && (BurstLength > 0))
\r
3588 return HAL_ERROR;
\r
3592 htim->State = HAL_TIM_STATE_BUSY;
\r
3595 switch(BurstRequestSrc)
\r
3597 case TIM_DMA_UPDATE:
\r
3599 /* Set the DMA Period elapsed callback */
\r
3600 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
\r
3602 /* Set the DMA error callback */
\r
3603 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
\r
3605 /* Enable the DMA Stream */
\r
3606 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
\r
3611 /* Set the DMA Period elapsed callback */
\r
3612 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
\r
3614 /* Set the DMA error callback */
\r
3615 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
\r
3617 /* Enable the DMA Stream */
\r
3618 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
\r
3623 /* Set the DMA Period elapsed callback */
\r
3624 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
\r
3626 /* Set the DMA error callback */
\r
3627 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
\r
3629 /* Enable the DMA Stream */
\r
3630 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
\r
3635 /* Set the DMA Period elapsed callback */
\r
3636 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
\r
3638 /* Set the DMA error callback */
\r
3639 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
\r
3641 /* Enable the DMA Stream */
\r
3642 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
\r
3647 /* Set the DMA Period elapsed callback */
\r
3648 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
\r
3650 /* Set the DMA error callback */
\r
3651 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
\r
3653 /* Enable the DMA Stream */
\r
3654 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
\r
3659 /* Set the DMA Period elapsed callback */
\r
3660 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
\r
3662 /* Set the DMA error callback */
\r
3663 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
\r
3665 /* Enable the DMA Stream */
\r
3666 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
\r
3669 case TIM_DMA_TRIGGER:
\r
3671 /* Set the DMA Period elapsed callback */
\r
3672 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
\r
3674 /* Set the DMA error callback */
\r
3675 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
\r
3677 /* Enable the DMA Stream */
\r
3678 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
\r
3685 /* configure the DMA Burst Mode */
\r
3686 htim->Instance->DCR = BurstBaseAddress | BurstLength;
\r
3688 /* Enable the TIM DMA Request */
\r
3689 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
\r
3691 htim->State = HAL_TIM_STATE_READY;
\r
3693 /* Return function status */
\r
3698 * @brief Stop the DMA burst reading
\r
3699 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
3700 * the configuration information for TIM module.
\r
3701 * @param BurstRequestSrc: TIM DMA Request sources to disable.
\r
3702 * @retval HAL status
\r
3704 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
\r
3706 /* Check the parameters */
\r
3707 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
\r
3709 /* Abort the DMA transfer (at least disable the DMA channel) */
\r
3710 switch(BurstRequestSrc)
\r
3712 case TIM_DMA_UPDATE:
\r
3714 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
\r
3719 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
\r
3724 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
\r
3729 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
\r
3734 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
\r
3739 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
\r
3742 case TIM_DMA_TRIGGER:
\r
3744 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
\r
3751 /* Disable the TIM Update DMA request */
\r
3752 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
\r
3754 /* Return function status */
\r
3759 * @brief Generate a software event
\r
3760 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
3761 * the configuration information for TIM module.
\r
3762 * @param EventSource: specifies the event source.
\r
3763 * This parameter can be one of the following values:
\r
3764 * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
\r
3765 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
\r
3766 * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
\r
3767 * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
\r
3768 * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
\r
3769 * @arg TIM_EVENTSOURCE_COM: Timer COM event source
\r
3770 * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
\r
3771 * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
\r
3772 * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
\r
3773 * @note TIM6 and TIM7 can only generate an update event.
\r
3774 * @note TIM_EVENTSOURCE_COM, TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are used only with TIM1 and TIM8.
\r
3775 * @retval HAL status
\r
3778 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
\r
3780 /* Check the parameters */
\r
3781 assert_param(IS_TIM_INSTANCE(htim->Instance));
\r
3782 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
\r
3784 /* Process Locked */
\r
3787 /* Change the TIM state */
\r
3788 htim->State = HAL_TIM_STATE_BUSY;
\r
3790 /* Set the event sources */
\r
3791 htim->Instance->EGR = EventSource;
\r
3793 /* Change the TIM state */
\r
3794 htim->State = HAL_TIM_STATE_READY;
\r
3796 __HAL_UNLOCK(htim);
\r
3798 /* Return function status */
\r
3803 * @brief Configures the OCRef clear feature
\r
3804 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
3805 * the configuration information for TIM module.
\r
3806 * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
\r
3807 * contains the OCREF clear feature and parameters for the TIM peripheral.
\r
3808 * @param Channel: specifies the TIM Channel.
\r
3809 * This parameter can be one of the following values:
\r
3810 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
3811 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
3812 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
\r
3813 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
\r
3814 * @retval HAL status
\r
3816 __weak HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
\r
3818 /* Check the parameters */
\r
3819 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
\r
3820 assert_param(IS_TIM_CHANNELS(Channel));
\r
3821 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
\r
3823 /* Process Locked */
\r
3826 htim->State = HAL_TIM_STATE_BUSY;
\r
3828 if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR)
\r
3830 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
\r
3831 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
\r
3832 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
\r
3834 TIM_ETR_SetConfig(htim->Instance,
\r
3835 sClearInputConfig->ClearInputPrescaler,
\r
3836 sClearInputConfig->ClearInputPolarity,
\r
3837 sClearInputConfig->ClearInputFilter);
\r
3842 case TIM_CHANNEL_1:
\r
3844 if(sClearInputConfig->ClearInputState != RESET)
\r
3846 /* Enable the Ocref clear feature for Channel 1 */
\r
3847 htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
\r
3851 /* Disable the Ocref clear feature for Channel 1 */
\r
3852 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
\r
3856 case TIM_CHANNEL_2:
\r
3858 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
\r
3859 if(sClearInputConfig->ClearInputState != RESET)
\r
3861 /* Enable the Ocref clear feature for Channel 2 */
\r
3862 htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
\r
3866 /* Disable the Ocref clear feature for Channel 2 */
\r
3867 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
\r
3871 case TIM_CHANNEL_3:
\r
3873 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
\r
3874 if(sClearInputConfig->ClearInputState != RESET)
\r
3876 /* Enable the Ocref clear feature for Channel 3 */
\r
3877 htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
\r
3881 /* Disable the Ocref clear feature for Channel 3 */
\r
3882 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
\r
3886 case TIM_CHANNEL_4:
\r
3888 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
\r
3889 if(sClearInputConfig->ClearInputState != RESET)
\r
3891 /* Enable the Ocref clear feature for Channel 4 */
\r
3892 htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
\r
3896 /* Disable the Ocref clear feature for Channel 4 */
\r
3897 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
\r
3905 htim->State = HAL_TIM_STATE_READY;
\r
3907 __HAL_UNLOCK(htim);
\r
3913 * @brief Configures the clock source to be used
\r
3914 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
3915 * the configuration information for TIM module.
\r
3916 * @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
\r
3917 * contains the clock source information for the TIM peripheral.
\r
3918 * @retval HAL status
\r
3920 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
\r
3922 uint32_t tmpsmcr = 0;
\r
3924 /* Process Locked */
\r
3927 htim->State = HAL_TIM_STATE_BUSY;
\r
3929 /* Check the parameters */
\r
3930 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
\r
3931 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
\r
3932 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
\r
3933 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
\r
3935 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
\r
3936 tmpsmcr = htim->Instance->SMCR;
\r
3937 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
\r
3938 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
\r
3939 htim->Instance->SMCR = tmpsmcr;
\r
3941 switch (sClockSourceConfig->ClockSource)
\r
3943 case TIM_CLOCKSOURCE_INTERNAL:
\r
3945 assert_param(IS_TIM_INSTANCE(htim->Instance));
\r
3946 /* Disable slave mode to clock the prescaler directly with the internal clock */
\r
3947 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
\r
3951 case TIM_CLOCKSOURCE_ETRMODE1:
\r
3953 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
\r
3954 /* Configure the ETR Clock source */
\r
3955 TIM_ETR_SetConfig(htim->Instance,
\r
3956 sClockSourceConfig->ClockPrescaler,
\r
3957 sClockSourceConfig->ClockPolarity,
\r
3958 sClockSourceConfig->ClockFilter);
\r
3959 /* Get the TIMx SMCR register value */
\r
3960 tmpsmcr = htim->Instance->SMCR;
\r
3961 /* Reset the SMS and TS Bits */
\r
3962 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
\r
3963 /* Select the External clock mode1 and the ETRF trigger */
\r
3964 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
\r
3965 /* Write to TIMx SMCR */
\r
3966 htim->Instance->SMCR = tmpsmcr;
\r
3970 case TIM_CLOCKSOURCE_ETRMODE2:
\r
3972 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
\r
3973 /* Configure the ETR Clock source */
\r
3974 TIM_ETR_SetConfig(htim->Instance,
\r
3975 sClockSourceConfig->ClockPrescaler,
\r
3976 sClockSourceConfig->ClockPolarity,
\r
3977 sClockSourceConfig->ClockFilter);
\r
3978 /* Enable the External clock mode2 */
\r
3979 htim->Instance->SMCR |= TIM_SMCR_ECE;
\r
3983 case TIM_CLOCKSOURCE_TI1:
\r
3985 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
\r
3986 TIM_TI1_ConfigInputStage(htim->Instance,
\r
3987 sClockSourceConfig->ClockPolarity,
\r
3988 sClockSourceConfig->ClockFilter);
\r
3989 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
\r
3992 case TIM_CLOCKSOURCE_TI2:
\r
3994 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
\r
3995 TIM_TI2_ConfigInputStage(htim->Instance,
\r
3996 sClockSourceConfig->ClockPolarity,
\r
3997 sClockSourceConfig->ClockFilter);
\r
3998 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
\r
4001 case TIM_CLOCKSOURCE_TI1ED:
\r
4003 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
\r
4004 TIM_TI1_ConfigInputStage(htim->Instance,
\r
4005 sClockSourceConfig->ClockPolarity,
\r
4006 sClockSourceConfig->ClockFilter);
\r
4007 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
\r
4010 case TIM_CLOCKSOURCE_ITR0:
\r
4012 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
\r
4013 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
\r
4016 case TIM_CLOCKSOURCE_ITR1:
\r
4018 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
\r
4019 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
\r
4022 case TIM_CLOCKSOURCE_ITR2:
\r
4024 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
\r
4025 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
\r
4028 case TIM_CLOCKSOURCE_ITR3:
\r
4030 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
\r
4031 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
\r
4038 htim->State = HAL_TIM_STATE_READY;
\r
4040 __HAL_UNLOCK(htim);
\r
4046 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
\r
4047 * or a XOR combination between CH1_input, CH2_input & CH3_input
\r
4048 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
4049 * the configuration information for TIM module.
\r
4050 * @param TI1_Selection: Indicate whether or not channel 1 is connected to the
\r
4051 * output of a XOR gate.
\r
4052 * This parameter can be one of the following values:
\r
4053 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
\r
4054 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
\r
4055 * pins are connected to the TI1 input (XOR combination)
\r
4056 * @retval HAL status
\r
4058 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
\r
4060 uint32_t tmpcr2 = 0;
\r
4062 /* Check the parameters */
\r
4063 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
\r
4064 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
\r
4066 /* Get the TIMx CR2 register value */
\r
4067 tmpcr2 = htim->Instance->CR2;
\r
4069 /* Reset the TI1 selection */
\r
4070 tmpcr2 &= ~TIM_CR2_TI1S;
\r
4072 /* Set the TI1 selection */
\r
4073 tmpcr2 |= TI1_Selection;
\r
4075 /* Write to TIMxCR2 */
\r
4076 htim->Instance->CR2 = tmpcr2;
\r
4082 * @brief Configures the TIM in Slave mode
\r
4083 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
4084 * the configuration information for TIM module.
\r
4085 * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
\r
4086 * contains the selected trigger (internal trigger input, filtered
\r
4087 * timer input or external trigger input) and the ) and the Slave
\r
4088 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
\r
4089 * @retval HAL status
\r
4091 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
\r
4093 uint32_t tmpsmcr = 0;
\r
4094 uint32_t tmpccmr1 = 0;
\r
4095 uint32_t tmpccer = 0;
\r
4097 /* Check the parameters */
\r
4098 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
\r
4099 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
\r
4100 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
\r
4104 htim->State = HAL_TIM_STATE_BUSY;
\r
4106 /* Get the TIMx SMCR register value */
\r
4107 tmpsmcr = htim->Instance->SMCR;
\r
4109 /* Reset the Trigger Selection Bits */
\r
4110 tmpsmcr &= ~TIM_SMCR_TS;
\r
4111 /* Set the Input Trigger source */
\r
4112 tmpsmcr |= sSlaveConfig->InputTrigger;
\r
4114 /* Reset the slave mode Bits */
\r
4115 tmpsmcr &= ~TIM_SMCR_SMS;
\r
4116 /* Set the slave mode */
\r
4117 tmpsmcr |= sSlaveConfig->SlaveMode;
\r
4119 /* Write to TIMx SMCR */
\r
4120 htim->Instance->SMCR = tmpsmcr;
\r
4122 /* Configure the trigger prescaler, filter, and polarity */
\r
4123 switch (sSlaveConfig->InputTrigger)
\r
4127 /* Check the parameters */
\r
4128 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
\r
4129 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
\r
4130 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
\r
4131 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
\r
4132 /* Configure the ETR Trigger source */
\r
4133 TIM_ETR_SetConfig(htim->Instance,
\r
4134 sSlaveConfig->TriggerPrescaler,
\r
4135 sSlaveConfig->TriggerPolarity,
\r
4136 sSlaveConfig->TriggerFilter);
\r
4140 case TIM_TS_TI1F_ED:
\r
4142 /* Check the parameters */
\r
4143 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
\r
4144 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
\r
4146 /* Disable the Channel 1: Reset the CC1E Bit */
\r
4147 tmpccer = htim->Instance->CCER;
\r
4148 htim->Instance->CCER &= ~TIM_CCER_CC1E;
\r
4149 tmpccmr1 = htim->Instance->CCMR1;
\r
4151 /* Set the filter */
\r
4152 tmpccmr1 &= ~TIM_CCMR1_IC1F;
\r
4153 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
\r
4155 /* Write to TIMx CCMR1 and CCER registers */
\r
4156 htim->Instance->CCMR1 = tmpccmr1;
\r
4157 htim->Instance->CCER = tmpccer;
\r
4162 case TIM_TS_TI1FP1:
\r
4164 /* Check the parameters */
\r
4165 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
\r
4166 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
\r
4167 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
\r
4169 /* Configure TI1 Filter and Polarity */
\r
4170 TIM_TI1_ConfigInputStage(htim->Instance,
\r
4171 sSlaveConfig->TriggerPolarity,
\r
4172 sSlaveConfig->TriggerFilter);
\r
4176 case TIM_TS_TI2FP2:
\r
4178 /* Check the parameters */
\r
4179 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
\r
4180 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
\r
4181 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
\r
4183 /* Configure TI2 Filter and Polarity */
\r
4184 TIM_TI2_ConfigInputStage(htim->Instance,
\r
4185 sSlaveConfig->TriggerPolarity,
\r
4186 sSlaveConfig->TriggerFilter);
\r
4192 /* Check the parameter */
\r
4193 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
\r
4199 /* Check the parameter */
\r
4200 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
\r
4206 /* Check the parameter */
\r
4207 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
\r
4213 /* Check the parameter */
\r
4214 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
\r
4222 htim->State = HAL_TIM_STATE_READY;
\r
4224 __HAL_UNLOCK(htim);
\r
4230 * @brief Configures the TIM in Slave mode in interrupt mode
\r
4231 * @param htim: TIM handle.
\r
4232 * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
\r
4233 * contains the selected trigger (internal trigger input, filtered
\r
4234 * timer input or external trigger input) and the ) and the Slave
\r
4235 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
\r
4236 * @retval HAL status
\r
4238 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
\r
4239 TIM_SlaveConfigTypeDef * sSlaveConfig)
\r
4241 /* Check the parameters */
\r
4242 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
\r
4243 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
\r
4244 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
\r
4248 htim->State = HAL_TIM_STATE_BUSY;
\r
4250 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
\r
4252 /* Enable Trigger Interrupt */
\r
4253 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
\r
4255 /* Disable Trigger DMA request */
\r
4256 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
\r
4258 htim->State = HAL_TIM_STATE_READY;
\r
4260 __HAL_UNLOCK(htim);
\r
4266 * @brief Read the captured value from Capture Compare unit
\r
4267 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
4268 * the configuration information for TIM module.
\r
4269 * @param Channel: TIM Channels to be enabled.
\r
4270 * This parameter can be one of the following values:
\r
4271 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
4272 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
4273 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
\r
4274 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
\r
4275 * @retval Captured value
\r
4277 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
\r
4279 uint32_t tmpreg = 0;
\r
4285 case TIM_CHANNEL_1:
\r
4287 /* Check the parameters */
\r
4288 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
\r
4290 /* Return the capture 1 value */
\r
4291 tmpreg = htim->Instance->CCR1;
\r
4295 case TIM_CHANNEL_2:
\r
4297 /* Check the parameters */
\r
4298 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
\r
4300 /* Return the capture 2 value */
\r
4301 tmpreg = htim->Instance->CCR2;
\r
4306 case TIM_CHANNEL_3:
\r
4308 /* Check the parameters */
\r
4309 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
\r
4311 /* Return the capture 3 value */
\r
4312 tmpreg = htim->Instance->CCR3;
\r
4317 case TIM_CHANNEL_4:
\r
4319 /* Check the parameters */
\r
4320 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
\r
4322 /* Return the capture 4 value */
\r
4323 tmpreg = htim->Instance->CCR4;
\r
4332 __HAL_UNLOCK(htim);
\r
4340 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
\r
4341 * @brief TIM Callbacks functions
\r
4344 ==============================================================================
\r
4345 ##### TIM Callbacks functions #####
\r
4346 ==============================================================================
\r
4348 This section provides TIM callback functions:
\r
4349 (+) Timer Period elapsed callback
\r
4350 (+) Timer Output Compare callback
\r
4351 (+) Timer Input capture callback
\r
4352 (+) Timer Trigger callback
\r
4353 (+) Timer Error callback
\r
4360 * @brief Period elapsed callback in non blocking mode
\r
4361 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
4362 * the configuration information for TIM module.
\r
4365 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
\r
4367 /* NOTE : This function Should not be modified, when the callback is needed,
\r
4368 the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
\r
4373 * @brief Output Compare callback in non blocking mode
\r
4374 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
4375 * the configuration information for TIM module.
\r
4378 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
\r
4380 /* NOTE : This function Should not be modified, when the callback is needed,
\r
4381 the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
\r
4385 * @brief Input Capture callback in non blocking mode
\r
4386 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
4387 * the configuration information for TIM module.
\r
4390 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
\r
4392 /* NOTE : This function Should not be modified, when the callback is needed,
\r
4393 the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
\r
4398 * @brief PWM Pulse finished callback in non blocking mode
\r
4399 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
4400 * the configuration information for TIM module.
\r
4403 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
\r
4405 /* NOTE : This function Should not be modified, when the callback is needed,
\r
4406 the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
\r
4411 * @brief Hall Trigger detection callback in non blocking mode
\r
4412 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
4413 * the configuration information for TIM module.
\r
4416 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
\r
4418 /* NOTE : This function Should not be modified, when the callback is needed,
\r
4419 the HAL_TIM_TriggerCallback could be implemented in the user file
\r
4424 * @brief Timer error callback in non blocking mode
\r
4425 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
4426 * the configuration information for TIM module.
\r
4429 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
\r
4431 /* NOTE : This function Should not be modified, when the callback is needed,
\r
4432 the HAL_TIM_ErrorCallback could be implemented in the user file
\r
4440 /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
\r
4441 * @brief Peripheral State functions
\r
4444 ==============================================================================
\r
4445 ##### Peripheral State functions #####
\r
4446 ==============================================================================
\r
4448 This subsection permits to get in run-time the status of the peripheral
\r
4449 and the data flow.
\r
4456 * @brief Return the TIM Base state
\r
4457 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
4458 * the configuration information for TIM module.
\r
4459 * @retval HAL state
\r
4461 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
\r
4463 return htim->State;
\r
4467 * @brief Return the TIM OC state
\r
4468 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
4469 * the configuration information for TIM module.
\r
4470 * @retval HAL state
\r
4472 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
\r
4474 return htim->State;
\r
4478 * @brief Return the TIM PWM state
\r
4479 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
4480 * the configuration information for TIM module.
\r
4481 * @retval HAL state
\r
4483 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
\r
4485 return htim->State;
\r
4489 * @brief Return the TIM Input Capture state
\r
4490 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
4491 * the configuration information for TIM module.
\r
4492 * @retval HAL state
\r
4494 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
\r
4496 return htim->State;
\r
4500 * @brief Return the TIM One Pulse Mode state
\r
4501 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
4502 * the configuration information for TIM module.
\r
4503 * @retval HAL state
\r
4505 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
\r
4507 return htim->State;
\r
4511 * @brief Return the TIM Encoder Mode state
\r
4512 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
4513 * the configuration information for TIM module.
\r
4514 * @retval HAL state
\r
4516 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
\r
4518 return htim->State;
\r
4526 * @brief TIM DMA error callback
\r
4527 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
\r
4528 * the configuration information for the specified DMA module.
\r
4531 void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma)
\r
4533 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
\r
4535 htim->State= HAL_TIM_STATE_READY;
\r
4537 HAL_TIM_ErrorCallback(htim);
\r
4541 * @brief TIM DMA Delay Pulse complete callback.
\r
4542 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
\r
4543 * the configuration information for the specified DMA module.
\r
4546 void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
\r
4548 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
\r
4550 htim->State= HAL_TIM_STATE_READY;
\r
4552 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
\r
4554 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
\r
4556 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
\r
4558 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
\r
4560 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
\r
4562 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
\r
4564 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
\r
4566 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
\r
4569 HAL_TIM_PWM_PulseFinishedCallback(htim);
\r
4571 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
\r
4574 * @brief TIM DMA Capture complete callback.
\r
4575 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
\r
4576 * the configuration information for the specified DMA module.
\r
4579 void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
\r
4581 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
\r
4583 htim->State= HAL_TIM_STATE_READY;
\r
4585 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
\r
4587 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
\r
4589 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
\r
4591 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
\r
4593 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
\r
4595 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
\r
4597 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
\r
4599 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
\r
4602 HAL_TIM_IC_CaptureCallback(htim);
\r
4604 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
\r
4609 * @brief TIM DMA Period Elapse complete callback.
\r
4610 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
\r
4611 * the configuration information for the specified DMA module.
\r
4614 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
\r
4616 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
\r
4618 htim->State= HAL_TIM_STATE_READY;
\r
4620 HAL_TIM_PeriodElapsedCallback(htim);
\r
4624 * @brief TIM DMA Trigger callback.
\r
4625 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
\r
4626 * the configuration information for the specified DMA module.
\r
4629 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
\r
4631 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
\r
4633 htim->State= HAL_TIM_STATE_READY;
\r
4635 HAL_TIM_TriggerCallback(htim);
\r
4639 * @brief Time Base configuration
\r
4640 * @param TIMx: TIM peripheral
\r
4641 * @param Structure: pointer on TIM Time Base required parameters
\r
4644 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
\r
4646 uint32_t tmpcr1 = 0;
\r
4647 tmpcr1 = TIMx->CR1;
\r
4649 /* Set TIM Time Base Unit parameters ---------------------------------------*/
\r
4650 if(IS_TIM_CC3_INSTANCE(TIMx) != RESET)
\r
4652 /* Select the Counter Mode */
\r
4653 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
\r
4654 tmpcr1 |= Structure->CounterMode;
\r
4657 if(IS_TIM_CC1_INSTANCE(TIMx) != RESET)
\r
4659 /* Set the clock division */
\r
4660 tmpcr1 &= ~TIM_CR1_CKD;
\r
4661 tmpcr1 |= (uint32_t)Structure->ClockDivision;
\r
4664 TIMx->CR1 = tmpcr1;
\r
4666 /* Set the Auto-reload value */
\r
4667 TIMx->ARR = (uint32_t)Structure->Period ;
\r
4669 /* Set the Prescaler value */
\r
4670 TIMx->PSC = (uint32_t)Structure->Prescaler;
\r
4672 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
\r
4674 /* Set the Repetition Counter value */
\r
4675 TIMx->RCR = Structure->RepetitionCounter;
\r
4678 /* Generate an update event to reload the Prescaler
\r
4679 and the repetition counter(only for TIM1 and TIM8) value immediately */
\r
4680 TIMx->EGR = TIM_EGR_UG;
\r
4684 * @brief Time Output Compare 1 configuration
\r
4685 * @param TIMx to select the TIM peripheral
\r
4686 * @param OC_Config: The output configuration structure
\r
4689 void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
\r
4691 uint32_t tmpccmrx = 0;
\r
4692 uint32_t tmpccer = 0;
\r
4693 uint32_t tmpcr2 = 0;
\r
4695 /* Disable the Channel 1: Reset the CC1E Bit */
\r
4696 TIMx->CCER &= ~TIM_CCER_CC1E;
\r
4698 /* Get the TIMx CCER register value */
\r
4699 tmpccer = TIMx->CCER;
\r
4700 /* Get the TIMx CR2 register value */
\r
4701 tmpcr2 = TIMx->CR2;
\r
4703 /* Get the TIMx CCMR1 register value */
\r
4704 tmpccmrx = TIMx->CCMR1;
\r
4706 /* Reset the Output Compare Mode Bits */
\r
4707 tmpccmrx &= ~TIM_CCMR1_OC1M;
\r
4708 tmpccmrx &= ~TIM_CCMR1_CC1S;
\r
4709 /* Select the Output Compare Mode */
\r
4710 tmpccmrx |= OC_Config->OCMode;
\r
4712 /* Reset the Output Polarity level */
\r
4713 tmpccer &= ~TIM_CCER_CC1P;
\r
4714 /* Set the Output Compare Polarity */
\r
4715 tmpccer |= OC_Config->OCPolarity;
\r
4718 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
\r
4720 /* Reset the Output N Polarity level */
\r
4721 tmpccer &= ~TIM_CCER_CC1NP;
\r
4722 /* Set the Output N Polarity */
\r
4723 tmpccer |= OC_Config->OCNPolarity;
\r
4724 /* Reset the Output N State */
\r
4725 tmpccer &= ~TIM_CCER_CC1NE;
\r
4727 /* Reset the Output Compare and Output Compare N IDLE State */
\r
4728 tmpcr2 &= ~TIM_CR2_OIS1;
\r
4729 tmpcr2 &= ~TIM_CR2_OIS1N;
\r
4730 /* Set the Output Idle state */
\r
4731 tmpcr2 |= OC_Config->OCIdleState;
\r
4732 /* Set the Output N Idle state */
\r
4733 tmpcr2 |= OC_Config->OCNIdleState;
\r
4735 /* Write to TIMx CR2 */
\r
4736 TIMx->CR2 = tmpcr2;
\r
4738 /* Write to TIMx CCMR1 */
\r
4739 TIMx->CCMR1 = tmpccmrx;
\r
4741 /* Set the Capture Compare Register value */
\r
4742 TIMx->CCR1 = OC_Config->Pulse;
\r
4744 /* Write to TIMx CCER */
\r
4745 TIMx->CCER = tmpccer;
\r
4749 * @brief Time Output Compare 2 configuration
\r
4750 * @param TIMx to select the TIM peripheral
\r
4751 * @param OC_Config: The output configuration structure
\r
4754 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
\r
4756 uint32_t tmpccmrx = 0;
\r
4757 uint32_t tmpccer = 0;
\r
4758 uint32_t tmpcr2 = 0;
\r
4760 /* Disable the Channel 2: Reset the CC2E Bit */
\r
4761 TIMx->CCER &= ~TIM_CCER_CC2E;
\r
4763 /* Get the TIMx CCER register value */
\r
4764 tmpccer = TIMx->CCER;
\r
4765 /* Get the TIMx CR2 register value */
\r
4766 tmpcr2 = TIMx->CR2;
\r
4768 /* Get the TIMx CCMR1 register value */
\r
4769 tmpccmrx = TIMx->CCMR1;
\r
4771 /* Reset the Output Compare mode and Capture/Compare selection Bits */
\r
4772 tmpccmrx &= ~TIM_CCMR1_OC2M;
\r
4773 tmpccmrx &= ~TIM_CCMR1_CC2S;
\r
4775 /* Select the Output Compare Mode */
\r
4776 tmpccmrx |= (OC_Config->OCMode << 8);
\r
4778 /* Reset the Output Polarity level */
\r
4779 tmpccer &= ~TIM_CCER_CC2P;
\r
4780 /* Set the Output Compare Polarity */
\r
4781 tmpccer |= (OC_Config->OCPolarity << 4);
\r
4783 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
\r
4785 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
\r
4786 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
\r
4787 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
\r
4789 /* Reset the Output N Polarity level */
\r
4790 tmpccer &= ~TIM_CCER_CC2NP;
\r
4791 /* Set the Output N Polarity */
\r
4792 tmpccer |= (OC_Config->OCNPolarity << 4);
\r
4793 /* Reset the Output N State */
\r
4794 tmpccer &= ~TIM_CCER_CC2NE;
\r
4796 /* Reset the Output Compare and Output Compare N IDLE State */
\r
4797 tmpcr2 &= ~TIM_CR2_OIS2;
\r
4798 tmpcr2 &= ~TIM_CR2_OIS2N;
\r
4799 /* Set the Output Idle state */
\r
4800 tmpcr2 |= (OC_Config->OCIdleState << 2);
\r
4801 /* Set the Output N Idle state */
\r
4802 tmpcr2 |= (OC_Config->OCNIdleState << 2);
\r
4804 /* Write to TIMx CR2 */
\r
4805 TIMx->CR2 = tmpcr2;
\r
4807 /* Write to TIMx CCMR1 */
\r
4808 TIMx->CCMR1 = tmpccmrx;
\r
4810 /* Set the Capture Compare Register value */
\r
4811 TIMx->CCR2 = OC_Config->Pulse;
\r
4813 /* Write to TIMx CCER */
\r
4814 TIMx->CCER = tmpccer;
\r
4818 * @brief Time Output Compare 3 configuration
\r
4819 * @param TIMx to select the TIM peripheral
\r
4820 * @param OC_Config: The output configuration structure
\r
4823 void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
\r
4825 uint32_t tmpccmrx = 0;
\r
4826 uint32_t tmpccer = 0;
\r
4827 uint32_t tmpcr2 = 0;
\r
4829 /* Disable the Channel 3: Reset the CC2E Bit */
\r
4830 TIMx->CCER &= ~TIM_CCER_CC3E;
\r
4832 /* Get the TIMx CCER register value */
\r
4833 tmpccer = TIMx->CCER;
\r
4834 /* Get the TIMx CR2 register value */
\r
4835 tmpcr2 = TIMx->CR2;
\r
4837 /* Get the TIMx CCMR2 register value */
\r
4838 tmpccmrx = TIMx->CCMR2;
\r
4840 /* Reset the Output Compare mode and Capture/Compare selection Bits */
\r
4841 tmpccmrx &= ~TIM_CCMR2_OC3M;
\r
4842 tmpccmrx &= ~TIM_CCMR2_CC3S;
\r
4843 /* Select the Output Compare Mode */
\r
4844 tmpccmrx |= OC_Config->OCMode;
\r
4846 /* Reset the Output Polarity level */
\r
4847 tmpccer &= ~TIM_CCER_CC3P;
\r
4848 /* Set the Output Compare Polarity */
\r
4849 tmpccer |= (OC_Config->OCPolarity << 8);
\r
4851 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
\r
4853 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
\r
4854 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
\r
4855 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
\r
4857 /* Reset the Output N Polarity level */
\r
4858 tmpccer &= ~TIM_CCER_CC3NP;
\r
4859 /* Set the Output N Polarity */
\r
4860 tmpccer |= (OC_Config->OCNPolarity << 8);
\r
4861 /* Reset the Output N State */
\r
4862 tmpccer &= ~TIM_CCER_CC3NE;
\r
4864 /* Reset the Output Compare and Output Compare N IDLE State */
\r
4865 tmpcr2 &= ~TIM_CR2_OIS3;
\r
4866 tmpcr2 &= ~TIM_CR2_OIS3N;
\r
4867 /* Set the Output Idle state */
\r
4868 tmpcr2 |= (OC_Config->OCIdleState << 4);
\r
4869 /* Set the Output N Idle state */
\r
4870 tmpcr2 |= (OC_Config->OCNIdleState << 4);
\r
4872 /* Write to TIMx CR2 */
\r
4873 TIMx->CR2 = tmpcr2;
\r
4875 /* Write to TIMx CCMR2 */
\r
4876 TIMx->CCMR2 = tmpccmrx;
\r
4878 /* Set the Capture Compare Register value */
\r
4879 TIMx->CCR3 = OC_Config->Pulse;
\r
4881 /* Write to TIMx CCER */
\r
4882 TIMx->CCER = tmpccer;
\r
4886 * @brief Time Output Compare 4 configuration
\r
4887 * @param TIMx to select the TIM peripheral
\r
4888 * @param OC_Config: The output configuration structure
\r
4891 void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
\r
4893 uint32_t tmpccmrx = 0;
\r
4894 uint32_t tmpccer = 0;
\r
4895 uint32_t tmpcr2 = 0;
\r
4897 /* Disable the Channel 4: Reset the CC4E Bit */
\r
4898 TIMx->CCER &= ~TIM_CCER_CC4E;
\r
4900 /* Get the TIMx CCER register value */
\r
4901 tmpccer = TIMx->CCER;
\r
4902 /* Get the TIMx CR2 register value */
\r
4903 tmpcr2 = TIMx->CR2;
\r
4905 /* Get the TIMx CCMR2 register value */
\r
4906 tmpccmrx = TIMx->CCMR2;
\r
4908 /* Reset the Output Compare mode and Capture/Compare selection Bits */
\r
4909 tmpccmrx &= ~TIM_CCMR2_OC4M;
\r
4910 tmpccmrx &= ~TIM_CCMR2_CC4S;
\r
4912 /* Select the Output Compare Mode */
\r
4913 tmpccmrx |= (OC_Config->OCMode << 8);
\r
4915 /* Reset the Output Polarity level */
\r
4916 tmpccer &= ~TIM_CCER_CC4P;
\r
4917 /* Set the Output Compare Polarity */
\r
4918 tmpccer |= (OC_Config->OCPolarity << 12);
\r
4920 /*if((TIMx == TIM1) || (TIMx == TIM8))*/
\r
4921 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
\r
4923 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
\r
4924 /* Reset the Output Compare IDLE State */
\r
4925 tmpcr2 &= ~TIM_CR2_OIS4;
\r
4926 /* Set the Output Idle state */
\r
4927 tmpcr2 |= (OC_Config->OCIdleState << 6);
\r
4929 /* Write to TIMx CR2 */
\r
4930 TIMx->CR2 = tmpcr2;
\r
4932 /* Write to TIMx CCMR2 */
\r
4933 TIMx->CCMR2 = tmpccmrx;
\r
4935 /* Set the Capture Compare Register value */
\r
4936 TIMx->CCR4 = OC_Config->Pulse;
\r
4938 /* Write to TIMx CCER */
\r
4939 TIMx->CCER = tmpccer;
\r
4943 * @brief Time Output Compare 4 configuration
\r
4944 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
4945 * the configuration information for TIM module.
\r
4946 * @param sSlaveConfig: The slave configuration structure
\r
4949 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
\r
4950 TIM_SlaveConfigTypeDef * sSlaveConfig)
\r
4952 uint32_t tmpsmcr = 0;
\r
4953 uint32_t tmpccmr1 = 0;
\r
4954 uint32_t tmpccer = 0;
\r
4956 /* Get the TIMx SMCR register value */
\r
4957 tmpsmcr = htim->Instance->SMCR;
\r
4959 /* Reset the Trigger Selection Bits */
\r
4960 tmpsmcr &= ~TIM_SMCR_TS;
\r
4961 /* Set the Input Trigger source */
\r
4962 tmpsmcr |= sSlaveConfig->InputTrigger;
\r
4964 /* Reset the slave mode Bits */
\r
4965 tmpsmcr &= ~TIM_SMCR_SMS;
\r
4966 /* Set the slave mode */
\r
4967 tmpsmcr |= sSlaveConfig->SlaveMode;
\r
4969 /* Write to TIMx SMCR */
\r
4970 htim->Instance->SMCR = tmpsmcr;
\r
4972 /* Configure the trigger prescaler, filter, and polarity */
\r
4973 switch (sSlaveConfig->InputTrigger)
\r
4977 /* Check the parameters */
\r
4978 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
\r
4979 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
\r
4980 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
\r
4981 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
\r
4982 /* Configure the ETR Trigger source */
\r
4983 TIM_ETR_SetConfig(htim->Instance,
\r
4984 sSlaveConfig->TriggerPrescaler,
\r
4985 sSlaveConfig->TriggerPolarity,
\r
4986 sSlaveConfig->TriggerFilter);
\r
4990 case TIM_TS_TI1F_ED:
\r
4992 /* Check the parameters */
\r
4993 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
\r
4994 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
\r
4995 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
\r
4997 /* Disable the Channel 1: Reset the CC1E Bit */
\r
4998 tmpccer = htim->Instance->CCER;
\r
4999 htim->Instance->CCER &= ~TIM_CCER_CC1E;
\r
5000 tmpccmr1 = htim->Instance->CCMR1;
\r
5002 /* Set the filter */
\r
5003 tmpccmr1 &= ~TIM_CCMR1_IC1F;
\r
5004 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
\r
5006 /* Write to TIMx CCMR1 and CCER registers */
\r
5007 htim->Instance->CCMR1 = tmpccmr1;
\r
5008 htim->Instance->CCER = tmpccer;
\r
5013 case TIM_TS_TI1FP1:
\r
5015 /* Check the parameters */
\r
5016 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
\r
5017 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
\r
5018 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
\r
5020 /* Configure TI1 Filter and Polarity */
\r
5021 TIM_TI1_ConfigInputStage(htim->Instance,
\r
5022 sSlaveConfig->TriggerPolarity,
\r
5023 sSlaveConfig->TriggerFilter);
\r
5027 case TIM_TS_TI2FP2:
\r
5029 /* Check the parameters */
\r
5030 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
\r
5031 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
\r
5032 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
\r
5034 /* Configure TI2 Filter and Polarity */
\r
5035 TIM_TI2_ConfigInputStage(htim->Instance,
\r
5036 sSlaveConfig->TriggerPolarity,
\r
5037 sSlaveConfig->TriggerFilter);
\r
5043 /* Check the parameter */
\r
5044 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
\r
5050 /* Check the parameter */
\r
5051 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
\r
5057 /* Check the parameter */
\r
5058 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
\r
5064 /* Check the parameter */
\r
5065 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
\r
5075 * @brief Configure the TI1 as Input.
\r
5076 * @param TIMx to select the TIM peripheral.
\r
5077 * @param TIM_ICPolarity : The Input Polarity.
\r
5078 * This parameter can be one of the following values:
\r
5079 * @arg TIM_ICPolarity_Rising
\r
5080 * @arg TIM_ICPolarity_Falling
\r
5081 * @arg TIM_ICPolarity_BothEdge
\r
5082 * @param TIM_ICSelection: specifies the input to be used.
\r
5083 * This parameter can be one of the following values:
\r
5084 * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
\r
5085 * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
\r
5086 * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
\r
5087 * @param TIM_ICFilter: Specifies the Input Capture Filter.
\r
5088 * This parameter must be a value between 0x00 and 0x0F.
\r
5090 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
\r
5091 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
\r
5092 * protected against un-initialized filter and polarity values.
\r
5094 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
\r
5095 uint32_t TIM_ICFilter)
\r
5097 uint32_t tmpccmr1 = 0;
\r
5098 uint32_t tmpccer = 0;
\r
5100 /* Disable the Channel 1: Reset the CC1E Bit */
\r
5101 TIMx->CCER &= ~TIM_CCER_CC1E;
\r
5102 tmpccmr1 = TIMx->CCMR1;
\r
5103 tmpccer = TIMx->CCER;
\r
5105 /* Select the Input */
\r
5106 if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
\r
5108 tmpccmr1 &= ~TIM_CCMR1_CC1S;
\r
5109 tmpccmr1 |= TIM_ICSelection;
\r
5113 tmpccmr1 |= TIM_CCMR1_CC1S_0;
\r
5116 /* Set the filter */
\r
5117 tmpccmr1 &= ~TIM_CCMR1_IC1F;
\r
5118 tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);
\r
5120 /* Select the Polarity and set the CC1E Bit */
\r
5121 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
\r
5122 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
\r
5124 /* Write to TIMx CCMR1 and CCER registers */
\r
5125 TIMx->CCMR1 = tmpccmr1;
\r
5126 TIMx->CCER = tmpccer;
\r
5130 * @brief Configure the Polarity and Filter for TI1.
\r
5131 * @param TIMx to select the TIM peripheral.
\r
5132 * @param TIM_ICPolarity : The Input Polarity.
\r
5133 * This parameter can be one of the following values:
\r
5134 * @arg TIM_ICPolarity_Rising
\r
5135 * @arg TIM_ICPolarity_Falling
\r
5136 * @arg TIM_ICPolarity_BothEdge
\r
5137 * @param TIM_ICFilter: Specifies the Input Capture Filter.
\r
5138 * This parameter must be a value between 0x00 and 0x0F.
\r
5141 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
\r
5143 uint32_t tmpccmr1 = 0;
\r
5144 uint32_t tmpccer = 0;
\r
5146 /* Disable the Channel 1: Reset the CC1E Bit */
\r
5147 tmpccer = TIMx->CCER;
\r
5148 TIMx->CCER &= ~TIM_CCER_CC1E;
\r
5149 tmpccmr1 = TIMx->CCMR1;
\r
5151 /* Set the filter */
\r
5152 tmpccmr1 &= ~TIM_CCMR1_IC1F;
\r
5153 tmpccmr1 |= (TIM_ICFilter << 4);
\r
5155 /* Select the Polarity and set the CC1E Bit */
\r
5156 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
\r
5157 tmpccer |= TIM_ICPolarity;
\r
5159 /* Write to TIMx CCMR1 and CCER registers */
\r
5160 TIMx->CCMR1 = tmpccmr1;
\r
5161 TIMx->CCER = tmpccer;
\r
5165 * @brief Configure the TI2 as Input.
\r
5166 * @param TIMx to select the TIM peripheral
\r
5167 * @param TIM_ICPolarity : The Input Polarity.
\r
5168 * This parameter can be one of the following values:
\r
5169 * @arg TIM_ICPolarity_Rising
\r
5170 * @arg TIM_ICPolarity_Falling
\r
5171 * @arg TIM_ICPolarity_BothEdge
\r
5172 * @param TIM_ICSelection: specifies the input to be used.
\r
5173 * This parameter can be one of the following values:
\r
5174 * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
\r
5175 * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
\r
5176 * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
\r
5177 * @param TIM_ICFilter: Specifies the Input Capture Filter.
\r
5178 * This parameter must be a value between 0x00 and 0x0F.
\r
5180 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
\r
5181 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
\r
5182 * protected against un-initialized filter and polarity values.
\r
5184 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
\r
5185 uint32_t TIM_ICFilter)
\r
5187 uint32_t tmpccmr1 = 0;
\r
5188 uint32_t tmpccer = 0;
\r
5190 /* Disable the Channel 2: Reset the CC2E Bit */
\r
5191 TIMx->CCER &= ~TIM_CCER_CC2E;
\r
5192 tmpccmr1 = TIMx->CCMR1;
\r
5193 tmpccer = TIMx->CCER;
\r
5195 /* Select the Input */
\r
5196 tmpccmr1 &= ~TIM_CCMR1_CC2S;
\r
5197 tmpccmr1 |= (TIM_ICSelection << 8);
\r
5199 /* Set the filter */
\r
5200 tmpccmr1 &= ~TIM_CCMR1_IC2F;
\r
5201 tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F);
\r
5203 /* Select the Polarity and set the CC2E Bit */
\r
5204 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
\r
5205 tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
\r
5207 /* Write to TIMx CCMR1 and CCER registers */
\r
5208 TIMx->CCMR1 = tmpccmr1 ;
\r
5209 TIMx->CCER = tmpccer;
\r
5213 * @brief Configure the Polarity and Filter for TI2.
\r
5214 * @param TIMx to select the TIM peripheral.
\r
5215 * @param TIM_ICPolarity : The Input Polarity.
\r
5216 * This parameter can be one of the following values:
\r
5217 * @arg TIM_ICPolarity_Rising
\r
5218 * @arg TIM_ICPolarity_Falling
\r
5219 * @arg TIM_ICPolarity_BothEdge
\r
5220 * @param TIM_ICFilter: Specifies the Input Capture Filter.
\r
5221 * This parameter must be a value between 0x00 and 0x0F.
\r
5224 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
\r
5226 uint32_t tmpccmr1 = 0;
\r
5227 uint32_t tmpccer = 0;
\r
5229 /* Disable the Channel 2: Reset the CC2E Bit */
\r
5230 TIMx->CCER &= ~TIM_CCER_CC2E;
\r
5231 tmpccmr1 = TIMx->CCMR1;
\r
5232 tmpccer = TIMx->CCER;
\r
5234 /* Set the filter */
\r
5235 tmpccmr1 &= ~TIM_CCMR1_IC2F;
\r
5236 tmpccmr1 |= (TIM_ICFilter << 12);
\r
5238 /* Select the Polarity and set the CC2E Bit */
\r
5239 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
\r
5240 tmpccer |= (TIM_ICPolarity << 4);
\r
5242 /* Write to TIMx CCMR1 and CCER registers */
\r
5243 TIMx->CCMR1 = tmpccmr1 ;
\r
5244 TIMx->CCER = tmpccer;
\r
5248 * @brief Configure the TI3 as Input.
\r
5249 * @param TIMx to select the TIM peripheral
\r
5250 * @param TIM_ICPolarity : The Input Polarity.
\r
5251 * This parameter can be one of the following values:
\r
5252 * @arg TIM_ICPolarity_Rising
\r
5253 * @arg TIM_ICPolarity_Falling
\r
5254 * @arg TIM_ICPolarity_BothEdge
\r
5255 * @param TIM_ICSelection: specifies the input to be used.
\r
5256 * This parameter can be one of the following values:
\r
5257 * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
\r
5258 * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
\r
5259 * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
\r
5260 * @param TIM_ICFilter: Specifies the Input Capture Filter.
\r
5261 * This parameter must be a value between 0x00 and 0x0F.
\r
5263 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
\r
5264 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
\r
5265 * protected against un-initialized filter and polarity values.
\r
5267 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
\r
5268 uint32_t TIM_ICFilter)
\r
5270 uint32_t tmpccmr2 = 0;
\r
5271 uint32_t tmpccer = 0;
\r
5273 /* Disable the Channel 3: Reset the CC3E Bit */
\r
5274 TIMx->CCER &= ~TIM_CCER_CC3E;
\r
5275 tmpccmr2 = TIMx->CCMR2;
\r
5276 tmpccer = TIMx->CCER;
\r
5278 /* Select the Input */
\r
5279 tmpccmr2 &= ~TIM_CCMR2_CC3S;
\r
5280 tmpccmr2 |= TIM_ICSelection;
\r
5282 /* Set the filter */
\r
5283 tmpccmr2 &= ~TIM_CCMR2_IC3F;
\r
5284 tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F);
\r
5286 /* Select the Polarity and set the CC3E Bit */
\r
5287 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
\r
5288 tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
\r
5290 /* Write to TIMx CCMR2 and CCER registers */
\r
5291 TIMx->CCMR2 = tmpccmr2;
\r
5292 TIMx->CCER = tmpccer;
\r
5296 * @brief Configure the TI4 as Input.
\r
5297 * @param TIMx to select the TIM peripheral
\r
5298 * @param TIM_ICPolarity : The Input Polarity.
\r
5299 * This parameter can be one of the following values:
\r
5300 * @arg TIM_ICPolarity_Rising
\r
5301 * @arg TIM_ICPolarity_Falling
\r
5302 * @arg TIM_ICPolarity_BothEdge
\r
5303 * @param TIM_ICSelection: specifies the input to be used.
\r
5304 * This parameter can be one of the following values:
\r
5305 * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
\r
5306 * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
\r
5307 * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
\r
5308 * @param TIM_ICFilter: Specifies the Input Capture Filter.
\r
5309 * This parameter must be a value between 0x00 and 0x0F.
\r
5311 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
\r
5312 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
\r
5313 * protected against un-initialized filter and polarity values.
\r
5315 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
\r
5316 uint32_t TIM_ICFilter)
\r
5318 uint32_t tmpccmr2 = 0;
\r
5319 uint32_t tmpccer = 0;
\r
5321 /* Disable the Channel 4: Reset the CC4E Bit */
\r
5322 TIMx->CCER &= ~TIM_CCER_CC4E;
\r
5323 tmpccmr2 = TIMx->CCMR2;
\r
5324 tmpccer = TIMx->CCER;
\r
5326 /* Select the Input */
\r
5327 tmpccmr2 &= ~TIM_CCMR2_CC4S;
\r
5328 tmpccmr2 |= (TIM_ICSelection << 8);
\r
5330 /* Set the filter */
\r
5331 tmpccmr2 &= ~TIM_CCMR2_IC4F;
\r
5332 tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F);
\r
5334 /* Select the Polarity and set the CC4E Bit */
\r
5335 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
\r
5336 tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
\r
5338 /* Write to TIMx CCMR2 and CCER registers */
\r
5339 TIMx->CCMR2 = tmpccmr2;
\r
5340 TIMx->CCER = tmpccer ;
\r
5344 * @brief Selects the Input Trigger source
\r
5345 * @param TIMx to select the TIM peripheral
\r
5346 * @param TIM_ITRx: The Input Trigger source.
\r
5347 * This parameter can be one of the following values:
\r
5348 * @arg TIM_TS_ITR0: Internal Trigger 0
\r
5349 * @arg TIM_TS_ITR1: Internal Trigger 1
\r
5350 * @arg TIM_TS_ITR2: Internal Trigger 2
\r
5351 * @arg TIM_TS_ITR3: Internal Trigger 3
\r
5352 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
\r
5353 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
\r
5354 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
\r
5355 * @arg TIM_TS_ETRF: External Trigger input
\r
5358 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t TIM_ITRx)
\r
5360 uint32_t tmpsmcr = 0;
\r
5362 /* Get the TIMx SMCR register value */
\r
5363 tmpsmcr = TIMx->SMCR;
\r
5364 /* Reset the TS Bits */
\r
5365 tmpsmcr &= ~TIM_SMCR_TS;
\r
5366 /* Set the Input Trigger source and the slave mode*/
\r
5367 tmpsmcr |= TIM_ITRx | TIM_SLAVEMODE_EXTERNAL1;
\r
5368 /* Write to TIMx SMCR */
\r
5369 TIMx->SMCR = tmpsmcr;
\r
5373 * @brief Configures the TIMx External Trigger (ETR).
\r
5374 * @param TIMx to select the TIM peripheral
\r
5375 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
\r
5376 * This parameter can be one of the following values:
\r
5377 * @arg TIM_ExtTRGPSC_DIV1: ETRP Prescaler OFF.
\r
5378 * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
\r
5379 * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
\r
5380 * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
\r
5381 * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
\r
5382 * This parameter can be one of the following values:
\r
5383 * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
\r
5384 * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
\r
5385 * @param ExtTRGFilter: External Trigger Filter.
\r
5386 * This parameter must be a value between 0x00 and 0x0F
\r
5389 void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
\r
5390 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
\r
5392 uint32_t tmpsmcr = 0;
\r
5394 tmpsmcr = TIMx->SMCR;
\r
5396 /* Reset the ETR Bits */
\r
5397 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
\r
5399 /* Set the Prescaler, the Filter value and the Polarity */
\r
5400 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));
\r
5402 /* Write to TIMx SMCR */
\r
5403 TIMx->SMCR = tmpsmcr;
\r
5407 * @brief Enables or disables the TIM Capture Compare Channel x.
\r
5408 * @param TIMx to select the TIM peripheral
\r
5409 * @param Channel: specifies the TIM Channel
\r
5410 * This parameter can be one of the following values:
\r
5411 * @arg TIM_Channel_1: TIM Channel 1
\r
5412 * @arg TIM_Channel_2: TIM Channel 2
\r
5413 * @arg TIM_Channel_3: TIM Channel 3
\r
5414 * @arg TIM_Channel_4: TIM Channel 4
\r
5415 * @param ChannelState: specifies the TIM Channel CCxE bit new state.
\r
5416 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
\r
5419 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
\r
5423 /* Check the parameters */
\r
5424 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
\r
5425 assert_param(IS_TIM_CHANNELS(Channel));
\r
5427 tmp = TIM_CCER_CC1E << Channel;
\r
5429 /* Reset the CCxE Bit */
\r
5430 TIMx->CCER &= ~tmp;
\r
5432 /* Set or reset the CCxE Bit */
\r
5433 TIMx->CCER |= (uint32_t)(ChannelState << Channel);
\r
5441 #endif /* HAL_TIM_MODULE_ENABLED */
\r
5449 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
\r