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   1 /**\r
   2   ******************************************************************************\r
   3   * @file    stm32f7xx_ll_fmc.c\r
   4   * @author  MCD Application Team\r
   5   * @version V0.3.0\r
   6   * @date    06-March-2015\r
   7   * @brief   FMC Low Layer HAL module driver.\r
   8   *    \r
   9   *          This file provides firmware functions to manage the following \r
  10   *          functionalities of the Flexible Memory Controller (FMC) peripheral memories:\r
  11   *           + Initialization/de-initialization functions\r
  12   *           + Peripheral Control functions \r
  13   *           + Peripheral State functions\r
  14   *         \r
  15   @verbatim\r
  16   ==============================================================================\r
  17                         ##### FMC peripheral features #####\r
  18   ==============================================================================\r
  19   [..] The Flexible memory controller (FMC) includes three memory controllers:\r
  20        (+) The NOR/PSRAM memory controller\r
  21        (+) The NAND memory controller\r
  22        (+) The Synchronous DRAM (SDRAM) controller \r
  23        \r
  24   [..] The FMC functional block makes the interface with synchronous and asynchronous static\r
  25        memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are:\r
  26        (+) to translate AHB transactions into the appropriate external device protocol\r
  27        (+) to meet the access time requirements of the external memory devices\r
  28    \r
  29   [..] All external memories share the addresses, data and control signals with the controller.\r
  30        Each external device is accessed by means of a unique Chip Select. The FMC performs\r
  31        only one access at a time to an external device.\r
  32        The main features of the FMC controller are the following:\r
  33         (+) Interface with static-memory mapped devices including:\r
  34            (++) Static random access memory (SRAM)\r
  35            (++) Read-only memory (ROM)\r
  36            (++) NOR Flash memory/OneNAND Flash memory\r
  37            (++) PSRAM (4 memory banks)\r
  38            (++) 16-bit PC Card compatible devices\r
  39            (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of\r
  40                 data\r
  41         (+) Interface with synchronous DRAM (SDRAM) memories\r
  42         (+) Independent Chip Select control for each memory bank\r
  43         (+) Independent configuration for each memory bank\r
  44                     \r
  45   @endverbatim\r
  46   ******************************************************************************\r
  47   * @attention\r
  48   *\r
  49   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
  50   *\r
  51   * Redistribution and use in source and binary forms, with or without modification,\r
  52   * are permitted provided that the following conditions are met:\r
  53   *   1. Redistributions of source code must retain the above copyright notice,\r
  54   *      this list of conditions and the following disclaimer.\r
  55   *   2. Redistributions in binary form must reproduce the above copyright notice,\r
  56   *      this list of conditions and the following disclaimer in the documentation\r
  57   *      and/or other materials provided with the distribution.\r
  58   *   3. Neither the name of STMicroelectronics nor the names of its contributors\r
  59   *      may be used to endorse or promote products derived from this software\r
  60   *      without specific prior written permission.\r
  61   *\r
  62   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
  63   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
  64   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
  65   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
  66   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
  67   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
  68   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
  69   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
  70   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
  71   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
  72   *\r
  73   ******************************************************************************\r
  74   */ \r
  75 \r
  76 /* Includes ------------------------------------------------------------------*/\r
  77 #include "stm32f7xx_hal.h"\r
  78 \r
  79 /** @addtogroup STM32F7xx_HAL_Driver\r
  80   * @{\r
  81   */\r
  82 \r
  83 /** @defgroup FMC_LL  FMC Low Layer\r
  84   * @brief FMC driver modules\r
  85   * @{\r
  86   */\r
  87 \r
  88 #if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)\r
  89 \r
  90 /* Private typedef -----------------------------------------------------------*/\r
  91 /* Private define ------------------------------------------------------------*/\r
  92 /* Private macro -------------------------------------------------------------*/\r
  93 /* Private variables ---------------------------------------------------------*/\r
  94 /* Private function prototypes -----------------------------------------------*/\r
  95 /* Exported functions --------------------------------------------------------*/\r
  96 \r
  97 /** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions\r
  98   * @{\r
  99   */\r
 100 \r
 101 /** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions\r
 102   * @brief  NORSRAM Controller functions \r
 103   *\r
 104   @verbatim \r
 105   ==============================================================================   \r
 106                    ##### How to use NORSRAM device driver #####\r
 107   ==============================================================================\r
 108  \r
 109   [..] \r
 110     This driver contains a set of APIs to interface with the FMC NORSRAM banks in order\r
 111     to run the NORSRAM external devices.\r
 112       \r
 113     (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit() \r
 114     (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()\r
 115     (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()\r
 116     (+) FMC NORSRAM bank extended timing configuration using the function \r
 117         FMC_NORSRAM_Extended_Timing_Init()\r
 118     (+) FMC NORSRAM bank enable/disable write operation using the functions\r
 119         FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()\r
 120         \r
 121 \r
 122 @endverbatim\r
 123   * @{\r
 124   */\r
 125        \r
 126 /** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions\r
 127   * @brief    Initialization and Configuration functions \r
 128   *\r
 129   @verbatim    \r
 130   ==============================================================================\r
 131               ##### Initialization and de_initialization functions #####\r
 132   ==============================================================================\r
 133   [..]  \r
 134     This section provides functions allowing to:\r
 135     (+) Initialize and configure the FMC NORSRAM interface\r
 136     (+) De-initialize the FMC NORSRAM interface \r
 137     (+) Configure the FMC clock and associated GPIOs    \r
 138  \r
 139 @endverbatim\r
 140   * @{\r
 141   */\r
 142   \r
 143 /**\r
 144   * @brief  Initialize the FMC_NORSRAM device according to the specified\r
 145   *         control parameters in the FMC_NORSRAM_InitTypeDef\r
 146   * @param  Device: Pointer to NORSRAM device instance\r
 147   * @param  Init: Pointer to NORSRAM Initialization structure   \r
 148   * @retval HAL status\r
 149   */\r
 150 HAL_StatusTypeDef  FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef* Init)\r
 151 { \r
 152   uint32_t tmpr = 0;\r
 153     \r
 154   /* Check the parameters */\r
 155   assert_param(IS_FMC_NORSRAM_DEVICE(Device));\r
 156   assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));\r
 157   assert_param(IS_FMC_MUX(Init->DataAddressMux));\r
 158   assert_param(IS_FMC_MEMORY(Init->MemoryType));\r
 159   assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));\r
 160   assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));\r
 161   assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));\r
 162   assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));\r
 163   assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));\r
 164   assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));\r
 165   assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));\r
 166   assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));\r
 167   assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));\r
 168   assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock)); \r
 169   assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo));\r
 170   assert_param(IS_FMC_PAGESIZE(Init->PageSize));\r
 171 \r
 172   /* Get the BTCR register value */\r
 173   tmpr = Device->BTCR[Init->NSBank];\r
 174   \r
 175   /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WAITCFG, WREN,\r
 176            WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW and CCLKEN bits */\r
 177   tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN     | FMC_BCR1_MUXEN    | FMC_BCR1_MTYP     | \\r
 178                        FMC_BCR1_MWID      | FMC_BCR1_FACCEN   | FMC_BCR1_BURSTEN  | \\r
 179                        FMC_BCR1_WAITPOL   | FMC_BCR1_CPSIZE    | FMC_BCR1_WAITCFG  | \\r
 180                        FMC_BCR1_WREN      | FMC_BCR1_WAITEN   | FMC_BCR1_EXTMOD   | \\r
 181                        FMC_BCR1_ASYNCWAIT | FMC_BCR1_CBURSTRW | FMC_BCR1_CCLKEN | FMC_BCR1_WFDIS));\r
 182   \r
 183   /* Set NORSRAM device control parameters */\r
 184   tmpr |= (uint32_t)(Init->DataAddressMux       |\\r
 185                     Init->MemoryType           |\\r
 186                     Init->MemoryDataWidth      |\\r
 187                     Init->BurstAccessMode      |\\r
 188                     Init->WaitSignalPolarity   |\\r
 189                     Init->WaitSignalActive     |\\r
 190                     Init->WriteOperation       |\\r
 191                     Init->WaitSignal           |\\r
 192                     Init->ExtendedMode         |\\r
 193                     Init->AsynchronousWait     |\\r
 194                     Init->WriteBurst           |\\r
 195                     Init->ContinuousClock      |\\r
 196                     Init->PageSize             |\\r
 197                     Init->WriteFifo);\r
 198                     \r
 199   if(Init->MemoryType == FMC_MEMORY_TYPE_NOR)\r
 200   {\r
 201     tmpr |= (uint32_t)FMC_NORSRAM_FLASH_ACCESS_ENABLE;\r
 202   }\r
 203   \r
 204   Device->BTCR[Init->NSBank] = tmpr;\r
 205 \r
 206   /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */\r
 207   if((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))\r
 208   { \r
 209     Init->BurstAccessMode = FMC_BURST_ACCESS_MODE_ENABLE; \r
 210     Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->BurstAccessMode  |\\r
 211                                                   Init->ContinuousClock);\r
 212   }\r
 213   if(Init->NSBank != FMC_NORSRAM_BANK1)\r
 214   {\r
 215     Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->WriteFifo);              \r
 216   }\r
 217   \r
 218   return HAL_OK;\r
 219 }\r
 220 \r
 221 \r
 222 /**\r
 223   * @brief  DeInitialize the FMC_NORSRAM peripheral \r
 224   * @param  Device: Pointer to NORSRAM device instance\r
 225   * @param  ExDevice: Pointer to NORSRAM extended mode device instance  \r
 226   * @param  Bank: NORSRAM bank number  \r
 227   * @retval HAL status\r
 228   */\r
 229 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)\r
 230 {\r
 231   /* Check the parameters */\r
 232   assert_param(IS_FMC_NORSRAM_DEVICE(Device));\r
 233   assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));\r
 234   assert_param(IS_FMC_NORSRAM_BANK(Bank));\r
 235   \r
 236   /* Disable the FMC_NORSRAM device */\r
 237   __FMC_NORSRAM_DISABLE(Device, Bank);\r
 238   \r
 239   /* De-initialize the FMC_NORSRAM device */\r
 240   /* FMC_NORSRAM_BANK1 */\r
 241   if(Bank == FMC_NORSRAM_BANK1)\r
 242   {\r
 243     Device->BTCR[Bank] = 0x000030DB;    \r
 244   }\r
 245   /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */\r
 246   else\r
 247   {   \r
 248     Device->BTCR[Bank] = 0x000030D2; \r
 249   }\r
 250   \r
 251   Device->BTCR[Bank + 1] = 0x0FFFFFFF;\r
 252   ExDevice->BWTR[Bank]   = 0x0FFFFFFF;\r
 253    \r
 254   return HAL_OK;\r
 255 }\r
 256 \r
 257 \r
 258 /**\r
 259   * @brief  Initialize the FMC_NORSRAM Timing according to the specified\r
 260   *         parameters in the FMC_NORSRAM_TimingTypeDef\r
 261   * @param  Device: Pointer to NORSRAM device instance\r
 262   * @param  Timing: Pointer to NORSRAM Timing structure\r
 263   * @param  Bank: NORSRAM bank number  \r
 264   * @retval HAL status\r
 265   */\r
 266 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)\r
 267 {\r
 268   uint32_t tmpr = 0;\r
 269   \r
 270   /* Check the parameters */\r
 271   assert_param(IS_FMC_NORSRAM_DEVICE(Device));\r
 272   assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));\r
 273   assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));\r
 274   assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));\r
 275   assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));\r
 276   assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));\r
 277   assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));\r
 278   assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));\r
 279   assert_param(IS_FMC_NORSRAM_BANK(Bank));\r
 280   \r
 281   /* Get the BTCR register value */\r
 282   tmpr = Device->BTCR[Bank + 1];\r
 283 \r
 284   /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */\r
 285   tmpr &= ((uint32_t)~(FMC_BTR1_ADDSET  | FMC_BTR1_ADDHLD | FMC_BTR1_DATAST | \\r
 286                        FMC_BTR1_BUSTURN | FMC_BTR1_CLKDIV | FMC_BTR1_DATLAT | \\r
 287                        FMC_BTR1_ACCMOD));\r
 288   \r
 289   /* Set FMC_NORSRAM device timing parameters */  \r
 290   tmpr |= (uint32_t)(Timing->AddressSetupTime                  |\\r
 291                    ((Timing->AddressHoldTime) << 4)          |\\r
 292                    ((Timing->DataSetupTime) << 8)            |\\r
 293                    ((Timing->BusTurnAroundDuration) << 16)   |\\r
 294                    (((Timing->CLKDivision)-1) << 20)         |\\r
 295                    (((Timing->DataLatency)-2) << 24)         |\\r
 296                     (Timing->AccessMode)\r
 297                     );\r
 298   \r
 299   Device->BTCR[Bank + 1] = tmpr;\r
 300   \r
 301   /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */\r
 302   if(HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))\r
 303   {\r
 304     tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << 20)); \r
 305     tmpr |= (uint32_t)(((Timing->CLKDivision)-1) << 20);\r
 306     Device->BTCR[FMC_NORSRAM_BANK1 + 1] = tmpr;\r
 307   }  \r
 308   \r
 309   return HAL_OK;   \r
 310 }\r
 311 \r
 312 /**\r
 313   * @brief  Initialize the FMC_NORSRAM Extended mode Timing according to the specified\r
 314   *         parameters in the FMC_NORSRAM_TimingTypeDef\r
 315   * @param  Device: Pointer to NORSRAM device instance\r
 316   * @param  Timing: Pointer to NORSRAM Timing structure\r
 317   * @param  Bank: NORSRAM bank number  \r
 318   * @retval HAL status\r
 319   */\r
 320 HAL_StatusTypeDef  FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)\r
 321 {  \r
 322   uint32_t tmpr = 0;\r
 323  \r
 324   /* Check the parameters */\r
 325   assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));\r
 326   \r
 327   /* Set NORSRAM device timing register for write configuration, if extended mode is used */\r
 328   if(ExtendedMode == FMC_EXTENDED_MODE_ENABLE)\r
 329   {\r
 330     /* Check the parameters */\r
 331     assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));  \r
 332     assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));\r
 333     assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));\r
 334     assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));\r
 335     assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));\r
 336     assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));\r
 337     assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));\r
 338     assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));\r
 339     assert_param(IS_FMC_NORSRAM_BANK(Bank));  \r
 340     \r
 341     /* Get the BWTR register value */\r
 342     tmpr = Device->BWTR[Bank];\r
 343 \r
 344     /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */\r
 345     tmpr &= ((uint32_t)~(FMC_BWTR1_ADDSET  | FMC_BWTR1_ADDHLD | FMC_BWTR1_DATAST | \\r
 346                          FMC_BWTR1_BUSTURN | FMC_BWTR1_ACCMOD));\r
 347     \r
 348     tmpr |= (uint32_t)(Timing->AddressSetupTime                 |\\r
 349                       ((Timing->AddressHoldTime) << 4)          |\\r
 350                       ((Timing->DataSetupTime) << 8)            |\\r
 351                       ((Timing->BusTurnAroundDuration) << 16)   |\\r
 352                       (Timing->AccessMode));\r
 353 \r
 354     Device->BWTR[Bank] = tmpr;\r
 355   }\r
 356   else\r
 357   {\r
 358     Device->BWTR[Bank] = 0x0FFFFFFF;\r
 359   }   \r
 360   \r
 361   return HAL_OK;  \r
 362 }\r
 363 /**\r
 364   * @}\r
 365   */\r
 366 \r
 367 /** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2\r
 368  *  @brief   management functions \r
 369  *\r
 370 @verbatim   \r
 371   ==============================================================================\r
 372                       ##### FMC_NORSRAM Control functions #####\r
 373   ==============================================================================  \r
 374   [..]\r
 375     This subsection provides a set of functions allowing to control dynamically\r
 376     the FMC NORSRAM interface.\r
 377 \r
 378 @endverbatim\r
 379   * @{\r
 380   */\r
 381 \r
 382 /**\r
 383   * @brief  Enables dynamically FMC_NORSRAM write operation.\r
 384   * @param  Device: Pointer to NORSRAM device instance\r
 385   * @param  Bank: NORSRAM bank number   \r
 386   * @retval HAL status\r
 387   */\r
 388 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)\r
 389 {\r
 390   /* Check the parameters */\r
 391   assert_param(IS_FMC_NORSRAM_DEVICE(Device));\r
 392   assert_param(IS_FMC_NORSRAM_BANK(Bank));\r
 393   \r
 394   /* Enable write operation */\r
 395   Device->BTCR[Bank] |= FMC_WRITE_OPERATION_ENABLE; \r
 396 \r
 397   return HAL_OK;  \r
 398 }\r
 399 \r
 400 /**\r
 401   * @brief  Disables dynamically FMC_NORSRAM write operation.\r
 402   * @param  Device: Pointer to NORSRAM device instance\r
 403   * @param  Bank: NORSRAM bank number   \r
 404   * @retval HAL status\r
 405   */\r
 406 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)\r
 407 { \r
 408   /* Check the parameters */\r
 409   assert_param(IS_FMC_NORSRAM_DEVICE(Device));\r
 410   assert_param(IS_FMC_NORSRAM_BANK(Bank));\r
 411     \r
 412   /* Disable write operation */\r
 413   Device->BTCR[Bank] &= ~FMC_WRITE_OPERATION_ENABLE; \r
 414 \r
 415   return HAL_OK;  \r
 416 }\r
 417 \r
 418 /**\r
 419   * @}\r
 420   */\r
 421 \r
 422 /**\r
 423   * @}\r
 424   */\r
 425 \r
 426 /** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions\r
 427   * @brief    NAND Controller functions \r
 428   *\r
 429   @verbatim \r
 430   ==============================================================================\r
 431                     ##### How to use NAND device driver #####\r
 432   ==============================================================================\r
 433   [..]\r
 434     This driver contains a set of APIs to interface with the FMC NAND banks in order\r
 435     to run the NAND external devices.\r
 436   \r
 437     (+) FMC NAND bank reset using the function FMC_NAND_DeInit() \r
 438     (+) FMC NAND bank control configuration using the function FMC_NAND_Init()\r
 439     (+) FMC NAND bank common space timing configuration using the function \r
 440         FMC_NAND_CommonSpace_Timing_Init()\r
 441     (+) FMC NAND bank attribute space timing configuration using the function \r
 442         FMC_NAND_AttributeSpace_Timing_Init()\r
 443     (+) FMC NAND bank enable/disable ECC correction feature using the functions\r
 444         FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()\r
 445     (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()    \r
 446 \r
 447 @endverbatim\r
 448   * @{\r
 449   */\r
 450 \r
 451 /** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions\r
 452  *  @brief    Initialization and Configuration functions \r
 453  *\r
 454 @verbatim    \r
 455   ==============================================================================\r
 456               ##### Initialization and de_initialization functions #####\r
 457   ==============================================================================\r
 458   [..]  \r
 459     This section provides functions allowing to:\r
 460     (+) Initialize and configure the FMC NAND interface\r
 461     (+) De-initialize the FMC NAND interface \r
 462     (+) Configure the FMC clock and associated GPIOs\r
 463         \r
 464 @endverbatim\r
 465   * @{\r
 466   */\r
 467 \r
 468 /**\r
 469   * @brief  Initializes the FMC_NAND device according to the specified\r
 470   *         control parameters in the FMC_NAND_HandleTypeDef\r
 471   * @param  Device: Pointer to NAND device instance\r
 472   * @param  Init: Pointer to NAND Initialization structure\r
 473   * @retval HAL status\r
 474   */\r
 475 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)\r
 476 {\r
 477   uint32_t tmpr  = 0; \r
 478     \r
 479   /* Check the parameters */\r
 480   assert_param(IS_FMC_NAND_DEVICE(Device));\r
 481   assert_param(IS_FMC_NAND_BANK(Init->NandBank));\r
 482   assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));\r
 483   assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));\r
 484   assert_param(IS_FMC_ECC_STATE(Init->EccComputation));\r
 485   assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));\r
 486   assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));\r
 487   assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));   \r
 488 \r
 489   /* Get the NAND bank 3 register value */\r
 490   tmpr = Device->PCR;\r
 491 \r
 492   /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */\r
 493   tmpr &= ((uint32_t)~(FMC_PCR_PWAITEN  | FMC_PCR_PBKEN | FMC_PCR_PTYP | \\r
 494                        FMC_PCR_PWID | FMC_PCR_ECCEN | FMC_PCR_TCLR | \\r
 495                        FMC_PCR_TAR | FMC_PCR_ECCPS));  \r
 496   /* Set NAND device control parameters */\r
 497   tmpr |= (uint32_t)(Init->Waitfeature                |\\r
 498                       FMC_PCR_MEMORY_TYPE_NAND         |\\r
 499                       Init->MemoryDataWidth            |\\r
 500                       Init->EccComputation             |\\r
 501                       Init->ECCPageSize                |\\r
 502                       ((Init->TCLRSetupTime) << 9)     |\\r
 503                       ((Init->TARSetupTime) << 13));   \r
 504   \r
 505     /* NAND bank 3 registers configuration */\r
 506     Device->PCR  = tmpr;\r
 507   \r
 508   return HAL_OK;\r
 509 \r
 510 }\r
 511 \r
 512 /**\r
 513   * @brief  Initializes the FMC_NAND Common space Timing according to the specified\r
 514   *         parameters in the FMC_NAND_PCC_TimingTypeDef\r
 515   * @param  Device: Pointer to NAND device instance\r
 516   * @param  Timing: Pointer to NAND timing structure\r
 517   * @param  Bank: NAND bank number   \r
 518   * @retval HAL status\r
 519   */\r
 520 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)\r
 521 {\r
 522   uint32_t tmpr = 0;  \r
 523   \r
 524   /* Check the parameters */\r
 525   assert_param(IS_FMC_NAND_DEVICE(Device));\r
 526   assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));\r
 527   assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));\r
 528   assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));\r
 529   assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));\r
 530   assert_param(IS_FMC_NAND_BANK(Bank));\r
 531   \r
 532   /* Get the NAND bank 3 register value */\r
 533   tmpr = Device->PMEM;\r
 534 \r
 535   /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */\r
 536   tmpr &= ((uint32_t)~(FMC_PMEM_MEMSET3  | FMC_PMEM_MEMWAIT3 | FMC_PMEM_MEMHOLD3 | \\r
 537                        FMC_PMEM_MEMHIZ3)); \r
 538   /* Set FMC_NAND device timing parameters */\r
 539   tmpr |= (uint32_t)(Timing->SetupTime                  |\\r
 540                        ((Timing->WaitSetupTime) << 8)     |\\r
 541                        ((Timing->HoldSetupTime) << 16)    |\\r
 542                        ((Timing->HiZSetupTime) << 24)\r
 543                        );\r
 544                             \r
 545     /* NAND bank 3 registers configuration */\r
 546     Device->PMEM = tmpr;\r
 547   \r
 548   return HAL_OK;  \r
 549 }\r
 550 \r
 551 /**\r
 552   * @brief  Initializes the FMC_NAND Attribute space Timing according to the specified\r
 553   *         parameters in the FMC_NAND_PCC_TimingTypeDef\r
 554   * @param  Device: Pointer to NAND device instance\r
 555   * @param  Timing: Pointer to NAND timing structure\r
 556   * @param  Bank: NAND bank number \r
 557   * @retval HAL status\r
 558   */\r
 559 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)\r
 560 {\r
 561   uint32_t tmpr = 0;  \r
 562   \r
 563   /* Check the parameters */ \r
 564   assert_param(IS_FMC_NAND_DEVICE(Device)); \r
 565   assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));\r
 566   assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));\r
 567   assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));\r
 568   assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));\r
 569   assert_param(IS_FMC_NAND_BANK(Bank));\r
 570   \r
 571   /* Get the NAND bank 3 register value */\r
 572   tmpr = Device->PATT;\r
 573 \r
 574   /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */\r
 575   tmpr &= ((uint32_t)~(FMC_PATT_ATTSET3  | FMC_PATT_ATTWAIT3 | FMC_PATT_ATTHOLD3 | \\r
 576                        FMC_PATT_ATTHIZ3));\r
 577   /* Set FMC_NAND device timing parameters */\r
 578   tmpr |= (uint32_t)(Timing->SetupTime                  |\\r
 579                    ((Timing->WaitSetupTime) << 8)     |\\r
 580                    ((Timing->HoldSetupTime) << 16)    |\\r
 581                    ((Timing->HiZSetupTime) << 24));\r
 582                        \r
 583     /* NAND bank 3 registers configuration */\r
 584     Device->PATT = tmpr;\r
 585   \r
 586   return HAL_OK;\r
 587 }\r
 588 \r
 589 /**\r
 590   * @brief  DeInitializes the FMC_NAND device \r
 591   * @param  Device: Pointer to NAND device instance\r
 592   * @param  Bank: NAND bank number\r
 593   * @retval HAL status\r
 594   */\r
 595 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)\r
 596 {\r
 597   /* Check the parameters */ \r
 598   assert_param(IS_FMC_NAND_DEVICE(Device)); \r
 599   assert_param(IS_FMC_NAND_BANK(Bank));\r
 600       \r
 601   /* Disable the NAND Bank */\r
 602   __FMC_NAND_DISABLE(Device);\r
 603  \r
 604     /* Set the FMC_NAND_BANK3 registers to their reset values */\r
 605     Device->PCR  = 0x00000018;\r
 606     Device->SR   = 0x00000040;\r
 607     Device->PMEM = 0xFCFCFCFC;\r
 608     Device->PATT = 0xFCFCFCFC; \r
 609   \r
 610   return HAL_OK;\r
 611 }\r
 612 \r
 613 /**\r
 614   * @}\r
 615   */\r
 616 \r
 617 /** @defgroup HAL_FMC_NAND_Group3 Control functions \r
 618   *  @brief   management functions \r
 619   *\r
 620 @verbatim   \r
 621   ==============================================================================\r
 622                        ##### FMC_NAND Control functions #####\r
 623   ==============================================================================  \r
 624   [..]\r
 625     This subsection provides a set of functions allowing to control dynamically\r
 626     the FMC NAND interface.\r
 627 \r
 628 @endverbatim\r
 629   * @{\r
 630   */ \r
 631 \r
 632     \r
 633 /**\r
 634   * @brief  Enables dynamically FMC_NAND ECC feature.\r
 635   * @param  Device: Pointer to NAND device instance\r
 636   * @param  Bank: NAND bank number\r
 637   * @retval HAL status\r
 638   */    \r
 639 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)\r
 640 {\r
 641   /* Check the parameters */ \r
 642   assert_param(IS_FMC_NAND_DEVICE(Device)); \r
 643   assert_param(IS_FMC_NAND_BANK(Bank));\r
 644     \r
 645   /* Enable ECC feature */\r
 646     Device->PCR |= FMC_PCR_ECCEN;\r
 647   \r
 648   return HAL_OK;  \r
 649 }\r
 650 \r
 651 \r
 652 /**\r
 653   * @brief  Disables dynamically FMC_NAND ECC feature.\r
 654   * @param  Device: Pointer to NAND device instance\r
 655   * @param  Bank: NAND bank number\r
 656   * @retval HAL status\r
 657   */  \r
 658 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)  \r
 659 {  \r
 660   /* Check the parameters */ \r
 661   assert_param(IS_FMC_NAND_DEVICE(Device)); \r
 662   assert_param(IS_FMC_NAND_BANK(Bank));\r
 663     \r
 664   /* Disable ECC feature */\r
 665     Device->PCR &= ~FMC_PCR_ECCEN;\r
 666 \r
 667   return HAL_OK;  \r
 668 }\r
 669 \r
 670 /**\r
 671   * @brief  Disables dynamically FMC_NAND ECC feature.\r
 672   * @param  Device: Pointer to NAND device instance\r
 673   * @param  ECCval: Pointer to ECC value\r
 674   * @param  Bank: NAND bank number\r
 675   * @param  Timeout: Timeout wait value  \r
 676   * @retval HAL status\r
 677   */\r
 678 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)\r
 679 {\r
 680   uint32_t tickstart = 0;\r
 681 \r
 682   /* Check the parameters */ \r
 683   assert_param(IS_FMC_NAND_DEVICE(Device)); \r
 684   assert_param(IS_FMC_NAND_BANK(Bank));\r
 685 \r
 686   /* Get tick */ \r
 687   tickstart = HAL_GetTick();\r
 688 \r
 689   /* Wait until FIFO is empty */\r
 690   while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)\r
 691   {\r
 692     /* Check for the Timeout */\r
 693     if(Timeout != HAL_MAX_DELAY)\r
 694     {\r
 695       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
 696       {\r
 697         return HAL_TIMEOUT;\r
 698       }\r
 699     }  \r
 700   }\r
 701  \r
 702   /* Get the ECCR register value */\r
 703   *ECCval = (uint32_t)Device->ECCR;\r
 704 \r
 705   return HAL_OK;  \r
 706 }\r
 707 \r
 708 /**\r
 709   * @}\r
 710   */\r
 711   \r
 712 /**\r
 713   * @}\r
 714   */\r
 715 \r
 716 /** @defgroup FMC_LL_SDRAM\r
 717   * @brief    SDRAM Controller functions \r
 718   *\r
 719   @verbatim \r
 720   ==============================================================================\r
 721                      ##### How to use SDRAM device driver #####\r
 722   ==============================================================================\r
 723   [..] \r
 724     This driver contains a set of APIs to interface with the FMC SDRAM banks in order\r
 725     to run the SDRAM external devices.\r
 726     \r
 727     (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit() \r
 728     (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init()\r
 729     (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init()\r
 730     (+) FMC SDRAM bank enable/disable write operation using the functions\r
 731         FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable()   \r
 732     (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand()      \r
 733        \r
 734 @endverbatim\r
 735   * @{\r
 736   */\r
 737          \r
 738 /** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1\r
 739   *  @brief    Initialization and Configuration functions \r
 740   *\r
 741 @verbatim    \r
 742   ==============================================================================\r
 743               ##### Initialization and de_initialization functions #####\r
 744   ==============================================================================\r
 745   [..]  \r
 746     This section provides functions allowing to:\r
 747     (+) Initialize and configure the FMC SDRAM interface\r
 748     (+) De-initialize the FMC SDRAM interface \r
 749     (+) Configure the FMC clock and associated GPIOs\r
 750         \r
 751 @endverbatim\r
 752   * @{\r
 753   */\r
 754 \r
 755 /**\r
 756   * @brief  Initializes the FMC_SDRAM device according to the specified\r
 757   *         control parameters in the FMC_SDRAM_InitTypeDef\r
 758   * @param  Device: Pointer to SDRAM device instance\r
 759   * @param  Init: Pointer to SDRAM Initialization structure   \r
 760   * @retval HAL status\r
 761   */\r
 762 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init)\r
 763 {\r
 764   uint32_t tmpr1 = 0;\r
 765   uint32_t tmpr2 = 0;\r
 766     \r
 767   /* Check the parameters */\r
 768   assert_param(IS_FMC_SDRAM_DEVICE(Device));\r
 769   assert_param(IS_FMC_SDRAM_BANK(Init->SDBank));\r
 770   assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber));\r
 771   assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber));\r
 772   assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth));\r
 773   assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber));\r
 774   assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency));\r
 775   assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection));\r
 776   assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));\r
 777   assert_param(IS_FMC_READ_BURST(Init->ReadBurst));\r
 778   assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay));   \r
 779 \r
 780   /* Set SDRAM bank configuration parameters */\r
 781   if (Init->SDBank != FMC_SDRAM_BANK2) \r
 782   { \r
 783     tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];\r
 784     \r
 785     /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */\r
 786     tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC  | FMC_SDCR1_NR | FMC_SDCR1_MWID | \\r
 787                          FMC_SDCR1_NB  | FMC_SDCR1_CAS | FMC_SDCR1_WP | \\r
 788                          FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));\r
 789 \r
 790     tmpr1 |= (uint32_t)(Init->ColumnBitsNumber   |\\r
 791                         Init->RowBitsNumber      |\\r
 792                         Init->MemoryDataWidth    |\\r
 793                         Init->InternalBankNumber |\\r
 794                         Init->CASLatency         |\\r
 795                         Init->WriteProtection    |\\r
 796                         Init->SDClockPeriod      |\\r
 797                         Init->ReadBurst          |\\r
 798                         Init->ReadPipeDelay\r
 799                         );                                      \r
 800     Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;\r
 801   }\r
 802   else /* FMC_Bank2_SDRAM */                      \r
 803   {\r
 804     tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];\r
 805     \r
 806     /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */\r
 807     tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC  | FMC_SDCR1_NR | FMC_SDCR1_MWID | \\r
 808                           FMC_SDCR1_NB  | FMC_SDCR1_CAS | FMC_SDCR1_WP | \\r
 809                           FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));\r
 810     \r
 811     tmpr1 |= (uint32_t)(Init->SDClockPeriod      |\\r
 812                         Init->ReadBurst          |\\r
 813                         Init->ReadPipeDelay);  \r
 814     \r
 815     tmpr2 = Device->SDCR[FMC_SDRAM_BANK2];\r
 816     \r
 817     /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */\r
 818     tmpr2 &= ((uint32_t)~(FMC_SDCR1_NC  | FMC_SDCR1_NR | FMC_SDCR1_MWID | \\r
 819                           FMC_SDCR1_NB  | FMC_SDCR1_CAS | FMC_SDCR1_WP | \\r
 820                           FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));\r
 821 \r
 822     tmpr2 |= (uint32_t)(Init->ColumnBitsNumber   |\\r
 823                        Init->RowBitsNumber      |\\r
 824                        Init->MemoryDataWidth    |\\r
 825                        Init->InternalBankNumber |\\r
 826                        Init->CASLatency         |\\r
 827                        Init->WriteProtection);\r
 828 \r
 829     Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;\r
 830     Device->SDCR[FMC_SDRAM_BANK2] = tmpr2;\r
 831   }  \r
 832   \r
 833   return HAL_OK;\r
 834 }\r
 835 \r
 836 /**\r
 837   * @brief  Initializes the FMC_SDRAM device timing according to the specified\r
 838   *         parameters in the FMC_SDRAM_TimingTypeDef\r
 839   * @param  Device: Pointer to SDRAM device instance\r
 840   * @param  Timing: Pointer to SDRAM Timing structure\r
 841   * @param  Bank: SDRAM bank number   \r
 842   * @retval HAL status\r
 843   */\r
 844 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)\r
 845 {\r
 846   uint32_t tmpr1 = 0;\r
 847   uint32_t tmpr2 = 0;\r
 848     \r
 849   /* Check the parameters */\r
 850   assert_param(IS_FMC_SDRAM_DEVICE(Device));\r
 851   assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay));\r
 852   assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay));\r
 853   assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime));\r
 854   assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay));\r
 855   assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime));\r
 856   assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));\r
 857   assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));\r
 858   assert_param(IS_FMC_SDRAM_BANK(Bank));\r
 859   \r
 860   /* Set SDRAM device timing parameters */ \r
 861   if (Bank != FMC_SDRAM_BANK2) \r
 862   { \r
 863     tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];\r
 864     \r
 865     /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */\r
 866     tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD  | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \\r
 867                           FMC_SDTR1_TRC  | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \\r
 868                           FMC_SDTR1_TRCD));\r
 869     \r
 870     tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1)           |\\r
 871                        (((Timing->ExitSelfRefreshDelay)-1) << 4) |\\r
 872                        (((Timing->SelfRefreshTime)-1) << 8)      |\\r
 873                        (((Timing->RowCycleDelay)-1) << 12)       |\\r
 874                        (((Timing->WriteRecoveryTime)-1) <<16)    |\\r
 875                        (((Timing->RPDelay)-1) << 20)             |\\r
 876                        (((Timing->RCDDelay)-1) << 24));\r
 877     Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;\r
 878   }\r
 879   else /* FMC_Bank2_SDRAM */\r
 880   {  \r
 881     tmpr1 = Device->SDTR[FMC_SDRAM_BANK2];\r
 882     \r
 883     /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */\r
 884     tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD  | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \\r
 885                           FMC_SDTR1_TRC  | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \\r
 886                           FMC_SDTR1_TRCD));\r
 887     \r
 888     tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1)           |\\r
 889                        (((Timing->ExitSelfRefreshDelay)-1) << 4) |\\r
 890                        (((Timing->SelfRefreshTime)-1) << 8)      |\\r
 891                        (((Timing->WriteRecoveryTime)-1) <<16)    |\\r
 892                        (((Timing->RCDDelay)-1) << 24));   \r
 893     \r
 894     tmpr2 = Device->SDTR[FMC_SDRAM_BANK1];\r
 895     \r
 896     /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */\r
 897     tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD  | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \\r
 898                           FMC_SDTR1_TRC  | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \\r
 899                           FMC_SDTR1_TRCD));\r
 900     tmpr2 |= (uint32_t)((((Timing->RowCycleDelay)-1) << 12)       |\\r
 901                         (((Timing->RPDelay)-1) << 20)); \r
 902 \r
 903     Device->SDTR[FMC_SDRAM_BANK2] = tmpr1;\r
 904     Device->SDTR[FMC_SDRAM_BANK1] = tmpr2;\r
 905   }   \r
 906   \r
 907   return HAL_OK;\r
 908 }\r
 909 \r
 910 /**\r
 911   * @brief  DeInitializes the FMC_SDRAM peripheral \r
 912   * @param  Device: Pointer to SDRAM device instance\r
 913   * @retval HAL status\r
 914   */\r
 915 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)\r
 916 {\r
 917   /* Check the parameters */\r
 918   assert_param(IS_FMC_SDRAM_DEVICE(Device));\r
 919   assert_param(IS_FMC_SDRAM_BANK(Bank));\r
 920   \r
 921   /* De-initialize the SDRAM device */\r
 922   Device->SDCR[Bank] = 0x000002D0;\r
 923   Device->SDTR[Bank] = 0x0FFFFFFF;    \r
 924   Device->SDCMR      = 0x00000000;\r
 925   Device->SDRTR      = 0x00000000;\r
 926   Device->SDSR       = 0x00000000;\r
 927 \r
 928   return HAL_OK;\r
 929 }\r
 930 \r
 931 /**\r
 932   * @}\r
 933   */\r
 934 \r
 935 /** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2\r
 936   *  @brief   management functions \r
 937   *\r
 938 @verbatim   \r
 939   ==============================================================================\r
 940                       ##### FMC_SDRAM Control functions #####\r
 941   ==============================================================================  \r
 942   [..]\r
 943     This subsection provides a set of functions allowing to control dynamically\r
 944     the FMC SDRAM interface.\r
 945 \r
 946 @endverbatim\r
 947   * @{\r
 948   */\r
 949 \r
 950 /**\r
 951   * @brief  Enables dynamically FMC_SDRAM write protection.\r
 952   * @param  Device: Pointer to SDRAM device instance\r
 953   * @param  Bank: SDRAM bank number \r
 954   * @retval HAL status\r
 955   */\r
 956 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)\r
 957 { \r
 958   /* Check the parameters */\r
 959   assert_param(IS_FMC_SDRAM_DEVICE(Device));\r
 960   assert_param(IS_FMC_SDRAM_BANK(Bank));\r
 961   \r
 962   /* Enable write protection */\r
 963   Device->SDCR[Bank] |= FMC_SDRAM_WRITE_PROTECTION_ENABLE;\r
 964   \r
 965   return HAL_OK;  \r
 966 }\r
 967 \r
 968 /**\r
 969   * @brief  Disables dynamically FMC_SDRAM write protection.\r
 970   * @param  hsdram: FMC_SDRAM handle\r
 971   * @retval HAL status\r
 972   */\r
 973 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)\r
 974 {\r
 975   /* Check the parameters */\r
 976   assert_param(IS_FMC_SDRAM_DEVICE(Device));\r
 977   assert_param(IS_FMC_SDRAM_BANK(Bank));\r
 978   \r
 979   /* Disable write protection */\r
 980   Device->SDCR[Bank] &= ~FMC_SDRAM_WRITE_PROTECTION_ENABLE;\r
 981   \r
 982   return HAL_OK;\r
 983 }\r
 984   \r
 985 /**\r
 986   * @brief  Send Command to the FMC SDRAM bank\r
 987   * @param  Device: Pointer to SDRAM device instance\r
 988   * @param  Command: Pointer to SDRAM command structure   \r
 989   * @param  Timing: Pointer to SDRAM Timing structure\r
 990   * @param  Timeout: Timeout wait value\r
 991   * @retval HAL state\r
 992   */  \r
 993 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)\r
 994 {\r
 995   __IO uint32_t tmpr = 0;\r
 996   uint32_t tickstart = 0;\r
 997   \r
 998   /* Check the parameters */\r
 999   assert_param(IS_FMC_SDRAM_DEVICE(Device));\r
1000   assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode));\r
1001   assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget));\r
1002   assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber));\r
1003   assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition));  \r
1004 \r
1005   /* Set command register */\r
1006   tmpr = (uint32_t)((Command->CommandMode)                  |\\r
1007                     (Command->CommandTarget)                |\\r
1008                     (((Command->AutoRefreshNumber)-1) << 5) |\\r
1009                     ((Command->ModeRegisterDefinition) << 9)\r
1010                     );\r
1011     \r
1012   Device->SDCMR = tmpr;\r
1013 \r
1014   /* Get tick */ \r
1015   tickstart = HAL_GetTick();\r
1016 \r
1017   /* wait until command is send */\r
1018   while(HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY))\r
1019   {\r
1020     /* Check for the Timeout */\r
1021     if(Timeout != HAL_MAX_DELAY)\r
1022     {\r
1023       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
1024       {\r
1025         return HAL_TIMEOUT;\r
1026       }\r
1027     }     \r
1028     \r
1029     return HAL_ERROR;\r
1030   }\r
1031   \r
1032   return HAL_OK;  \r
1033 }\r
1034 \r
1035 /**\r
1036   * @brief  Program the SDRAM Memory Refresh rate.\r
1037   * @param  Device: Pointer to SDRAM device instance  \r
1038   * @param  RefreshRate: The SDRAM refresh rate value.       \r
1039   * @retval HAL state\r
1040   */\r
1041 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)\r
1042 {\r
1043   /* Check the parameters */\r
1044   assert_param(IS_FMC_SDRAM_DEVICE(Device));\r
1045   assert_param(IS_FMC_REFRESH_RATE(RefreshRate));\r
1046   \r
1047   /* Set the refresh rate in command register */\r
1048   Device->SDRTR |= (RefreshRate<<1);\r
1049   \r
1050   return HAL_OK;   \r
1051 }\r
1052 \r
1053 /**\r
1054   * @brief  Set the Number of consecutive SDRAM Memory auto Refresh commands.\r
1055   * @param  Device: Pointer to SDRAM device instance  \r
1056   * @param  AutoRefreshNumber: Specifies the auto Refresh number.       \r
1057   * @retval None\r
1058   */\r
1059 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber)\r
1060 {\r
1061   /* Check the parameters */\r
1062   assert_param(IS_FMC_SDRAM_DEVICE(Device));\r
1063   assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber));\r
1064   \r
1065   /* Set the Auto-refresh number in command register */\r
1066   Device->SDCMR |= (AutoRefreshNumber << 5); \r
1067 \r
1068   return HAL_OK;  \r
1069 }\r
1070 \r
1071 /**\r
1072   * @brief  Returns the indicated FMC SDRAM bank mode status.\r
1073   * @param  Device: Pointer to SDRAM device instance  \r
1074   * @param  Bank: Defines the FMC SDRAM bank. This parameter can be \r
1075   *                     FMC_Bank1_SDRAM or FMC_Bank2_SDRAM. \r
1076   * @retval The FMC SDRAM bank mode status, could be on of the following values:\r
1077   *         FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or \r
1078   *         FMC_SDRAM_POWER_DOWN_MODE.           \r
1079   */\r
1080 uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank)\r
1081 {\r
1082   uint32_t tmpreg = 0;\r
1083   \r
1084   /* Check the parameters */\r
1085   assert_param(IS_FMC_SDRAM_DEVICE(Device));\r
1086   assert_param(IS_FMC_SDRAM_BANK(Bank));\r
1087 \r
1088   /* Get the corresponding bank mode */\r
1089   if(Bank == FMC_SDRAM_BANK1)\r
1090   {\r
1091     tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1); \r
1092   }\r
1093   else\r
1094   {\r
1095     tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2);\r
1096   }\r
1097   \r
1098   /* Return the mode status */\r
1099   return tmpreg;\r
1100 }\r
1101 \r
1102 /**\r
1103   * @}\r
1104   */\r
1105 \r
1106 /**\r
1107   * @}\r
1108   */\r
1109 \r
1110 /**\r
1111   * @}\r
1112   */\r
1113 #endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_SDRAM_MODULE_ENABLED */\r
1114 \r
1115 /**\r
1116   * @}\r
1117   */\r
1118 \r
1119 /**\r
1120   * @}\r
1121   */\r
1122 \r
1123 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r