2 ******************************************************************************
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3 * @file stm32f7xx_hal_eth.h
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4 * @author MCD Application Team
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6 * @date 24-March-2015
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7 * @brief Header file of ETH HAL module.
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8 ******************************************************************************
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11 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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13 * Redistribution and use in source and binary forms, with or without modification,
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14 * are permitted provided that the following conditions are met:
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15 * 1. Redistributions of source code must retain the above copyright notice,
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16 * this list of conditions and the following disclaimer.
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17 * 2. Redistributions in binary form must reproduce the above copyright notice,
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18 * this list of conditions and the following disclaimer in the documentation
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19 * and/or other materials provided with the distribution.
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20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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21 * may be used to endorse or promote products derived from this software
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22 * without specific prior written permission.
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24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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35 ******************************************************************************
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38 /* Define to prevent recursive inclusion -------------------------------------*/
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39 #ifndef __STM32F7xx_HAL_ETH_H
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40 #define __STM32F7xx_HAL_ETH_H
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46 /* Includes ------------------------------------------------------------------*/
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47 #include "stm32f7xx_hal_def.h"
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49 /** @addtogroup STM32F7xx_HAL_Driver
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57 /** @addtogroup ETH_Private_Macros
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60 #define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
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61 #define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \
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62 ((CMD) == ETH_AUTONEGOTIATION_DISABLE))
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63 #define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \
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64 ((SPEED) == ETH_SPEED_100M))
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65 #define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \
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66 ((MODE) == ETH_MODE_HALFDUPLEX))
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67 #define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \
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68 ((MODE) == ETH_MODE_HALFDUPLEX))
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69 #define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
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70 ((MODE) == ETH_RXINTERRUPT_MODE))
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71 #define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
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72 ((MODE) == ETH_RXINTERRUPT_MODE))
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73 #define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
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74 ((MODE) == ETH_RXINTERRUPT_MODE))
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75 #define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \
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76 ((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
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77 #define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \
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78 ((MODE) == ETH_MEDIA_INTERFACE_RMII))
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79 #define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \
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80 ((CMD) == ETH_WATCHDOG_DISABLE))
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81 #define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \
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82 ((CMD) == ETH_JABBER_DISABLE))
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83 #define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \
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84 ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \
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85 ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \
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86 ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \
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87 ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \
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88 ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \
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89 ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \
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90 ((GAP) == ETH_INTERFRAMEGAP_40BIT))
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91 #define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \
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92 ((CMD) == ETH_CARRIERSENCE_DISABLE))
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93 #define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \
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94 ((CMD) == ETH_RECEIVEOWN_DISABLE))
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95 #define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \
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96 ((CMD) == ETH_LOOPBACKMODE_DISABLE))
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97 #define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \
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98 ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
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99 #define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \
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100 ((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
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101 #define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \
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102 ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
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103 #define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \
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104 ((LIMIT) == ETH_BACKOFFLIMIT_8) || \
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105 ((LIMIT) == ETH_BACKOFFLIMIT_4) || \
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106 ((LIMIT) == ETH_BACKOFFLIMIT_1))
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107 #define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \
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108 ((CMD) == ETH_DEFFERRALCHECK_DISABLE))
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109 #define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \
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110 ((CMD) == ETH_RECEIVEAll_DISABLE))
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111 #define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \
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112 ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \
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113 ((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
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114 #define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \
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115 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \
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116 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
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117 #define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \
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118 ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
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119 #define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \
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120 ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
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121 #define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \
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122 ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))
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123 #define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \
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124 ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \
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125 ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \
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126 ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
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127 #define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \
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128 ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \
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129 ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
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130 #define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
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131 #define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \
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132 ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
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133 #define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \
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134 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \
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135 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \
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136 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
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137 #define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \
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138 ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
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139 #define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \
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140 ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
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141 #define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \
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142 ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
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143 #define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \
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144 ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
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145 #define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
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146 #define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \
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147 ((ADDRESS) == ETH_MAC_ADDRESS1) || \
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148 ((ADDRESS) == ETH_MAC_ADDRESS2) || \
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149 ((ADDRESS) == ETH_MAC_ADDRESS3))
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150 #define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \
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151 ((ADDRESS) == ETH_MAC_ADDRESS2) || \
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152 ((ADDRESS) == ETH_MAC_ADDRESS3))
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153 #define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \
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154 ((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
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155 #define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \
\r
156 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \
\r
157 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \
\r
158 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \
\r
159 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \
\r
160 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
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161 #define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \
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162 ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
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163 #define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \
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164 ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
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165 #define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \
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166 ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
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167 #define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \
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168 ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
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169 #define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \
\r
170 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \
\r
171 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \
\r
172 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \
\r
173 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \
\r
174 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \
\r
175 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \
\r
176 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
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177 #define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \
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178 ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
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179 #define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \
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180 ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
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181 #define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \
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182 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \
\r
183 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \
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184 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
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185 #define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \
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186 ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
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187 #define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \
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188 ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
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189 #define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \
\r
190 ((CMD) == ETH_FIXEDBURST_DISABLE))
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191 #define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \
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192 ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \
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193 ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \
\r
194 ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \
\r
195 ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \
\r
196 ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \
\r
197 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \
\r
198 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \
\r
199 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \
\r
200 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \
\r
201 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \
\r
202 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
\r
203 #define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \
\r
204 ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \
\r
205 ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \
\r
206 ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \
\r
207 ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \
\r
208 ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \
\r
209 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \
\r
210 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \
\r
211 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \
\r
212 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \
\r
213 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \
\r
214 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
\r
215 #define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
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216 #define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \
\r
217 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \
\r
218 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \
\r
219 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \
\r
220 ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
\r
221 #define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \
\r
222 ((FLAG) == ETH_DMATXDESC_IC) || \
\r
223 ((FLAG) == ETH_DMATXDESC_LS) || \
\r
224 ((FLAG) == ETH_DMATXDESC_FS) || \
\r
225 ((FLAG) == ETH_DMATXDESC_DC) || \
\r
226 ((FLAG) == ETH_DMATXDESC_DP) || \
\r
227 ((FLAG) == ETH_DMATXDESC_TTSE) || \
\r
228 ((FLAG) == ETH_DMATXDESC_TER) || \
\r
229 ((FLAG) == ETH_DMATXDESC_TCH) || \
\r
230 ((FLAG) == ETH_DMATXDESC_TTSS) || \
\r
231 ((FLAG) == ETH_DMATXDESC_IHE) || \
\r
232 ((FLAG) == ETH_DMATXDESC_ES) || \
\r
233 ((FLAG) == ETH_DMATXDESC_JT) || \
\r
234 ((FLAG) == ETH_DMATXDESC_FF) || \
\r
235 ((FLAG) == ETH_DMATXDESC_PCE) || \
\r
236 ((FLAG) == ETH_DMATXDESC_LCA) || \
\r
237 ((FLAG) == ETH_DMATXDESC_NC) || \
\r
238 ((FLAG) == ETH_DMATXDESC_LCO) || \
\r
239 ((FLAG) == ETH_DMATXDESC_EC) || \
\r
240 ((FLAG) == ETH_DMATXDESC_VF) || \
\r
241 ((FLAG) == ETH_DMATXDESC_CC) || \
\r
242 ((FLAG) == ETH_DMATXDESC_ED) || \
\r
243 ((FLAG) == ETH_DMATXDESC_UF) || \
\r
244 ((FLAG) == ETH_DMATXDESC_DB))
\r
245 #define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \
\r
246 ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
\r
247 #define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \
\r
248 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \
\r
249 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \
\r
250 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
\r
251 #define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
\r
252 #define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \
\r
253 ((FLAG) == ETH_DMARXDESC_AFM) || \
\r
254 ((FLAG) == ETH_DMARXDESC_ES) || \
\r
255 ((FLAG) == ETH_DMARXDESC_DE) || \
\r
256 ((FLAG) == ETH_DMARXDESC_SAF) || \
\r
257 ((FLAG) == ETH_DMARXDESC_LE) || \
\r
258 ((FLAG) == ETH_DMARXDESC_OE) || \
\r
259 ((FLAG) == ETH_DMARXDESC_VLAN) || \
\r
260 ((FLAG) == ETH_DMARXDESC_FS) || \
\r
261 ((FLAG) == ETH_DMARXDESC_LS) || \
\r
262 ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \
\r
263 ((FLAG) == ETH_DMARXDESC_LC) || \
\r
264 ((FLAG) == ETH_DMARXDESC_FT) || \
\r
265 ((FLAG) == ETH_DMARXDESC_RWT) || \
\r
266 ((FLAG) == ETH_DMARXDESC_RE) || \
\r
267 ((FLAG) == ETH_DMARXDESC_DBE) || \
\r
268 ((FLAG) == ETH_DMARXDESC_CE) || \
\r
269 ((FLAG) == ETH_DMARXDESC_MAMPCE))
\r
270 #define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \
\r
271 ((BUFFER) == ETH_DMARXDESC_BUFFER2))
\r
272 #define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
\r
273 ((FLAG) == ETH_PMT_FLAG_MPR))
\r
274 #define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800) == 0x00) && ((FLAG) != 0x00))
\r
275 #define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
\r
276 ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \
\r
277 ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \
\r
278 ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
\r
279 ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
\r
280 ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
\r
281 ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
\r
282 ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
\r
283 ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
\r
284 ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
\r
285 ((FLAG) == ETH_DMA_FLAG_T))
\r
286 #define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF1) == 0x00) && ((IT) != 0x00))
\r
287 #define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
\r
288 ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
\r
289 ((IT) == ETH_MAC_IT_PMT))
\r
290 #define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
\r
291 ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
\r
292 ((FLAG) == ETH_MAC_FLAG_PMT))
\r
293 #define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800) == 0x00) && ((IT) != 0x00))
\r
294 #define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
\r
295 ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
\r
296 ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
\r
297 ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \
\r
298 ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \
\r
299 ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \
\r
300 ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \
\r
301 ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \
\r
302 ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))
\r
303 #define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \
\r
304 ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
\r
305 #define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \
\r
307 #define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
\r
308 ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
\r
309 ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))
\r
310 #define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \
\r
311 ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))
\r
318 /** @addtogroup ETH_Private_Defines
\r
321 /* Delay to wait when writing to some Ethernet registers */
\r
322 #define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001)
\r
324 /* ETHERNET Errors */
\r
325 #define ETH_SUCCESS ((uint32_t)0)
\r
326 #define ETH_ERROR ((uint32_t)1)
\r
328 /* ETHERNET DMA Tx descriptors Collision Count Shift */
\r
329 #define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3)
\r
331 /* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
\r
332 #define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
\r
334 /* ETHERNET DMA Rx descriptors Frame Length Shift */
\r
335 #define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16)
\r
337 /* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
\r
338 #define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
\r
340 /* ETHERNET DMA Rx descriptors Frame length Shift */
\r
341 #define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16)
\r
343 /* ETHERNET MAC address offsets */
\r
344 #define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40) /* ETHERNET MAC address high offset */
\r
345 #define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44) /* ETHERNET MAC address low offset */
\r
347 /* ETHERNET MACMIIAR register Mask */
\r
348 #define ETH_MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3)
\r
350 /* ETHERNET MACCR register Mask */
\r
351 #define ETH_MACCR_CLEAR_MASK ((uint32_t)0xFF20810F)
\r
353 /* ETHERNET MACFCR register Mask */
\r
354 #define ETH_MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41)
\r
356 /* ETHERNET DMAOMR register Mask */
\r
357 #define ETH_DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23)
\r
359 /* ETHERNET Remote Wake-up frame register length */
\r
360 #define ETH_WAKEUP_REGISTER_LENGTH 8
\r
362 /* ETHERNET Missed frames counter Shift */
\r
363 #define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17
\r
368 /* Exported types ------------------------------------------------------------*/
\r
369 /** @defgroup ETH_Exported_Types ETH Exported Types
\r
374 * @brief HAL State structures definition
\r
378 HAL_ETH_STATE_RESET = 0x00, /*!< Peripheral not yet Initialized or disabled */
\r
379 HAL_ETH_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
\r
380 HAL_ETH_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
\r
381 HAL_ETH_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
\r
382 HAL_ETH_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
\r
383 HAL_ETH_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
\r
384 HAL_ETH_STATE_BUSY_WR = 0x42, /*!< Write process is ongoing */
\r
385 HAL_ETH_STATE_BUSY_RD = 0x82, /*!< Read process is ongoing */
\r
386 HAL_ETH_STATE_TIMEOUT = 0x03, /*!< Timeout state */
\r
387 HAL_ETH_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
\r
388 }HAL_ETH_StateTypeDef;
\r
391 * @brief ETH Init Structure definition
\r
396 uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY
\r
397 The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
\r
398 and the mode (half/full-duplex).
\r
399 This parameter can be a value of @ref ETH_AutoNegotiation */
\r
401 uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.
\r
402 This parameter can be a value of @ref ETH_Speed */
\r
404 uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
\r
405 This parameter can be a value of @ref ETH_Duplex_Mode */
\r
407 uint16_t PhyAddress; /*!< Ethernet PHY address.
\r
408 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
\r
410 uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
\r
412 uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
\r
413 This parameter can be a value of @ref ETH_Rx_Mode */
\r
415 uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.
\r
416 This parameter can be a value of @ref ETH_Checksum_Mode */
\r
418 uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface.
\r
419 This parameter can be a value of @ref ETH_Media_Interface */
\r
425 * @brief ETH MAC Configuration Structure definition
\r
430 uint32_t Watchdog; /*!< Selects or not the Watchdog timer
\r
431 When enabled, the MAC allows no more then 2048 bytes to be received.
\r
432 When disabled, the MAC can receive up to 16384 bytes.
\r
433 This parameter can be a value of @ref ETH_Watchdog */
\r
435 uint32_t Jabber; /*!< Selects or not Jabber timer
\r
436 When enabled, the MAC allows no more then 2048 bytes to be sent.
\r
437 When disabled, the MAC can send up to 16384 bytes.
\r
438 This parameter can be a value of @ref ETH_Jabber */
\r
440 uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission.
\r
441 This parameter can be a value of @ref ETH_Inter_Frame_Gap */
\r
443 uint32_t CarrierSense; /*!< Selects or not the Carrier Sense.
\r
444 This parameter can be a value of @ref ETH_Carrier_Sense */
\r
446 uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn,
\r
447 ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
\r
448 in Half-Duplex mode.
\r
449 This parameter can be a value of @ref ETH_Receive_Own */
\r
451 uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode.
\r
452 This parameter can be a value of @ref ETH_Loop_Back_Mode */
\r
454 uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
\r
455 This parameter can be a value of @ref ETH_Checksum_Offload */
\r
457 uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
\r
458 when a collision occurs (Half-Duplex mode).
\r
459 This parameter can be a value of @ref ETH_Retry_Transmission */
\r
461 uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
\r
462 This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
\r
464 uint32_t BackOffLimit; /*!< Selects the BackOff limit value.
\r
465 This parameter can be a value of @ref ETH_Back_Off_Limit */
\r
467 uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode).
\r
468 This parameter can be a value of @ref ETH_Deferral_Check */
\r
470 uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).
\r
471 This parameter can be a value of @ref ETH_Receive_All */
\r
473 uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.
\r
474 This parameter can be a value of @ref ETH_Source_Addr_Filter */
\r
476 uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
\r
477 This parameter can be a value of @ref ETH_Pass_Control_Frames */
\r
479 uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.
\r
480 This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
\r
482 uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames.
\r
483 This parameter can be a value of @ref ETH_Destination_Addr_Filter */
\r
485 uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode
\r
486 This parameter can be a value of @ref ETH_Promiscuous_Mode */
\r
488 uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
\r
489 This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
\r
491 uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
\r
492 This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
\r
494 uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.
\r
495 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
\r
497 uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.
\r
498 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
\r
500 uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
\r
501 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
\r
503 uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
\r
504 This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
\r
506 uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
\r
507 automatic retransmission of PAUSE Frame.
\r
508 This parameter can be a value of @ref ETH_Pause_Low_Threshold */
\r
510 uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
\r
511 unicast address and unique multicast address).
\r
512 This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
\r
514 uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and
\r
515 disable its transmitter for a specified time (Pause Time)
\r
516 This parameter can be a value of @ref ETH_Receive_Flow_Control */
\r
518 uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
\r
519 or the MAC back-pressure operation (Half-Duplex mode)
\r
520 This parameter can be a value of @ref ETH_Transmit_Flow_Control */
\r
522 uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
\r
523 comparison and filtering.
\r
524 This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
\r
526 uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */
\r
528 } ETH_MACInitTypeDef;
\r
532 * @brief ETH DMA Configuration Structure definition
\r
537 uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
\r
538 This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
\r
540 uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode.
\r
541 This parameter can be a value of @ref ETH_Receive_Store_Forward */
\r
543 uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames.
\r
544 This parameter can be a value of @ref ETH_Flush_Received_Frame */
\r
546 uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode.
\r
547 This parameter can be a value of @ref ETH_Transmit_Store_Forward */
\r
549 uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control.
\r
550 This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
\r
552 uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames.
\r
553 This parameter can be a value of @ref ETH_Forward_Error_Frames */
\r
555 uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
\r
556 and length less than 64 bytes) including pad-bytes and CRC)
\r
557 This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
\r
559 uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO.
\r
560 This parameter can be a value of @ref ETH_Receive_Threshold_Control */
\r
562 uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
\r
563 frame of Transmit data even before obtaining the status for the first frame.
\r
564 This parameter can be a value of @ref ETH_Second_Frame_Operate */
\r
566 uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats.
\r
567 This parameter can be a value of @ref ETH_Address_Aligned_Beats */
\r
569 uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.
\r
570 This parameter can be a value of @ref ETH_Fixed_Burst */
\r
572 uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
\r
573 This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
\r
575 uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
\r
576 This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
\r
578 uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format.
\r
579 This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */
\r
581 uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
\r
582 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
\r
584 uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.
\r
585 This parameter can be a value of @ref ETH_DMA_Arbitration */
\r
586 } ETH_DMAInitTypeDef;
\r
590 * @brief ETH DMA Descriptors data structure definition
\r
595 __IO uint32_t Status; /*!< Status */
\r
597 uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */
\r
599 uint32_t Buffer1Addr; /*!< Buffer1 address pointer */
\r
601 uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */
\r
603 /*!< Enhanced ETHERNET DMA PTP Descriptors */
\r
604 uint32_t ExtendedStatus; /*!< Extended status for PTP receive descriptor */
\r
606 uint32_t Reserved1; /*!< Reserved */
\r
608 uint32_t TimeStampLow; /*!< Time Stamp Low value for transmit and receive */
\r
610 uint32_t TimeStampHigh; /*!< Time Stamp High value for transmit and receive */
\r
612 } ETH_DMADescTypeDef;
\r
616 * @brief Received Frame Informations structure definition
\r
620 ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */
\r
622 ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */
\r
624 uint32_t SegCount; /*!< Segment count */
\r
626 uint32_t length; /*!< Frame length */
\r
628 uint32_t buffer; /*!< Frame buffer */
\r
630 } ETH_DMARxFrameInfos;
\r
634 * @brief ETH Handle Structure definition
\r
639 ETH_TypeDef *Instance; /*!< Register base address */
\r
641 ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */
\r
643 uint32_t LinkStatus; /*!< Ethernet link status */
\r
645 ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */
\r
647 ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */
\r
649 ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */
\r
651 __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */
\r
653 HAL_LockTypeDef Lock; /*!< ETH Lock */
\r
655 } ETH_HandleTypeDef;
\r
661 /* Exported constants --------------------------------------------------------*/
\r
662 /** @defgroup ETH_Exported_Constants ETH Exported Constants
\r
666 /** @defgroup ETH_Buffers_setting ETH Buffers setting
\r
669 #define ETH_MAX_PACKET_SIZE ((uint32_t)1524) /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */
\r
670 #define ETH_HEADER ((uint32_t)14) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
\r
671 #define ETH_CRC ((uint32_t)4) /*!< Ethernet CRC */
\r
672 #define ETH_EXTRA ((uint32_t)2) /*!< Extra bytes in some cases */
\r
673 #define ETH_VLAN_TAG ((uint32_t)4) /*!< optional 802.1q VLAN Tag */
\r
674 #define ETH_MIN_ETH_PAYLOAD ((uint32_t)46) /*!< Minimum Ethernet payload size */
\r
675 #define ETH_MAX_ETH_PAYLOAD ((uint32_t)1500) /*!< Maximum Ethernet payload size */
\r
676 #define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000) /*!< Jumbo frame payload size */
\r
678 /* Ethernet driver receive buffers are organized in a chained linked-list, when
\r
679 an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
\r
680 to the driver receive buffers memory.
\r
682 Depending on the size of the received ethernet packet and the size of
\r
683 each ethernet driver receive buffer, the received packet can take one or more
\r
684 ethernet driver receive buffer.
\r
686 In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
\r
687 and the total count of the driver receive buffers ETH_RXBUFNB.
\r
689 The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
\r
690 example, they can be reconfigured in the application layer to fit the application
\r
693 /* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
\r
695 #ifndef ETH_RX_BUF_SIZE
\r
696 #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
\r
699 /* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
\r
700 #ifndef ETH_RXBUFNB
\r
701 #define ETH_RXBUFNB ((uint32_t)5 /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
\r
705 /* Ethernet driver transmit buffers are organized in a chained linked-list, when
\r
706 an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
\r
707 driver transmit buffers memory to the TxFIFO.
\r
709 Depending on the size of the Ethernet packet to be transmitted and the size of
\r
710 each ethernet driver transmit buffer, the packet to be transmitted can take
\r
711 one or more ethernet driver transmit buffer.
\r
713 In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
\r
714 and the total count of the driver transmit buffers ETH_TXBUFNB.
\r
716 The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
\r
717 example, they can be reconfigured in the application layer to fit the application
\r
720 /* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
\r
722 #ifndef ETH_TX_BUF_SIZE
\r
723 #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
\r
726 /* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
\r
727 #ifndef ETH_TXBUFNB
\r
728 #define ETH_TXBUFNB ((uint32_t)5 /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
\r
735 /** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor
\r
741 -----------------------------------------------------------------------------------------------
\r
742 TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
\r
743 -----------------------------------------------------------------------------------------------
\r
744 TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
\r
745 -----------------------------------------------------------------------------------------------
\r
746 TDES2 | Buffer1 Address [31:0] |
\r
747 -----------------------------------------------------------------------------------------------
\r
748 TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
\r
749 -----------------------------------------------------------------------------------------------
\r
753 * @brief Bit definition of TDES0 register: DMA Tx descriptor status register
\r
755 #define ETH_DMATXDESC_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */
\r
756 #define ETH_DMATXDESC_IC ((uint32_t)0x40000000) /*!< Interrupt on Completion */
\r
757 #define ETH_DMATXDESC_LS ((uint32_t)0x20000000) /*!< Last Segment */
\r
758 #define ETH_DMATXDESC_FS ((uint32_t)0x10000000) /*!< First Segment */
\r
759 #define ETH_DMATXDESC_DC ((uint32_t)0x08000000) /*!< Disable CRC */
\r
760 #define ETH_DMATXDESC_DP ((uint32_t)0x04000000) /*!< Disable Padding */
\r
761 #define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000) /*!< Transmit Time Stamp Enable */
\r
762 #define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000) /*!< Checksum Insertion Control: 4 cases */
\r
763 #define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000) /*!< Do Nothing: Checksum Engine is bypassed */
\r
764 #define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000) /*!< IPV4 header Checksum Insertion */
\r
765 #define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
\r
766 #define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
\r
767 #define ETH_DMATXDESC_TER ((uint32_t)0x00200000) /*!< Transmit End of Ring */
\r
768 #define ETH_DMATXDESC_TCH ((uint32_t)0x00100000) /*!< Second Address Chained */
\r
769 #define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000) /*!< Tx Time Stamp Status */
\r
770 #define ETH_DMATXDESC_IHE ((uint32_t)0x00010000) /*!< IP Header Error */
\r
771 #define ETH_DMATXDESC_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
\r
772 #define ETH_DMATXDESC_JT ((uint32_t)0x00004000) /*!< Jabber Timeout */
\r
773 #define ETH_DMATXDESC_FF ((uint32_t)0x00002000) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
\r
774 #define ETH_DMATXDESC_PCE ((uint32_t)0x00001000) /*!< Payload Checksum Error */
\r
775 #define ETH_DMATXDESC_LCA ((uint32_t)0x00000800) /*!< Loss of Carrier: carrier lost during transmission */
\r
776 #define ETH_DMATXDESC_NC ((uint32_t)0x00000400) /*!< No Carrier: no carrier signal from the transceiver */
\r
777 #define ETH_DMATXDESC_LCO ((uint32_t)0x00000200) /*!< Late Collision: transmission aborted due to collision */
\r
778 #define ETH_DMATXDESC_EC ((uint32_t)0x00000100) /*!< Excessive Collision: transmission aborted after 16 collisions */
\r
779 #define ETH_DMATXDESC_VF ((uint32_t)0x00000080) /*!< VLAN Frame */
\r
780 #define ETH_DMATXDESC_CC ((uint32_t)0x00000078) /*!< Collision Count */
\r
781 #define ETH_DMATXDESC_ED ((uint32_t)0x00000004) /*!< Excessive Deferral */
\r
782 #define ETH_DMATXDESC_UF ((uint32_t)0x00000002) /*!< Underflow Error: late data arrival from the memory */
\r
783 #define ETH_DMATXDESC_DB ((uint32_t)0x00000001) /*!< Deferred Bit */
\r
786 * @brief Bit definition of TDES1 register
\r
788 #define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000) /*!< Transmit Buffer2 Size */
\r
789 #define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFF) /*!< Transmit Buffer1 Size */
\r
792 * @brief Bit definition of TDES2 register
\r
794 #define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */
\r
797 * @brief Bit definition of TDES3 register
\r
799 #define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */
\r
801 /*---------------------------------------------------------------------------------------------
\r
802 TDES6 | Transmit Time Stamp Low [31:0] |
\r
803 -----------------------------------------------------------------------------------------------
\r
804 TDES7 | Transmit Time Stamp High [31:0] |
\r
805 ----------------------------------------------------------------------------------------------*/
\r
807 /* Bit definition of TDES6 register */
\r
808 #define ETH_DMAPTPTXDESC_TTSL ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp Low */
\r
810 /* Bit definition of TDES7 register */
\r
811 #define ETH_DMAPTPTXDESC_TTSH ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp High */
\r
816 /** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor
\r
822 --------------------------------------------------------------------------------------------------------------------
\r
823 RDES0 | OWN(31) | Status [30:0] |
\r
824 ---------------------------------------------------------------------------------------------------------------------
\r
825 RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
\r
826 ---------------------------------------------------------------------------------------------------------------------
\r
827 RDES2 | Buffer1 Address [31:0] |
\r
828 ---------------------------------------------------------------------------------------------------------------------
\r
829 RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
\r
830 ---------------------------------------------------------------------------------------------------------------------
\r
834 * @brief Bit definition of RDES0 register: DMA Rx descriptor status register
\r
836 #define ETH_DMARXDESC_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */
\r
837 #define ETH_DMARXDESC_AFM ((uint32_t)0x40000000) /*!< DA Filter Fail for the rx frame */
\r
838 #define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000) /*!< Receive descriptor frame length */
\r
839 #define ETH_DMARXDESC_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
\r
840 #define ETH_DMARXDESC_DE ((uint32_t)0x00004000) /*!< Descriptor error: no more descriptors for receive frame */
\r
841 #define ETH_DMARXDESC_SAF ((uint32_t)0x00002000) /*!< SA Filter Fail for the received frame */
\r
842 #define ETH_DMARXDESC_LE ((uint32_t)0x00001000) /*!< Frame size not matching with length field */
\r
843 #define ETH_DMARXDESC_OE ((uint32_t)0x00000800) /*!< Overflow Error: Frame was damaged due to buffer overflow */
\r
844 #define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400) /*!< VLAN Tag: received frame is a VLAN frame */
\r
845 #define ETH_DMARXDESC_FS ((uint32_t)0x00000200) /*!< First descriptor of the frame */
\r
846 #define ETH_DMARXDESC_LS ((uint32_t)0x00000100) /*!< Last descriptor of the frame */
\r
847 #define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */
\r
848 #define ETH_DMARXDESC_LC ((uint32_t)0x00000040) /*!< Late collision occurred during reception */
\r
849 #define ETH_DMARXDESC_FT ((uint32_t)0x00000020) /*!< Frame type - Ethernet, otherwise 802.3 */
\r
850 #define ETH_DMARXDESC_RWT ((uint32_t)0x00000010) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */
\r
851 #define ETH_DMARXDESC_RE ((uint32_t)0x00000008) /*!< Receive error: error reported by MII interface */
\r
852 #define ETH_DMARXDESC_DBE ((uint32_t)0x00000004) /*!< Dribble bit error: frame contains non int multiple of 8 bits */
\r
853 #define ETH_DMARXDESC_CE ((uint32_t)0x00000002) /*!< CRC error */
\r
854 #define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
\r
857 * @brief Bit definition of RDES1 register
\r
859 #define ETH_DMARXDESC_DIC ((uint32_t)0x80000000) /*!< Disable Interrupt on Completion */
\r
860 #define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000) /*!< Receive Buffer2 Size */
\r
861 #define ETH_DMARXDESC_RER ((uint32_t)0x00008000) /*!< Receive End of Ring */
\r
862 #define ETH_DMARXDESC_RCH ((uint32_t)0x00004000) /*!< Second Address Chained */
\r
863 #define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFF) /*!< Receive Buffer1 Size */
\r
866 * @brief Bit definition of RDES2 register
\r
868 #define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */
\r
871 * @brief Bit definition of RDES3 register
\r
873 #define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */
\r
875 /*---------------------------------------------------------------------------------------------------------------------
\r
876 RDES4 | Reserved[31:15] | Extended Status [14:0] |
\r
877 ---------------------------------------------------------------------------------------------------------------------
\r
878 RDES5 | Reserved[31:0] |
\r
879 ---------------------------------------------------------------------------------------------------------------------
\r
880 RDES6 | Receive Time Stamp Low [31:0] |
\r
881 ---------------------------------------------------------------------------------------------------------------------
\r
882 RDES7 | Receive Time Stamp High [31:0] |
\r
883 --------------------------------------------------------------------------------------------------------------------*/
\r
885 /* Bit definition of RDES4 register */
\r
886 #define ETH_DMAPTPRXDESC_PTPV ((uint32_t)0x00002000) /* PTP Version */
\r
887 #define ETH_DMAPTPRXDESC_PTPFT ((uint32_t)0x00001000) /* PTP Frame Type */
\r
888 #define ETH_DMAPTPRXDESC_PTPMT ((uint32_t)0x00000F00) /* PTP Message Type */
\r
889 #define ETH_DMAPTPRXDESC_PTPMT_SYNC ((uint32_t)0x00000100) /* SYNC message (all clock types) */
\r
890 #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP ((uint32_t)0x00000200) /* FollowUp message (all clock types) */
\r
891 #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ ((uint32_t)0x00000300) /* DelayReq message (all clock types) */
\r
892 #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP ((uint32_t)0x00000400) /* DelayResp message (all clock types) */
\r
893 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE ((uint32_t)0x00000500) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
\r
894 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG ((uint32_t)0x00000600) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */
\r
895 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
\r
896 #define ETH_DMAPTPRXDESC_IPV6PR ((uint32_t)0x00000080) /* IPv6 Packet Received */
\r
897 #define ETH_DMAPTPRXDESC_IPV4PR ((uint32_t)0x00000040) /* IPv4 Packet Received */
\r
898 #define ETH_DMAPTPRXDESC_IPCB ((uint32_t)0x00000020) /* IP Checksum Bypassed */
\r
899 #define ETH_DMAPTPRXDESC_IPPE ((uint32_t)0x00000010) /* IP Payload Error */
\r
900 #define ETH_DMAPTPRXDESC_IPHE ((uint32_t)0x00000008) /* IP Header Error */
\r
901 #define ETH_DMAPTPRXDESC_IPPT ((uint32_t)0x00000007) /* IP Payload Type */
\r
902 #define ETH_DMAPTPRXDESC_IPPT_UDP ((uint32_t)0x00000001) /* UDP payload encapsulated in the IP datagram */
\r
903 #define ETH_DMAPTPRXDESC_IPPT_TCP ((uint32_t)0x00000002) /* TCP payload encapsulated in the IP datagram */
\r
904 #define ETH_DMAPTPRXDESC_IPPT_ICMP ((uint32_t)0x00000003) /* ICMP payload encapsulated in the IP datagram */
\r
906 /* Bit definition of RDES6 register */
\r
907 #define ETH_DMAPTPRXDESC_RTSL ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp Low */
\r
909 /* Bit definition of RDES7 register */
\r
910 #define ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp High */
\r
914 /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation
\r
917 #define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001)
\r
918 #define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000)
\r
923 /** @defgroup ETH_Speed ETH Speed
\r
926 #define ETH_SPEED_10M ((uint32_t)0x00000000)
\r
927 #define ETH_SPEED_100M ((uint32_t)0x00004000)
\r
932 /** @defgroup ETH_Duplex_Mode ETH Duplex Mode
\r
935 #define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800)
\r
936 #define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000)
\r
940 /** @defgroup ETH_Rx_Mode ETH Rx Mode
\r
943 #define ETH_RXPOLLING_MODE ((uint32_t)0x00000000)
\r
944 #define ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001)
\r
949 /** @defgroup ETH_Checksum_Mode ETH Checksum Mode
\r
952 #define ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000)
\r
953 #define ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001)
\r
958 /** @defgroup ETH_Media_Interface ETH Media Interface
\r
961 #define ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000)
\r
962 #define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)
\r
967 /** @defgroup ETH_Watchdog ETH Watchdog
\r
970 #define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000)
\r
971 #define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000)
\r
976 /** @defgroup ETH_Jabber ETH Jabber
\r
979 #define ETH_JABBER_ENABLE ((uint32_t)0x00000000)
\r
980 #define ETH_JABBER_DISABLE ((uint32_t)0x00400000)
\r
985 /** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap
\r
988 #define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000) /*!< minimum IFG between frames during transmission is 96Bit */
\r
989 #define ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000) /*!< minimum IFG between frames during transmission is 88Bit */
\r
990 #define ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000) /*!< minimum IFG between frames during transmission is 80Bit */
\r
991 #define ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000) /*!< minimum IFG between frames during transmission is 72Bit */
\r
992 #define ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000) /*!< minimum IFG between frames during transmission is 64Bit */
\r
993 #define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000) /*!< minimum IFG between frames during transmission is 56Bit */
\r
994 #define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000) /*!< minimum IFG between frames during transmission is 48Bit */
\r
995 #define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000) /*!< minimum IFG between frames during transmission is 40Bit */
\r
1000 /** @defgroup ETH_Carrier_Sense ETH Carrier Sense
\r
1003 #define ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000)
\r
1004 #define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000)
\r
1009 /** @defgroup ETH_Receive_Own ETH Receive Own
\r
1012 #define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000)
\r
1013 #define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000)
\r
1018 /** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode
\r
1021 #define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000)
\r
1022 #define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000)
\r
1027 /** @defgroup ETH_Checksum_Offload ETH Checksum Offload
\r
1030 #define ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400)
\r
1031 #define ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000)
\r
1036 /** @defgroup ETH_Retry_Transmission ETH Retry Transmission
\r
1039 #define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000)
\r
1040 #define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200)
\r
1045 /** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip
\r
1048 #define ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080)
\r
1049 #define ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000)
\r
1054 /** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
\r
1057 #define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000)
\r
1058 #define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020)
\r
1059 #define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040)
\r
1060 #define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060)
\r
1065 /** @defgroup ETH_Deferral_Check ETH Deferral Check
\r
1068 #define ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010)
\r
1069 #define ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000)
\r
1074 /** @defgroup ETH_Receive_All ETH Receive All
\r
1077 #define ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000)
\r
1078 #define ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000)
\r
1083 /** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter
\r
1086 #define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200)
\r
1087 #define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300)
\r
1088 #define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000)
\r
1093 /** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames
\r
1096 #define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040) /*!< MAC filters all control frames from reaching the application */
\r
1097 #define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080) /*!< MAC forwards all control frames to application even if they fail the Address Filter */
\r
1098 #define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0) /*!< MAC forwards control frames that pass the Address Filter. */
\r
1103 /** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception
\r
1106 #define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000)
\r
1107 #define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020)
\r
1112 /** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter
\r
1115 #define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000)
\r
1116 #define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008)
\r
1121 /** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode
\r
1124 #define ETH_PROMISCUOUS_MODE_ENABLE ((uint32_t)0x00000001)
\r
1125 #define ETH_PROMISCUOUS_MODE_DISABLE ((uint32_t)0x00000000)
\r
1130 /** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter
\r
1133 #define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404)
\r
1134 #define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004)
\r
1135 #define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
\r
1136 #define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010)
\r
1141 /** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter
\r
1144 #define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402)
\r
1145 #define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002)
\r
1146 #define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
\r
1151 /** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause
\r
1154 #define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000)
\r
1155 #define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080)
\r
1160 /** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
\r
1163 #define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000) /*!< Pause time minus 4 slot times */
\r
1164 #define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010) /*!< Pause time minus 28 slot times */
\r
1165 #define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020) /*!< Pause time minus 144 slot times */
\r
1166 #define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030) /*!< Pause time minus 256 slot times */
\r
1171 /** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect
\r
1174 #define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008)
\r
1175 #define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000)
\r
1180 /** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control
\r
1183 #define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004)
\r
1184 #define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
\r
1189 /** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control
\r
1192 #define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002)
\r
1193 #define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
\r
1198 /** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
\r
1201 #define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000)
\r
1202 #define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000)
\r
1207 /** @defgroup ETH_MAC_addresses ETH MAC addresses
\r
1210 #define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000)
\r
1211 #define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008)
\r
1212 #define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010)
\r
1213 #define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018)
\r
1218 /** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA
\r
1221 #define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000)
\r
1222 #define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008)
\r
1227 /** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes
\r
1230 #define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000) /*!< Mask MAC Address high reg bits [15:8] */
\r
1231 #define ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000) /*!< Mask MAC Address high reg bits [7:0] */
\r
1232 #define ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000) /*!< Mask MAC Address low reg bits [31:24] */
\r
1233 #define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000) /*!< Mask MAC Address low reg bits [23:16] */
\r
1234 #define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000) /*!< Mask MAC Address low reg bits [15:8] */
\r
1235 #define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000) /*!< Mask MAC Address low reg bits [70] */
\r
1240 /** @defgroup ETH_MAC_Debug_flags ETH MAC Debug flags
\r
1243 #define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
\r
1244 #define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
\r
1245 #define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
\r
1246 #define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
\r
1247 #define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
\r
1248 #define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
\r
1249 #define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
\r
1250 #define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
\r
1251 #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
\r
1252 #define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
\r
1253 #define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
\r
1254 #define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
\r
1255 #define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
\r
1256 #define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
\r
1257 #define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
\r
1258 #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
\r
1259 #define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
\r
1260 #define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000060) /* Rx FIFO read controller IDLE state */
\r
1261 #define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame data */
\r
1262 #define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame status (or time-stamp) */
\r
1263 #define ETH_MAC_READCONTROLLER_ FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
\r
1264 #define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
\r
1265 #define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
\r
1266 #define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
\r
1267 #define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
\r
1268 #define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
\r
1269 #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
\r
1274 /** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame
\r
1277 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000)
\r
1278 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000)
\r
1283 /** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward
\r
1286 #define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000)
\r
1287 #define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000)
\r
1292 /** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame
\r
1295 #define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000)
\r
1296 #define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000)
\r
1301 /** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward
\r
1304 #define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000)
\r
1305 #define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000)
\r
1310 /** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control
\r
1313 #define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
\r
1314 #define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
\r
1315 #define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
\r
1316 #define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000) /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */
\r
1317 #define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000) /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */
\r
1318 #define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
\r
1319 #define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
\r
1320 #define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
\r
1325 /** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames
\r
1328 #define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080)
\r
1329 #define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000)
\r
1334 /** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames
\r
1337 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040)
\r
1338 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000)
\r
1343 /** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control
\r
1346 #define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
\r
1347 #define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
\r
1348 #define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
\r
1349 #define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
\r
1354 /** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate
\r
1357 #define ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004)
\r
1358 #define ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000)
\r
1363 /** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats
\r
1366 #define ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000)
\r
1367 #define ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000)
\r
1372 /** @defgroup ETH_Fixed_Burst ETH Fixed Burst
\r
1375 #define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000)
\r
1376 #define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000)
\r
1381 /** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
\r
1384 #define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
\r
1385 #define ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
\r
1386 #define ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
\r
1387 #define ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
\r
1388 #define ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
\r
1389 #define ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
\r
1390 #define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
\r
1391 #define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
\r
1392 #define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
\r
1393 #define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
\r
1394 #define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
\r
1395 #define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
\r
1400 /** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
\r
1403 #define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
\r
1404 #define ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
\r
1405 #define ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
\r
1406 #define ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
\r
1407 #define ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
\r
1408 #define ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
\r
1409 #define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
\r
1410 #define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
\r
1411 #define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
\r
1412 #define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
\r
1413 #define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
\r
1414 #define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
\r
1419 /** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format
\r
1422 #define ETH_DMAENHANCEDDESCRIPTOR_ENABLE ((uint32_t)0x00000080)
\r
1423 #define ETH_DMAENHANCEDDESCRIPTOR_DISABLE ((uint32_t)0x00000000)
\r
1428 /** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
\r
1431 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000)
\r
1432 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000)
\r
1433 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000)
\r
1434 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000)
\r
1435 #define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002)
\r
1440 /** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment
\r
1443 #define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000) /*!< Last Segment */
\r
1444 #define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000) /*!< First Segment */
\r
1449 /** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control
\r
1452 #define ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000) /*!< Checksum engine bypass */
\r
1453 #define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000) /*!< IPv4 header checksum insertion */
\r
1454 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
\r
1455 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */
\r
1460 /** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers
\r
1463 #define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000) /*!< DMA Rx Desc Buffer1 */
\r
1464 #define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001) /*!< DMA Rx Desc Buffer2 */
\r
1469 /** @defgroup ETH_PMT_Flags ETH PMT Flags
\r
1472 #define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /*!< Wake-Up Frame Filter Register Pointer Reset */
\r
1473 #define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /*!< Wake-Up Frame Received */
\r
1474 #define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /*!< Magic Packet Received */
\r
1479 /** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts
\r
1482 #define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /*!< When Tx good frame counter reaches half the maximum value */
\r
1483 #define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /*!< When Tx good multi col counter reaches half the maximum value */
\r
1484 #define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /*!< When Tx good single col counter reaches half the maximum value */
\r
1489 /** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts
\r
1492 #define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /*!< When Rx good unicast frames counter reaches half the maximum value */
\r
1493 #define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /*!< When Rx alignment error counter reaches half the maximum value */
\r
1494 #define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /*!< When Rx crc error counter reaches half the maximum value */
\r
1499 /** @defgroup ETH_MAC_Flags ETH MAC Flags
\r
1502 #define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /*!< Time stamp trigger flag (on MAC) */
\r
1503 #define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /*!< MMC transmit flag */
\r
1504 #define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /*!< MMC receive flag */
\r
1505 #define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /*!< MMC flag (on MAC) */
\r
1506 #define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /*!< PMT flag (on MAC) */
\r
1511 /** @defgroup ETH_DMA_Flags ETH DMA Flags
\r
1514 #define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */
\r
1515 #define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */
\r
1516 #define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */
\r
1517 #define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000) /*!< Error bits 0-Rx DMA, 1-Tx DMA */
\r
1518 #define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000) /*!< Error bits 0-write transfer, 1-read transfer */
\r
1519 #define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000) /*!< Error bits 0-data buffer, 1-desc. access */
\r
1520 #define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary flag */
\r
1521 #define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary flag */
\r
1522 #define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /*!< Early receive flag */
\r
1523 #define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /*!< Fatal bus error flag */
\r
1524 #define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /*!< Early transmit flag */
\r
1525 #define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout flag */
\r
1526 #define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /*!< Receive process stopped flag */
\r
1527 #define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable flag */
\r
1528 #define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /*!< Receive flag */
\r
1529 #define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /*!< Underflow flag */
\r
1530 #define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /*!< Overflow flag */
\r
1531 #define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout flag */
\r
1532 #define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable flag */
\r
1533 #define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped flag */
\r
1534 #define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /*!< Transmit flag */
\r
1539 /** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
\r
1542 #define ETH_MAC_IT_TST ((uint32_t)0x00000200) /*!< Time stamp trigger interrupt (on MAC) */
\r
1543 #define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /*!< MMC transmit interrupt */
\r
1544 #define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /*!< MMC receive interrupt */
\r
1545 #define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /*!< MMC interrupt (on MAC) */
\r
1546 #define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /*!< PMT interrupt (on MAC) */
\r
1551 /** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
\r
1554 #define ETH_DMA_IT_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */
\r
1555 #define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */
\r
1556 #define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */
\r
1557 #define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary */
\r
1558 #define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary */
\r
1559 #define ETH_DMA_IT_ER ((uint32_t)0x00004000) /*!< Early receive interrupt */
\r
1560 #define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /*!< Fatal bus error interrupt */
\r
1561 #define ETH_DMA_IT_ET ((uint32_t)0x00000400) /*!< Early transmit interrupt */
\r
1562 #define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout interrupt */
\r
1563 #define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /*!< Receive process stopped interrupt */
\r
1564 #define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable interrupt */
\r
1565 #define ETH_DMA_IT_R ((uint32_t)0x00000040) /*!< Receive interrupt */
\r
1566 #define ETH_DMA_IT_TU ((uint32_t)0x00000020) /*!< Underflow interrupt */
\r
1567 #define ETH_DMA_IT_RO ((uint32_t)0x00000010) /*!< Overflow interrupt */
\r
1568 #define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout interrupt */
\r
1569 #define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable interrupt */
\r
1570 #define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped interrupt */
\r
1571 #define ETH_DMA_IT_T ((uint32_t)0x00000001) /*!< Transmit interrupt */
\r
1576 /** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state
\r
1579 #define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Tx Command issued */
\r
1580 #define ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000) /*!< Running - fetching the Tx descriptor */
\r
1581 #define ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000) /*!< Running - waiting for status */
\r
1582 #define ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000) /*!< Running - reading the data from host memory */
\r
1583 #define ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000) /*!< Suspended - Tx Descriptor unavailable */
\r
1584 #define ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000) /*!< Running - closing Rx descriptor */
\r
1591 /** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state
\r
1594 #define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Rx Command issued */
\r
1595 #define ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000) /*!< Running - fetching the Rx descriptor */
\r
1596 #define ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000) /*!< Running - waiting for packet */
\r
1597 #define ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000) /*!< Suspended - Rx Descriptor unavailable */
\r
1598 #define ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000) /*!< Running - closing descriptor */
\r
1599 #define ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000) /*!< Running - queuing the receive frame into host memory */
\r
1605 /** @defgroup ETH_DMA_overflow ETH DMA overflow
\r
1608 #define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000) /*!< Overflow bit for FIFO overflow counter */
\r
1609 #define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000) /*!< Overflow bit for missed frame counter */
\r
1614 /** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP
\r
1617 #define ETH_EXTI_LINE_WAKEUP ((uint32_t)0x00080000) /*!< External interrupt line 19 Connected to the ETH EXTI Line */
\r
1627 /* Exported macro ------------------------------------------------------------*/
\r
1628 /** @defgroup ETH_Exported_Macros ETH Exported Macros
\r
1629 * @brief macros to handle interrupts and specific clock configurations
\r
1633 /** @brief Reset ETH handle state
\r
1634 * @param __HANDLE__: specifies the ETH handle.
\r
1637 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
\r
1640 * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
\r
1641 * @param __HANDLE__: ETH Handle
\r
1642 * @param __FLAG__: specifies the flag of TDES0 to check.
\r
1643 * @retval the ETH_DMATxDescFlag (SET or RESET).
\r
1645 #define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
\r
1648 * @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
\r
1649 * @param __HANDLE__: ETH Handle
\r
1650 * @param __FLAG__: specifies the flag of RDES0 to check.
\r
1651 * @retval the ETH_DMATxDescFlag (SET or RESET).
\r
1653 #define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
\r
1656 * @brief Enables the specified DMA Rx Desc receive interrupt.
\r
1657 * @param __HANDLE__: ETH Handle
\r
1660 #define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
\r
1663 * @brief Disables the specified DMA Rx Desc receive interrupt.
\r
1664 * @param __HANDLE__: ETH Handle
\r
1667 #define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC)
\r
1670 * @brief Set the specified DMA Rx Desc Own bit.
\r
1671 * @param __HANDLE__: ETH Handle
\r
1674 #define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN)
\r
1677 * @brief Returns the specified ETHERNET DMA Tx Desc collision count.
\r
1678 * @param __HANDLE__: ETH Handle
\r
1679 * @retval The Transmit descriptor collision counter value.
\r
1681 #define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
\r
1684 * @brief Set the specified DMA Tx Desc Own bit.
\r
1685 * @param __HANDLE__: ETH Handle
\r
1688 #define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN)
\r
1691 * @brief Enables the specified DMA Tx Desc Transmit interrupt.
\r
1692 * @param __HANDLE__: ETH Handle
\r
1695 #define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)
\r
1698 * @brief Disables the specified DMA Tx Desc Transmit interrupt.
\r
1699 * @param __HANDLE__: ETH Handle
\r
1702 #define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
\r
1705 * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
\r
1706 * @param __HANDLE__: ETH Handle
\r
1707 * @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.
\r
1708 * This parameter can be one of the following values:
\r
1709 * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
\r
1710 * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
\r
1711 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
\r
1712 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
\r
1715 #define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__))
\r
1718 * @brief Enables the DMA Tx Desc CRC.
\r
1719 * @param __HANDLE__: ETH Handle
\r
1722 #define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
\r
1725 * @brief Disables the DMA Tx Desc CRC.
\r
1726 * @param __HANDLE__: ETH Handle
\r
1729 #define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)
\r
1732 * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
\r
1733 * @param __HANDLE__: ETH Handle
\r
1736 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
\r
1739 * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
\r
1740 * @param __HANDLE__: ETH Handle
\r
1743 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)
\r
1746 * @brief Enables the specified ETHERNET MAC interrupts.
\r
1747 * @param __HANDLE__ : ETH Handle
\r
1748 * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
\r
1749 * enabled or disabled.
\r
1750 * This parameter can be any combination of the following values:
\r
1751 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
\r
1752 * @arg ETH_MAC_IT_PMT : PMT interrupt
\r
1755 #define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__))
\r
1758 * @brief Disables the specified ETHERNET MAC interrupts.
\r
1759 * @param __HANDLE__ : ETH Handle
\r
1760 * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
\r
1761 * enabled or disabled.
\r
1762 * This parameter can be any combination of the following values:
\r
1763 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
\r
1764 * @arg ETH_MAC_IT_PMT : PMT interrupt
\r
1767 #define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
\r
1770 * @brief Initiate a Pause Control Frame (Full-duplex only).
\r
1771 * @param __HANDLE__: ETH Handle
\r
1774 #define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
\r
1777 * @brief Checks whether the ETHERNET flow control busy bit is set or not.
\r
1778 * @param __HANDLE__: ETH Handle
\r
1779 * @retval The new state of flow control busy status bit (SET or RESET).
\r
1781 #define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
\r
1784 * @brief Enables the MAC Back Pressure operation activation (Half-duplex only).
\r
1785 * @param __HANDLE__: ETH Handle
\r
1788 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
\r
1791 * @brief Disables the MAC BackPressure operation activation (Half-duplex only).
\r
1792 * @param __HANDLE__: ETH Handle
\r
1795 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
\r
1798 * @brief Checks whether the specified ETHERNET MAC flag is set or not.
\r
1799 * @param __HANDLE__: ETH Handle
\r
1800 * @param __FLAG__: specifies the flag to check.
\r
1801 * This parameter can be one of the following values:
\r
1802 * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
\r
1803 * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
\r
1804 * @arg ETH_MAC_FLAG_MMCR : MMC receive flag
\r
1805 * @arg ETH_MAC_FLAG_MMC : MMC flag
\r
1806 * @arg ETH_MAC_FLAG_PMT : PMT flag
\r
1807 * @retval The state of ETHERNET MAC flag.
\r
1809 #define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
\r
1812 * @brief Enables the specified ETHERNET DMA interrupts.
\r
1813 * @param __HANDLE__ : ETH Handle
\r
1814 * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
\r
1815 * enabled @ref ETH_DMA_Interrupts
\r
1818 #define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__))
\r
1821 * @brief Disables the specified ETHERNET DMA interrupts.
\r
1822 * @param __HANDLE__ : ETH Handle
\r
1823 * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
\r
1824 * disabled. @ref ETH_DMA_Interrupts
\r
1827 #define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
\r
1830 * @brief Clears the ETHERNET DMA IT pending bit.
\r
1831 * @param __HANDLE__ : ETH Handle
\r
1832 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
\r
1835 #define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
\r
1838 * @brief Checks whether the specified ETHERNET DMA flag is set or not.
\r
1839 * @param __HANDLE__: ETH Handle
\r
1840 * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags
\r
1841 * @retval The new state of ETH_DMA_FLAG (SET or RESET).
\r
1843 #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
\r
1846 * @brief Checks whether the specified ETHERNET DMA flag is set or not.
\r
1847 * @param __HANDLE__: ETH Handle
\r
1848 * @param __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags
\r
1849 * @retval The new state of ETH_DMA_FLAG (SET or RESET).
\r
1851 #define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))
\r
1854 * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not.
\r
1855 * @param __HANDLE__: ETH Handle
\r
1856 * @param __OVERFLOW__: specifies the DMA overflow flag to check.
\r
1857 * This parameter can be one of the following values:
\r
1858 * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
\r
1859 * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
\r
1860 * @retval The state of ETHERNET DMA overflow Flag (SET or RESET).
\r
1862 #define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
\r
1865 * @brief Set the DMA Receive status watchdog timer register value
\r
1866 * @param __HANDLE__: ETH Handle
\r
1867 * @param __VALUE__: DMA Receive status watchdog timer register value
\r
1870 #define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
\r
1873 * @brief Enables any unicast packet filtered by the MAC address
\r
1874 * recognition to be a wake-up frame.
\r
1875 * @param __HANDLE__: ETH Handle.
\r
1878 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU)
\r
1881 * @brief Disables any unicast packet filtered by the MAC address
\r
1882 * recognition to be a wake-up frame.
\r
1883 * @param __HANDLE__: ETH Handle.
\r
1886 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
\r
1889 * @brief Enables the MAC Wake-Up Frame Detection.
\r
1890 * @param __HANDLE__: ETH Handle.
\r
1893 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE)
\r
1896 * @brief Disables the MAC Wake-Up Frame Detection.
\r
1897 * @param __HANDLE__: ETH Handle.
\r
1900 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
\r
1903 * @brief Enables the MAC Magic Packet Detection.
\r
1904 * @param __HANDLE__: ETH Handle.
\r
1907 #define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE)
\r
1910 * @brief Disables the MAC Magic Packet Detection.
\r
1911 * @param __HANDLE__: ETH Handle.
\r
1914 #define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
\r
1917 * @brief Enables the MAC Power Down.
\r
1918 * @param __HANDLE__: ETH Handle
\r
1921 #define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD)
\r
1924 * @brief Disables the MAC Power Down.
\r
1925 * @param __HANDLE__: ETH Handle
\r
1928 #define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
\r
1931 * @brief Checks whether the specified ETHERNET PMT flag is set or not.
\r
1932 * @param __HANDLE__: ETH Handle.
\r
1933 * @param __FLAG__: specifies the flag to check.
\r
1934 * This parameter can be one of the following values:
\r
1935 * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
\r
1936 * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
\r
1937 * @arg ETH_PMT_FLAG_MPR : Magic Packet Received
\r
1938 * @retval The new state of ETHERNET PMT Flag (SET or RESET).
\r
1940 #define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
\r
1943 * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
\r
1944 * @param __HANDLE__: ETH Handle.
\r
1947 #define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP))
\r
1950 * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
\r
1951 * @param __HANDLE__: ETH Handle.
\r
1954 #define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
\r
1955 (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0)
\r
1958 * @brief Enables the MMC Counter Freeze.
\r
1959 * @param __HANDLE__: ETH Handle.
\r
1962 #define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF)
\r
1965 * @brief Disables the MMC Counter Freeze.
\r
1966 * @param __HANDLE__: ETH Handle.
\r
1969 #define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
\r
1972 * @brief Enables the MMC Reset On Read.
\r
1973 * @param __HANDLE__: ETH Handle.
\r
1976 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR)
\r
1979 * @brief Disables the MMC Reset On Read.
\r
1980 * @param __HANDLE__: ETH Handle.
\r
1983 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
\r
1986 * @brief Enables the MMC Counter Stop Rollover.
\r
1987 * @param __HANDLE__: ETH Handle.
\r
1990 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
\r
1993 * @brief Disables the MMC Counter Stop Rollover.
\r
1994 * @param __HANDLE__: ETH Handle.
\r
1997 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR)
\r
2000 * @brief Resets the MMC Counters.
\r
2001 * @param __HANDLE__: ETH Handle.
\r
2004 #define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR)
\r
2007 * @brief Enables the specified ETHERNET MMC Rx interrupts.
\r
2008 * @param __HANDLE__: ETH Handle.
\r
2009 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
\r
2010 * This parameter can be one of the following values:
\r
2011 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
\r
2012 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
\r
2013 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
\r
2016 #define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF)
\r
2018 * @brief Disables the specified ETHERNET MMC Rx interrupts.
\r
2019 * @param __HANDLE__: ETH Handle.
\r
2020 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
\r
2021 * This parameter can be one of the following values:
\r
2022 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
\r
2023 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
\r
2024 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
\r
2027 #define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFF)
\r
2029 * @brief Enables the specified ETHERNET MMC Tx interrupts.
\r
2030 * @param __HANDLE__: ETH Handle.
\r
2031 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
\r
2032 * This parameter can be one of the following values:
\r
2033 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
\r
2034 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
\r
2035 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
\r
2038 #define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
\r
2041 * @brief Disables the specified ETHERNET MMC Tx interrupts.
\r
2042 * @param __HANDLE__: ETH Handle.
\r
2043 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
\r
2044 * This parameter can be one of the following values:
\r
2045 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
\r
2046 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
\r
2047 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
\r
2050 #define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))
\r
2053 * @brief Enables the ETH External interrupt line.
\r
2056 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP)
\r
2059 * @brief Disables the ETH External interrupt line.
\r
2062 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
\r
2065 * @brief Enable event on ETH External event line.
\r
2068 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP)
\r
2071 * @brief Disable event on ETH External event line
\r
2074 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)
\r
2077 * @brief Get flag of the ETH External interrupt line.
\r
2080 #define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
\r
2083 * @brief Clear flag of the ETH External interrupt line.
\r
2086 #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
\r
2089 * @brief Enables rising edge trigger to the ETH External interrupt line.
\r
2092 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP
\r
2095 * @brief Disables the rising edge trigger to the ETH External interrupt line.
\r
2098 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
\r
2101 * @brief Enables falling edge trigger to the ETH External interrupt line.
\r
2104 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP)
\r
2107 * @brief Disables falling edge trigger to the ETH External interrupt line.
\r
2110 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
\r
2113 * @brief Enables rising/falling edge trigger to the ETH External interrupt line.
\r
2116 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\
\r
2117 EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP
\r
2120 * @brief Disables rising/falling edge trigger to the ETH External interrupt line.
\r
2123 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
\r
2124 EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
\r
2127 * @brief Generate a Software interrupt on selected EXTI line.
\r
2130 #define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP
\r
2135 /* Exported functions --------------------------------------------------------*/
\r
2137 /** @addtogroup ETH_Exported_Functions
\r
2141 /* Initialization and de-initialization functions ****************************/
\r
2143 /** @addtogroup ETH_Exported_Functions_Group1
\r
2146 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
\r
2147 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
\r
2148 void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
\r
2149 void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
\r
2150 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
\r
2151 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
\r
2156 /* IO operation functions ****************************************************/
\r
2158 /** @addtogroup ETH_Exported_Functions_Group2
\r
2161 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
\r
2162 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
\r
2163 /* Communication with PHY functions*/
\r
2164 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue);
\r
2165 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
\r
2166 /* Non-Blocking mode: Interrupt */
\r
2167 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
\r
2168 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
\r
2169 /* Callback in non blocking modes (Interrupt) */
\r
2170 void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
\r
2171 void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
\r
2172 void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
\r
2177 /* Peripheral Control functions **********************************************/
\r
2179 /** @addtogroup ETH_Exported_Functions_Group3
\r
2183 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
\r
2184 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
\r
2185 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf);
\r
2186 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf);
\r
2191 /* Peripheral State functions ************************************************/
\r
2193 /** @addtogroup ETH_Exported_Functions_Group4
\r
2196 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
\r
2212 #ifdef __cplusplus
\r
2216 #endif /* __STM32F7xx_HAL_ETH_H */
\r
2220 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
\r
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