2 ******************************************************************************
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3 * @file stm32f7xx_hal_rcc.h
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4 * @author MCD Application Team
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6 * @date 24-March-2015
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7 * @brief Header file of RCC HAL module.
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8 ******************************************************************************
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11 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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13 * Redistribution and use in source and binary forms, with or without modification,
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14 * are permitted provided that the following conditions are met:
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15 * 1. Redistributions of source code must retain the above copyright notice,
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16 * this list of conditions and the following disclaimer.
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17 * 2. Redistributions in binary form must reproduce the above copyright notice,
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18 * this list of conditions and the following disclaimer in the documentation
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19 * and/or other materials provided with the distribution.
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20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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21 * may be used to endorse or promote products derived from this software
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22 * without specific prior written permission.
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24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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35 ******************************************************************************
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38 /* Define to prevent recursive inclusion -------------------------------------*/
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39 #ifndef __STM32F7xx_HAL_RCC_H
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40 #define __STM32F7xx_HAL_RCC_H
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46 /* Includes ------------------------------------------------------------------*/
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47 #include "stm32f7xx_hal_def.h"
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49 /** @addtogroup STM32F7xx_HAL_Driver
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57 /* Exported types ------------------------------------------------------------*/
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59 /** @defgroup RCC_Exported_Types RCC Exported Types
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64 * @brief RCC PLL configuration structure definition
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68 uint32_t PLLState; /*!< The new state of the PLL.
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69 This parameter can be a value of @ref RCC_PLL_Config */
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71 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
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72 This parameter must be a value of @ref RCC_PLL_Clock_Source */
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74 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
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75 This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
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77 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
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78 This parameter must be a number between Min_Data = 192 and Max_Data = 432 */
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80 uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).
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81 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
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83 uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDMMC and RNG clocks.
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84 This parameter must be a number between Min_Data = 2 and Max_Data = 15 */
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86 }RCC_PLLInitTypeDef;
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89 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
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93 uint32_t OscillatorType; /*!< The oscillators to be configured.
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94 This parameter can be a value of @ref RCC_Oscillator_Type */
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96 uint32_t HSEState; /*!< The new state of the HSE.
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97 This parameter can be a value of @ref RCC_HSE_Config */
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99 uint32_t LSEState; /*!< The new state of the LSE.
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100 This parameter can be a value of @ref RCC_LSE_Config */
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102 uint32_t HSIState; /*!< The new state of the HSI.
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103 This parameter can be a value of @ref RCC_HSI_Config */
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105 uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
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106 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
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108 uint32_t LSIState; /*!< The new state of the LSI.
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109 This parameter can be a value of @ref RCC_LSI_Config */
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111 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
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113 }RCC_OscInitTypeDef;
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116 * @brief RCC System, AHB and APB busses clock configuration structure definition
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120 uint32_t ClockType; /*!< The clock to be configured.
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121 This parameter can be a value of @ref RCC_System_Clock_Type */
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123 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
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124 This parameter can be a value of @ref RCC_System_Clock_Source */
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126 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
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127 This parameter can be a value of @ref RCC_AHB_Clock_Source */
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129 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
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130 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
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132 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
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133 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
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135 }RCC_ClkInitTypeDef;
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141 /* Exported constants --------------------------------------------------------*/
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142 /** @defgroup RCC_Exported_Constants RCC Exported Constants
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146 /** @defgroup RCC_Oscillator_Type Oscillator Type
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149 #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
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150 #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
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151 #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
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152 #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
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153 #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
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158 /** @defgroup RCC_HSE_Config RCC HSE Config
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161 #define RCC_HSE_OFF ((uint32_t)0x00000000)
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162 #define RCC_HSE_ON RCC_CR_HSEON
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163 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
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168 /** @defgroup RCC_LSE_Config RCC LSE Config
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171 #define RCC_LSE_OFF ((uint32_t)0x00000000)
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172 #define RCC_LSE_ON RCC_BDCR_LSEON
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173 #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
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178 /** @defgroup RCC_HSI_Config RCC HSI Config
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181 #define RCC_HSI_OFF ((uint32_t)0x00000000)
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182 #define RCC_HSI_ON RCC_CR_HSION
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187 /** @defgroup RCC_LSI_Config RCC LSI Config
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190 #define RCC_LSI_OFF ((uint32_t)0x00000000)
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191 #define RCC_LSI_ON RCC_CSR_LSION
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196 /** @defgroup RCC_PLL_Config RCC PLL Config
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199 #define RCC_PLL_NONE ((uint32_t)0x00000000)
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200 #define RCC_PLL_OFF ((uint32_t)0x00000001)
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201 #define RCC_PLL_ON ((uint32_t)0x00000002)
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206 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
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209 #define RCC_PLLP_DIV2 ((uint32_t)0x00000002)
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210 #define RCC_PLLP_DIV4 ((uint32_t)0x00000004)
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211 #define RCC_PLLP_DIV6 ((uint32_t)0x00000006)
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212 #define RCC_PLLP_DIV8 ((uint32_t)0x00000008)
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217 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
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220 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
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221 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
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226 /** @defgroup RCC_System_Clock_Type RCC System Clock Type
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229 #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
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230 #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
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231 #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
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232 #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008)
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237 /** @defgroup RCC_System_Clock_Source RCC System Clock Source
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240 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
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241 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
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242 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
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248 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
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251 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
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252 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
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253 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
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258 /** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source
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261 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
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262 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
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263 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
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264 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
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265 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
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266 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
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267 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
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268 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
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269 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
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274 /** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1/APB2 Clock Source
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277 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
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278 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
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279 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
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280 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
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281 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
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286 /** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source
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289 #define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100)
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290 #define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200)
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291 #define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300)
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292 #define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300)
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293 #define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300)
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294 #define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300)
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295 #define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300)
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296 #define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300)
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297 #define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300)
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298 #define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300)
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299 #define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300)
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300 #define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300)
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301 #define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300)
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302 #define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300)
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303 #define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300)
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304 #define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300)
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305 #define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300)
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306 #define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300)
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307 #define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300)
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308 #define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300)
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309 #define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300)
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310 #define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300)
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311 #define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300)
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312 #define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300)
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313 #define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300)
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314 #define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300)
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315 #define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300)
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316 #define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300)
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317 #define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300)
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318 #define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300)
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319 #define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300)
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320 #define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300)
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327 /** @defgroup RCC_MCO_Index RCC MCO Index
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330 #define RCC_MCO1 ((uint32_t)0x00000000)
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331 #define RCC_MCO2 ((uint32_t)0x00000001)
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336 /** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source
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339 #define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000)
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340 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
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341 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
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342 #define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
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347 /** @defgroup RCC_MCO2_Clock_Source RCC MCO2 Clock Source
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350 #define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000)
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351 #define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
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352 #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
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353 #define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
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358 /** @defgroup RCC_MCOx_Clock_Prescaler RCC MCO1 Clock Prescaler
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361 #define RCC_MCODIV_1 ((uint32_t)0x00000000)
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362 #define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
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363 #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
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364 #define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
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365 #define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
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370 /** @defgroup RCC_Interrupt RCC Interrupt
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373 #define RCC_IT_LSIRDY ((uint8_t)0x01)
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374 #define RCC_IT_LSERDY ((uint8_t)0x02)
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375 #define RCC_IT_HSIRDY ((uint8_t)0x04)
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376 #define RCC_IT_HSERDY ((uint8_t)0x08)
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377 #define RCC_IT_PLLRDY ((uint8_t)0x10)
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378 #define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
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379 #define RCC_IT_PLLSAIRDY ((uint8_t)0x40)
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380 #define RCC_IT_CSS ((uint8_t)0x80)
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385 /** @defgroup RCC_Flag RCC Flags
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386 * Elements values convention: 0XXYYYYYb
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387 * - YYYYY : Flag position in the register
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388 * - 0XX : Register index
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389 * - 01: CR register
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390 * - 10: BDCR register
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391 * - 11: CSR register
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394 /* Flags in the CR register */
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395 #define RCC_FLAG_HSIRDY ((uint8_t)0x21)
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396 #define RCC_FLAG_HSERDY ((uint8_t)0x31)
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397 #define RCC_FLAG_PLLRDY ((uint8_t)0x39)
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398 #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
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399 #define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3C)
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401 /* Flags in the BDCR register */
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402 #define RCC_FLAG_LSERDY ((uint8_t)0x41)
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404 /* Flags in the CSR register */
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405 #define RCC_FLAG_LSIRDY ((uint8_t)0x61)
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406 #define RCC_FLAG_BORRST ((uint8_t)0x79)
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407 #define RCC_FLAG_PINRST ((uint8_t)0x7A)
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408 #define RCC_FLAG_PORRST ((uint8_t)0x7B)
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409 #define RCC_FLAG_SFTRST ((uint8_t)0x7C)
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410 #define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
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411 #define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
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412 #define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
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417 /** @defgroup RCC_LSEDrive_Configuration RCC LSE Drive configurations
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420 #define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000)
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421 #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1
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422 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0
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423 #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV
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432 /* Exported macro ------------------------------------------------------------*/
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433 /** @defgroup RCC_Exported_Macros RCC Exported Macros
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437 /** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
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438 * @brief Enable or disable the AHB1 peripheral clock.
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439 * @note After reset, the peripheral clock (used for registers read/write access)
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440 * is disabled and the application software has to enable this clock before
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444 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
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445 __IO uint32_t tmpreg; \
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446 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
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447 /* Delay after an RCC peripheral clock enabling */ \
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448 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
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452 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \
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453 __IO uint32_t tmpreg; \
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454 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
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455 /* Delay after an RCC peripheral clock enabling */ \
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456 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
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460 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
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461 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
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467 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
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468 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
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469 * @note After reset, the peripheral clock (used for registers read/write access)
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470 * is disabled and the application software has to enable this clock before
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474 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \
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475 __IO uint32_t tmpreg; \
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476 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
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477 /* Delay after an RCC peripheral clock enabling */ \
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478 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
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482 #define __HAL_RCC_PWR_CLK_ENABLE() do { \
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483 __IO uint32_t tmpreg; \
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484 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
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485 /* Delay after an RCC peripheral clock enabling */ \
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486 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
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490 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
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491 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
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496 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
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497 * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
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498 * @note After reset, the peripheral clock (used for registers read/write access)
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499 * is disabled and the application software has to enable this clock before
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503 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
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504 __IO uint32_t tmpreg; \
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505 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
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506 /* Delay after an RCC peripheral clock enabling */ \
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507 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
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511 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
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517 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
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518 * @brief Get the enable or disable status of the AHB1 peripheral clock.
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519 * @note After reset, the peripheral clock (used for registers read/write access)
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520 * is disabled and the application software has to enable this clock before
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524 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
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525 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) != RESET)
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527 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
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528 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) == RESET)
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533 /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
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534 * @brief Get the enable or disable status of the APB1 peripheral clock.
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535 * @note After reset, the peripheral clock (used for registers read/write access)
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536 * is disabled and the application software has to enable this clock before
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540 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR1 & (RCC_APB1ENR1_WWDGEN)) != RESET)
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541 #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR1 & (RCC_APB1ENR1_PWREN)) != RESET)
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543 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR1 & (RCC_APB1ENR1_WWDGEN)) == RESET)
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544 #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR1 & (RCC_APB1ENR1_PWREN)) == RESET)
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549 /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
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550 * @brief EGet the enable or disable status of the APB2 peripheral clock.
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551 * @note After reset, the peripheral clock (used for registers read/write access)
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552 * is disabled and the application software has to enable this clock before
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556 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
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557 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
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562 /** @defgroup RCC_Peripheral_Clock_Force_Release RCC Peripheral Clock Force Release
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563 * @brief Force or release AHB peripheral reset.
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566 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFF)
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567 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
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568 #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
\r
570 #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00)
\r
571 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
\r
572 #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
\r
577 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
\r
578 * @brief Force or release APB1 peripheral reset.
\r
581 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
\r
582 #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
\r
583 #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
\r
585 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
\r
586 #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
\r
587 #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
\r
592 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
\r
593 * @brief Force or release APB2 peripheral reset.
\r
596 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
\r
597 #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
\r
599 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
\r
600 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
\r
606 /** @defgroup RCC_Peripheral_Clock_Sleep_Enable_Disable RCC Peripheral Clock Sleep Enable Disable
\r
607 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
608 * power consumption.
\r
609 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
610 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
613 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
\r
614 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
\r
616 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
\r
617 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
\r
619 /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
\r
620 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
621 * power consumption.
\r
622 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
623 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
625 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
\r
626 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
\r
628 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
\r
629 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
\r
631 /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
\r
632 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
633 * power consumption.
\r
634 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
635 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
637 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
\r
638 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
\r
644 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enable Disable Status
\r
645 * @brief Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode.
\r
646 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
647 * power consumption.
\r
648 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
649 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
652 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1SMENR & (RCC_AHB1SMENR_CRCSMEN)) != RESET)
\r
653 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1SMENR & (RCC_AHB1SMENR_DMA1SMEN)) != RESET)
\r
655 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1SMENR & (RCC_AHB1SMENR_CRCSMEN)) == RESET)
\r
656 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1SMENR & (RCC_AHB1SMENR_DMA1SMEN)) == RESET)
\r
661 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enable Disable Status
\r
662 * @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.
\r
663 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
664 * power consumption.
\r
665 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
666 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
669 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() ((RCC->APB1SMENR1 & (RCC_APB1SMENR1_WWDGSMEN)) != RESET)
\r
670 #define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() ((RCC->APB1SMENR1 & (RCC_APB1SMENR1_PWRSMEN)) != RESET)
\r
672 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() ((RCC->APB1SMENR1 & (RCC_APB1SMENR1_WWDGSMEN)) == RESET)
\r
673 #define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() ((RCC->APB1SMENR1 & (RCC_APB1SMENR1_PWRSMEN)) == RESET)
\r
678 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enable Disable Status
\r
679 * @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.
\r
680 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
681 * power consumption.
\r
682 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
683 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
686 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB2SMENR & (RCC_APB2SMENR_SYSCFGSMEN)) != RESET)
\r
687 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB2SMENR & (RCC_APB2SMENR_SYSCFGSMEN)) == RESET)
\r
692 /** @defgroup RCC_HSI_Configuration HSI Configuration
\r
696 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
\r
697 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
\r
698 * It is used (enabled by hardware) as system clock source after startup
\r
699 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
\r
700 * of the HSE used directly or indirectly as system clock (if the Clock
\r
701 * Security System CSS is enabled).
\r
702 * @note HSI can not be stopped if it is used as system clock source. In this case,
\r
703 * you have to select another source of the system clock then stop the HSI.
\r
704 * @note After enabling the HSI, the application software should wait on HSIRDY
\r
705 * flag to be set indicating that HSI clock is stable and can be used as
\r
706 * system clock source.
\r
707 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
\r
710 #define __HAL_RCC_HSI_ENABLE() (RCC->CR |= (RCC_CR_HSION))
\r
711 #define __HAL_RCC_HSI_DISABLE() (RCC->CR &= ~(RCC_CR_HSION))
\r
713 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
\r
714 * @note The calibration is used to compensate for the variations in voltage
\r
715 * and temperature that influence the frequency of the internal HSI RC.
\r
716 * @param __HSICALIBRATIONVALUE__: specifies the calibration trimming value.
\r
717 * This parameter must be a number between 0 and 0x1F.
\r
719 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) (MODIFY_REG(RCC->CR,\
\r
720 RCC_CR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << POSITION_VAL(RCC_CR_HSITRIM)))
\r
725 /** @defgroup RCC_LSI_Configuration LSI Configuration
\r
729 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
\r
730 * @note After enabling the LSI, the application software should wait on
\r
731 * LSIRDY flag to be set indicating that LSI clock is stable and can
\r
732 * be used to clock the IWDG and/or the RTC.
\r
733 * @note LSI can not be disabled if the IWDG is running.
\r
734 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
\r
737 #define __HAL_RCC_LSI_ENABLE() (RCC->CSR |= (RCC_CSR_LSION))
\r
738 #define __HAL_RCC_LSI_DISABLE() (RCC->CSR &= ~(RCC_CSR_LSION))
\r
743 /** @defgroup RCC_HSE_Configuration HSE Configuration
\r
747 * @brief Macro to configure the External High Speed oscillator (__HSE__).
\r
748 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
\r
749 * software should wait on HSERDY flag to be set indicating that HSE clock
\r
750 * is stable and can be used to clock the PLL and/or system clock.
\r
751 * @note HSE state can not be changed if it is used directly or through the
\r
752 * PLL as system clock. In this case, you have to select another source
\r
753 * of the system clock then change the HSE state (ex. disable it).
\r
754 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
\r
755 * @note This function reset the CSSON bit, so if the clock security system(CSS)
\r
756 * was previously enabled you have to enable it again after calling this
\r
758 * @param __STATE__: specifies the new state of the HSE.
\r
759 * This parameter can be one of the following values:
\r
760 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
\r
761 * 6 HSE oscillator clock cycles.
\r
762 * @arg RCC_HSE_ON: turn ON the HSE oscillator.
\r
763 * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
\r
765 #define __HAL_RCC_HSE_CONFIG(__STATE__) \
\r
767 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
\r
768 if((__STATE__) == RCC_HSE_ON) \
\r
770 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
\r
771 SET_BIT(RCC->CR, RCC_CR_HSEON); \
\r
773 else if((__STATE__) == RCC_HSE_BYPASS) \
\r
775 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
\r
776 SET_BIT(RCC->CR, RCC_CR_HSEON); \
\r
780 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
\r
781 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
\r
788 /** @defgroup RCC_LSE_Configuration LSE Configuration
\r
793 * @brief Macro to configure the External Low Speed oscillator (LSE).
\r
794 * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
\r
795 * User should request a transition to LSE Off first and then LSE On or LSE Bypass.
\r
796 * @note As the LSE is in the Backup domain and write access is denied to
\r
797 * this domain after reset, you have to enable write access using
\r
798 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
\r
799 * (to be done once after reset).
\r
800 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
\r
801 * software should wait on LSERDY flag to be set indicating that LSE clock
\r
802 * is stable and can be used to clock the RTC.
\r
803 * @param __STATE__: specifies the new state of the LSE.
\r
804 * This parameter can be one of the following values:
\r
805 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
\r
806 * 6 LSE oscillator clock cycles.
\r
807 * @arg RCC_LSE_ON: turn ON the LSE oscillator.
\r
808 * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
\r
810 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
\r
812 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
\r
813 if((__STATE__) == RCC_LSE_ON) \
\r
815 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
\r
816 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
\r
818 else if((__STATE__) == RCC_LSE_BYPASS) \
\r
820 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
\r
821 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
\r
825 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
\r
826 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
\r
833 /** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration
\r
837 /** @brief Macros to enable or disable the RTC clock.
\r
838 * @note These macros must be used only after the RTC clock source was selected.
\r
840 #define __HAL_RCC_RTC_ENABLE() (RCC->BDCR |= (RCC_BDCR_RTCEN))
\r
841 #define __HAL_RCC_RTC_DISABLE() (RCC->BDCR &= ~(RCC_BDCR_RTCEN))
\r
843 /** @brief Macros to configure the RTC clock (RTCCLK).
\r
844 * @note As the RTC clock configuration bits are in the Backup domain and write
\r
845 * access is denied to this domain after reset, you have to enable write
\r
846 * access using the Power Backup Access macro before to configure
\r
847 * the RTC clock source (to be done once after reset).
\r
848 * @note Once the RTC clock is configured it can't be changed unless the
\r
849 * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
\r
850 * a Power On Reset (POR).
\r
851 * @param __RTCCLKSource__: specifies the RTC clock source.
\r
852 * This parameter can be one of the following values:
\r
853 * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
\r
854 * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
\r
855 * @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
\r
856 * as RTC clock, where x:[2,31]
\r
857 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
\r
858 * work in STOP and STANDBY modes, and can be used as wakeup source.
\r
859 * However, when the HSE clock is used as RTC clock source, the RTC
\r
860 * cannot be used in STOP and STANDBY modes.
\r
861 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
\r
862 * RTC clock source).
\r
864 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
\r
865 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
\r
867 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
\r
868 RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFF); \
\r
871 /** @brief Macros to force or release the Backup domain reset.
\r
872 * @note This function resets the RTC peripheral (including the backup registers)
\r
873 * and the RTC clock source selection in RCC_CSR register.
\r
874 * @note The BKPSRAM is not affected by this reset.
\r
876 #define __HAL_RCC_BACKUPRESET_FORCE() (RCC->BDCR |= (RCC_BDCR_BDRST))
\r
877 #define __HAL_RCC_BACKUPRESET_RELEASE() (RCC->BDCR &= ~(RCC_BDCR_BDRST))
\r
882 /** @defgroup RCC_PLL_Configuration PLL Configuration
\r
886 /** @brief Macros to enable or disable the main PLL.
\r
887 * @note After enabling the main PLL, the application software should wait on
\r
888 * PLLRDY flag to be set indicating that PLL clock is stable and can
\r
889 * be used as system clock source.
\r
890 * @note The main PLL can not be disabled if it is used as system clock source
\r
891 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
\r
893 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
\r
894 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
\r
897 /** @brief Macro to configure the main PLL clock source, multiplication and division factors.
\r
898 * @note This function must be used only when the main PLL is disabled.
\r
899 * @param __RCC_PLLSource__: specifies the PLL entry clock source.
\r
900 * This parameter can be one of the following values:
\r
901 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
\r
902 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
\r
903 * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
\r
904 * @param __PLLM__: specifies the division factor for PLL VCO input clock
\r
905 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
\r
906 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
\r
907 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
\r
908 * of 2 MHz to limit PLL jitter.
\r
909 * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
\r
910 * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
\r
911 * @note You have to set the PLLN parameter correctly to ensure that the VCO
\r
912 * output frequency is between 192 and 432 MHz.
\r
913 * @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
\r
914 * This parameter must be a number in the range {2, 4, 6, or 8}.
\r
915 * @note You have to set the PLLP parameter correctly to not exceed 200 MHz on
\r
916 * the System clock frequency.
\r
917 * @param __PLLQ__: specifies the division factor for OTG FS, SDMMC and RNG clocks
\r
918 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
\r
919 * @note If the USB OTG FS is used in your application, you have to set the
\r
920 * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
\r
921 * the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work
\r
924 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__)\
\r
925 (RCC->PLLCFGR = (0x20000000 | (__PLLM__) | ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
\r
926 ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | (__RCC_PLLSource__) | \
\r
927 ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
\r
932 /** @defgroup RCC_PLL_I2S_Configuration PLL I2S Configuration
\r
936 /** @brief Macro to configure the I2S clock source (I2SCLK).
\r
937 * @note This function must be called before enabling the I2S APB clock.
\r
938 * @param __SOURCE__: specifies the I2S clock source.
\r
939 * This parameter can be one of the following values:
\r
940 * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
\r
941 * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
\r
942 * used as I2S clock source.
\r
944 #define __HAL_RCC_I2S_CONFIG(__SOURCE__) do {RCC->CFGR &= ~(RCC_CFGR_I2SSRC); \
\r
945 RCC->CFGR |= (__SOURCE__); \
\r
948 /** @brief Macros to enable or disable the PLLI2S.
\r
949 * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
\r
951 #define __HAL_RCC_PLLI2S_ENABLE() (RCC->CR |= (RCC_CR_PLLI2SON))
\r
952 #define __HAL_RCC_PLLI2S_DISABLE() (RCC->CR &= ~(RCC_CR_PLLI2SON))
\r
957 /** @defgroup RCC_Get_Clock_source Get Clock source
\r
961 * @brief Macro to configure the system clock source.
\r
962 * @param __RCC_SYSCLKSOURCE__: specifies the system clock source.
\r
963 * This parameter can be one of the following values:
\r
964 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
\r
965 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
\r
966 * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
\r
968 #define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
\r
970 /** @brief Macro to get the clock source used as system clock.
\r
971 * @retval The clock source used as system clock. The returned value can be one
\r
972 * of the following:
\r
973 * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
\r
974 * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
\r
975 * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
\r
977 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
\r
980 * @brief Macro to configures the External Low Speed oscillator (LSE) drive capability.
\r
981 * @note As the LSE is in the Backup domain and write access is denied to
\r
982 * this domain after reset, you have to enable write access using
\r
983 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
\r
984 * (to be done once after reset).
\r
985 * @param __RCC_LSEDRIVE__: specifies the new state of the LSE drive capability.
\r
986 * This parameter can be one of the following values:
\r
987 * @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability.
\r
988 * @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.
\r
989 * @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability.
\r
990 * @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability.
\r
993 #define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) \
\r
994 (MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) ))
\r
996 /** @brief Macro to get the oscillator used as PLL clock source.
\r
997 * @retval The oscillator used as PLL clock source. The returned value can be one
\r
998 * of the following:
\r
999 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
\r
1000 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
\r
1002 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
\r
1007 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
\r
1008 * @brief macros to manage the specified RCC Flags and interrupts.
\r
1012 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
\r
1013 * the selected interrupts).
\r
1014 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
\r
1015 * This parameter can be any combination of the following values:
\r
1016 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
\r
1017 * @arg RCC_IT_LSERDY: LSE ready interrupt.
\r
1018 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
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1019 * @arg RCC_IT_HSERDY: HSE ready interrupt.
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1020 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
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1021 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
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1023 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
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1025 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
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1026 * the selected interrupts).
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1027 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
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1028 * This parameter can be any combination of the following values:
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1029 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
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1030 * @arg RCC_IT_LSERDY: LSE ready interrupt.
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1031 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
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1032 * @arg RCC_IT_HSERDY: HSE ready interrupt.
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1033 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
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1034 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
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1036 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
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1038 /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
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1039 * bits to clear the selected interrupt pending bits.
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1040 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
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1041 * This parameter can be any combination of the following values:
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1042 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
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1043 * @arg RCC_IT_LSERDY: LSE ready interrupt.
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1044 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
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1045 * @arg RCC_IT_HSERDY: HSE ready interrupt.
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1046 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
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1047 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
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1048 * @arg RCC_IT_CSS: Clock Security System interrupt
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1050 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
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1052 /** @brief Check the RCC's interrupt has occurred or not.
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1053 * @param __INTERRUPT__: specifies the RCC interrupt source to check.
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1054 * This parameter can be one of the following values:
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1055 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
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1056 * @arg RCC_IT_LSERDY: LSE ready interrupt.
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1057 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
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1058 * @arg RCC_IT_HSERDY: HSE ready interrupt.
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1059 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
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1060 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
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1061 * @arg RCC_IT_CSS: Clock Security System interrupt
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1062 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
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1064 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
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1066 /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
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1067 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
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1069 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
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1071 /** @brief Check RCC flag is set or not.
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1072 * @param __FLAG__: specifies the flag to check.
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1073 * This parameter can be one of the following values:
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1074 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
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1075 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
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1076 * @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
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1077 * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
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1078 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
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1079 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
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1080 * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
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1081 * @arg RCC_FLAG_PINRST: Pin reset.
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1082 * @arg RCC_FLAG_PORRST: POR/PDR reset.
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1083 * @arg RCC_FLAG_SFTRST: Software reset.
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1084 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
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1085 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
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1086 * @arg RCC_FLAG_LPWRRST: Low Power reset.
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1087 * @retval The new state of __FLAG__ (TRUE or FALSE).
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1089 #define RCC_FLAG_MASK ((uint8_t)0x1F)
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1090 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)
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1100 /* Include RCC HAL Extension module */
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1101 #include "stm32f7xx_hal_rcc_ex.h"
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1103 /* Exported functions --------------------------------------------------------*/
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1104 /** @addtogroup RCC_Exported_Functions
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1108 /** @addtogroup RCC_Exported_Functions_Group1
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1111 /* Initialization and de-initialization functions ******************************/
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1112 void HAL_RCC_DeInit(void);
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1113 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
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1114 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
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1119 /** @addtogroup RCC_Exported_Functions_Group2
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1122 /* Peripheral Control functions ************************************************/
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1123 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
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1124 void HAL_RCC_EnableCSS(void);
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1125 void HAL_RCC_DisableCSS(void);
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1126 uint32_t HAL_RCC_GetSysClockFreq(void);
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1127 uint32_t HAL_RCC_GetHCLKFreq(void);
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1128 uint32_t HAL_RCC_GetPCLK1Freq(void);
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1129 uint32_t HAL_RCC_GetPCLK2Freq(void);
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1130 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
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1131 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
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1133 /* CSS NMI IRQ handler */
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1134 void HAL_RCC_NMI_IRQHandler(void);
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1136 /* User Callbacks in non blocking mode (IT mode) */
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1137 void HAL_RCC_CSSCallback(void);
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1146 /* Private types -------------------------------------------------------------*/
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1147 /* Private variables ---------------------------------------------------------*/
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1148 /* Private constants ---------------------------------------------------------*/
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1149 /** @defgroup RCC_Private_Constants RCC Private Constants
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1152 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
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1153 #define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
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1154 #define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
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1155 #define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
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1156 #define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
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1158 /** @defgroup RCC_BitAddress_Alias RCC BitAddress Alias
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1159 * @brief RCC registers bit address alias
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1162 /* CIR register byte 2 (Bits[15:8]) base address */
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1163 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))
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1165 /* CIR register byte 3 (Bits[23:16]) base address */
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1166 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
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1168 #define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100)
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1169 #define RCC_LSE_TIMEOUT_VALUE ((uint32_t)5000)
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1177 /* Private macros ------------------------------------------------------------*/
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1178 /** @addtogroup RCC_Private_Macros RCC Private Macros
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1182 /** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
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1185 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15)
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1187 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
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1188 ((HSE) == RCC_HSE_BYPASS))
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1190 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
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1191 ((LSE) == RCC_LSE_BYPASS))
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1193 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
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1195 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
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1197 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
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1199 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
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1200 ((SOURCE) == RCC_PLLSOURCE_HSE))
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1202 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
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1203 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
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1204 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
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1205 #define IS_RCC_PLLM_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 63))
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1207 #define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
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1209 #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == RCC_PLLP_DIV2) || ((VALUE) == RCC_PLLP_DIV4) || \
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1210 ((VALUE) == RCC_PLLP_DIV6) || ((VALUE) == RCC_PLLP_DIV8))
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1211 #define IS_RCC_PLLQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
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1213 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \
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1214 ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \
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1215 ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \
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1216 ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
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1217 ((HCLK) == RCC_SYSCLK_DIV512))
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1219 #define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15))
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1221 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
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1222 ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
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1223 ((PCLK) == RCC_HCLK_DIV16))
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1225 #define IS_RCC_MCO(MCOX) (((MCOX) == RCC_MCO1) || ((MCOX) == RCC_MCO2))
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1228 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
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1229 ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
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1231 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \
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1232 ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
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1234 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
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1235 ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
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1236 ((DIV) == RCC_MCODIV_5))
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1237 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
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1239 #define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE) || ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \
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1240 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3) || \
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1241 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5) || \
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1242 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7) || \
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1243 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9) || \
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1244 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \
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1245 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \
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1246 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \
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1247 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \
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1248 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \
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1249 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \
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1250 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \
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1251 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \
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1252 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \
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1253 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \
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1254 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31))
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1257 #define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDRIVE_LOW) || \
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1258 ((DRIVE) == RCC_LSEDRIVE_MEDIUMLOW) || \
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1259 ((DRIVE) == RCC_LSEDRIVE_MEDIUMHIGH) || \
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1260 ((DRIVE) == RCC_LSEDRIVE_HIGH))
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1277 #ifdef __cplusplus
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1281 #endif /* __STM32F7xx_HAL_RCC_H */
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1283 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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