2 ******************************************************************************
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3 * @file stm32f7xx_hal_rcc_ex.h
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4 * @author MCD Application Team
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6 * @date 24-March-2015
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7 * @brief Header file of RCC HAL Extension module.
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8 ******************************************************************************
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11 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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13 * Redistribution and use in source and binary forms, with or without modification,
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14 * are permitted provided that the following conditions are met:
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15 * 1. Redistributions of source code must retain the above copyright notice,
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16 * this list of conditions and the following disclaimer.
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17 * 2. Redistributions in binary form must reproduce the above copyright notice,
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18 * this list of conditions and the following disclaimer in the documentation
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19 * and/or other materials provided with the distribution.
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20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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21 * may be used to endorse or promote products derived from this software
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22 * without specific prior written permission.
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24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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35 ******************************************************************************
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38 /* Define to prevent recursive inclusion -------------------------------------*/
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39 #ifndef __STM32F7xx_HAL_RCC_EX_H
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40 #define __STM32F7xx_HAL_RCC_EX_H
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46 /* Includes ------------------------------------------------------------------*/
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47 #include "stm32f7xx_hal_def.h"
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49 /** @addtogroup STM32F7xx_HAL_Driver
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53 /** @addtogroup RCCEx
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57 /* Exported types ------------------------------------------------------------*/
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58 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
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63 * @brief PLLI2S Clock structure definition
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67 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
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68 This parameter must be a number between Min_Data = 49 and Max_Data = 432.
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69 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
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71 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
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72 This parameter must be a number between Min_Data = 2 and Max_Data = 7.
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73 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
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75 uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock.
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76 This parameter must be a number between Min_Data = 2 and Max_Data = 15.
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77 This parameter will be used only when PLLI2S is selected as Clock Source SAI */
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79 uint32_t PLLI2SP; /*!< Specifies the division factor for SPDIF-RX clock.
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80 This parameter must be a number between Min_Data = 2 and Max_Data = 8.
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81 This parameter will be used only when PLLI2S is selected as Clock Source SAI */
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82 }RCC_PLLI2SInitTypeDef;
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85 * @brief PLLSAI Clock structure definition
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89 uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
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90 This parameter must be a number between Min_Data = 49 and Max_Data = 432.
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91 This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
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93 uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.
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94 This parameter must be a number between Min_Data = 2 and Max_Data = 15.
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95 This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
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97 uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock
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98 This parameter must be a number between Min_Data = 2 and Max_Data = 7.
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99 This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
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101 uint32_t PLLSAIP; /*!< Specifies the division factor for 48MHz clock.
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102 This parameter must be a number between Min_Data = 2 and Max_Data = 8.
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103 This parameter will be used only when PLLSAI is disabled */
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104 }RCC_PLLSAIInitTypeDef;
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107 * @brief RCC extended clocks structure definition
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111 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
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112 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
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114 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
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115 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
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117 RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
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118 This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
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120 uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
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121 This parameter must be a number between Min_Data = 1 and Max_Data = 32
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122 This parameter will be used only when PLLI2S is selected as Clock Source SAI */
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124 uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
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125 This parameter must be a number between Min_Data = 1 and Max_Data = 32
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126 This parameter will be used only when PLLSAI is selected as Clock Source SAI */
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128 uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock.
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129 This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
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131 uint32_t RTCClockSelection; /*!< Specifies RTC Clock source Selection.
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132 This parameter can be a value of @ref RCC_RTC_Clock_Source */
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134 uint32_t I2sClockSelection; /*!< Specifies I2S Clock source Selection.
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135 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
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137 uint32_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
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138 This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */
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140 uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Prescalers Selection
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141 This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
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143 uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Prescalers Selection
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144 This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
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146 uint32_t Usart1ClockSelection; /*!< USART1 clock source
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147 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
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149 uint32_t Usart2ClockSelection; /*!< USART2 clock source
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150 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
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152 uint32_t Usart3ClockSelection; /*!< USART3 clock source
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153 This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
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155 uint32_t Uart4ClockSelection; /*!< UART4 clock source
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156 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
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158 uint32_t Uart5ClockSelection; /*!< UART5 clock source
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159 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
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161 uint32_t Usart6ClockSelection; /*!< USART6 clock source
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162 This parameter can be a value of @ref RCCEx_USART6_Clock_Source */
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164 uint32_t Uart7ClockSelection; /*!< UART7 clock source
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165 This parameter can be a value of @ref RCCEx_UART7_Clock_Source */
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167 uint32_t Uart8ClockSelection; /*!< UART8 clock source
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168 This parameter can be a value of @ref RCCEx_UART8_Clock_Source */
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170 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
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171 This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
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173 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
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174 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
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176 uint32_t I2c3ClockSelection; /*!< I2C3 clock source
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177 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
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179 uint32_t I2c4ClockSelection; /*!< I2C4 clock source
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180 This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */
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182 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source
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183 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
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185 uint32_t CecClockSelection; /*!< CEC clock source
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186 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
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188 uint32_t Clk48ClockSelection; /*!< Specifies 48Mhz clock source used by USB OTG FS, RNG and SDMMC
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189 This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
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191 uint32_t Sdmmc1ClockSelection; /*!< SDMMC1 clock source
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192 This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */
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194 }RCC_PeriphCLKInitTypeDef;
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199 /* Exported constants --------------------------------------------------------*/
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200 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
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204 /** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
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207 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
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208 #define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008)
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209 #define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010)
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210 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
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211 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000040)
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212 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000080)
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213 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000100)
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214 #define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000200)
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215 #define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000400)
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216 #define RCC_PERIPHCLK_USART6 ((uint32_t)0x00000800)
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217 #define RCC_PERIPHCLK_UART7 ((uint32_t)0x00001000)
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218 #define RCC_PERIPHCLK_UART8 ((uint32_t)0x00002000)
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219 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00004000)
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220 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00008000)
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221 #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00010000)
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222 #define RCC_PERIPHCLK_I2C4 ((uint32_t)0x00020000)
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223 #define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00040000)
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224 #define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00080000)
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225 #define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00100000)
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226 #define RCC_PERIPHCLK_CLK48 ((uint32_t)0x00200000)
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227 #define RCC_PERIPHCLK_CEC ((uint32_t)0x00400000)
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228 #define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00800000)
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229 #define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x01000000)
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236 /** @defgroup RCCEx_PLLSAIP_Clock_Divider RCCEx PLLSAIP Clock Divider
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239 #define RCC_PLLSAIP_DIV2 ((uint32_t)0x00000000)
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240 #define RCC_PLLSAIP_DIV4 ((uint32_t)0x00000001)
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241 #define RCC_PLLSAIP_DIV6 ((uint32_t)0x00000002)
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242 #define RCC_PLLSAIP_DIV8 ((uint32_t)0x00000003)
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247 /** @defgroup RCCEx_PLLSAI_DIVR RCCEx PLLSAI DIVR
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250 #define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000)
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251 #define RCC_PLLSAIDIVR_4 RCC_DCKCFGR1_PLLSAIDIVR_0
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252 #define RCC_PLLSAIDIVR_8 RCC_DCKCFGR1_PLLSAIDIVR_1
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253 #define RCC_PLLSAIDIVR_16 RCC_DCKCFGR1_PLLSAIDIVR
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258 /** @defgroup RCCEx_I2S_Clock_Source RCCEx I2S Clock Source
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261 #define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000)
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262 #define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC
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269 /** @defgroup RCCEx_SAI1_Clock_Source RCCEx SAI1 Clock Source
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272 #define RCC_SAI1CLKSOURCE_PLLSAI ((uint32_t)0x00000000)
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273 #define RCC_SAI1CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI1SEL_0
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274 #define RCC_SAI1CLKSOURCE_PIN RCC_DCKCFGR1_SAI1SEL_1
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280 /** @defgroup RCCEx_SAI2_Clock_Source RCCEx SAI2 Clock Source
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283 #define RCC_SAI2CLKSOURCE_PLLSAI ((uint32_t)0x00000000)
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284 #define RCC_SAI2CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI2SEL_0
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285 #define RCC_SAI2CLKSOURCE_PIN RCC_DCKCFGR1_SAI2SEL_1
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290 /** @defgroup RCCEx_SDMMC1_Clock_Source RCCEx SDMMC1 Clock Source
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293 #define RCC_SDMMC1CLKSOURCE_CLK48 ((uint32_t)0x00000000)
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294 #define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC1SEL
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299 /** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source
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302 #define RCC_CECCLKSOURCE_LSE ((uint32_t)0x00000000)
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303 #define RCC_CECCLKSOURCE_HSI RCC_DCKCFGR2_CECSEL /* CEC clock is HSI/488*/
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308 /** @defgroup RCCEx_USART1_Clock_Source RCCEx USART1 Clock Source
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311 #define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000)
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312 #define RCC_USART1CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART1SEL_0
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313 #define RCC_USART1CLKSOURCE_HSI RCC_DCKCFGR2_USART1SEL_1
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314 #define RCC_USART1CLKSOURCE_LSE RCC_DCKCFGR2_USART1SEL
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319 /** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source
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322 #define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
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323 #define RCC_USART2CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART2SEL_0
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324 #define RCC_USART2CLKSOURCE_HSI RCC_DCKCFGR2_USART2SEL_1
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325 #define RCC_USART2CLKSOURCE_LSE RCC_DCKCFGR2_USART2SEL
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330 /** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source
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333 #define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
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334 #define RCC_USART3CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART3SEL_0
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335 #define RCC_USART3CLKSOURCE_HSI RCC_DCKCFGR2_USART3SEL_1
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336 #define RCC_USART3CLKSOURCE_LSE RCC_DCKCFGR2_USART3SEL
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341 /** @defgroup RCCEx_UART4_Clock_Source RCCEx UART4 Clock Source
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344 #define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
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345 #define RCC_UART4CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART4SEL_0
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346 #define RCC_UART4CLKSOURCE_HSI RCC_DCKCFGR2_UART4SEL_1
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347 #define RCC_UART4CLKSOURCE_LSE RCC_DCKCFGR2_UART4SEL
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352 /** @defgroup RCCEx_UART5_Clock_Source RCCEx UART5 Clock Source
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355 #define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
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356 #define RCC_UART5CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART5SEL_0
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357 #define RCC_UART5CLKSOURCE_HSI RCC_DCKCFGR2_UART5SEL_1
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358 #define RCC_UART5CLKSOURCE_LSE RCC_DCKCFGR2_UART5SEL
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363 /** @defgroup RCCEx_USART6_Clock_Source RCCEx USART6 Clock Source
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366 #define RCC_USART6CLKSOURCE_PCLK2 ((uint32_t)0x00000000)
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367 #define RCC_USART6CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART6SEL_0
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368 #define RCC_USART6CLKSOURCE_HSI RCC_DCKCFGR2_USART6SEL_1
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369 #define RCC_USART6CLKSOURCE_LSE RCC_DCKCFGR2_USART6SEL
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374 /** @defgroup RCCEx_UART7_Clock_Source RCCEx UART7 Clock Source
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377 #define RCC_UART7CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
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378 #define RCC_UART7CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART7SEL_0
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379 #define RCC_UART7CLKSOURCE_HSI RCC_DCKCFGR2_UART7SEL_1
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380 #define RCC_UART7CLKSOURCE_LSE RCC_DCKCFGR2_UART7SEL
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385 /** @defgroup RCCEx_UART8_Clock_Source RCCEx UART8 Clock Source
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388 #define RCC_UART8CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
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389 #define RCC_UART8CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART8SEL_0
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390 #define RCC_UART8CLKSOURCE_HSI RCC_DCKCFGR2_UART8SEL_1
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391 #define RCC_UART8CLKSOURCE_LSE RCC_DCKCFGR2_UART8SEL
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396 /** @defgroup RCCEx_I2C1_Clock_Source RCCEx I2C1 Clock Source
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399 #define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
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400 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C1SEL_0
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401 #define RCC_I2C1CLKSOURCE_HSI RCC_DCKCFGR2_I2C1SEL_1
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406 /** @defgroup RCCEx_I2C2_Clock_Source RCCEx I2C2 Clock Source
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409 #define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
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410 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C2SEL_0
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411 #define RCC_I2C2CLKSOURCE_HSI RCC_DCKCFGR2_I2C2SEL_1
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417 /** @defgroup RCCEx_I2C3_Clock_Source RCCEx I2C3 Clock Source
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420 #define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
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421 #define RCC_I2C3CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C3SEL_0
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422 #define RCC_I2C3CLKSOURCE_HSI RCC_DCKCFGR2_I2C3SEL_1
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427 /** @defgroup RCCEx_I2C4_Clock_Source RCCEx I2C4 Clock Source
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430 #define RCC_I2C4CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
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431 #define RCC_I2C4CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C4SEL_0
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432 #define RCC_I2C4CLKSOURCE_HSI RCC_DCKCFGR2_I2C4SEL_1
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438 /** @defgroup RCCEx_LPTIM1_Clock_Source RCCEx LPTIM1 Clock Source
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441 #define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000)
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442 #define RCC_LPTIM1CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_0
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443 #define RCC_LPTIM1CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_1
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444 #define RCC_LPTIM1CLKSOURCE_LSE RCC_DCKCFGR2_LPTIM1SEL
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450 /** @defgroup RCCEx_CLK48_Clock_Source RCCEx CLK48 Clock Source
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453 #define RCC_CLK48SOURCE_PLL ((uint32_t)0x00000000)
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454 #define RCC_CLK48SOURCE_PLLSAIP RCC_DCKCFGR2_CK48MSEL
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459 /** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection
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462 #define RCC_TIMPRES_DESACTIVATED ((uint32_t)0x00000000)
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463 #define RCC_TIMPRES_ACTIVATED RCC_DCKCFGR1_TIMPRE
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474 /* Exported macro ------------------------------------------------------------*/
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475 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
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478 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable
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479 * @brief Enables or disables the AHB/APB peripheral clock.
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480 * @note After reset, the peripheral clock (used for registers read/write access)
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481 * is disabled and the application software has to enable this clock before
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486 /** @brief Enables or disables the AHB1 peripheral clock.
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487 * @note After reset, the peripheral clock (used for registers read/write access)
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488 * is disabled and the application software has to enable this clock before
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491 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
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492 __IO uint32_t tmpreg; \
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493 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
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494 /* Delay after an RCC peripheral clock enabling */ \
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495 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
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499 #define __HAL_RCC_DTCMRAMEN_CLK_ENABLE() do { \
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500 __IO uint32_t tmpreg; \
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501 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\
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502 /* Delay after an RCC peripheral clock enabling */ \
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503 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\
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507 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \
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508 __IO uint32_t tmpreg; \
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509 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
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510 /* Delay after an RCC peripheral clock enabling */ \
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511 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
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515 #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \
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516 __IO uint32_t tmpreg; \
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517 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
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518 /* Delay after an RCC peripheral clock enabling */ \
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519 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
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523 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
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524 __IO uint32_t tmpreg; \
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525 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
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526 /* Delay after an RCC peripheral clock enabling */ \
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527 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
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531 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
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532 __IO uint32_t tmpreg; \
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533 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
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534 /* Delay after an RCC peripheral clock enabling */ \
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535 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
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539 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
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540 __IO uint32_t tmpreg; \
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541 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
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542 /* Delay after an RCC peripheral clock enabling */ \
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543 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
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547 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
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548 __IO uint32_t tmpreg; \
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549 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
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550 /* Delay after an RCC peripheral clock enabling */ \
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551 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
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555 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
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556 __IO uint32_t tmpreg; \
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557 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
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558 /* Delay after an RCC peripheral clock enabling */ \
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559 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
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563 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
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564 __IO uint32_t tmpreg; \
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565 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
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566 /* Delay after an RCC peripheral clock enabling */ \
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567 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
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571 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
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572 __IO uint32_t tmpreg; \
\r
573 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
\r
574 /* Delay after an RCC peripheral clock enabling */ \
\r
575 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
\r
579 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
\r
580 __IO uint32_t tmpreg; \
\r
581 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
\r
582 /* Delay after an RCC peripheral clock enabling */ \
\r
583 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
\r
587 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
\r
588 __IO uint32_t tmpreg; \
\r
589 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
\r
590 /* Delay after an RCC peripheral clock enabling */ \
\r
591 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
\r
595 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
\r
596 __IO uint32_t tmpreg; \
\r
597 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
\r
598 /* Delay after an RCC peripheral clock enabling */ \
\r
599 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
\r
603 #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
\r
604 __IO uint32_t tmpreg; \
\r
605 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
\r
606 /* Delay after an RCC peripheral clock enabling */ \
\r
607 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
\r
611 #define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \
\r
612 __IO uint32_t tmpreg; \
\r
613 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
\r
614 /* Delay after an RCC peripheral clock enabling */ \
\r
615 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
\r
619 #define __HAL_RCC_GPIOK_CLK_ENABLE() do { \
\r
620 __IO uint32_t tmpreg; \
\r
621 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
\r
622 /* Delay after an RCC peripheral clock enabling */ \
\r
623 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
\r
627 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
\r
628 #define __HAL_RCC_DTCMRAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DTCMRAMEN))
\r
629 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
\r
630 #define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
\r
631 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
\r
632 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
\r
633 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
\r
634 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
\r
635 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
\r
636 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
\r
637 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
\r
638 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
\r
639 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
\r
640 #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
\r
641 #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
\r
642 #define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
\r
643 #define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
\r
645 * @brief Enable ETHERNET clock.
\r
647 #define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
\r
648 __IO uint32_t tmpreg; \
\r
649 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
\r
650 /* Delay after an RCC peripheral clock enabling */ \
\r
651 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
\r
655 #define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
\r
656 __IO uint32_t tmpreg; \
\r
657 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
\r
658 /* Delay after an RCC peripheral clock enabling */ \
\r
659 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
\r
663 #define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
\r
664 __IO uint32_t tmpreg; \
\r
665 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
\r
666 /* Delay after an RCC peripheral clock enabling */ \
\r
667 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
\r
671 #define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
\r
672 __IO uint32_t tmpreg; \
\r
673 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
\r
674 /* Delay after an RCC peripheral clock enabling */ \
\r
675 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
\r
679 #define __HAL_RCC_ETH_CLK_ENABLE() do { \
\r
680 __HAL_RCC_ETHMAC_CLK_ENABLE(); \
\r
681 __HAL_RCC_ETHMACTX_CLK_ENABLE(); \
\r
682 __HAL_RCC_ETHMACRX_CLK_ENABLE(); \
\r
685 * @brief Disable ETHERNET clock.
\r
687 #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
\r
688 #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
\r
689 #define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
\r
690 #define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
\r
691 #define __HAL_RCC_ETH_CLK_DISABLE() do { \
\r
692 __HAL_RCC_ETHMACTX_CLK_DISABLE(); \
\r
693 __HAL_RCC_ETHMACRX_CLK_DISABLE(); \
\r
694 __HAL_RCC_ETHMAC_CLK_DISABLE(); \
\r
697 /** @brief Enable or disable the AHB2 peripheral clock.
\r
698 * @note After reset, the peripheral clock (used for registers read/write access)
\r
699 * is disabled and the application software has to enable this clock before
\r
702 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \
\r
703 __IO uint32_t tmpreg; \
\r
704 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
\r
705 /* Delay after an RCC peripheral clock enabling */ \
\r
706 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
\r
710 #define __HAL_RCC_RNG_CLK_ENABLE() do { \
\r
711 __IO uint32_t tmpreg; \
\r
712 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
\r
713 /* Delay after an RCC peripheral clock enabling */ \
\r
714 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
\r
718 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \
\r
719 __IO uint32_t tmpreg; \
\r
720 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\
\r
721 /* Delay after an RCC peripheral clock enabling */ \
\r
722 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\
\r
724 __HAL_RCC_SYSCFG_CLK_ENABLE();\
\r
727 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
\r
728 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
\r
730 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() do { (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN));\
\r
731 __HAL_RCC_SYSCFG_CLK_DISABLE();\
\r
733 #if defined(STM32F756xx)
\r
734 #define __HAL_RCC_CRYP_CLK_ENABLE() do { \
\r
735 __IO uint32_t tmpreg; \
\r
736 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
\r
737 /* Delay after an RCC peripheral clock enabling */ \
\r
738 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
\r
742 #define __HAL_RCC_HASH_CLK_ENABLE() do { \
\r
743 __IO uint32_t tmpreg; \
\r
744 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
\r
745 /* Delay after an RCC peripheral clock enabling */ \
\r
746 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
\r
750 #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
\r
751 #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
\r
752 #endif /* STM32F756x */
\r
753 /** @brief Enables or disables the AHB3 peripheral clock.
\r
754 * @note After reset, the peripheral clock (used for registers read/write access)
\r
755 * is disabled and the application software has to enable this clock before
\r
758 #define __HAL_RCC_FMC_CLK_ENABLE() do { \
\r
759 __IO uint32_t tmpreg; \
\r
760 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
\r
761 /* Delay after an RCC peripheral clock enabling */ \
\r
762 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
\r
766 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \
\r
767 __IO uint32_t tmpreg; \
\r
768 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
\r
769 /* Delay after an RCC peripheral clock enabling */ \
\r
770 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
\r
774 #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
\r
775 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
\r
777 /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
\r
778 * @note After reset, the peripheral clock (used for registers read/write access)
\r
779 * is disabled and the application software has to enable this clock before
\r
782 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \
\r
783 __IO uint32_t tmpreg; \
\r
784 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
\r
785 /* Delay after an RCC peripheral clock enabling */ \
\r
786 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
\r
790 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
\r
791 __IO uint32_t tmpreg; \
\r
792 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
\r
793 /* Delay after an RCC peripheral clock enabling */ \
\r
794 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
\r
798 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \
\r
799 __IO uint32_t tmpreg; \
\r
800 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
\r
801 /* Delay after an RCC peripheral clock enabling */ \
\r
802 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
\r
806 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \
\r
807 __IO uint32_t tmpreg; \
\r
808 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
\r
809 /* Delay after an RCC peripheral clock enabling */ \
\r
810 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
\r
814 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \
\r
815 __IO uint32_t tmpreg; \
\r
816 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
\r
817 /* Delay after an RCC peripheral clock enabling */ \
\r
818 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
\r
822 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \
\r
823 __IO uint32_t tmpreg; \
\r
824 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
\r
825 /* Delay after an RCC peripheral clock enabling */ \
\r
826 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
\r
830 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \
\r
831 __IO uint32_t tmpreg; \
\r
832 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
\r
833 /* Delay after an RCC peripheral clock enabling */ \
\r
834 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
\r
838 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \
\r
839 __IO uint32_t tmpreg; \
\r
840 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
\r
841 /* Delay after an RCC peripheral clock enabling */ \
\r
842 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
\r
846 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \
\r
847 __IO uint32_t tmpreg; \
\r
848 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
\r
849 /* Delay after an RCC peripheral clock enabling */ \
\r
850 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
\r
854 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
\r
855 __IO uint32_t tmpreg; \
\r
856 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
\r
857 /* Delay after an RCC peripheral clock enabling */ \
\r
858 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
\r
862 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \
\r
863 __IO uint32_t tmpreg; \
\r
864 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
\r
865 /* Delay after an RCC peripheral clock enabling */ \
\r
866 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
\r
870 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
\r
871 __IO uint32_t tmpreg; \
\r
872 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
\r
873 /* Delay after an RCC peripheral clock enabling */ \
\r
874 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
\r
878 #define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \
\r
879 __IO uint32_t tmpreg; \
\r
880 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
\r
881 /* Delay after an RCC peripheral clock enabling */ \
\r
882 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
\r
886 #define __HAL_RCC_USART2_CLK_ENABLE() do { \
\r
887 __IO uint32_t tmpreg; \
\r
888 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
\r
889 /* Delay after an RCC peripheral clock enabling */ \
\r
890 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
\r
894 #define __HAL_RCC_USART3_CLK_ENABLE() do { \
\r
895 __IO uint32_t tmpreg; \
\r
896 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
\r
897 /* Delay after an RCC peripheral clock enabling */ \
\r
898 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
\r
902 #define __HAL_RCC_UART4_CLK_ENABLE() do { \
\r
903 __IO uint32_t tmpreg; \
\r
904 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
\r
905 /* Delay after an RCC peripheral clock enabling */ \
\r
906 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
\r
910 #define __HAL_RCC_UART5_CLK_ENABLE() do { \
\r
911 __IO uint32_t tmpreg; \
\r
912 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
\r
913 /* Delay after an RCC peripheral clock enabling */ \
\r
914 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
\r
918 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \
\r
919 __IO uint32_t tmpreg; \
\r
920 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
\r
921 /* Delay after an RCC peripheral clock enabling */ \
\r
922 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
\r
926 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \
\r
927 __IO uint32_t tmpreg; \
\r
928 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
\r
929 /* Delay after an RCC peripheral clock enabling */ \
\r
930 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
\r
934 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \
\r
935 __IO uint32_t tmpreg; \
\r
936 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
\r
937 /* Delay after an RCC peripheral clock enabling */ \
\r
938 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
\r
942 #define __HAL_RCC_I2C4_CLK_ENABLE() do { \
\r
943 __IO uint32_t tmpreg; \
\r
944 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\
\r
945 /* Delay after an RCC peripheral clock enabling */ \
\r
946 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\
\r
950 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \
\r
951 __IO uint32_t tmpreg; \
\r
952 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
\r
953 /* Delay after an RCC peripheral clock enabling */ \
\r
954 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
\r
958 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \
\r
959 __IO uint32_t tmpreg; \
\r
960 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
\r
961 /* Delay after an RCC peripheral clock enabling */ \
\r
962 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
\r
966 #define __HAL_RCC_CEC_CLK_ENABLE() do { \
\r
967 __IO uint32_t tmpreg; \
\r
968 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
\r
969 /* Delay after an RCC peripheral clock enabling */ \
\r
970 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
\r
974 #define __HAL_RCC_DAC_CLK_ENABLE() do { \
\r
975 __IO uint32_t tmpreg; \
\r
976 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
\r
977 /* Delay after an RCC peripheral clock enabling */ \
\r
978 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
\r
982 #define __HAL_RCC_UART7_CLK_ENABLE() do { \
\r
983 __IO uint32_t tmpreg; \
\r
984 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
\r
985 /* Delay after an RCC peripheral clock enabling */ \
\r
986 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
\r
990 #define __HAL_RCC_UART8_CLK_ENABLE() do { \
\r
991 __IO uint32_t tmpreg; \
\r
992 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
\r
993 /* Delay after an RCC peripheral clock enabling */ \
\r
994 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
\r
998 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
\r
999 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
\r
1000 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
\r
1001 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
\r
1002 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
\r
1003 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
\r
1004 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
\r
1005 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
\r
1006 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
\r
1007 #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
\r
1008 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
\r
1009 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
\r
1010 #define __HAL_RCC_SPDIFRX_CLK_DISABLE()(RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))
\r
1011 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
\r
1012 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
\r
1013 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
\r
1014 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
\r
1015 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
\r
1016 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
\r
1017 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
\r
1018 #define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C4EN))
\r
1019 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
\r
1020 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
\r
1021 #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
\r
1022 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
\r
1023 #define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
\r
1024 #define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
\r
1026 /** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
\r
1027 * @note After reset, the peripheral clock (used for registers read/write access)
\r
1028 * is disabled and the application software has to enable this clock before
\r
1031 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \
\r
1032 __IO uint32_t tmpreg; \
\r
1033 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
\r
1034 /* Delay after an RCC peripheral clock enabling */ \
\r
1035 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
\r
1039 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \
\r
1040 __IO uint32_t tmpreg; \
\r
1041 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
\r
1042 /* Delay after an RCC peripheral clock enabling */ \
\r
1043 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
\r
1047 #define __HAL_RCC_USART1_CLK_ENABLE() do { \
\r
1048 __IO uint32_t tmpreg; \
\r
1049 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
\r
1050 /* Delay after an RCC peripheral clock enabling */ \
\r
1051 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
\r
1055 #define __HAL_RCC_USART6_CLK_ENABLE() do { \
\r
1056 __IO uint32_t tmpreg; \
\r
1057 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
\r
1058 /* Delay after an RCC peripheral clock enabling */ \
\r
1059 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
\r
1063 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \
\r
1064 __IO uint32_t tmpreg; \
\r
1065 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
\r
1066 /* Delay after an RCC peripheral clock enabling */ \
\r
1067 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
\r
1071 #define __HAL_RCC_ADC2_CLK_ENABLE() do { \
\r
1072 __IO uint32_t tmpreg; \
\r
1073 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
\r
1074 /* Delay after an RCC peripheral clock enabling */ \
\r
1075 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
\r
1079 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \
\r
1080 __IO uint32_t tmpreg; \
\r
1081 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
\r
1082 /* Delay after an RCC peripheral clock enabling */ \
\r
1083 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
\r
1087 #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \
\r
1088 __IO uint32_t tmpreg; \
\r
1089 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\
\r
1090 /* Delay after an RCC peripheral clock enabling */ \
\r
1091 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\
\r
1095 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \
\r
1096 __IO uint32_t tmpreg; \
\r
1097 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
\r
1098 /* Delay after an RCC peripheral clock enabling */ \
\r
1099 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
\r
1103 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \
\r
1104 __IO uint32_t tmpreg; \
\r
1105 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
\r
1106 /* Delay after an RCC peripheral clock enabling */ \
\r
1107 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
\r
1111 #define __HAL_RCC_TIM9_CLK_ENABLE() do { \
\r
1112 __IO uint32_t tmpreg; \
\r
1113 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
\r
1114 /* Delay after an RCC peripheral clock enabling */ \
\r
1115 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
\r
1119 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \
\r
1120 __IO uint32_t tmpreg; \
\r
1121 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
\r
1122 /* Delay after an RCC peripheral clock enabling */ \
\r
1123 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
\r
1127 #define __HAL_RCC_TIM11_CLK_ENABLE() do { \
\r
1128 __IO uint32_t tmpreg; \
\r
1129 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
\r
1130 /* Delay after an RCC peripheral clock enabling */ \
\r
1131 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
\r
1135 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \
\r
1136 __IO uint32_t tmpreg; \
\r
1137 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
\r
1138 /* Delay after an RCC peripheral clock enabling */ \
\r
1139 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
\r
1143 #define __HAL_RCC_SPI6_CLK_ENABLE() do { \
\r
1144 __IO uint32_t tmpreg; \
\r
1145 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
\r
1146 /* Delay after an RCC peripheral clock enabling */ \
\r
1147 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
\r
1151 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \
\r
1152 __IO uint32_t tmpreg; \
\r
1153 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
\r
1154 /* Delay after an RCC peripheral clock enabling */ \
\r
1155 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
\r
1159 #define __HAL_RCC_SAI2_CLK_ENABLE() do { \
\r
1160 __IO uint32_t tmpreg; \
\r
1161 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
\r
1162 /* Delay after an RCC peripheral clock enabling */ \
\r
1163 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
\r
1167 #define __HAL_RCC_LTDC_CLK_ENABLE() do { \
\r
1168 __IO uint32_t tmpreg; \
\r
1169 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
\r
1170 /* Delay after an RCC peripheral clock enabling */ \
\r
1171 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
\r
1175 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
\r
1176 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
\r
1177 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
\r
1178 #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
\r
1179 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
\r
1180 #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
\r
1181 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
\r
1182 #define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC1EN))
\r
1183 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
\r
1184 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
\r
1185 #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
\r
1186 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
\r
1187 #define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
\r
1188 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
\r
1189 #define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
\r
1190 #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
\r
1191 #define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))
\r
1192 #define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
\r
1199 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status
\r
1200 * @brief Get the enable or disable status of the AHB/APB peripheral clock.
\r
1201 * @note After reset, the peripheral clock (used for registers read/write access)
\r
1202 * is disabled and the application software has to enable this clock before
\r
1207 /** @brief Get the enable or disable status of the AHB1 peripheral clock.
\r
1208 * @note After reset, the peripheral clock (used for registers read/write access)
\r
1209 * is disabled and the application software has to enable this clock before
\r
1212 #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
\r
1213 #define __HAL_RCC_DTCMRAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) != RESET)
\r
1214 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) != RESET)
\r
1215 #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET)
\r
1216 #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
\r
1217 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
\r
1218 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) != RESET)
\r
1219 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) != RESET)
\r
1220 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) != RESET)
\r
1221 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
\r
1222 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
\r
1223 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
\r
1224 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
\r
1225 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) != RESET)
\r
1226 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
\r
1227 #define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET)
\r
1228 #define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET)
\r
1230 #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
\r
1231 #define __HAL_RCC_DTCMRAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) == RESET)
\r
1232 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) == RESET)
\r
1233 #define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET)
\r
1234 #define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
\r
1235 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
\r
1236 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) == RESET)
\r
1237 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) == RESET)
\r
1238 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) == RESET)
\r
1239 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
\r
1240 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
\r
1241 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
\r
1242 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
\r
1243 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) == RESET)
\r
1244 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
\r
1245 #define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET)
\r
1246 #define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET)
\r
1248 * @brief Enable ETHERNET clock.
\r
1250 #define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)
\r
1251 #define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
\r
1252 #define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
\r
1253 #define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
\r
1254 #define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \
\r
1255 __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
\r
1256 __HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
\r
1259 * @brief Disable ETHERNET clock.
\r
1261 #define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)
\r
1262 #define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
\r
1263 #define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
\r
1264 #define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
\r
1265 #define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \
\r
1266 __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
\r
1267 __HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
\r
1269 /** @brief Get the enable or disable status of the AHB2 peripheral clock.
\r
1270 * @note After reset, the peripheral clock (used for registers read/write access)
\r
1271 * is disabled and the application software has to enable this clock before
\r
1274 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
\r
1275 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
\r
1276 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
\r
1279 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
\r
1280 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
\r
1281 #define __HAL_RCC_USB_IS_OTG_FS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
\r
1283 #if defined(STM32F756xx)
\r
1284 #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)
\r
1285 #define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)
\r
1286 #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)
\r
1287 #define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)
\r
1288 #endif /* STM32F756x */
\r
1290 /** @brief Get the enable or disable status of the AHB3 peripheral clock.
\r
1291 * @note After reset, the peripheral clock (used for registers read/write access)
\r
1292 * is disabled and the application software has to enable this clock before
\r
1295 #define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
\r
1296 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
\r
1298 #define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
\r
1299 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
\r
1301 /** @brief Get the enable or disable status of the APB1 peripheral clock.
\r
1302 * @note After reset, the peripheral clock (used for registers read/write access)
\r
1303 * is disabled and the application software has to enable this clock before
\r
1306 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
\r
1307 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
\r
1308 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
\r
1309 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
\r
1310 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
\r
1311 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
\r
1312 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
\r
1313 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
\r
1314 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
\r
1315 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)
\r
1316 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
\r
1317 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
\r
1318 #define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET)
\r
1319 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
\r
1320 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
\r
1321 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
\r
1322 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
\r
1323 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
\r
1324 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
\r
1325 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
\r
1326 #define __HAL_RCC_I2C4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) != RESET)
\r
1327 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
\r
1328 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
\r
1329 #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
\r
1330 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
\r
1331 #define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
\r
1332 #define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)
\r
1334 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
\r
1335 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
\r
1336 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
\r
1337 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
\r
1338 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
\r
1339 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
\r
1340 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
\r
1341 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
\r
1342 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
\r
1343 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)
\r
1344 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
\r
1345 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
\r
1346 #define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED()((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET)
\r
1347 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
\r
1348 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
\r
1349 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
\r
1350 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
\r
1351 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
\r
1352 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
\r
1353 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
\r
1354 #define __HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) == RESET)
\r
1355 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
\r
1356 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
\r
1357 #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
\r
1358 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
\r
1359 #define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
\r
1360 #define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)
\r
1362 /** @brief Get the enable or disable status of the APB2 peripheral clock.
\r
1363 * @note After reset, the peripheral clock (used for registers read/write access)
\r
1364 * is disabled and the application software has to enable this clock before
\r
1367 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
\r
1368 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
\r
1369 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
\r
1370 #define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
\r
1371 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
\r
1372 #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
\r
1373 #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
\r
1374 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) != RESET)
\r
1375 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
\r
1376 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
\r
1377 #define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
\r
1378 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
\r
1379 #define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
\r
1380 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
\r
1381 #define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET)
\r
1382 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
\r
1383 #define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET)
\r
1384 #define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET)
\r
1386 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
\r
1387 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
\r
1388 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
\r
1389 #define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
\r
1390 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
\r
1391 #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
\r
1392 #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
\r
1393 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) == RESET)
\r
1394 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
\r
1395 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
\r
1396 #define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
\r
1397 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
\r
1398 #define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
\r
1399 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
\r
1400 #define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET)
\r
1401 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
\r
1402 #define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET)
\r
1403 #define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET)
\r
1409 /** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset
\r
1410 * @brief Forces or releases AHB/APB peripheral reset.
\r
1414 /** @brief Force or release AHB1 peripheral reset.
\r
1416 #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
\r
1417 #define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST))
\r
1418 #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
\r
1419 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
\r
1420 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
\r
1421 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
\r
1422 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
\r
1423 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
\r
1424 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
\r
1425 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
\r
1426 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
\r
1427 #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
\r
1428 #define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
\r
1429 #define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST))
\r
1430 #define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST))
\r
1432 #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
\r
1433 #define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
\r
1434 #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
\r
1435 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
\r
1436 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
\r
1437 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
\r
1438 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
\r
1439 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
\r
1440 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
\r
1441 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
\r
1442 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
\r
1443 #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
\r
1444 #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
\r
1445 #define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
\r
1446 #define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
\r
1448 /** @brief Force or release AHB2 peripheral reset.
\r
1450 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF)
\r
1451 #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
\r
1453 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
\r
1454 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
\r
1456 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00)
\r
1457 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
\r
1458 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
\r
1459 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
\r
1461 #if defined(STM32F756xx)
\r
1462 #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
\r
1463 #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
\r
1464 #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
\r
1465 #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
\r
1466 #endif /* STM32F756xx */
\r
1468 /** @brief Force or release AHB3 peripheral reset
\r
1470 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF)
\r
1471 #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
\r
1472 #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
\r
1474 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
\r
1475 #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
\r
1476 #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
\r
1478 /** @brief Force or release APB1 peripheral reset.
\r
1480 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
\r
1481 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
\r
1482 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
\r
1483 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
\r
1484 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
\r
1485 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
\r
1486 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
\r
1487 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
\r
1488 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
\r
1489 #define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
\r
1490 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
\r
1491 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
\r
1492 #define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST))
\r
1493 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
\r
1494 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
\r
1495 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
\r
1496 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
\r
1497 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
\r
1498 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
\r
1499 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
\r
1500 #define __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C4RST))
\r
1501 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
\r
1502 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
\r
1503 #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
\r
1504 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
\r
1505 #define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))
\r
1506 #define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))
\r
1508 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
\r
1509 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
\r
1510 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
\r
1511 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
\r
1512 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
\r
1513 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
\r
1514 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
\r
1515 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
\r
1516 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
\r
1517 #define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
\r
1518 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
\r
1519 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
\r
1520 #define __HAL_RCC_SPDIFRX_RELEASE_RESET()(RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))
\r
1521 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
\r
1522 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
\r
1523 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
\r
1524 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
\r
1525 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
\r
1526 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
\r
1527 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
\r
1528 #define __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C4RST))
\r
1529 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
\r
1530 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
\r
1531 #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
\r
1532 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
\r
1533 #define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
\r
1534 #define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
\r
1536 /** @brief Force or release APB2 peripheral reset.
\r
1538 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
\r
1539 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
\r
1540 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
\r
1541 #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
\r
1542 #define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
\r
1543 #define __HAL_RCC_SDMMC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC1RST))
\r
1544 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
\r
1545 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
\r
1546 #define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
\r
1547 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
\r
1548 #define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
\r
1549 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
\r
1550 #define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))
\r
1551 #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
\r
1552 #define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST))
\r
1553 #define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST))
\r
1555 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
\r
1556 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
\r
1557 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
\r
1558 #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
\r
1559 #define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
\r
1560 #define __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC1RST))
\r
1561 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
\r
1562 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
\r
1563 #define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
\r
1564 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
\r
1565 #define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
\r
1566 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
\r
1567 #define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
\r
1568 #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
\r
1569 #define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))
\r
1570 #define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
\r
1576 /** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable RCCEx Peripheral Clock Sleep Enable Disable
\r
1577 * @brief Enables or disables the AHB/APB peripheral clock during Low Power (Sleep) mode.
\r
1578 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
1579 * power consumption.
\r
1580 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
1581 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
1585 /** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
\r
1587 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
\r
1588 #define __HAL_RCC_AXI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_AXILPEN))
\r
1589 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
\r
1590 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
\r
1591 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
\r
1592 #define __HAL_RCC_DTCM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DTCMLPEN))
\r
1593 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
\r
1594 #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN))
\r
1595 #define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
\r
1596 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
\r
1597 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
\r
1598 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
\r
1599 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
\r
1600 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
\r
1601 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
\r
1602 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
\r
1603 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
\r
1604 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
\r
1605 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
\r
1606 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
\r
1607 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
\r
1608 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
\r
1609 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
\r
1610 #define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN))
\r
1611 #define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN))
\r
1613 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
\r
1614 #define __HAL_RCC_AXI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_AXILPEN))
\r
1615 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
\r
1616 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
\r
1617 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
\r
1618 #define __HAL_RCC_DTCM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DTCMLPEN))
\r
1619 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
\r
1620 #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
\r
1621 #define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
\r
1622 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
\r
1623 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
\r
1624 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
\r
1625 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
\r
1626 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
\r
1627 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
\r
1628 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
\r
1629 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
\r
1630 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
\r
1631 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
\r
1632 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
\r
1633 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
\r
1634 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
\r
1635 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
\r
1636 #define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
\r
1637 #define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
\r
1639 /** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
\r
1640 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
1641 * power consumption.
\r
1642 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
1643 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
1645 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
\r
1646 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
\r
1648 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
\r
1649 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
\r
1651 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
\r
1652 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
\r
1654 #if defined(STM32F756xx)
\r
1655 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
\r
1656 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
\r
1658 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
\r
1659 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
\r
1660 #endif /* STM32F756xx */
\r
1662 /** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
\r
1663 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
1664 * power consumption.
\r
1665 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
1666 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
1668 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
\r
1669 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
\r
1671 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
\r
1672 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
\r
1674 /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
\r
1675 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
1676 * power consumption.
\r
1677 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
1678 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
1680 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
\r
1681 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
\r
1682 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
\r
1683 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
\r
1684 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
\r
1685 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
\r
1686 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
\r
1687 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
\r
1688 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
\r
1689 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN))
\r
1690 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
\r
1691 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
\r
1692 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN))
\r
1693 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
\r
1694 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
\r
1695 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
\r
1696 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
\r
1697 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
\r
1698 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
\r
1699 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
\r
1700 #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C4LPEN))
\r
1701 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
\r
1702 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
\r
1703 #define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN))
\r
1704 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
\r
1705 #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))
\r
1706 #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))
\r
1708 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
\r
1709 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
\r
1710 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
\r
1711 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
\r
1712 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
\r
1713 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
\r
1714 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
\r
1715 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
\r
1716 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
\r
1717 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
\r
1718 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
\r
1719 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
\r
1720 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))
\r
1721 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
\r
1722 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
\r
1723 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
\r
1724 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
\r
1725 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
\r
1726 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
\r
1727 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
\r
1728 #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C4LPEN))
\r
1729 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
\r
1730 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
\r
1731 #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))
\r
1732 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
\r
1733 #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
\r
1734 #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
\r
1736 /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
\r
1737 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
1738 * power consumption.
\r
1739 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
1740 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
1742 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
\r
1743 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
\r
1744 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
\r
1745 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
\r
1746 #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
\r
1747 #define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
\r
1748 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
\r
1749 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC1LPEN))
\r
1750 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
\r
1751 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
\r
1752 #define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
\r
1753 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
\r
1754 #define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
\r
1755 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
\r
1756 #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))
\r
1757 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
\r
1758 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN))
\r
1759 #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN))
\r
1761 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
\r
1762 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
\r
1763 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
\r
1764 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
\r
1765 #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
\r
1766 #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
\r
1767 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
\r
1768 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC1LPEN))
\r
1769 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
\r
1770 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
\r
1771 #define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
\r
1772 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
\r
1773 #define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
\r
1774 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
\r
1775 #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
\r
1776 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
\r
1777 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))
\r
1778 #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
\r
1784 /** @defgroup RCC_Clock_Sleep_Enable_Disable_Status AHB/APB Peripheral Clock Sleep Enable Disable Status
\r
1785 * @brief Get the enable or disable status of the AHB/APB peripheral clock during Low Power (Sleep) mode.
\r
1786 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
1787 * power consumption.
\r
1788 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
1789 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
1793 /** @brief Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode.
\r
1794 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
1795 * power consumption.
\r
1796 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
1797 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
1799 #define __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) != RESET)
\r
1800 #define __HAL_RCC_AXI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) != RESET)
\r
1801 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) != RESET)
\r
1802 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) != RESET)
\r
1803 #define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) != RESET)
\r
1804 #define __HAL_RCC_DTCM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) != RESET)
\r
1805 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != RESET)
\r
1806 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) != RESET)
\r
1807 #define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) != RESET)
\r
1808 #define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) != RESET)
\r
1809 #define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) != RESET)
\r
1810 #define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) != RESET)
\r
1811 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) != RESET)
\r
1812 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) != RESET)
\r
1813 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) != RESET)
\r
1814 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) != RESET)
\r
1815 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) != RESET)
\r
1816 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) != RESET)
\r
1817 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) != RESET)
\r
1818 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) != RESET)
\r
1819 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) != RESET)
\r
1820 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) != RESET)
\r
1821 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) != RESET)
\r
1822 #define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) != RESET)
\r
1823 #define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) != RESET)
\r
1825 #define __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) == RESET)
\r
1826 #define __HAL_RCC_AXI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) == RESET)
\r
1827 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) == RESET)
\r
1828 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) == RESET)
\r
1829 #define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) == RESET)
\r
1830 #define __HAL_RCC_DTCM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) == RESET)
\r
1831 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == RESET)
\r
1832 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) == RESET)
\r
1833 #define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) == RESET)
\r
1834 #define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) == RESET)
\r
1835 #define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) == RESET)
\r
1836 #define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) == RESET)
\r
1837 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) == RESET)
\r
1838 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) == RESET)
\r
1839 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) == RESET)
\r
1840 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) == RESET)
\r
1841 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) == RESET)
\r
1842 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) == RESET)
\r
1843 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) == RESET)
\r
1844 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) == RESET)
\r
1845 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) == RESET)
\r
1846 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) == RESET)
\r
1847 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) == RESET)
\r
1848 #define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) == RESET)
\r
1849 #define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) == RESET)
\r
1851 /** @brief Get the enable or disable status of the AHB2 peripheral clock during Low Power (Sleep) mode.
\r
1852 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
1853 * power consumption.
\r
1854 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
1855 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
1857 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != RESET)
\r
1858 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == RESET)
\r
1860 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != RESET)
\r
1861 #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == RESET)
\r
1863 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) != RESET)
\r
1864 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) == RESET)
\r
1866 #if defined(STM32F756xx)
\r
1867 #define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != RESET)
\r
1868 #define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != RESET)
\r
1870 #define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == RESET)
\r
1871 #define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == RESET)
\r
1872 #endif /* STM32F756xx */
\r
1874 /** @brief Get the enable or disable status of the AHB3 peripheral clock during Low Power (Sleep) mode.
\r
1875 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
1876 * power consumption.
\r
1877 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
1878 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
1880 #define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) != RESET)
\r
1881 #define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) == RESET)
\r
1883 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) != RESET)
\r
1884 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) == RESET)
\r
1886 /** @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.
\r
1887 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
1888 * power consumption.
\r
1889 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
1890 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
1892 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) != RESET)
\r
1893 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) != RESET)
\r
1894 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) != RESET)
\r
1895 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != RESET)
\r
1896 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) != RESET)
\r
1897 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) != RESET)
\r
1898 #define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) != RESET)
\r
1899 #define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) != RESET)
\r
1900 #define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) != RESET)
\r
1901 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) != RESET)
\r
1902 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != RESET)
\r
1903 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != RESET)
\r
1904 #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) != RESET)
\r
1905 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) != RESET)
\r
1906 #define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) != RESET)
\r
1907 #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != RESET)
\r
1908 #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != RESET)
\r
1909 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) != RESET)
\r
1910 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) != RESET)
\r
1911 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) != RESET)
\r
1912 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) != RESET)
\r
1913 #define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) != RESET)
\r
1914 #define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) != RESET)
\r
1915 #define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) != RESET)
\r
1916 #define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) != RESET)
\r
1917 #define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) != RESET)
\r
1918 #define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) != RESET)
\r
1920 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) == RESET)
\r
1921 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) == RESET)
\r
1922 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) == RESET)
\r
1923 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == RESET)
\r
1924 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) == RESET)
\r
1925 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) == RESET)
\r
1926 #define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) == RESET)
\r
1927 #define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) == RESET)
\r
1928 #define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) == RESET)
\r
1929 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) == RESET)
\r
1930 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == RESET)
\r
1931 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == RESET)
\r
1932 #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED()((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) == RESET)
\r
1933 #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) == RESET)
\r
1934 #define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) == RESET)
\r
1935 #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == RESET)
\r
1936 #define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == RESET)
\r
1937 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) == RESET)
\r
1938 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) == RESET)
\r
1939 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) == RESET)
\r
1940 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) == RESET)
\r
1941 #define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) == RESET)
\r
1942 #define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) == RESET)
\r
1943 #define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) == RESET)
\r
1944 #define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) == RESET)
\r
1945 #define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) == RESET)
\r
1946 #define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) == RESET)
\r
1948 /** @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.
\r
1949 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
1950 * power consumption.
\r
1951 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
1952 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
1954 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != RESET)
\r
1955 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != RESET)
\r
1956 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != RESET)
\r
1957 #define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != RESET)
\r
1958 #define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) != RESET)
\r
1959 #define __HAL_RCC_ADC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) != RESET)
\r
1960 #define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) != RESET)
\r
1961 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) != RESET)
\r
1962 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != RESET)
\r
1963 #define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != RESET)
\r
1964 #define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) != RESET)
\r
1965 #define __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) != RESET)
\r
1966 #define __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) != RESET)
\r
1967 #define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != RESET)
\r
1968 #define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) != RESET)
\r
1969 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != RESET)
\r
1970 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != RESET)
\r
1971 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) != RESET)
\r
1973 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == RESET)
\r
1974 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == RESET)
\r
1975 #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == RESET)
\r
1976 #define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == RESET)
\r
1977 #define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) == RESET)
\r
1978 #define __HAL_RCC_ADC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) == RESET)
\r
1979 #define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) == RESET)
\r
1980 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) == RESET)
\r
1981 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == RESET)
\r
1982 #define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == RESET)
\r
1983 #define __HAL_RCC_TIM9_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) == RESET)
\r
1984 #define __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) == RESET)
\r
1985 #define __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) == RESET)
\r
1986 #define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == RESET)
\r
1987 #define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET)
\r
1988 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == RESET)
\r
1989 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == RESET)
\r
1990 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) == RESET)
\r
1995 /*---------------------------------------------------------------------------------------------*/
\r
1997 /** @brief Macro to configure the Timers clocks prescalers
\r
1998 * @param __PRESC__ : specifies the Timers clocks prescalers selection
\r
1999 * This parameter can be one of the following values:
\r
2000 * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
\r
2001 * equal to HPRE if PPREx is corresponding to division by 1 or 2,
\r
2002 * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
\r
2003 * division by 4 or more.
\r
2004 * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
\r
2005 * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
\r
2006 * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
\r
2007 * to division by 8 or more.
\r
2009 #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->DCKCFGR1 &= ~(RCC_DCKCFGR1_TIMPRE);\
\r
2010 RCC->DCKCFGR1 |= (__PRESC__);\
\r
2013 /** @brief Macros to Enable or Disable the PLLISAI.
\r
2014 * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
\r
2016 #define __HAL_RCC_PLLSAI_ENABLE() (RCC->CR |= (RCC_CR_PLLSAION))
\r
2017 #define __HAL_RCC_PLLSAI_DISABLE() (RCC->CR &= ~(RCC_CR_PLLSAION))
\r
2019 /** @brief Macro to configure the PLLSAI clock multiplication and division factors.
\r
2020 * @note This function must be used only when the PLLSAI is disabled.
\r
2021 * @note PLLSAI clock source is common with the main PLL (configured in
\r
2022 * RCC_PLLConfig function )
\r
2023 * @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
\r
2024 * This parameter must be a number between Min_Data = 49 and Max_Data = 432.
\r
2025 * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
\r
2026 * output frequency is between Min_Data = 49 and Max_Data = 432 MHz.
\r
2027 * @param __PLLSAIQ__: specifies the division factor for SAI clock
\r
2028 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
\r
2029 * @param __PLLSAIR__: specifies the division factor for LTDC clock
\r
2030 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
\r
2031 * @param __PLLSAIP__: specifies the division factor for USB, RNG, SDMMC clocks
\r
2032 * This parameter can be a divider by 2, 4, 6 or 8.
\r
2034 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) (RCC->PLLSAICFGR = ((__PLLSAIN__) << 6) | ((__PLLSAIP__) << 16) | ((__PLLSAIQ__) << 24) | ((__PLLSAIR__) << 28))
\r
2036 /** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.
\r
2037 * @note This macro must be used only when the PLLI2S is disabled.
\r
2038 * @note PLLI2S clock source is common with the main PLL (configured in
\r
2039 * HAL_RCC_ClockConfig() API)
\r
2040 * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
\r
2041 * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
\r
2042 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
\r
2043 * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
\r
2044 * @param __PLLI2SQ__: specifies the division factor for SAI clock.
\r
2045 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
\r
2046 * @param __PLLI2SR__: specifies the division factor for I2S clock
\r
2047 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
\r
2048 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
\r
2049 * on the I2S clock frequency.
\r
2050 * @param __PLLI2SP__: specifies the division factor for SPDDIF-RX clock.
\r
2051 * This parameter can be a divider by 2, 4, 6 or 8.
\r
2053 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6) | ((__PLLI2SP__) << 16) | ((__PLLI2SQ__) << 24) | ((__PLLI2SR__) << 28))
\r
2055 /** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
\r
2056 * @note This function must be called before enabling the PLLI2S.
\r
2057 * @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock .
\r
2058 * This parameter must be a number between 1 and 32.
\r
2059 * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
\r
2061 #define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
\r
2063 /** @brief Macro to configure the SAI clock Divider coming from PLLSAI.
\r
2064 * @note This function must be called before enabling the PLLSAI.
\r
2065 * @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .
\r
2066 * This parameter must be a number between Min_Data = 1 and Max_Data = 32.
\r
2067 * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
\r
2069 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
\r
2071 /** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.
\r
2073 * @note This function must be called before enabling the PLLSAI.
\r
2074 * @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
\r
2075 * This parameter must be a number between Min_Data = 2 and Max_Data = 16.
\r
2076 * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
\r
2078 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__)\
\r
2079 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, (uint32_t)(__PLLSAIDivR__))
\r
2081 /** @brief Macro to configure SAI1 clock source selection.
\r
2082 * @note This function must be called before enabling PLLSAI, PLLI2S and
\r
2084 * @param __SOURCE__: specifies the SAI1 clock source.
\r
2085 * This parameter can be one of the following values:
\r
2086 * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
\r
2088 * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
\r
2090 * @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
\r
2091 * used as SAI1 clock.
\r
2093 #define __HAL_RCC_SAI1_CONFIG(__SOURCE__)\
\r
2094 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL, (uint32_t)(__SOURCE__))
\r
2096 /** @brief Macro to get the SAI1 clock source.
\r
2097 * @retval The clock source can be one of the following values:
\r
2098 * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
\r
2100 * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
\r
2102 * @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
\r
2103 * used as SAI1 clock.
\r
2105 #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL)))
\r
2108 /** @brief Macro to configure SAI2 clock source selection.
\r
2109 * @note This function must be called before enabling PLLSAI, PLLI2S and
\r
2111 * @param __SOURCE__: specifies the SAI2 clock source.
\r
2112 * This parameter can be one of the following values:
\r
2113 * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
\r
2115 * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
\r
2117 * @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
\r
2118 * used as SAI2 clock.
\r
2120 #define __HAL_RCC_SAI2_CONFIG(__SOURCE__)\
\r
2121 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL, (uint32_t)(__SOURCE__))
\r
2124 /** @brief Macro to get the SAI2 clock source.
\r
2125 * @retval The clock source can be one of the following values:
\r
2126 * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
\r
2128 * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
\r
2130 * @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
\r
2131 * used as SAI2 clock.
\r
2133 #define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL)))
\r
2136 /** @brief Enable PLLSAI_RDY interrupt.
\r
2138 #define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))
\r
2140 /** @brief Disable PLLSAI_RDY interrupt.
\r
2142 #define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
\r
2144 /** @brief Clear the PLLSAI RDY interrupt pending bits.
\r
2146 #define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF))
\r
2148 /** @brief Check the PLLSAI RDY interrupt has occurred or not.
\r
2149 * @retval The new state (TRUE or FALSE).
\r
2151 #define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
\r
2153 /** @brief Check PLLSAI RDY flag is set or not.
\r
2154 * @retval The new state (TRUE or FALSE).
\r
2156 #define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
\r
2158 /** @brief Macro to Get I2S clock source selection.
\r
2159 * @retval The clock source can be one of the following values:
\r
2160 * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
\r
2161 * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S clock source
\r
2163 #define __HAL_RCC_GET_I2SCLKSOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC))
\r
2165 /** @brief Macro to configure the I2C1 clock (I2C1CLK).
\r
2167 * @param __I2C1_CLKSOURCE__: specifies the I2C1 clock source.
\r
2168 * This parameter can be one of the following values:
\r
2169 * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
\r
2170 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
\r
2171 * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
\r
2173 #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \
\r
2174 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))
\r
2176 /** @brief Macro to get the I2C1 clock source.
\r
2177 * @retval The clock source can be one of the following values:
\r
2178 * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
\r
2179 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
\r
2180 * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
\r
2182 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL)))
\r
2184 /** @brief Macro to configure the I2C2 clock (I2C2CLK).
\r
2186 * @param __I2C2_CLKSOURCE__: specifies the I2C2 clock source.
\r
2187 * This parameter can be one of the following values:
\r
2188 * @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock
\r
2189 * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
\r
2190 * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
\r
2192 #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \
\r
2193 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__))
\r
2195 /** @brief Macro to get the I2C2 clock source.
\r
2196 * @retval The clock source can be one of the following values:
\r
2197 * @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock
\r
2198 * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
\r
2199 * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
\r
2201 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL)))
\r
2203 /** @brief Macro to configure the I2C3 clock (I2C3CLK).
\r
2205 * @param __I2C3_CLKSOURCE__: specifies the I2C3 clock source.
\r
2206 * This parameter can be one of the following values:
\r
2207 * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
\r
2208 * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
\r
2209 * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
\r
2211 #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \
\r
2212 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))
\r
2214 /** @brief macro to get the I2C3 clock source.
\r
2215 * @retval The clock source can be one of the following values:
\r
2216 * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
\r
2217 * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
\r
2218 * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
\r
2220 #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL)))
\r
2222 /** @brief Macro to configure the I2C4 clock (I2C4CLK).
\r
2224 * @param __I2C4_CLKSOURCE__: specifies the I2C4 clock source.
\r
2225 * This parameter can be one of the following values:
\r
2226 * @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock
\r
2227 * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
\r
2228 * @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock
\r
2230 #define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \
\r
2231 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__))
\r
2233 /** @brief macro to get the I2C4 clock source.
\r
2234 * @retval The clock source can be one of the following values:
\r
2235 * @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock
\r
2236 * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
\r
2237 * @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock
\r
2239 #define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL)))
\r
2241 /** @brief Macro to configure the USART1 clock (USART1CLK).
\r
2243 * @param __USART1_CLKSOURCE__: specifies the USART1 clock source.
\r
2244 * This parameter can be one of the following values:
\r
2245 * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
\r
2246 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
\r
2247 * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
\r
2248 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
\r
2250 #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \
\r
2251 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))
\r
2253 /** @brief macro to get the USART1 clock source.
\r
2254 * @retval The clock source can be one of the following values:
\r
2255 * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
\r
2256 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
\r
2257 * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
\r
2258 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
\r
2260 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL)))
\r
2262 /** @brief Macro to configure the USART2 clock (USART2CLK).
\r
2264 * @param __USART2_CLKSOURCE__: specifies the USART2 clock source.
\r
2265 * This parameter can be one of the following values:
\r
2266 * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
\r
2267 * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
\r
2268 * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
\r
2269 * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
\r
2271 #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \
\r
2272 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))
\r
2274 /** @brief macro to get the USART2 clock source.
\r
2275 * @retval The clock source can be one of the following values:
\r
2276 * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
\r
2277 * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
\r
2278 * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
\r
2279 * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
\r
2281 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL)))
\r
2283 /** @brief Macro to configure the USART3 clock (USART3CLK).
\r
2285 * @param __USART3_CLKSOURCE__: specifies the USART3 clock source.
\r
2286 * This parameter can be one of the following values:
\r
2287 * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
\r
2288 * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
\r
2289 * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
\r
2290 * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
\r
2292 #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \
\r
2293 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__))
\r
2295 /** @brief macro to get the USART3 clock source.
\r
2296 * @retval The clock source can be one of the following values:
\r
2297 * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
\r
2298 * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
\r
2299 * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
\r
2300 * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
\r
2302 #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL)))
\r
2304 /** @brief Macro to configure the UART4 clock (UART4CLK).
\r
2306 * @param __UART4_CLKSOURCE__: specifies the UART4 clock source.
\r
2307 * This parameter can be one of the following values:
\r
2308 * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
\r
2309 * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
\r
2310 * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
\r
2311 * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
\r
2313 #define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \
\r
2314 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__))
\r
2316 /** @brief macro to get the UART4 clock source.
\r
2317 * @retval The clock source can be one of the following values:
\r
2318 * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
\r
2319 * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
\r
2320 * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
\r
2321 * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
\r
2323 #define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL)))
\r
2325 /** @brief Macro to configure the UART5 clock (UART5CLK).
\r
2327 * @param __UART5_CLKSOURCE__: specifies the UART5 clock source.
\r
2328 * This parameter can be one of the following values:
\r
2329 * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
\r
2330 * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
\r
2331 * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
\r
2332 * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
\r
2334 #define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \
\r
2335 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__))
\r
2337 /** @brief macro to get the UART5 clock source.
\r
2338 * @retval The clock source can be one of the following values:
\r
2339 * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
\r
2340 * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
\r
2341 * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
\r
2342 * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
\r
2344 #define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL)))
\r
2346 /** @brief Macro to configure the USART6 clock (USART6CLK).
\r
2348 * @param __USART6_CLKSOURCE__: specifies the USART6 clock source.
\r
2349 * This parameter can be one of the following values:
\r
2350 * @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock
\r
2351 * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
\r
2352 * @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock
\r
2353 * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
\r
2355 #define __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__) \
\r
2356 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL, (uint32_t)(__USART6_CLKSOURCE__))
\r
2358 /** @brief macro to get the USART6 clock source.
\r
2359 * @retval The clock source can be one of the following values:
\r
2360 * @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock
\r
2361 * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
\r
2362 * @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock
\r
2363 * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
\r
2365 #define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL)))
\r
2367 /** @brief Macro to configure the UART7 clock (UART7CLK).
\r
2369 * @param __UART7_CLKSOURCE__: specifies the UART7 clock source.
\r
2370 * This parameter can be one of the following values:
\r
2371 * @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock
\r
2372 * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
\r
2373 * @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock
\r
2374 * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
\r
2376 #define __HAL_RCC_UART7_CONFIG(__UART7_CLKSOURCE__) \
\r
2377 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL, (uint32_t)(__UART7_CLKSOURCE__))
\r
2379 /** @brief macro to get the UART7 clock source.
\r
2380 * @retval The clock source can be one of the following values:
\r
2381 * @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock
\r
2382 * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
\r
2383 * @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock
\r
2384 * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
\r
2386 #define __HAL_RCC_GET_UART7_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL)))
\r
2388 /** @brief Macro to configure the UART8 clock (UART8CLK).
\r
2390 * @param __UART8_CLKSOURCE__: specifies the UART8 clock source.
\r
2391 * This parameter can be one of the following values:
\r
2392 * @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock
\r
2393 * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
\r
2394 * @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock
\r
2395 * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
\r
2397 #define __HAL_RCC_UART8_CONFIG(__UART8_CLKSOURCE__) \
\r
2398 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL, (uint32_t)(__UART8_CLKSOURCE__))
\r
2400 /** @brief macro to get the UART8 clock source.
\r
2401 * @retval The clock source can be one of the following values:
\r
2402 * @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock
\r
2403 * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
\r
2404 * @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock
\r
2405 * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
\r
2407 #define __HAL_RCC_GET_UART8_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL)))
\r
2409 /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK).
\r
2411 * @param __LPTIM1_CLKSOURCE__: specifies the LPTIM1 clock source.
\r
2412 * This parameter can be one of the following values:
\r
2413 * @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock
\r
2414 * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock
\r
2415 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
\r
2416 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
\r
2418 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \
\r
2419 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))
\r
2421 /** @brief macro to get the LPTIM1 clock source.
\r
2422 * @retval The clock source can be one of the following values:
\r
2423 * @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock
\r
2424 * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock
\r
2425 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
\r
2426 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
\r
2428 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)))
\r
2430 /** @brief Macro to configure the CEC clock (CECCLK).
\r
2432 * @param __CEC_CLKSOURCE__: specifies the CEC clock source.
\r
2433 * This parameter can be one of the following values:
\r
2434 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
\r
2435 * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
\r
2437 #define __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__) \
\r
2438 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__CEC_CLKSOURCE__))
\r
2440 /** @brief macro to get the CEC clock source.
\r
2441 * @retval The clock source can be one of the following values:
\r
2442 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
\r
2443 * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
\r
2445 #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL)))
\r
2447 /** @brief Macro to configure the CLK48 source (CLK48CLK).
\r
2449 * @param __CLK48_SOURCE__: specifies the CLK48 clock source.
\r
2450 * This parameter can be one of the following values:
\r
2451 * @arg RCC_CLK48SOURCE_PLL: PLL selected as CLK48 source
\r
2452 * @arg RCC_CLK48SOURCE_PLSAI1: PLLSAI1 selected as CLK48 source
\r
2454 #define __HAL_RCC_CLK48_CONFIG(__CLK48_SOURCE__) \
\r
2455 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__CLK48_SOURCE__))
\r
2457 /** @brief macro to get the CLK48 source.
\r
2458 * @retval The clock source can be one of the following values:
\r
2459 * @arg RCC_CLK48SOURCE_PLL: PLL used as CLK48 source
\r
2460 * @arg RCC_CLK48SOURCE_PLSAI1: PLLSAI1 used as CLK48 source
\r
2462 #define __HAL_RCC_GET_CLK48_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL)))
\r
2464 /** @brief Macro to configure the SDMMC1 clock (SDMMC1CLK).
\r
2466 * @param __SDMMC1_CLKSOURCE__: specifies the SDMMC1 clock source.
\r
2467 * This parameter can be one of the following values:
\r
2468 * @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC clock
\r
2469 * @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC clock
\r
2471 #define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \
\r
2472 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL, (uint32_t)(__SDMMC1_CLKSOURCE__))
\r
2474 /** @brief macro to get the SDMMC1 clock source.
\r
2475 * @retval The clock source can be one of the following values:
\r
2476 * @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC1 clock
\r
2477 * @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC1 clock
\r
2479 #define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL)))
\r
2485 /* Exported functions --------------------------------------------------------*/
\r
2486 /** @addtogroup RCCEx_Exported_Functions_Group1
\r
2489 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
\r
2490 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
\r
2491 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
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2496 /* Private macros ------------------------------------------------------------*/
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2497 /** @addtogroup RCCEx_Private_Macros RCCEx Private Macros
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2500 /** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
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2503 #define IS_RCC_PERIPHCLOCK(SELECTION) \
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2504 ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
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2505 (((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \
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2506 (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \
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2507 (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
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2508 (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
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2509 (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
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2510 (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
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2511 (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
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2512 (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \
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2513 (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \
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2514 (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \
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2515 (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
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2516 (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
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2517 (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
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2518 (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
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2519 (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
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2520 (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
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2521 (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
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2522 (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \
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2523 (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \
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2524 (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \
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2525 (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \
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2526 (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
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2527 #define IS_RCC_PLLI2SN_VALUE(VALUE) ((49 <= (VALUE)) && ((VALUE) <= 432))
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2528 #define IS_RCC_PLLI2SP_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 8))
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2529 #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
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2530 #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
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2532 #define IS_RCC_PLLSAIN_VALUE(VALUE) ((49 <= (VALUE)) && ((VALUE) <= 432))
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2533 #define IS_RCC_PLLSAIP_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 8))
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2534 #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
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2535 #define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
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2537 #define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
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2539 #define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
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2541 #define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\
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2542 ((VALUE) == RCC_PLLSAIDIVR_4) ||\
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2543 ((VALUE) == RCC_PLLSAIDIVR_8) ||\
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2544 ((VALUE) == RCC_PLLSAIDIVR_16))
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2545 #define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_PLLI2S) || \
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2546 ((SOURCE) == RCC_I2SCLKSOURCE_EXT))
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2547 #define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \
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2548 ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \
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2549 ((SOURCE) == RCC_SAI1CLKSOURCE_PIN))
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2550 #define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \
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2551 ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \
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2552 ((SOURCE) == RCC_SAI2CLKSOURCE_PIN))
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2554 #define IS_RCC_SDMMC1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC1CLKSOURCE_SYSCLK) || \
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2555 ((SOURCE) == RCC_SDMMC1CLKSOURCE_CLK48))
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2557 #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \
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2558 ((SOURCE) == RCC_CECCLKSOURCE_LSE))
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2559 #define IS_RCC_USART1CLKSOURCE(SOURCE) \
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2560 (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \
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2561 ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
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2562 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
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2563 ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
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2565 #define IS_RCC_USART2CLKSOURCE(SOURCE) \
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2566 (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \
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2567 ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \
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2568 ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \
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2569 ((SOURCE) == RCC_USART2CLKSOURCE_HSI))
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2570 #define IS_RCC_USART3CLKSOURCE(SOURCE) \
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2571 (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \
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2572 ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \
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2573 ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \
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2574 ((SOURCE) == RCC_USART3CLKSOURCE_HSI))
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2576 #define IS_RCC_UART4CLKSOURCE(SOURCE) \
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2577 (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) || \
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2578 ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \
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2579 ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \
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2580 ((SOURCE) == RCC_UART4CLKSOURCE_HSI))
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2582 #define IS_RCC_UART5CLKSOURCE(SOURCE) \
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2583 (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) || \
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2584 ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \
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2585 ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \
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2586 ((SOURCE) == RCC_UART5CLKSOURCE_HSI))
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2588 #define IS_RCC_USART6CLKSOURCE(SOURCE) \
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2589 (((SOURCE) == RCC_USART6CLKSOURCE_PCLK2) || \
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2590 ((SOURCE) == RCC_USART6CLKSOURCE_SYSCLK) || \
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2591 ((SOURCE) == RCC_USART6CLKSOURCE_LSE) || \
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2592 ((SOURCE) == RCC_USART6CLKSOURCE_HSI))
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2594 #define IS_RCC_UART7CLKSOURCE(SOURCE) \
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2595 (((SOURCE) == RCC_UART7CLKSOURCE_PCLK1) || \
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2596 ((SOURCE) == RCC_UART7CLKSOURCE_SYSCLK) || \
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2597 ((SOURCE) == RCC_UART7CLKSOURCE_LSE) || \
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2598 ((SOURCE) == RCC_UART7CLKSOURCE_HSI))
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2600 #define IS_RCC_UART8CLKSOURCE(SOURCE) \
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2601 (((SOURCE) == RCC_UART8CLKSOURCE_PCLK1) || \
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2602 ((SOURCE) == RCC_UART8CLKSOURCE_SYSCLK) || \
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2603 ((SOURCE) == RCC_UART8CLKSOURCE_LSE) || \
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2604 ((SOURCE) == RCC_UART8CLKSOURCE_HSI))
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2605 #define IS_RCC_I2C1CLKSOURCE(SOURCE) \
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2606 (((SOURCE) == RCC_I2C1CLKSOURCE_PCLK1) || \
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2607 ((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
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2608 ((SOURCE) == RCC_I2C1CLKSOURCE_HSI))
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2609 #define IS_RCC_I2C2CLKSOURCE(SOURCE) \
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2610 (((SOURCE) == RCC_I2C2CLKSOURCE_PCLK1) || \
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2611 ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK)|| \
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2612 ((SOURCE) == RCC_I2C2CLKSOURCE_HSI))
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2614 #define IS_RCC_I2C3CLKSOURCE(SOURCE) \
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2615 (((SOURCE) == RCC_I2C3CLKSOURCE_PCLK1) || \
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2616 ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK)|| \
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2617 ((SOURCE) == RCC_I2C3CLKSOURCE_HSI))
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2618 #define IS_RCC_I2C4CLKSOURCE(SOURCE) \
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2619 (((SOURCE) == RCC_I2C4CLKSOURCE_PCLK1) || \
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2620 ((SOURCE) == RCC_I2C4CLKSOURCE_SYSCLK)|| \
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2621 ((SOURCE) == RCC_I2C4CLKSOURCE_HSI))
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2622 #define IS_RCC_LPTIM1CLK(SOURCE) \
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2623 (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK) || \
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2624 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || \
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2625 ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) || \
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2626 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
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2627 #define IS_RCC_CLK48SOURCE(SOURCE) \
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2628 (((SOURCE) == RCC_CLK48SOURCE_PLLSAIP) || \
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2629 ((SOURCE) == RCC_CLK48SOURCE_PLL))
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2630 #define IS_RCC_TIMPRES(VALUE) \
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2631 (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \
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2632 ((VALUE) == RCC_TIMPRES_ACTIVATED))
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2648 #ifdef __cplusplus
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2652 #endif /* __STM32F7xx_HAL_RCC_EX_H */
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2654 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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