git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_tim_ex.h

   1 /**\r
   2   ******************************************************************************\r
   3   * @file    stm32f7xx_hal_tim_ex.h\r
   4   * @author  MCD Application Team\r
   5   * @version V1.0.0RC1\r
   6   * @date    24-March-2015\r
   7   * @brief   Header file of TIM HAL Extension module.\r
   8   ******************************************************************************\r
   9   * @attention\r
  10   *\r
  11   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
  12   *\r
  13   * Redistribution and use in source and binary forms, with or without modification,\r
  14   * are permitted provided that the following conditions are met:\r
  15   *   1. Redistributions of source code must retain the above copyright notice,\r
  16   *      this list of conditions and the following disclaimer.\r
  17   *   2. Redistributions in binary form must reproduce the above copyright notice,\r
  18   *      this list of conditions and the following disclaimer in the documentation\r
  19   *      and/or other materials provided with the distribution.\r
  20   *   3. Neither the name of STMicroelectronics nor the names of its contributors\r
  21   *      may be used to endorse or promote products derived from this software\r
  22   *      without specific prior written permission.\r
  23   *\r
  24   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
  25   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
  26   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
  27   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
  28   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
  29   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
  30   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
  31   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
  32   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
  33   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
  34   *\r
  35   ******************************************************************************\r
  36   */ \r
  37 \r
  38 /* Define to prevent recursive inclusion -------------------------------------*/\r
  39 #ifndef __STM32F7xx_HAL_TIM_EX_H\r
  40 #define __STM32F7xx_HAL_TIM_EX_H\r
  41 \r
  42 #ifdef __cplusplus\r
  43  extern "C" {\r
  44 #endif\r
  45 \r
  46 /* Includes ------------------------------------------------------------------*/\r
  47 #include "stm32f7xx_hal_def.h"\r
  48 \r
  49 /** @addtogroup STM32F7xx_HAL\r
  50   * @{\r
  51   */\r
  52 \r
  53 /** @addtogroup TIMEx\r
  54   * @{\r
  55   */ \r
  56 \r
  57 /* Exported types ------------------------------------------------------------*/ \r
  58 /** @defgroup TIMEx_Exported_Types TIM Exported Types\r
  59   * @{\r
  60   */\r
  61   \r
  62 /** \r
  63   * @brief  TIM Hall sensor Configuration Structure definition  \r
  64   */\r
  65 \r
  66 typedef struct\r
  67 {\r
  68                                   \r
  69   uint32_t IC1Polarity;            /*!< Specifies the active edge of the input signal.\r
  70                                         This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r
  71                                                                    \r
  72   uint32_t IC1Prescaler;        /*!< Specifies the Input Capture Prescaler.\r
  73                                      This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r
  74                                   \r
  75   uint32_t IC1Filter;           /*!< Specifies the input capture filter.\r
  76                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */  \r
  77   uint32_t Commutation_Delay;  /*!< Specifies the pulse value to be loaded into the Capture Compare Register. \r
  78                                     This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */                              \r
  79 } TIM_HallSensor_InitTypeDef;\r
  80 \r
  81 /** \r
  82   * @brief  TIM Master configuration Structure definition  \r
  83   */ \r
  84 typedef struct {\r
  85   uint32_t  MasterOutputTrigger;   /*!< Trigger output (TRGO) selection. \r
  86                                       This parameter can be a value of @ref TIM_Master_Mode_Selection */ \r
  87   uint32_t  MasterOutputTrigger2;  /*!< Trigger output2 (TRGO2) selection \r
  88                                       This parameter can be a value of @ref TIMEx_Master_Mode_Selection_2 */\r
  89   uint32_t  MasterSlaveMode;       /*!< Master/slave mode selection. \r
  90                                       This parameter can be a value of @ref TIM_Master_Slave_Mode */\r
  91 }TIM_MasterConfigTypeDef;\r
  92 \r
  93 /** \r
  94   * @brief  TIM Break input(s) and Dead time configuration Structure definition  \r
  95   * @note   2 break inputs can be configured (BKIN and BKIN2) with configurable \r
  96   *        filter and polarity.\r
  97   */ \r
  98 typedef struct\r
  99 {\r
 100   uint32_t OffStateRunMode;             /*!< TIM off state in run mode.\r
 101                                        This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */\r
 102   uint32_t OffStateIDLEMode;        /*!< TIM off state in IDLE mode.\r
 103                                        This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */\r
 104   uint32_t LockLevel;                   /*!< TIM Lock level.\r
 105                                        This parameter can be a value of @ref TIM_Lock_level */                             \r
 106   uint32_t DeadTime;                    /*!< TIM dead Time.\r
 107                                        This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */\r
 108   uint32_t BreakState;                  /*!< TIM Break State.\r
 109                                        This parameter can be a value of @ref TIM_Break_Input_enable_disable */\r
 110   uint32_t BreakPolarity;           /*!< TIM Break input polarity.\r
 111                                        This parameter can be a value of @ref TIM_Break_Polarity */\r
 112   uint32_t BreakFilter;             /*!< Specifies the break input filter.\r
 113                                        This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */  \r
 114   uint32_t Break2State;                 /*!< TIM Break2 State \r
 115                                        This parameter can be a value of @ref TIMEx_Break2_Input_enable_disable */\r
 116   uint32_t Break2Polarity;          /*!< TIM Break2 input polarity \r
 117                                        This parameter can be a value of @ref TIMEx_Break2_Polarity */\r
 118   uint32_t Break2Filter;            /*!< TIM break2 input filter.\r
 119                                        This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */  \r
 120   uint32_t AutomaticOutput;         /*!< TIM Automatic Output Enable state \r
 121                                        This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */           \r
 122 } TIM_BreakDeadTimeConfigTypeDef;\r
 123 \r
 124 /**\r
 125   * @}\r
 126   */\r
 127   \r
 128 /* Exported constants --------------------------------------------------------*/\r
 129 /** @defgroup TIMEx_Exported_Constants  TIM Exported Constants\r
 130   * @{\r
 131   */\r
 132   \r
 133 /** @defgroup TIMEx_Channel TIM Channel\r
 134   * @{\r
 135   */\r
 136 \r
 137 #define TIM_CHANNEL_1                      ((uint32_t)0x0000)\r
 138 #define TIM_CHANNEL_2                      ((uint32_t)0x0004)\r
 139 #define TIM_CHANNEL_3                      ((uint32_t)0x0008)\r
 140 #define TIM_CHANNEL_4                      ((uint32_t)0x000C)\r
 141 #define TIM_CHANNEL_5                      ((uint32_t)0x0010)\r
 142 #define TIM_CHANNEL_6                      ((uint32_t)0x0014)\r
 143 #define TIM_CHANNEL_ALL                    ((uint32_t)0x003C)\r
 144                                  \r
 145 /**\r
 146   * @}\r
 147   */ \r
 148     \r
 149 /** @defgroup TIMEx_Output_Compare_and_PWM_modes TIM  Extended Output Compare and PWM Modes\r
 150   * @{\r
 151   */\r
 152 #define TIM_OCMODE_TIMING                   ((uint32_t)0x0000)\r
 153 #define TIM_OCMODE_ACTIVE                   ((uint32_t)TIM_CCMR1_OC1M_0)\r
 154 #define TIM_OCMODE_INACTIVE                 ((uint32_t)TIM_CCMR1_OC1M_1)\r
 155 #define TIM_OCMODE_TOGGLE                   ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)\r
 156 #define TIM_OCMODE_PWM1                     ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)\r
 157 #define TIM_OCMODE_PWM2                     ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)\r
 158 #define TIM_OCMODE_FORCED_ACTIVE            ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)\r
 159 #define TIM_OCMODE_FORCED_INACTIVE          ((uint32_t)TIM_CCMR1_OC1M_2)\r
 160 \r
 161 #define TIM_OCMODE_RETRIGERRABLE_OPM1      ((uint32_t)TIM_CCMR1_OC1M_3)\r
 162 #define TIM_OCMODE_RETRIGERRABLE_OPM2      ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)\r
 163 #define TIM_OCMODE_COMBINED_PWM1           ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)\r
 164 #define TIM_OCMODE_COMBINED_PWM2           ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)\r
 165 #define TIM_OCMODE_ASSYMETRIC_PWM1         ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)\r
 166 #define TIM_OCMODE_ASSYMETRIC_PWM2         ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)\r
 167 /**\r
 168   * @}\r
 169   */\r
 170       \r
 171 /** @defgroup TIMEx_Remap  TIM Remap\r
 172   * @{\r
 173   */\r
 174 #define TIM_TIM2_TIM8_TRGO                     (0x00000000)\r
 175 #define TIM_TIM2_ETH_PTP                       (0x00000400)\r
 176 #define TIM_TIM2_USBFS_SOF                     (0x00000800)\r
 177 #define TIM_TIM2_USBHS_SOF                     (0x00000C00)\r
 178 #define TIM_TIM5_GPIO                          (0x00000000)\r
 179 #define TIM_TIM5_LSI                           (0x00000040)\r
 180 #define TIM_TIM5_LSE                           (0x00000080)\r
 181 #define TIM_TIM5_RTC                           (0x000000C0)\r
 182 #define TIM_TIM11_GPIO                         (0x00000000)\r
 183 #define TIM_TIM11_SPDIFRX                      (0x00000001)\r
 184 #define TIM_TIM11_HSE                          (0x00000002)\r
 185 #define TIM_TIM11_MCO1                         (0x00000003)\r
 186 /**\r
 187   * @}\r
 188   */    \r
 189 \r
 190 /** @defgroup TIMEx_ClearInput_Source TIM  Extended Clear Input Source\r
 191   * @{\r
 192   */\r
 193 #define TIM_CLEARINPUTSOURCE_ETR            ((uint32_t)0x0001) \r
 194 #define TIM_CLEARINPUTSOURCE_OCREFCLR       ((uint32_t)0x0002) \r
 195 #define TIM_CLEARINPUTSOURCE_NONE           ((uint32_t)0x0000)\r
 196 /**\r
 197   * @}\r
 198   */\r
 199   \r
 200 /** @defgroup TIMEx_Break2_Input_enable_disable  TIMEX Break input 2 Enable\r
 201   * @{\r
 202   */                         \r
 203 #define TIM_BREAK2_DISABLE         ((uint32_t)0x00000000)\r
 204 #define TIM_BREAK2_ENABLE          ((uint32_t)TIM_BDTR_BK2E)\r
 205 /**\r
 206   * @}\r
 207   */\r
 208     \r
 209 /** @defgroup TIMEx_Break2_Polarity TIMEx Break2 Polarity\r
 210   * @{\r
 211   */\r
 212 #define TIM_BREAK2POLARITY_LOW        ((uint32_t)0x00000000)\r
 213 #define TIM_BREAK2POLARITY_HIGH       (TIM_BDTR_BK2P)\r
 214 /**\r
 215   * @}\r
 216   */\r
 217  \r
 218 /** @defgroup TIMEx_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3\r
 219   * @{\r
 220   */\r
 221 #define TIM_GROUPCH5_NONE       (uint32_t)0x00000000  /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */\r
 222 #define TIM_GROUPCH5_OC1REFC    (TIM_CCR5_GC5C1)      /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */\r
 223 #define TIM_GROUPCH5_OC2REFC    (TIM_CCR5_GC5C2)      /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */\r
 224 #define TIM_GROUPCH5_OC3REFC    (TIM_CCR5_GC5C3)       /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */\r
 225 /**\r
 226   * @}\r
 227   */\r
 228         \r
 229 /** @defgroup TIMEx_Master_Mode_Selection_2 TIM  Extended Master Mode Selection 2 (TRGO2)\r
 230   * @{\r
 231   */  \r
 232 #define TIM_TRGO2_RESET                          ((uint32_t)0x00000000)             \r
 233 #define TIM_TRGO2_ENABLE                         ((uint32_t)(TIM_CR2_MMS2_0))          \r
 234 #define TIM_TRGO2_UPDATE                         ((uint32_t)(TIM_CR2_MMS2_1))\r
 235 #define TIM_TRGO2_OC1                            ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))   \r
 236 #define TIM_TRGO2_OC1REF                         ((uint32_t)(TIM_CR2_MMS2_2))           \r
 237 #define TIM_TRGO2_OC2REF                         ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))          \r
 238 #define TIM_TRGO2_OC3REF                         ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1))           \r
 239 #define TIM_TRGO2_OC4REF                         ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))  \r
 240 #define TIM_TRGO2_OC5REF                         ((uint32_t)(TIM_CR2_MMS2_3))   \r
 241 #define TIM_TRGO2_OC6REF                         ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0))   \r
 242 #define TIM_TRGO2_OC4REF_RISINGFALLING           ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1))   \r
 243 #define TIM_TRGO2_OC6REF_RISINGFALLING           ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))   \r
 244 #define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING    ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2))   \r
 245 #define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING   ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))   \r
 246 #define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING    ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1))   \r
 247 #define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING   ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))   \r
 248 /**\r
 249   * @}\r
 250   */ \r
 251     \r
 252 /** @defgroup TIMEx_Slave_Mode TIM  Extended Slave mode\r
 253   * @{\r
 254   */\r
 255 #define TIM_SLAVEMODE_DISABLE                ((uint32_t)0x0000)\r
 256 #define TIM_SLAVEMODE_RESET                  ((uint32_t)(TIM_SMCR_SMS_2))\r
 257 #define TIM_SLAVEMODE_GATED                  ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0))\r
 258 #define TIM_SLAVEMODE_TRIGGER                ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1))\r
 259 #define TIM_SLAVEMODE_EXTERNAL1              ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0))\r
 260 #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER  ((uint32_t)(TIM_SMCR_SMS_3))\r
 261 /**\r
 262   * @}\r
 263   */\r
 264 /**\r
 265   * @}\r
 266   */\r
 267 \r
 268 /* Exported macro ------------------------------------------------------------*/\r
 269 /** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros\r
 270   * @{\r
 271   */  \r
 272 \r
 273 /**\r
 274   * @brief  Sets the TIM Capture Compare Register value on runtime without\r
 275   *         calling another time ConfigChannel function.\r
 276   * @param  __HANDLE__: TIM handle.\r
 277   * @param  __CHANNEL__ : TIM Channels to be configured.\r
 278   *          This parameter can be one of the following values:\r
 279   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
 280   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
 281   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
 282   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
 283   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected\r
 284   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected\r
 285   * @param  __COMPARE__: specifies the Capture Compare register new value.\r
 286   * @retval None\r
 287   */\r
 288 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \\r
 289 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\\r
 290  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\\r
 291  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\\r
 292  ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\\r
 293  ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\\r
 294  ((__HANDLE__)->Instance->CCR6 |= (__COMPARE__)))\r
 295 \r
 296 /**\r
 297   * @brief  Gets the TIM Capture Compare Register value on runtime\r
 298   * @param  __HANDLE__: TIM handle.\r
 299   * @param  __CHANNEL__ : TIM Channel associated with the capture compare register\r
 300   *          This parameter can be one of the following values:\r
 301   *            @arg TIM_CHANNEL_1: get capture/compare 1 register value\r
 302   *            @arg TIM_CHANNEL_2: get capture/compare 2 register value\r
 303   *            @arg TIM_CHANNEL_3: get capture/compare 3 register value\r
 304   *            @arg TIM_CHANNEL_4: get capture/compare 4 register value\r
 305   *            @arg TIM_CHANNEL_5: get capture/compare 5 register value\r
 306   *            @arg TIM_CHANNEL_6: get capture/compare 6 register value\r
 307   * @retval None\r
 308   */\r
 309 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \\r
 310 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\\r
 311  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\\r
 312  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\\r
 313  ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\\r
 314  ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\\r
 315  ((__HANDLE__)->Instance->CCR6))\r
 316 \r
 317 /**\r
 318   * @}\r
 319   */ \r
 320 \r
 321 /* Exported functions --------------------------------------------------------*/\r
 322 /** @addtogroup TIMEx_Exported_Functions\r
 323   * @{\r
 324   */\r
 325 \r
 326 /** @addtogroup TIMEx_Exported_Functions_Group1\r
 327   * @{\r
 328   */\r
 329 /*  Timer Hall Sensor functions  **********************************************/\r
 330 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef* htim, TIM_HallSensor_InitTypeDef* sConfig);\r
 331 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef* htim);\r
 332 \r
 333 void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef* htim);\r
 334 void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef* htim);\r
 335 \r
 336  /* Blocking mode: Polling */\r
 337 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef* htim);\r
 338 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef* htim);\r
 339 /* Non-Blocking mode: Interrupt */\r
 340 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef* htim);\r
 341 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef* htim);\r
 342 /* Non-Blocking mode: DMA */\r
 343 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef* htim, uint32_t *pData, uint16_t Length);\r
 344 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef* htim);\r
 345 /**\r
 346   * @}\r
 347   */\r
 348 \r
 349 /** @addtogroup TIMEx_Exported_Functions_Group2\r
 350   * @{\r
 351   */\r
 352 /*  Timer Complementary Output Compare functions  *****************************/\r
 353 /* Blocking mode: Polling */\r
 354 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);\r
 355 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef* htim, uint32_t Channel);\r
 356 \r
 357 /* Non-Blocking mode: Interrupt */\r
 358 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef* htim, uint32_t Channel);\r
 359 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Channel);\r
 360 \r
 361 /* Non-Blocking mode: DMA */\r
 362 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\r
 363 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);\r
 364 /**\r
 365   * @}\r
 366   */\r
 367 \r
 368 /** @addtogroup TIMEx_Exported_Functions_Group3\r
 369   * @{\r
 370   */\r
 371 /*  Timer Complementary PWM functions  ****************************************/\r
 372 /* Blocking mode: Polling */\r
 373 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);\r
 374 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef* htim, uint32_t Channel);\r
 375 \r
 376 /* Non-Blocking mode: Interrupt */\r
 377 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef* htim, uint32_t Channel);\r
 378 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Channel);\r
 379 /* Non-Blocking mode: DMA */\r
 380 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\r
 381 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);\r
 382 /**\r
 383   * @}\r
 384   */\r
 385 \r
 386 /** @addtogroup TIMEx_Exported_Functions_Group4\r
 387   * @{\r
 388   */\r
 389 /*  Timer Complementary One Pulse functions  **********************************/\r
 390 /* Blocking mode: Polling */\r
 391 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef* htim, uint32_t OutputChannel);\r
 392 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef* htim, uint32_t OutputChannel);\r
 393 \r
 394 /* Non-Blocking mode: Interrupt */\r
 395 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);\r
 396 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);\r
 397 /**\r
 398   * @}\r
 399   */\r
 400 \r
 401 /** @addtogroup TIMEx_Exported_Functions_Group5\r
 402   * @{\r
 403   */\r
 404 /* Extension Control functions  ************************************************/\r
 405 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef* htim, uint32_t  InputTrigger, uint32_t  CommutationSource);\r
 406 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef* htim, uint32_t  InputTrigger, uint32_t  CommutationSource);\r
 407 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef* htim, uint32_t  InputTrigger, uint32_t  CommutationSource);\r
 408 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef* htim, TIM_MasterConfigTypeDef * sMasterConfig);\r
 409 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef* htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);\r
 410 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef* htim, uint32_t Remap);\r
 411 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t OCRef);\r
 412 /**\r
 413   * @}\r
 414   */\r
 415 \r
 416 /** @addtogroup TIMEx_Exported_Functions_Group6\r
 417   * @{\r
 418   */ \r
 419 /* Extension Callback *********************************************************/\r
 420 void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef* htim);\r
 421 void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef* htim);\r
 422 void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);\r
 423 /**\r
 424   * @}\r
 425   */\r
 426 \r
 427 /** @addtogroup TIMEx_Exported_Functions_Group7\r
 428   * @{\r
 429   */\r
 430 /* Extension Peripheral State functions  **************************************/\r
 431 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef* htim);\r
 432 /**\r
 433   * @}\r
 434   */ \r
 435 \r
 436 /**\r
 437   * @}\r
 438   */ \r
 439 \r
 440 /* Private types -------------------------------------------------------------*/\r
 441 /* Private variables ---------------------------------------------------------*/\r
 442 /* Private constants ---------------------------------------------------------*/\r
 443 /* Private macros ------------------------------------------------------------*/\r
 444 /** @defgroup TIMEx_Private_Macros TIM Private Macros\r
 445   * @{\r
 446   */\r
 447 #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \\r
 448                                   ((CHANNEL) == TIM_CHANNEL_2) || \\r
 449                                   ((CHANNEL) == TIM_CHANNEL_3) || \\r
 450                                   ((CHANNEL) == TIM_CHANNEL_4) || \\r
 451                                   ((CHANNEL) == TIM_CHANNEL_5) || \\r
 452                                   ((CHANNEL) == TIM_CHANNEL_6) || \\r
 453                                   ((CHANNEL) == TIM_CHANNEL_ALL))\r
 454                                  \r
 455 #define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \\r
 456                                        ((CHANNEL) == TIM_CHANNEL_2))\r
 457                                       \r
 458 #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \\r
 459                                       ((CHANNEL) == TIM_CHANNEL_2))                                       \r
 460 \r
 461 #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \\r
 462                                                 ((CHANNEL) == TIM_CHANNEL_2) || \\r
 463                                                 ((CHANNEL) == TIM_CHANNEL_3))\r
 464 #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1)               || \\r
 465                                ((MODE) == TIM_OCMODE_PWM2)               || \\r
 466                                ((MODE) == TIM_OCMODE_COMBINED_PWM1)      || \\r
 467                                ((MODE) == TIM_OCMODE_COMBINED_PWM2)      || \\r
 468                                ((MODE) == TIM_OCMODE_ASSYMETRIC_PWM1)    || \\r
 469                                ((MODE) == TIM_OCMODE_ASSYMETRIC_PWM2))\r
 470                               \r
 471 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING)             || \\r
 472                              ((MODE) == TIM_OCMODE_ACTIVE)             || \\r
 473                              ((MODE) == TIM_OCMODE_INACTIVE)           || \\r
 474                              ((MODE) == TIM_OCMODE_TOGGLE)             || \\r
 475                              ((MODE) == TIM_OCMODE_FORCED_ACTIVE)      || \\r
 476                              ((MODE) == TIM_OCMODE_FORCED_INACTIVE)    || \\r
 477                              ((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \\r
 478                              ((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM2))\r
 479 #define IS_TIM_REMAP(__TIM_REMAP__)      (((__TIM_REMAP__) == TIM_TIM2_TIM8_TRGO)||\\r
 480                                       ((__TIM_REMAP__) == TIM_TIM2_ETH_PTP)||\\r
 481                                       ((__TIM_REMAP__) == TIM_TIM2_USBFS_SOF)||\\r
 482                                       ((__TIM_REMAP__) == TIM_TIM2_USBHS_SOF)||\\r
 483                                       ((__TIM_REMAP__) == TIM_TIM5_GPIO)||\\r
 484                                       ((__TIM_REMAP__) == TIM_TIM5_LSI)||\\r
 485                                       ((__TIM_REMAP__) == TIM_TIM5_LSE)||\\r
 486                                       ((__TIM_REMAP__) == TIM_TIM5_RTC)||\\r
 487                                       ((__TIM_REMAP__) == TIM_TIM11_GPIO)||\\r
 488                                       ((__TIM_REMAP__) == TIM_TIM11_SPDIFRX)||\\r
 489                                       ((__TIM_REMAP__) == TIM_TIM11_HSE)||\\r
 490                                       ((__TIM_REMAP__) == TIM_TIM11_MCO1))  \r
 491 #define IS_TIM_DEADTIME(__DEADTIME__)      ((__DEADTIME__) <= 0xFF) \r
 492 #define IS_TIM_BREAK_FILTER(__FILTER__) ((__FILTER__) <= 0xF)\r
 493 #define IS_TIM_CLEARINPUT_SOURCE(MODE) (((MODE) == TIM_CLEARINPUTSOURCE_ETR)      || \\r
 494                                         ((MODE) == TIM_CLEARINPUTSOURCE_OCREFCLR)  || \\r
 495                                         ((MODE) == TIM_CLEARINPUTSOURCE_NONE))\r
 496 #define IS_TIM_BREAK2_STATE(STATE) (((STATE) == TIM_BREAK2_ENABLE) || \\r
 497                                     ((STATE) == TIM_BREAK2_DISABLE))\r
 498 #define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \\r
 499                                               ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))\r
 500 #define IS_TIM_GROUPCH5(OCREF) ((((OCREF) & 0x1FFFFFFF) == 0x00000000))\r
 501 #define IS_TIM_TRGO2_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO2_RESET)                        || \\r
 502                                      ((SOURCE) == TIM_TRGO2_ENABLE)                       || \\r
 503                                      ((SOURCE) == TIM_TRGO2_UPDATE)                       || \\r
 504                                      ((SOURCE) == TIM_TRGO2_OC1)                          || \\r
 505                                      ((SOURCE) == TIM_TRGO2_OC1REF)                       || \\r
 506                                      ((SOURCE) == TIM_TRGO2_OC2REF)                       || \\r
 507                                      ((SOURCE) == TIM_TRGO2_OC3REF)                       || \\r
 508                                      ((SOURCE) == TIM_TRGO2_OC3REF)                       || \\r
 509                                      ((SOURCE) == TIM_TRGO2_OC4REF)                       || \\r
 510                                      ((SOURCE) == TIM_TRGO2_OC5REF)                       || \\r
 511                                      ((SOURCE) == TIM_TRGO2_OC6REF)                       || \\r
 512                                      ((SOURCE) == TIM_TRGO2_OC4REF_RISINGFALLING)         || \\r
 513                                      ((SOURCE) == TIM_TRGO2_OC6REF_RISINGFALLING)         || \\r
 514                                      ((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING)  || \\r
 515                                      ((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \\r
 516                                      ((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING)  || \\r
 517                                      ((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))\r
 518 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE)   || \\r
 519                                  ((MODE) == TIM_SLAVEMODE_RESET)     || \\r
 520                                  ((MODE) == TIM_SLAVEMODE_GATED)     || \\r
 521                                  ((MODE) == TIM_SLAVEMODE_TRIGGER)   || \\r
 522                                  ((MODE) == TIM_SLAVEMODE_EXTERNAL1) || \\r
 523                                  ((MODE) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))\r
 524 \r
 525 /**\r
 526   * @}\r
 527   */  \r
 528 \r
 529 /* Private functions ---------------------------------------------------------*/\r
 530 /** @defgroup TIMEx_Private_Functions TIM Private Functions\r
 531   * @{\r
 532   */\r
 533   \r
 534 /**\r
 535   * @}\r
 536   */\r
 537 \r
 538 /**\r
 539   * @}\r
 540   */ \r
 541 \r
 542 /**\r
 543   * @}\r
 544   */\r
 545     \r
 546 #ifdef __cplusplus\r
 547 }\r
 548 #endif\r
 549 \r
 550 #endif /* __STM32F7xx_HAL_TIM_EX_H */\r
 551 \r
 552 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r