2 ******************************************************************************
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3 * @file stm32f7xx_hal_nor.c
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4 * @author MCD Application Team
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6 * @date 24-March-2015
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7 * @brief NOR HAL module driver.
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8 * This file provides a generic firmware to drive NOR memories mounted
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9 * as external device.
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12 ==============================================================================
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13 ##### How to use this driver #####
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14 ==============================================================================
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16 This driver is a generic layered driver which contains a set of APIs used to
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17 control NOR flash memories. It uses the FMC layer functions to interface
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18 with NOR devices. This driver is used as follows:
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20 (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
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21 with control and timing parameters for both normal and extended mode.
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23 (+) Read NOR flash memory manufacturer code and device IDs using the function
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24 HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
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25 structure declared by the function caller.
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27 (+) Access NOR flash memory by read/write data unit operations using the functions
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28 HAL_NOR_Read(), HAL_NOR_Program().
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30 (+) Perform NOR flash erase block/chip operations using the functions
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31 HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
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33 (+) Read the NOR flash CFI (common flash interface) IDs using the function
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34 HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
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35 structure declared by the function caller.
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37 (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
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38 HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
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40 (+) You can monitor the NOR device HAL state by calling the function
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43 (@) This driver is a set of generic APIs which handle standard NOR flash operations.
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44 If a NOR flash device contains different operations and/or implementations,
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45 it should be implemented separately.
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47 *** NOR HAL driver macros list ***
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48 =============================================
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50 Below the list of most used macros in NOR HAL driver.
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52 (+) NOR_WRITE : NOR memory write data to specified address
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55 ******************************************************************************
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58 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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60 * Redistribution and use in source and binary forms, with or without modification,
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61 * are permitted provided that the following conditions are met:
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62 * 1. Redistributions of source code must retain the above copyright notice,
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63 * this list of conditions and the following disclaimer.
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64 * 2. Redistributions in binary form must reproduce the above copyright notice,
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65 * this list of conditions and the following disclaimer in the documentation
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66 * and/or other materials provided with the distribution.
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67 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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68 * may be used to endorse or promote products derived from this software
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69 * without specific prior written permission.
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71 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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72 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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73 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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74 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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75 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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76 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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77 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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78 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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79 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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80 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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82 ******************************************************************************
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85 /* Includes ------------------------------------------------------------------*/
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86 #include "stm32f7xx_hal.h"
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88 /** @addtogroup STM32F7xx_HAL_Driver
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92 /** @defgroup NOR NOR
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93 * @brief NOR driver modules
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96 #ifdef HAL_NOR_MODULE_ENABLED
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97 #if defined(STM32F756xx) || defined(STM32F746xx)
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99 /* Private typedef -----------------------------------------------------------*/
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100 /* Private define ------------------------------------------------------------*/
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102 /** @defgroup NOR_Private_Defines NOR Private Defines
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106 /* Constants to define address to set to write a command */
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107 #define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
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108 #define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
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109 #define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
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110 #define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555
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111 #define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555
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112 #define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA
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113 #define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555
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115 /* Constants to define data to program a command */
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116 #define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0
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117 #define NOR_CMD_DATA_FIRST (uint16_t)0x00AA
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118 #define NOR_CMD_DATA_SECOND (uint16_t)0x0055
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119 #define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090
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120 #define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0
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121 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080
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122 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA
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123 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055
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124 #define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010
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125 #define NOR_CMD_DATA_CFI (uint16_t)0x0098
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127 #define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25
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128 #define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
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129 #define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
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131 /* Mask on NOR STATUS REGISTER */
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132 #define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
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133 #define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040
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139 /* Private macro -------------------------------------------------------------*/
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140 /* Private variables ---------------------------------------------------------*/
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141 /* Private functions ---------------------------------------------------------*/
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142 /* Exported functions --------------------------------------------------------*/
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143 /** @defgroup NOR_Exported_Functions NOR Exported Functions
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147 /** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
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148 * @brief Initialization and Configuration functions
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151 ==============================================================================
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152 ##### NOR Initialization and de_initialization functions #####
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153 ==============================================================================
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155 This section provides functions allowing to initialize/de-initialize
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163 * @brief Perform the NOR memory Initialization sequence
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164 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
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165 * the configuration information for NOR module.
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166 * @param Timing: pointer to NOR control timing structure
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167 * @param ExtTiming: pointer to NOR extended mode timing structure
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168 * @retval HAL status
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170 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
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172 /* Check the NOR handle parameter */
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178 if(hnor->State == HAL_NOR_STATE_RESET)
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180 /* Allocate lock resource and initialize it */
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181 hnor->Lock = HAL_UNLOCKED;
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182 /* Initialize the low level hardware (MSP) */
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183 HAL_NOR_MspInit(hnor);
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186 /* Initialize NOR control Interface */
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187 FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
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189 /* Initialize NOR timing Interface */
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190 FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
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192 /* Initialize NOR extended mode timing Interface */
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193 FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
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195 /* Enable the NORSRAM device */
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196 __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
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198 /* Check the NOR controller state */
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199 hnor->State = HAL_NOR_STATE_READY;
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205 * @brief Perform NOR memory De-Initialization sequence
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206 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
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207 * the configuration information for NOR module.
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208 * @retval HAL status
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210 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
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212 /* De-Initialize the low level hardware (MSP) */
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213 HAL_NOR_MspDeInit(hnor);
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215 /* Configure the NOR registers with their reset values */
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216 FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
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218 /* Update the NOR controller state */
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219 hnor->State = HAL_NOR_STATE_RESET;
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222 __HAL_UNLOCK(hnor);
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228 * @brief NOR MSP Init
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229 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
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230 * the configuration information for NOR module.
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233 __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
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235 /* NOTE : This function Should not be modified, when the callback is needed,
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236 the HAL_NOR_MspInit could be implemented in the user file
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241 * @brief NOR MSP DeInit
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242 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
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243 * the configuration information for NOR module.
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246 __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
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248 /* NOTE : This function Should not be modified, when the callback is needed,
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249 the HAL_NOR_MspDeInit could be implemented in the user file
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254 * @brief NOR MSP Wait for Ready/Busy signal
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255 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
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256 * the configuration information for NOR module.
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257 * @param Timeout: Maximum timeout value
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260 __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
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262 /* NOTE : This function Should not be modified, when the callback is needed,
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263 the HAL_NOR_MspWait could be implemented in the user file
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271 /** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
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272 * @brief Input Output and memory control functions
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275 ==============================================================================
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276 ##### NOR Input and Output functions #####
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277 ==============================================================================
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279 This section provides functions allowing to use and control the NOR memory
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286 * @brief Read NOR flash IDs
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287 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
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288 * the configuration information for NOR module.
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289 * @param pNOR_ID : pointer to NOR ID structure
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290 * @retval HAL status
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292 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
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294 uint32_t deviceaddress = 0;
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296 /* Process Locked */
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299 /* Check the NOR controller state */
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300 if(hnor->State == HAL_NOR_STATE_BUSY)
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305 /* Select the NOR device address */
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306 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
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308 deviceaddress = NOR_MEMORY_ADRESS1;
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310 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
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312 deviceaddress = NOR_MEMORY_ADRESS2;
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314 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
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316 deviceaddress = NOR_MEMORY_ADRESS3;
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318 else /* FMC_NORSRAM_BANK4 */
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320 deviceaddress = NOR_MEMORY_ADRESS4;
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323 /* Update the NOR controller state */
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324 hnor->State = HAL_NOR_STATE_BUSY;
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326 /* Send read ID command */
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327 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
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328 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
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329 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
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331 /* Read the NOR IDs */
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332 pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, MC_ADDRESS);
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333 pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, DEVICE_CODE1_ADDR);
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334 pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, DEVICE_CODE2_ADDR);
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335 pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, DEVICE_CODE3_ADDR);
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337 /* Check the NOR controller state */
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338 hnor->State = HAL_NOR_STATE_READY;
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340 /* Process unlocked */
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341 __HAL_UNLOCK(hnor);
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347 * @brief Returns the NOR memory to Read mode.
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348 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
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349 * the configuration information for NOR module.
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350 * @retval HAL status
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352 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
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354 uint32_t deviceaddress = 0;
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356 /* Process Locked */
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359 /* Check the NOR controller state */
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360 if(hnor->State == HAL_NOR_STATE_BUSY)
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365 /* Select the NOR device address */
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366 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
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368 deviceaddress = NOR_MEMORY_ADRESS1;
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370 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
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372 deviceaddress = NOR_MEMORY_ADRESS2;
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374 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
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376 deviceaddress = NOR_MEMORY_ADRESS3;
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378 else /* FMC_NORSRAM_BANK4 */
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380 deviceaddress = NOR_MEMORY_ADRESS4;
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383 NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
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385 /* Check the NOR controller state */
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386 hnor->State = HAL_NOR_STATE_READY;
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388 /* Process unlocked */
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389 __HAL_UNLOCK(hnor);
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395 * @brief Read data from NOR memory
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396 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
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397 * the configuration information for NOR module.
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398 * @param pAddress: pointer to Device address
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399 * @param pData : pointer to read data
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400 * @retval HAL status
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402 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
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404 uint32_t deviceaddress = 0;
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406 /* Process Locked */
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409 /* Check the NOR controller state */
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410 if(hnor->State == HAL_NOR_STATE_BUSY)
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415 /* Select the NOR device address */
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416 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
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418 deviceaddress = NOR_MEMORY_ADRESS1;
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420 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
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422 deviceaddress = NOR_MEMORY_ADRESS2;
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424 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
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426 deviceaddress = NOR_MEMORY_ADRESS3;
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428 else /* FMC_NORSRAM_BANK4 */
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430 deviceaddress = NOR_MEMORY_ADRESS4;
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433 /* Update the NOR controller state */
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434 hnor->State = HAL_NOR_STATE_BUSY;
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436 /* Send read data command */
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437 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
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438 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
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439 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
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441 /* Read the data */
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442 *pData = *(__IO uint32_t *)(uint32_t)pAddress;
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444 /* Check the NOR controller state */
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445 hnor->State = HAL_NOR_STATE_READY;
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447 /* Process unlocked */
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448 __HAL_UNLOCK(hnor);
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454 * @brief Program data to NOR memory
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455 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
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456 * the configuration information for NOR module.
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457 * @param pAddress: Device address
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458 * @param pData : pointer to the data to write
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459 * @retval HAL status
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461 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
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463 uint32_t deviceaddress = 0;
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465 /* Process Locked */
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468 /* Check the NOR controller state */
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469 if(hnor->State == HAL_NOR_STATE_BUSY)
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474 /* Select the NOR device address */
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475 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
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477 deviceaddress = NOR_MEMORY_ADRESS1;
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479 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
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481 deviceaddress = NOR_MEMORY_ADRESS2;
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483 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
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485 deviceaddress = NOR_MEMORY_ADRESS3;
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487 else /* FMC_NORSRAM_BANK4 */
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489 deviceaddress = NOR_MEMORY_ADRESS4;
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492 /* Update the NOR controller state */
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493 hnor->State = HAL_NOR_STATE_BUSY;
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495 /* Send program data command */
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496 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
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497 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
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498 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
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500 /* Write the data */
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501 NOR_WRITE(pAddress, *pData);
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503 /* Check the NOR controller state */
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504 hnor->State = HAL_NOR_STATE_READY;
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506 /* Process unlocked */
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507 __HAL_UNLOCK(hnor);
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513 * @brief Reads a half-word buffer from the NOR memory.
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514 * @param hnor: pointer to the NOR handle
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515 * @param uwAddress: NOR memory internal address to read from.
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516 * @param pData: pointer to the buffer that receives the data read from the
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518 * @param uwBufferSize : number of Half word to read.
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519 * @retval HAL status
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521 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
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523 uint32_t deviceaddress = 0;
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525 /* Process Locked */
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528 /* Check the NOR controller state */
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529 if(hnor->State == HAL_NOR_STATE_BUSY)
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534 /* Select the NOR device address */
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535 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
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537 deviceaddress = NOR_MEMORY_ADRESS1;
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539 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
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541 deviceaddress = NOR_MEMORY_ADRESS2;
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543 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
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545 deviceaddress = NOR_MEMORY_ADRESS3;
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547 else /* FMC_NORSRAM_BANK4 */
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549 deviceaddress = NOR_MEMORY_ADRESS4;
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552 /* Update the NOR controller state */
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553 hnor->State = HAL_NOR_STATE_BUSY;
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555 /* Send read data command */
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556 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
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557 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
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558 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
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561 while( uwBufferSize > 0)
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563 *pData++ = *(__IO uint16_t *)uwAddress;
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568 /* Check the NOR controller state */
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569 hnor->State = HAL_NOR_STATE_READY;
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571 /* Process unlocked */
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572 __HAL_UNLOCK(hnor);
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578 * @brief Writes a half-word buffer to the NOR memory. This function must be used
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579 only with S29GL128P NOR memory.
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580 * @param hnor: pointer to the NOR handle
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581 * @param uwAddress: NOR memory internal start write address
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582 * @param pData: pointer to source data buffer.
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583 * @param uwBufferSize: Size of the buffer to write
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584 * @retval HAL status
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586 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
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588 uint16_t * p_currentaddress = (uint16_t *)NULL;
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589 uint16_t * p_endaddress = (uint16_t *)NULL;
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590 uint32_t lastloadedaddress = 0, deviceaddress = 0;
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592 /* Process Locked */
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595 /* Check the NOR controller state */
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596 if(hnor->State == HAL_NOR_STATE_BUSY)
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601 /* Select the NOR device address */
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602 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
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604 deviceaddress = NOR_MEMORY_ADRESS1;
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606 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
\r
608 deviceaddress = NOR_MEMORY_ADRESS2;
\r
610 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
\r
612 deviceaddress = NOR_MEMORY_ADRESS3;
\r
614 else /* FMC_NORSRAM_BANK4 */
\r
616 deviceaddress = NOR_MEMORY_ADRESS4;
\r
619 /* Update the NOR controller state */
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620 hnor->State = HAL_NOR_STATE_BUSY;
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622 /* Initialize variables */
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623 p_currentaddress = (uint16_t*)((uint32_t)(uwAddress));
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624 p_endaddress = p_currentaddress + (uwBufferSize-1);
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625 lastloadedaddress = (uint32_t)(uwAddress);
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627 /* Issue unlock command sequence */
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628 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
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629 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
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631 /* Write Buffer Load Command */
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632 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
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633 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, uwAddress), (uwBufferSize - 1));
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635 /* Load Data into NOR Buffer */
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636 while(p_currentaddress <= p_endaddress)
\r
638 /* Store last loaded address & data value (for polling) */
\r
639 lastloadedaddress = (uint32_t)p_currentaddress;
\r
641 NOR_WRITE(p_currentaddress, *pData++);
\r
643 p_currentaddress ++;
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646 NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
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648 /* Check the NOR controller state */
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649 hnor->State = HAL_NOR_STATE_READY;
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651 /* Process unlocked */
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652 __HAL_UNLOCK(hnor);
\r
659 * @brief Erase the specified block of the NOR memory
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660 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
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661 * the configuration information for NOR module.
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662 * @param BlockAddress : Block to erase address
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663 * @param Address: Device address
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664 * @retval HAL status
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666 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
\r
668 uint32_t deviceaddress = 0;
\r
670 /* Process Locked */
\r
673 /* Check the NOR controller state */
\r
674 if(hnor->State == HAL_NOR_STATE_BUSY)
\r
679 /* Select the NOR device address */
\r
680 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
\r
682 deviceaddress = NOR_MEMORY_ADRESS1;
\r
684 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
\r
686 deviceaddress = NOR_MEMORY_ADRESS2;
\r
688 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
\r
690 deviceaddress = NOR_MEMORY_ADRESS3;
\r
692 else /* FMC_NORSRAM_BANK4 */
\r
694 deviceaddress = NOR_MEMORY_ADRESS4;
\r
697 /* Update the NOR controller state */
\r
698 hnor->State = HAL_NOR_STATE_BUSY;
\r
700 /* Send block erase command sequence */
\r
701 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
\r
702 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
\r
703 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
\r
704 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
\r
705 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
\r
706 NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
\r
708 /* Check the NOR memory status and update the controller state */
\r
709 hnor->State = HAL_NOR_STATE_READY;
\r
711 /* Process unlocked */
\r
712 __HAL_UNLOCK(hnor);
\r
719 * @brief Erase the entire NOR chip.
\r
720 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
\r
721 * the configuration information for NOR module.
\r
722 * @param Address : Device address
\r
723 * @retval HAL status
\r
725 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
\r
727 uint32_t deviceaddress = 0;
\r
729 /* Process Locked */
\r
732 /* Check the NOR controller state */
\r
733 if(hnor->State == HAL_NOR_STATE_BUSY)
\r
738 /* Select the NOR device address */
\r
739 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
\r
741 deviceaddress = NOR_MEMORY_ADRESS1;
\r
743 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
\r
745 deviceaddress = NOR_MEMORY_ADRESS2;
\r
747 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
\r
749 deviceaddress = NOR_MEMORY_ADRESS3;
\r
751 else /* FMC_NORSRAM_BANK4 */
\r
753 deviceaddress = NOR_MEMORY_ADRESS4;
\r
756 /* Update the NOR controller state */
\r
757 hnor->State = HAL_NOR_STATE_BUSY;
\r
759 /* Send NOR chip erase command sequence */
\r
760 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
\r
761 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
\r
762 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
\r
763 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
\r
764 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
\r
765 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
\r
767 /* Check the NOR memory status and update the controller state */
\r
768 hnor->State = HAL_NOR_STATE_READY;
\r
770 /* Process unlocked */
\r
771 __HAL_UNLOCK(hnor);
\r
777 * @brief Read NOR flash CFI IDs
\r
778 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
\r
779 * the configuration information for NOR module.
\r
780 * @param pNOR_CFI : pointer to NOR CFI IDs structure
\r
781 * @retval HAL status
\r
783 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
\r
785 uint32_t deviceaddress = 0;
\r
787 /* Process Locked */
\r
790 /* Check the NOR controller state */
\r
791 if(hnor->State == HAL_NOR_STATE_BUSY)
\r
796 /* Select the NOR device address */
\r
797 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
\r
799 deviceaddress = NOR_MEMORY_ADRESS1;
\r
801 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
\r
803 deviceaddress = NOR_MEMORY_ADRESS2;
\r
805 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
\r
807 deviceaddress = NOR_MEMORY_ADRESS3;
\r
809 else /* FMC_NORSRAM_BANK4 */
\r
811 deviceaddress = NOR_MEMORY_ADRESS4;
\r
814 /* Update the NOR controller state */
\r
815 hnor->State = HAL_NOR_STATE_BUSY;
\r
817 /* Send read CFI query command */
\r
818 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
\r
820 /* read the NOR CFI information */
\r
821 pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI1_ADDRESS);
\r
822 pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI2_ADDRESS);
\r
823 pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI3_ADDRESS);
\r
824 pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI4_ADDRESS);
\r
826 /* Check the NOR controller state */
\r
827 hnor->State = HAL_NOR_STATE_READY;
\r
829 /* Process unlocked */
\r
830 __HAL_UNLOCK(hnor);
\r
839 /** @defgroup NOR_Exported_Functions_Group3 Control functions
\r
840 * @brief management functions
\r
843 ==============================================================================
\r
844 ##### NOR Control functions #####
\r
845 ==============================================================================
\r
847 This subsection provides a set of functions allowing to control dynamically
\r
855 * @brief Enables dynamically NOR write operation.
\r
856 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
\r
857 * the configuration information for NOR module.
\r
858 * @retval HAL status
\r
860 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
\r
862 /* Process Locked */
\r
865 /* Enable write operation */
\r
866 FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
\r
868 /* Update the NOR controller state */
\r
869 hnor->State = HAL_NOR_STATE_READY;
\r
871 /* Process unlocked */
\r
872 __HAL_UNLOCK(hnor);
\r
878 * @brief Disables dynamically NOR write operation.
\r
879 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
\r
880 * the configuration information for NOR module.
\r
881 * @retval HAL status
\r
883 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
\r
885 /* Process Locked */
\r
888 /* Update the SRAM controller state */
\r
889 hnor->State = HAL_NOR_STATE_BUSY;
\r
891 /* Disable write operation */
\r
892 FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
\r
894 /* Update the NOR controller state */
\r
895 hnor->State = HAL_NOR_STATE_PROTECTED;
\r
897 /* Process unlocked */
\r
898 __HAL_UNLOCK(hnor);
\r
907 /** @defgroup NOR_Exported_Functions_Group4 State functions
\r
908 * @brief Peripheral State functions
\r
911 ==============================================================================
\r
912 ##### NOR State functions #####
\r
913 ==============================================================================
\r
915 This subsection permits to get in run-time the status of the NOR controller
\r
923 * @brief return the NOR controller state
\r
924 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
\r
925 * the configuration information for NOR module.
\r
926 * @retval NOR controller state
\r
928 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
\r
930 return hnor->State;
\r
934 * @brief Returns the NOR operation status.
\r
935 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
\r
936 * the configuration information for NOR module.
\r
937 * @param Address: Device address
\r
938 * @param Timeout: NOR programming Timeout
\r
939 * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
\r
940 * or HAL_NOR_STATUS_TIMEOUT
\r
942 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
\r
944 HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
\r
945 uint16_t tmpSR1 = 0, tmpSR2 = 0;
\r
946 uint32_t tickstart = 0;
\r
948 /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
\r
949 HAL_NOR_MspWait(hnor, Timeout);
\r
951 /* Get the NOR memory operation status -------------------------------------*/
\r
954 tickstart = HAL_GetTick();
\r
955 while((status != HAL_NOR_STATUS_SUCCESS ) && (status != HAL_NOR_STATUS_TIMEOUT))
\r
957 /* Check for the Timeout */
\r
958 if(Timeout != HAL_MAX_DELAY)
\r
960 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
\r
962 status = HAL_NOR_STATUS_TIMEOUT;
\r
966 /* Read NOR status register (DQ6 and DQ5) */
\r
967 tmpSR1 = *(__IO uint16_t *)Address;
\r
968 tmpSR2 = *(__IO uint16_t *)Address;
\r
970 /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
\r
971 if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
\r
973 return HAL_NOR_STATUS_SUCCESS ;
\r
976 if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
\r
978 status = HAL_NOR_STATUS_ONGOING;
\r
981 tmpSR1 = *(__IO uint16_t *)Address;
\r
982 tmpSR2 = *(__IO uint16_t *)Address;
\r
984 /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
\r
985 if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
\r
987 return HAL_NOR_STATUS_SUCCESS;
\r
989 if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
\r
991 return HAL_NOR_STATUS_ERROR;
\r
995 /* Return the operation status */
\r
1006 #endif /* STM32F756xx || STM32F746xx */
\r
1007 #endif /* HAL_NOR_MODULE_ENABLED */
\r
1016 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
\r