2 ******************************************************************************
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3 * @file stm32f7xx_hal_rcc_ex.c
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4 * @author MCD Application Team
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6 * @date 24-March-2015
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7 * @brief Extension RCC HAL module driver.
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8 * This file provides firmware functions to manage the following
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9 * functionalities RCC extension peripheral:
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10 * + Extended Peripheral Control functions
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12 ******************************************************************************
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15 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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17 * Redistribution and use in source and binary forms, with or without modification,
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18 * are permitted provided that the following conditions are met:
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19 * 1. Redistributions of source code must retain the above copyright notice,
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20 * this list of conditions and the following disclaimer.
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21 * 2. Redistributions in binary form must reproduce the above copyright notice,
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22 * this list of conditions and the following disclaimer in the documentation
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23 * and/or other materials provided with the distribution.
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24 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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25 * may be used to endorse or promote products derived from this software
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26 * without specific prior written permission.
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28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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31 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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39 ******************************************************************************
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42 /* Includes ------------------------------------------------------------------*/
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43 #include "stm32f7xx_hal.h"
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45 /** @addtogroup STM32F7xx_HAL_Driver
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49 /** @defgroup RCCEx RCCEx
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50 * @brief RCCEx HAL module driver
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54 #ifdef HAL_RCC_MODULE_ENABLED
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56 /* Private typedef -----------------------------------------------------------*/
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57 /* Private define ------------------------------------------------------------*/
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58 /** @defgroup RCCEx_Private_Defines RCCEx Private Defines
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62 #define PLLI2S_TIMEOUT_VALUE 100 /* Timeout value fixed to 100 ms */
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63 #define PLLSAI_TIMEOUT_VALUE 100 /* Timeout value fixed to 100 ms */
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68 /* Private macro -------------------------------------------------------------*/
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69 /** @defgroup RCCEx_Private_Macros RCCEx Private Macros
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76 /** @defgroup RCCEx_Private_Macros RCCEx Private Macros
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85 /* Private variables ---------------------------------------------------------*/
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86 /* Private function prototypes -----------------------------------------------*/
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87 /* Private functions ---------------------------------------------------------*/
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89 /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
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93 /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
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94 * @brief Extended Peripheral Control functions
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97 ===============================================================================
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98 ##### Extended Peripheral Control functions #####
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99 ===============================================================================
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101 This subsection provides a set of functions allowing to control the RCC Clocks
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104 (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
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105 select the RTC clock source; in this case the Backup domain will be reset in
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106 order to modify the RTC Clock source, as consequence RTC registers (including
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107 the backup registers) and RCC_BDCR register will be set to their reset values.
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113 * @brief Initializes the RCC extended peripherals clocks according to the specified
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114 * parameters in the RCC_PeriphCLKInitTypeDef.
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115 * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
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116 * contains the configuration information for the Extended Peripherals
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117 * clocks(I2S, SAI, LTDC RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...).
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119 * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
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120 * the RTC clock source; in this case the Backup domain will be reset in
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121 * order to modify the RTC Clock source, as consequence RTC registers (including
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122 * the backup registers) and RCC_BDCR register are set to their reset values.
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124 * @retval HAL status
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126 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
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128 uint32_t tickstart = 0;
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129 uint32_t tmpreg0 = 0;
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130 uint32_t tmpreg1 = 0;
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131 uint32_t plli2sused = 0;
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132 uint32_t pllsaiused = 0;
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134 /* Check the parameters */
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135 assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
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137 /*----------------------------------- I2S configuration ----------------------------------*/
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138 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
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140 /* Check the parameters */
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141 assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
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143 /* Configure I2S Clock source */
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144 __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
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146 /* Enable the PLLI2S when it's used as clock source for I2S */
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147 if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)
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153 /*------------------------------------ SAI1 configuration --------------------------------------*/
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154 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
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156 /* Check the parameters */
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157 assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
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159 /* Configure SAI1 Clock source */
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160 __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
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161 /* Enable the PLLI2S when it's used as clock source for SAI */
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162 if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
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166 /* Enable the PLLSAI when it's used as clock source for SAI */
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167 if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
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173 /*------------------------------------ SAI2 configuration --------------------------------------*/
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174 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
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176 /* Check the parameters */
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177 assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
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179 /* Configure SAI2 Clock source */
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180 __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
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182 /* Enable the PLLI2S when it's used as clock source for SAI */
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183 if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
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187 /* Enable the PLLSAI when it's used as clock source for SAI */
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188 if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
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194 /*-------------------------------------- SPDIF-RX Configuration -----------------------------------*/
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195 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
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200 /*------------------------------------ RTC configuration --------------------------------------*/
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201 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
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203 /* Enable Power Clock*/
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204 __HAL_RCC_PWR_CLK_ENABLE();
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206 /* Enable write access to Backup domain */
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207 PWR->CR1 |= PWR_CR1_DBP;
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209 /* Get Start Tick*/
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210 tickstart = HAL_GetTick();
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212 /* Wait for Backup domain Write protection disable */
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213 while((PWR->CR1 & PWR_CR1_DBP) == RESET)
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215 if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
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217 return HAL_TIMEOUT;
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221 /* Reset the Backup domain only if the RTC Clock source selection is modified */
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222 if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
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224 /* Store the content of BDCR register before the reset of Backup Domain */
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225 tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
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227 /* RTC Clock selection can be changed only if the Backup Domain is reset */
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228 __HAL_RCC_BACKUPRESET_FORCE();
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229 __HAL_RCC_BACKUPRESET_RELEASE();
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231 /* Restore the Content of BDCR register */
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232 RCC->BDCR = tmpreg0;
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235 /* If LSE is selected as RTC clock source, wait for LSE reactivation */
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236 if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
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238 /* Get Start Tick*/
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239 tickstart = HAL_GetTick();
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241 /* Wait till LSE is ready */
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242 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
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244 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
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246 return HAL_TIMEOUT;
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250 __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
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252 /*------------------------------------ TIM configuration --------------------------------------*/
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253 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
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255 /* Check the parameters */
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256 assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
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258 /* Configure Timer Prescaler */
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259 __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
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262 /*-------------------------------------- I2C1 Configuration -----------------------------------*/
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263 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
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265 /* Check the parameters */
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266 assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
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268 /* Configure the I2C1 clock source */
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269 __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
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272 /*-------------------------------------- I2C2 Configuration -----------------------------------*/
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273 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
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275 /* Check the parameters */
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276 assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
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278 /* Configure the I2C2 clock source */
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279 __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
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282 /*-------------------------------------- I2C3 Configuration -----------------------------------*/
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283 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
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285 /* Check the parameters */
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286 assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
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288 /* Configure the I2C3 clock source */
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289 __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
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292 /*-------------------------------------- I2C4 Configuration -----------------------------------*/
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293 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
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295 /* Check the parameters */
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296 assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
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298 /* Configure the I2C4 clock source */
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299 __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
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302 /*-------------------------------------- USART1 Configuration -----------------------------------*/
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303 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
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305 /* Check the parameters */
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306 assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
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308 /* Configure the USART1 clock source */
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309 __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
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312 /*-------------------------------------- USART2 Configuration -----------------------------------*/
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313 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
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315 /* Check the parameters */
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316 assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
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318 /* Configure the USART2 clock source */
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319 __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
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322 /*-------------------------------------- USART3 Configuration -----------------------------------*/
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323 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
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325 /* Check the parameters */
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326 assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
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328 /* Configure the USART3 clock source */
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329 __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
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332 /*-------------------------------------- UART4 Configuration -----------------------------------*/
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333 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
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335 /* Check the parameters */
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336 assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
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338 /* Configure the UART4 clock source */
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339 __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
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342 /*-------------------------------------- UART5 Configuration -----------------------------------*/
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343 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
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345 /* Check the parameters */
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346 assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
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348 /* Configure the UART5 clock source */
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349 __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
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352 /*-------------------------------------- USART6 Configuration -----------------------------------*/
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353 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6)
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355 /* Check the parameters */
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356 assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection));
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358 /* Configure the USART6 clock source */
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359 __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection);
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362 /*-------------------------------------- UART7 Configuration -----------------------------------*/
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363 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7)
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365 /* Check the parameters */
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366 assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection));
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368 /* Configure the UART7 clock source */
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369 __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection);
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372 /*-------------------------------------- UART8 Configuration -----------------------------------*/
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373 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8)
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375 /* Check the parameters */
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376 assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection));
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378 /* Configure the UART8 clock source */
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379 __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection);
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382 /*--------------------------------------- CEC Configuration -----------------------------------*/
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383 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
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385 /* Check the parameters */
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386 assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
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388 /* Configure the CEC clock source */
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389 __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
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392 /*-------------------------------------- CK48 Configuration -----------------------------------*/
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393 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
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395 /* Check the parameters */
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396 assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection));
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398 /* Configure the CLK48 source */
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399 __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
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401 /* Enable the PLLSAI when it's used as clock source for CK48 */
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402 if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)
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408 /*-------------------------------------- LTDC Configuration -----------------------------------*/
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409 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
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414 /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/
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415 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
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417 /* Check the parameters */
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418 assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
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420 /* Configure the LTPIM1 clock source */
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421 __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
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424 /*------------------------------------- SDMMC Configuration ------------------------------------*/
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425 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)
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427 /* Check the parameters */
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428 assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
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430 /* Configure the SDMMC1 clock source */
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431 __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
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434 /*-------------------------------------- PLLI2S Configuration ---------------------------------*/
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435 /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */
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436 if(plli2sused == 1)
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438 /* Disable the PLLI2S */
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439 __HAL_RCC_PLLI2S_DISABLE();
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441 /* Get Start Tick*/
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442 tickstart = HAL_GetTick();
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444 /* Wait till PLLI2S is disabled */
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445 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
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447 if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
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449 /* return in case of Timeout detected */
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450 return HAL_TIMEOUT;
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454 /* check for common PLLI2S Parameters */
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455 assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
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457 /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/
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458 if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)))
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460 /* check for Parameters */
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461 assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
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463 /* Read PLLI2SP and PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
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464 tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP));
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465 tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
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466 /* Configure the PLLI2S division factors */
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467 /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLM) */
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468 /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
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469 __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI2S.PLLI2SR);
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472 /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/
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473 if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
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474 ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
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476 /* Check for PLLI2S Parameters */
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477 assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
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478 /* Check for PLLI2S/DIVQ parameters */
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479 assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
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481 /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */
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482 tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP));
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483 tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
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484 /* Configure the PLLI2S division factors */
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485 /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
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486 /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
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487 /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
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488 __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, tmpreg0, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1);
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490 /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
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491 __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
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494 /*----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX -------------------*/
\r
495 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
\r
497 /* check for Parameters */
\r
498 assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
\r
500 /* Read PLLI2SR value from PLLI2SCFGR register (this value is not needed for SPDIF-RX configuration) */
\r
501 tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
\r
502 tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
\r
503 /* Configure the PLLI2S division factors */
\r
504 /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLM) */
\r
505 /* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
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506 __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1);
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509 /* Enable the PLLI2S */
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510 __HAL_RCC_PLLI2S_ENABLE();
\r
512 /* Get Start Tick*/
\r
513 tickstart = HAL_GetTick();
\r
515 /* Wait till PLLI2S is ready */
\r
516 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
\r
518 if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
\r
520 /* return in case of Timeout detected */
\r
521 return HAL_TIMEOUT;
\r
526 /*-------------------------------------- PLLSAI Configuration ---------------------------------*/
\r
527 /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */
\r
528 if(pllsaiused == 1)
\r
530 /* Disable PLLSAI Clock */
\r
531 __HAL_RCC_PLLSAI_DISABLE();
\r
533 /* Get Start Tick*/
\r
534 tickstart = HAL_GetTick();
\r
536 /* Wait till PLLSAI is disabled */
\r
537 while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
\r
539 if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
\r
541 /* return in case of Timeout detected */
\r
542 return HAL_TIMEOUT;
\r
546 /* Check the PLLSAI division factors */
\r
547 assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
\r
549 /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/
\r
550 if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||
\r
551 ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
\r
553 /* check for PLLSAIQ Parameter */
\r
554 assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
\r
555 /* check for PLLSAI/DIVQ Parameter */
\r
556 assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
\r
558 /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
\r
559 tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP));
\r
560 tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
\r
561 /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
\r
562 /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
\r
563 /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
\r
564 __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);
\r
566 /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
\r
567 __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
\r
570 /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/
\r
571 /* In Case of PLLI2S is selected as source clock for CK48 */
\r
572 if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP))
\r
574 /* check for Parameters */
\r
575 assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
\r
576 /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */
\r
577 tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
\r
578 tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
\r
580 /* Configure the PLLSAI division factors */
\r
581 /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) × (PLLI2SN/PLLM) */
\r
582 /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
\r
583 __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1);
\r
586 /*---------------------------- LTDC configuration -------------------------------*/
\r
587 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
\r
589 assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
\r
590 assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
\r
592 /* Read PLLSAIP and PLLSAIQ value from PLLSAICFGR register (these value are not needed for LTDC configuration) */
\r
593 tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
\r
594 tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP));
\r
596 /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
\r
597 /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
\r
598 /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
\r
599 __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, tmpreg0, PeriphClkInit->PLLSAI.PLLSAIR);
\r
601 /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
\r
602 __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
\r
605 /* Enable PLLSAI Clock */
\r
606 __HAL_RCC_PLLSAI_ENABLE();
\r
608 /* Get Start Tick*/
\r
609 tickstart = HAL_GetTick();
\r
611 /* Wait till PLLSAI is ready */
\r
612 while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
\r
614 if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
\r
616 /* return in case of Timeout detected */
\r
617 return HAL_TIMEOUT;
\r
625 * @brief Get the RCC_PeriphCLKInitTypeDef according to the internal
\r
626 * RCC configuration registers.
\r
627 * @param PeriphClkInit: pointer to the configured RCC_PeriphCLKInitTypeDef structure
\r
630 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
\r
632 uint32_t tempreg = 0;
\r
634 /* Set all possible values for the extended clock type parameter------------*/
\r
635 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_LPTIM1 |\
\r
636 RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\
\r
637 RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\
\r
638 RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_I2C4 |\
\r
639 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 |\
\r
640 RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_USART1 |\
\r
641 RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\
\r
642 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 |\
\r
643 RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART7 |\
\r
644 RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_SDMMC1 |\
\r
645 RCC_PERIPHCLK_CLK48;
\r
647 /* Get the PLLI2S Clock configuration -----------------------------------------------*/
\r
648 PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
\r
649 PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP));
\r
650 PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
\r
651 PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
\r
653 /* Get the PLLSAI Clock configuration -----------------------------------------------*/
\r
654 PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN));
\r
655 PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP));
\r
656 PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
\r
657 PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
\r
659 /* Get the PLLSAI/PLLI2S division factors -------------------------------------------*/
\r
660 PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR1_PLLI2SDIVQ));
\r
661 PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR1_PLLSAIDIVQ));
\r
662 PeriphClkInit->PLLSAIDivR = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVR) >> POSITION_VAL(RCC_DCKCFGR1_PLLSAIDIVR));
\r
664 /* Get the SAI1 clock configuration ----------------------------------------------*/
\r
665 PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
\r
667 /* Get the SAI2 clock configuration ----------------------------------------------*/
\r
668 PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();
\r
670 /* Get the I2S clock configuration ------------------------------------------*/
\r
671 PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2SCLKSOURCE();
\r
673 /* Get the I2C1 clock configuration ------------------------------------------*/
\r
674 PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
\r
676 /* Get the I2C2 clock configuration ------------------------------------------*/
\r
677 PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE();
\r
679 /* Get the I2C3 clock configuration ------------------------------------------*/
\r
680 PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();
\r
682 /* Get the I2C4 clock configuration ------------------------------------------*/
\r
683 PeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE();
\r
685 /* Get the USART1 clock configuration ------------------------------------------*/
\r
686 PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
\r
688 /* Get the USART2 clock configuration ------------------------------------------*/
\r
689 PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
\r
691 /* Get the USART3 clock configuration ------------------------------------------*/
\r
692 PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();
\r
694 /* Get the UART4 clock configuration ------------------------------------------*/
\r
695 PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE();
\r
697 /* Get the UART5 clock configuration ------------------------------------------*/
\r
698 PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE();
\r
700 /* Get the USART6 clock configuration ------------------------------------------*/
\r
701 PeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE();
\r
703 /* Get the UART7 clock configuration ------------------------------------------*/
\r
704 PeriphClkInit->Uart7ClockSelection = __HAL_RCC_GET_UART7_SOURCE();
\r
706 /* Get the UART8 clock configuration ------------------------------------------*/
\r
707 PeriphClkInit->Uart8ClockSelection = __HAL_RCC_GET_UART8_SOURCE();
\r
709 /* Get the LPTIM1 clock configuration ------------------------------------------*/
\r
710 PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
\r
712 /* Get the CEC clock configuration -----------------------------------------------*/
\r
713 PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
\r
715 /* Get the CK48 clock configuration -----------------------------------------------*/
\r
716 PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
\r
718 /* Get the SDMMC clock configuration -----------------------------------------------*/
\r
719 PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE();
\r
721 /* Get the RTC Clock configuration -----------------------------------------------*/
\r
722 tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
\r
723 PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
\r
725 /* Get the TIM Prescaler configuration --------------------------------------------*/
\r
726 if ((RCC->DCKCFGR1 & RCC_DCKCFGR1_TIMPRE) == RESET)
\r
728 PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
\r
732 PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
\r
737 * @brief Return the peripheral clock frequency for a given peripheral(SAI..)
\r
738 * @note Return 0 if peripheral clock identifier not managed by this API
\r
739 * @param PeriphClk: Peripheral clock identifier
\r
740 * This parameter can be one of the following values:
\r
741 * @arg RCC_PERIPHCLK_SAI1: SAI1 peripheral clock
\r
742 * @arg RCC_PERIPHCLK_SAI2: SAI2 peripheral clock
\r
743 * @retval Frequency in KHz
\r
745 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
\r
747 uint32_t tmpreg = 0;
\r
748 /* This variable used to store the SAI clock frequency (value in Hz) */
\r
749 uint32_t frequency = 0;
\r
750 /* This variable used to store the VCO Input (value in Hz) */
\r
751 uint32_t vcoinput = 0;
\r
752 /* This variable used to store the SAI clock source */
\r
753 uint32_t saiclocksource = 0;
\r
754 if ((PeriphClk == RCC_PERIPHCLK_SAI1) || (PeriphClk == RCC_PERIPHCLK_SAI2))
\r
756 saiclocksource = RCC->DCKCFGR1;
\r
757 saiclocksource &= (RCC_DCKCFGR1_SAI1SEL | RCC_DCKCFGR1_SAI2SEL);
\r
758 switch (saiclocksource)
\r
760 case 0: /* PLLSAI is the clock source for SAI*/
\r
762 /* Configure the PLLSAI division factor */
\r
763 /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
\r
764 if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
\r
766 /* In Case the PLL Source is HSI (Internal Clock) */
\r
767 vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
\r
771 /* In Case the PLL Source is HSE (External Clock) */
\r
772 vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
\r
774 /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
\r
775 /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
\r
776 tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24;
\r
777 frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg);
\r
779 /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
\r
780 tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1);
\r
781 frequency = frequency/(tmpreg);
\r
784 case RCC_DCKCFGR1_SAI1SEL_0: /* PLLI2S is the clock source for SAI*/
\r
785 case RCC_DCKCFGR1_SAI2SEL_0: /* PLLI2S is the clock source for SAI*/
\r
787 /* Configure the PLLI2S division factor */
\r
788 /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
\r
789 if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
\r
791 /* In Case the PLL Source is HSI (Internal Clock) */
\r
792 vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
\r
796 /* In Case the PLL Source is HSE (External Clock) */
\r
797 vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
\r
800 /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
\r
801 /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
\r
802 tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24;
\r
803 frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);
\r
805 /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
\r
806 tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1);
\r
807 frequency = frequency/(tmpreg);
\r
810 case RCC_DCKCFGR1_SAI1SEL_1: /* External clock is the clock source for SAI*/
\r
811 case RCC_DCKCFGR1_SAI2SEL_1: /* External clock is the clock source for SAI*/
\r
813 frequency = EXTERNAL_CLOCK_VALUE;
\r
833 #endif /* HAL_RCC_MODULE_ENABLED */
\r
842 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
\r