2 ******************************************************************************
\r
3 * @file stm32f7xx_hal_tim_ex.c
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4 * @author MCD Application Team
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6 * @date 24-March-2015
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7 * @brief TIM HAL module driver.
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8 * This file provides firmware functions to manage the following
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9 * functionalities of the Timer extension peripheral:
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10 * + Time Hall Sensor Interface Initialization
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11 * + Time Hall Sensor Interface Start
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12 * + Time Complementary signal bread and dead time configuration
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13 * + Time Master and Slave synchronization configuration
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14 * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
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15 * + Time OCRef clear configuration
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16 * + Timer remapping capabilities configuration
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18 ==============================================================================
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19 ##### TIMER Extended features #####
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20 ==============================================================================
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22 The Timer Extension features include:
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23 (#) Complementary outputs with programmable dead-time for :
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26 (++) PWM generation (Edge and Center-aligned Mode)
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27 (++) One-pulse mode output
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28 (#) Synchronization circuit to control the timer with external signals and to
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29 interconnect several timers together.
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30 (#) Break input to put the timer output signals in reset state or in a known state.
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31 (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
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32 positioning purposes
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34 ##### How to use this driver #####
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35 ==============================================================================
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37 (#) Initialize the TIM low level resources by implementing the following functions
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38 depending from feature used :
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39 (++) Complementary Output Compare : HAL_TIM_OC_MspInit()
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40 (++) Complementary PWM generation : HAL_TIM_PWM_MspInit()
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41 (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit()
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42 (++) Hall Sensor output : HAL_TIM_HallSensor_MspInit()
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44 (#) Initialize the TIM low level resources :
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45 (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
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46 (##) TIM pins configuration
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47 (+++) Enable the clock for the TIM GPIOs using the following function:
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48 __GPIOx_CLK_ENABLE();
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49 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
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51 (#) The external Clock can be configured, if needed (the default clock is the
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52 internal clock from the APBx), using the following function:
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53 HAL_TIM_ConfigClockSource, the clock configuration should be done before
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56 (#) Configure the TIM in the desired functioning mode using one of the
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57 initialization function of this driver:
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58 (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the
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59 Timer Hall Sensor Interface and the commutation event with the corresponding
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60 Interrupt and DMA request if needed (Note that One Timer is used to interface
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61 with the Hall sensor Interface and another Timer should be used to use
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62 the commutation event).
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64 (#) Activate the TIM peripheral using one of the start functions:
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65 (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()
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66 (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
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67 (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
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68 (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
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72 ******************************************************************************
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75 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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77 * Redistribution and use in source and binary forms, with or without modification,
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78 * are permitted provided that the following conditions are met:
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79 * 1. Redistributions of source code must retain the above copyright notice,
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80 * this list of conditions and the following disclaimer.
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81 * 2. Redistributions in binary form must reproduce the above copyright notice,
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82 * this list of conditions and the following disclaimer in the documentation
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83 * and/or other materials provided with the distribution.
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84 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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85 * may be used to endorse or promote products derived from this software
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86 * without specific prior written permission.
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88 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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89 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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90 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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91 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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92 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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93 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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94 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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95 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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96 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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97 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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99 ******************************************************************************
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102 /* Includes ------------------------------------------------------------------*/
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103 #include "stm32f7xx_hal.h"
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105 /** @addtogroup STM32F7xx_HAL_Driver
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109 /** @defgroup TIMEx TIM Extended HAL module driver
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110 * @brief TIM Extended HAL module driver
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114 #ifdef HAL_TIM_MODULE_ENABLED
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116 /* Private typedef -----------------------------------------------------------*/
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117 /* Private define ------------------------------------------------------------*/
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118 #define BDTR_BKF_SHIFT (16)
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119 #define BDTR_BK2F_SHIFT (20)
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120 /* Private macro -------------------------------------------------------------*/
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121 /* Private variables ---------------------------------------------------------*/
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122 /* Private function prototypes -----------------------------------------------*/
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123 /** @addtogroup TIMEx_Private_Functions
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126 static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
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127 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
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128 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
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132 /* Private functions ---------------------------------------------------------*/
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134 /** @defgroup TIMEx_Private_Functions
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138 /** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
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139 * @brief Timer Hall Sensor functions
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142 ==============================================================================
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143 ##### Timer Hall Sensor functions #####
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144 ==============================================================================
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146 This section provides functions allowing to:
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147 (+) Initialize and configure TIM HAL Sensor.
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148 (+) De-initialize TIM HAL Sensor.
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149 (+) Start the Hall Sensor Interface.
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150 (+) Stop the Hall Sensor Interface.
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151 (+) Start the Hall Sensor Interface and enable interrupts.
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152 (+) Stop the Hall Sensor Interface and disable interrupts.
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153 (+) Start the Hall Sensor Interface and enable DMA transfers.
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154 (+) Stop the Hall Sensor Interface and disable DMA transfers.
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160 * @brief Initializes the TIM Hall Sensor Interface and create the associated handle.
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161 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
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162 * the configuration information for TIM module.
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163 * @param sConfig: TIM Hall Sensor configuration structure
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164 * @retval HAL status
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166 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)
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168 TIM_OC_InitTypeDef OC_Config;
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170 /* Check the TIM handle allocation */
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176 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
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177 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
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178 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
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179 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
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180 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
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181 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
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183 /* Set the TIM state */
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184 htim->State= HAL_TIM_STATE_BUSY;
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186 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
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187 HAL_TIMEx_HallSensor_MspInit(htim);
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189 /* Configure the Time base in the Encoder Mode */
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190 TIM_Base_SetConfig(htim->Instance, &htim->Init);
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192 /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */
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193 TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
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195 /* Reset the IC1PSC Bits */
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196 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
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197 /* Set the IC1PSC value */
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198 htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
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200 /* Enable the Hall sensor interface (XOR function of the three inputs) */
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201 htim->Instance->CR2 |= TIM_CR2_TI1S;
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203 /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
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204 htim->Instance->SMCR &= ~TIM_SMCR_TS;
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205 htim->Instance->SMCR |= TIM_TS_TI1F_ED;
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207 /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
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208 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
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209 htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
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211 /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
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212 OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
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213 OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
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214 OC_Config.OCMode = TIM_OCMODE_PWM2;
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215 OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
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216 OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
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217 OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
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218 OC_Config.Pulse = sConfig->Commutation_Delay;
\r
220 TIM_OC2_SetConfig(htim->Instance, &OC_Config);
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222 /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
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224 htim->Instance->CR2 &= ~TIM_CR2_MMS;
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225 htim->Instance->CR2 |= TIM_TRGO_OC2REF;
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227 /* Initialize the TIM state*/
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228 htim->State= HAL_TIM_STATE_READY;
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234 * @brief DeInitializes the TIM Hall Sensor interface
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235 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
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236 * the configuration information for TIM module.
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237 * @retval HAL status
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239 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
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241 /* Check the parameters */
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242 assert_param(IS_TIM_INSTANCE(htim->Instance));
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244 htim->State = HAL_TIM_STATE_BUSY;
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246 /* Disable the TIM Peripheral Clock */
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247 __HAL_TIM_DISABLE(htim);
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249 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
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250 HAL_TIMEx_HallSensor_MspDeInit(htim);
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252 /* Change TIM state */
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253 htim->State = HAL_TIM_STATE_RESET;
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256 __HAL_UNLOCK(htim);
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262 * @brief Initializes the TIM Hall Sensor MSP.
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263 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
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264 * the configuration information for TIM module.
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267 __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
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269 /* NOTE : This function Should not be modified, when the callback is needed,
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270 the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
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275 * @brief DeInitializes TIM Hall Sensor MSP.
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276 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
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277 * the configuration information for TIM module.
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280 __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
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282 /* NOTE : This function Should not be modified, when the callback is needed,
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283 the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
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288 * @brief Starts the TIM Hall Sensor Interface.
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289 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
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290 * the configuration information for TIM module.
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291 * @retval HAL status
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293 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
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295 /* Check the parameters */
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296 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
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298 /* Enable the Input Capture channels 1
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299 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
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300 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
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302 /* Enable the Peripheral */
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303 __HAL_TIM_ENABLE(htim);
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305 /* Return function status */
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310 * @brief Stops the TIM Hall sensor Interface.
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311 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
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312 * the configuration information for TIM module.
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313 * @retval HAL status
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315 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
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317 /* Check the parameters */
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318 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
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320 /* Disable the Input Capture channels 1, 2 and 3
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321 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
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322 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
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324 /* Disable the Peripheral */
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325 __HAL_TIM_DISABLE(htim);
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327 /* Return function status */
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332 * @brief Starts the TIM Hall Sensor Interface in interrupt mode.
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333 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
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334 * the configuration information for TIM module.
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335 * @retval HAL status
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337 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
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339 /* Check the parameters */
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340 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
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342 /* Enable the capture compare Interrupts 1 event */
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343 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
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345 /* Enable the Input Capture channels 1
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346 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
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347 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
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349 /* Enable the Peripheral */
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350 __HAL_TIM_ENABLE(htim);
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352 /* Return function status */
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357 * @brief Stops the TIM Hall Sensor Interface in interrupt mode.
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358 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
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359 * the configuration information for TIM module.
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360 * @retval HAL status
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362 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
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364 /* Check the parameters */
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365 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
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367 /* Disable the Input Capture channels 1
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368 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
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369 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
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371 /* Disable the capture compare Interrupts event */
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372 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
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374 /* Disable the Peripheral */
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375 __HAL_TIM_DISABLE(htim);
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377 /* Return function status */
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382 * @brief Starts the TIM Hall Sensor Interface in DMA mode.
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383 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
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384 * the configuration information for TIM module.
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385 * @param pData: The destination Buffer address.
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386 * @param Length: The length of data to be transferred from TIM peripheral to memory.
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387 * @retval HAL status
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389 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
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391 /* Check the parameters */
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392 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
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394 if((htim->State == HAL_TIM_STATE_BUSY))
\r
398 else if((htim->State == HAL_TIM_STATE_READY))
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400 if(((uint32_t)pData == 0 ) && (Length > 0))
\r
406 htim->State = HAL_TIM_STATE_BUSY;
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409 /* Enable the Input Capture channels 1
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410 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
\r
411 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
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413 /* Set the DMA Input Capture 1 Callback */
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414 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
\r
415 /* Set the DMA error callback */
\r
416 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
\r
418 /* Enable the DMA Stream for Capture 1*/
\r
419 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
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421 /* Enable the capture compare 1 Interrupt */
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422 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
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424 /* Enable the Peripheral */
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425 __HAL_TIM_ENABLE(htim);
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427 /* Return function status */
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432 * @brief Stops the TIM Hall Sensor Interface in DMA mode.
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433 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
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434 * the configuration information for TIM module.
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435 * @retval HAL status
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437 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
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439 /* Check the parameters */
\r
440 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
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442 /* Disable the Input Capture channels 1
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443 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
\r
444 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
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447 /* Disable the capture compare Interrupts 1 event */
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448 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
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450 /* Disable the Peripheral */
\r
451 __HAL_TIM_DISABLE(htim);
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453 /* Return function status */
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461 /** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
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462 * @brief Timer Complementary Output Compare functions
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465 ==============================================================================
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466 ##### Timer Complementary Output Compare functions #####
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467 ==============================================================================
\r
469 This section provides functions allowing to:
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470 (+) Start the Complementary Output Compare/PWM.
\r
471 (+) Stop the Complementary Output Compare/PWM.
\r
472 (+) Start the Complementary Output Compare/PWM and enable interrupts.
\r
473 (+) Stop the Complementary Output Compare/PWM and disable interrupts.
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474 (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
\r
475 (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
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482 * @brief Starts the TIM Output Compare signal generation on the complementary
\r
484 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
485 * the configuration information for TIM module.
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486 * @param Channel: TIM Channel to be enabled.
\r
487 * This parameter can be one of the following values:
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488 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
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489 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
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490 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
\r
491 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
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492 * @retval HAL status
\r
494 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
\r
496 /* Check the parameters */
\r
497 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
\r
499 /* Enable the Capture compare channel N */
\r
500 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
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502 /* Enable the Main Output */
\r
503 __HAL_TIM_MOE_ENABLE(htim);
\r
505 /* Enable the Peripheral */
\r
506 __HAL_TIM_ENABLE(htim);
\r
508 /* Return function status */
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513 * @brief Stops the TIM Output Compare signal generation on the complementary
\r
515 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
516 * the configuration information for TIM module.
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517 * @param Channel: TIM Channel to be disabled.
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518 * This parameter can be one of the following values:
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519 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
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520 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
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521 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
\r
522 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
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523 * @retval HAL status
\r
525 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
\r
527 /* Check the parameters */
\r
528 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
\r
530 /* Disable the Capture compare channel N */
\r
531 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
\r
533 /* Disable the Main Output */
\r
534 __HAL_TIM_MOE_DISABLE(htim);
\r
536 /* Disable the Peripheral */
\r
537 __HAL_TIM_DISABLE(htim);
\r
539 /* Return function status */
\r
544 * @brief Starts the TIM Output Compare signal generation in interrupt mode
\r
545 * on the complementary output.
\r
546 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
547 * the configuration information for TIM module.
\r
548 * @param Channel: TIM Channel to be enabled.
\r
549 * This parameter can be one of the following values:
\r
550 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
551 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
552 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
\r
553 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
\r
554 * @retval HAL status
\r
556 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
\r
558 /* Check the parameters */
\r
559 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
\r
563 case TIM_CHANNEL_1:
\r
565 /* Enable the TIM Output Compare interrupt */
\r
566 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
\r
570 case TIM_CHANNEL_2:
\r
572 /* Enable the TIM Output Compare interrupt */
\r
573 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
\r
577 case TIM_CHANNEL_3:
\r
579 /* Enable the TIM Output Compare interrupt */
\r
580 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
\r
584 case TIM_CHANNEL_4:
\r
586 /* Enable the TIM Output Compare interrupt */
\r
587 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
\r
595 /* Enable the TIM Break interrupt */
\r
596 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
\r
598 /* Enable the Capture compare channel N */
\r
599 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
\r
601 /* Enable the Main Output */
\r
602 __HAL_TIM_MOE_ENABLE(htim);
\r
604 /* Enable the Peripheral */
\r
605 __HAL_TIM_ENABLE(htim);
\r
607 /* Return function status */
\r
612 * @brief Stops the TIM Output Compare signal generation in interrupt mode
\r
613 * on the complementary output.
\r
614 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
615 * the configuration information for TIM module.
\r
616 * @param Channel: TIM Channel to be disabled.
\r
617 * This parameter can be one of the following values:
\r
618 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
619 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
620 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
\r
621 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
\r
622 * @retval HAL status
\r
624 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
\r
626 uint32_t tmpccer = 0;
\r
628 /* Check the parameters */
\r
629 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
\r
633 case TIM_CHANNEL_1:
\r
635 /* Disable the TIM Output Compare interrupt */
\r
636 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
\r
640 case TIM_CHANNEL_2:
\r
642 /* Disable the TIM Output Compare interrupt */
\r
643 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
\r
647 case TIM_CHANNEL_3:
\r
649 /* Disable the TIM Output Compare interrupt */
\r
650 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
\r
654 case TIM_CHANNEL_4:
\r
656 /* Disable the TIM Output Compare interrupt */
\r
657 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
\r
665 /* Disable the Capture compare channel N */
\r
666 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
\r
668 /* Disable the TIM Break interrupt (only if no more channel is active) */
\r
669 tmpccer = htim->Instance->CCER;
\r
670 if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
\r
672 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
\r
675 /* Disable the Main Output */
\r
676 __HAL_TIM_MOE_DISABLE(htim);
\r
678 /* Disable the Peripheral */
\r
679 __HAL_TIM_DISABLE(htim);
\r
681 /* Return function status */
\r
686 * @brief Starts the TIM Output Compare signal generation in DMA mode
\r
687 * on the complementary output.
\r
688 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
689 * the configuration information for TIM module.
\r
690 * @param Channel: TIM Channel to be enabled.
\r
691 * This parameter can be one of the following values:
\r
692 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
693 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
694 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
\r
695 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
\r
696 * @param pData: The source Buffer address.
\r
697 * @param Length: The length of data to be transferred from memory to TIM peripheral
\r
698 * @retval HAL status
\r
700 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
\r
702 /* Check the parameters */
\r
703 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
\r
705 if((htim->State == HAL_TIM_STATE_BUSY))
\r
709 else if((htim->State == HAL_TIM_STATE_READY))
\r
711 if(((uint32_t)pData == 0 ) && (Length > 0))
\r
717 htim->State = HAL_TIM_STATE_BUSY;
\r
722 case TIM_CHANNEL_1:
\r
724 /* Set the DMA Period elapsed callback */
\r
725 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
\r
727 /* Set the DMA error callback */
\r
728 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
\r
730 /* Enable the DMA Stream */
\r
731 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
\r
733 /* Enable the TIM Output Compare DMA request */
\r
734 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
\r
738 case TIM_CHANNEL_2:
\r
740 /* Set the DMA Period elapsed callback */
\r
741 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
\r
743 /* Set the DMA error callback */
\r
744 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
\r
746 /* Enable the DMA Stream */
\r
747 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
\r
749 /* Enable the TIM Output Compare DMA request */
\r
750 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
\r
754 case TIM_CHANNEL_3:
\r
756 /* Set the DMA Period elapsed callback */
\r
757 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
\r
759 /* Set the DMA error callback */
\r
760 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
\r
762 /* Enable the DMA Stream */
\r
763 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
\r
765 /* Enable the TIM Output Compare DMA request */
\r
766 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
\r
770 case TIM_CHANNEL_4:
\r
772 /* Set the DMA Period elapsed callback */
\r
773 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
\r
775 /* Set the DMA error callback */
\r
776 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
\r
778 /* Enable the DMA Stream */
\r
779 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
\r
781 /* Enable the TIM Output Compare DMA request */
\r
782 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
\r
790 /* Enable the Capture compare channel N */
\r
791 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
\r
793 /* Enable the Main Output */
\r
794 __HAL_TIM_MOE_ENABLE(htim);
\r
796 /* Enable the Peripheral */
\r
797 __HAL_TIM_ENABLE(htim);
\r
799 /* Return function status */
\r
804 * @brief Stops the TIM Output Compare signal generation in DMA mode
\r
805 * on the complementary output.
\r
806 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
807 * the configuration information for TIM module.
\r
808 * @param Channel: TIM Channel to be disabled.
\r
809 * This parameter can be one of the following values:
\r
810 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
811 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
812 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
\r
813 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
\r
814 * @retval HAL status
\r
816 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
\r
818 /* Check the parameters */
\r
819 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
\r
823 case TIM_CHANNEL_1:
\r
825 /* Disable the TIM Output Compare DMA request */
\r
826 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
\r
830 case TIM_CHANNEL_2:
\r
832 /* Disable the TIM Output Compare DMA request */
\r
833 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
\r
837 case TIM_CHANNEL_3:
\r
839 /* Disable the TIM Output Compare DMA request */
\r
840 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
\r
844 case TIM_CHANNEL_4:
\r
846 /* Disable the TIM Output Compare interrupt */
\r
847 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
\r
855 /* Disable the Capture compare channel N */
\r
856 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
\r
858 /* Disable the Main Output */
\r
859 __HAL_TIM_MOE_DISABLE(htim);
\r
861 /* Disable the Peripheral */
\r
862 __HAL_TIM_DISABLE(htim);
\r
864 /* Change the htim state */
\r
865 htim->State = HAL_TIM_STATE_READY;
\r
867 /* Return function status */
\r
875 /** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
\r
876 * @brief Timer Complementary PWM functions
\r
879 ==============================================================================
\r
880 ##### Timer Complementary PWM functions #####
\r
881 ==============================================================================
\r
883 This section provides functions allowing to:
\r
884 (+) Start the Complementary PWM.
\r
885 (+) Stop the Complementary PWM.
\r
886 (+) Start the Complementary PWM and enable interrupts.
\r
887 (+) Stop the Complementary PWM and disable interrupts.
\r
888 (+) Start the Complementary PWM and enable DMA transfers.
\r
889 (+) Stop the Complementary PWM and disable DMA transfers.
\r
890 (+) Start the Complementary Input Capture measurement.
\r
891 (+) Stop the Complementary Input Capture.
\r
892 (+) Start the Complementary Input Capture and enable interrupts.
\r
893 (+) Stop the Complementary Input Capture and disable interrupts.
\r
894 (+) Start the Complementary Input Capture and enable DMA transfers.
\r
895 (+) Stop the Complementary Input Capture and disable DMA transfers.
\r
896 (+) Start the Complementary One Pulse generation.
\r
897 (+) Stop the Complementary One Pulse.
\r
898 (+) Start the Complementary One Pulse and enable interrupts.
\r
899 (+) Stop the Complementary One Pulse and disable interrupts.
\r
906 * @brief Starts the PWM signal generation on the complementary output.
\r
907 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
908 * the configuration information for TIM module.
\r
909 * @param Channel: TIM Channel to be enabled.
\r
910 * This parameter can be one of the following values:
\r
911 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
912 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
913 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
\r
914 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
\r
915 * @retval HAL status
\r
917 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
\r
919 /* Check the parameters */
\r
920 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
\r
922 /* Enable the complementary PWM output */
\r
923 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
\r
925 /* Enable the Main Output */
\r
926 __HAL_TIM_MOE_ENABLE(htim);
\r
928 /* Enable the Peripheral */
\r
929 __HAL_TIM_ENABLE(htim);
\r
931 /* Return function status */
\r
936 * @brief Stops the PWM signal generation on the complementary output.
\r
937 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
938 * the configuration information for TIM module.
\r
939 * @param Channel: TIM Channel to be disabled.
\r
940 * This parameter can be one of the following values:
\r
941 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
942 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
943 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
\r
944 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
\r
945 * @retval HAL status
\r
947 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
\r
949 /* Check the parameters */
\r
950 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
\r
952 /* Disable the complementary PWM output */
\r
953 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
\r
955 /* Disable the Main Output */
\r
956 __HAL_TIM_MOE_DISABLE(htim);
\r
958 /* Disable the Peripheral */
\r
959 __HAL_TIM_DISABLE(htim);
\r
961 /* Return function status */
\r
966 * @brief Starts the PWM signal generation in interrupt mode on the
\r
967 * complementary output.
\r
968 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
969 * the configuration information for TIM module.
\r
970 * @param Channel: TIM Channel to be disabled.
\r
971 * This parameter can be one of the following values:
\r
972 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
973 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
974 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
\r
975 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
\r
976 * @retval HAL status
\r
978 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
\r
980 /* Check the parameters */
\r
981 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
\r
985 case TIM_CHANNEL_1:
\r
987 /* Enable the TIM Capture/Compare 1 interrupt */
\r
988 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
\r
992 case TIM_CHANNEL_2:
\r
994 /* Enable the TIM Capture/Compare 2 interrupt */
\r
995 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
\r
999 case TIM_CHANNEL_3:
\r
1001 /* Enable the TIM Capture/Compare 3 interrupt */
\r
1002 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
\r
1006 case TIM_CHANNEL_4:
\r
1008 /* Enable the TIM Capture/Compare 4 interrupt */
\r
1009 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
\r
1017 /* Enable the TIM Break interrupt */
\r
1018 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
\r
1020 /* Enable the complementary PWM output */
\r
1021 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
\r
1023 /* Enable the Main Output */
\r
1024 __HAL_TIM_MOE_ENABLE(htim);
\r
1026 /* Enable the Peripheral */
\r
1027 __HAL_TIM_ENABLE(htim);
\r
1029 /* Return function status */
\r
1034 * @brief Stops the PWM signal generation in interrupt mode on the
\r
1035 * complementary output.
\r
1036 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
1037 * the configuration information for TIM module.
\r
1038 * @param Channel: TIM Channel to be disabled.
\r
1039 * This parameter can be one of the following values:
\r
1040 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
1041 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
1042 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
\r
1043 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
\r
1044 * @retval HAL status
\r
1046 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
\r
1048 uint32_t tmpccer = 0;
\r
1050 /* Check the parameters */
\r
1051 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
\r
1055 case TIM_CHANNEL_1:
\r
1057 /* Disable the TIM Capture/Compare 1 interrupt */
\r
1058 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
\r
1062 case TIM_CHANNEL_2:
\r
1064 /* Disable the TIM Capture/Compare 2 interrupt */
\r
1065 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
\r
1069 case TIM_CHANNEL_3:
\r
1071 /* Disable the TIM Capture/Compare 3 interrupt */
\r
1072 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
\r
1076 case TIM_CHANNEL_4:
\r
1078 /* Disable the TIM Capture/Compare 3 interrupt */
\r
1079 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
\r
1087 /* Disable the complementary PWM output */
\r
1088 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
\r
1090 /* Disable the TIM Break interrupt (only if no more channel is active) */
\r
1091 tmpccer = htim->Instance->CCER;
\r
1092 if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
\r
1094 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
\r
1097 /* Disable the Main Output */
\r
1098 __HAL_TIM_MOE_DISABLE(htim);
\r
1100 /* Disable the Peripheral */
\r
1101 __HAL_TIM_DISABLE(htim);
\r
1103 /* Return function status */
\r
1108 * @brief Starts the TIM PWM signal generation in DMA mode on the
\r
1109 * complementary output
\r
1110 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
1111 * the configuration information for TIM module.
\r
1112 * @param Channel: TIM Channel to be enabled.
\r
1113 * This parameter can be one of the following values:
\r
1114 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
1115 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
1116 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
\r
1117 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
\r
1118 * @param pData: The source Buffer address.
\r
1119 * @param Length: The length of data to be transferred from memory to TIM peripheral
\r
1120 * @retval HAL status
\r
1122 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
\r
1124 /* Check the parameters */
\r
1125 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
\r
1127 if((htim->State == HAL_TIM_STATE_BUSY))
\r
1131 else if((htim->State == HAL_TIM_STATE_READY))
\r
1133 if(((uint32_t)pData == 0 ) && (Length > 0))
\r
1135 return HAL_ERROR;
\r
1139 htim->State = HAL_TIM_STATE_BUSY;
\r
1144 case TIM_CHANNEL_1:
\r
1146 /* Set the DMA Period elapsed callback */
\r
1147 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
\r
1149 /* Set the DMA error callback */
\r
1150 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
\r
1152 /* Enable the DMA Stream */
\r
1153 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
\r
1155 /* Enable the TIM Capture/Compare 1 DMA request */
\r
1156 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
\r
1160 case TIM_CHANNEL_2:
\r
1162 /* Set the DMA Period elapsed callback */
\r
1163 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
\r
1165 /* Set the DMA error callback */
\r
1166 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
\r
1168 /* Enable the DMA Stream */
\r
1169 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
\r
1171 /* Enable the TIM Capture/Compare 2 DMA request */
\r
1172 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
\r
1176 case TIM_CHANNEL_3:
\r
1178 /* Set the DMA Period elapsed callback */
\r
1179 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
\r
1181 /* Set the DMA error callback */
\r
1182 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
\r
1184 /* Enable the DMA Stream */
\r
1185 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
\r
1187 /* Enable the TIM Capture/Compare 3 DMA request */
\r
1188 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
\r
1192 case TIM_CHANNEL_4:
\r
1194 /* Set the DMA Period elapsed callback */
\r
1195 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
\r
1197 /* Set the DMA error callback */
\r
1198 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
\r
1200 /* Enable the DMA Stream */
\r
1201 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
\r
1203 /* Enable the TIM Capture/Compare 4 DMA request */
\r
1204 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
\r
1212 /* Enable the complementary PWM output */
\r
1213 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
\r
1215 /* Enable the Main Output */
\r
1216 __HAL_TIM_MOE_ENABLE(htim);
\r
1218 /* Enable the Peripheral */
\r
1219 __HAL_TIM_ENABLE(htim);
\r
1221 /* Return function status */
\r
1226 * @brief Stops the TIM PWM signal generation in DMA mode on the complementary
\r
1228 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
1229 * the configuration information for TIM module.
\r
1230 * @param Channel: TIM Channel to be disabled.
\r
1231 * This parameter can be one of the following values:
\r
1232 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
1233 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
1234 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
\r
1235 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
\r
1236 * @retval HAL status
\r
1238 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
\r
1240 /* Check the parameters */
\r
1241 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
\r
1245 case TIM_CHANNEL_1:
\r
1247 /* Disable the TIM Capture/Compare 1 DMA request */
\r
1248 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
\r
1252 case TIM_CHANNEL_2:
\r
1254 /* Disable the TIM Capture/Compare 2 DMA request */
\r
1255 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
\r
1259 case TIM_CHANNEL_3:
\r
1261 /* Disable the TIM Capture/Compare 3 DMA request */
\r
1262 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
\r
1266 case TIM_CHANNEL_4:
\r
1268 /* Disable the TIM Capture/Compare 4 DMA request */
\r
1269 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
\r
1277 /* Disable the complementary PWM output */
\r
1278 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
\r
1280 /* Disable the Main Output */
\r
1281 __HAL_TIM_MOE_DISABLE(htim);
\r
1283 /* Disable the Peripheral */
\r
1284 __HAL_TIM_DISABLE(htim);
\r
1286 /* Change the htim state */
\r
1287 htim->State = HAL_TIM_STATE_READY;
\r
1289 /* Return function status */
\r
1297 /** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
\r
1298 * @brief Timer Complementary One Pulse functions
\r
1301 ==============================================================================
\r
1302 ##### Timer Complementary One Pulse functions #####
\r
1303 ==============================================================================
\r
1305 This section provides functions allowing to:
\r
1306 (+) Start the Complementary One Pulse generation.
\r
1307 (+) Stop the Complementary One Pulse.
\r
1308 (+) Start the Complementary One Pulse and enable interrupts.
\r
1309 (+) Stop the Complementary One Pulse and disable interrupts.
\r
1316 * @brief Starts the TIM One Pulse signal generation on the complemetary
\r
1318 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
1319 * the configuration information for TIM module.
\r
1320 * @param OutputChannel: TIM Channel to be enabled.
\r
1321 * This parameter can be one of the following values:
\r
1322 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
1323 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
1324 * @retval HAL status
\r
1326 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
\r
1328 /* Check the parameters */
\r
1329 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
\r
1331 /* Enable the complementary One Pulse output */
\r
1332 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
\r
1334 /* Enable the Main Output */
\r
1335 __HAL_TIM_MOE_ENABLE(htim);
\r
1337 /* Return function status */
\r
1342 * @brief Stops the TIM One Pulse signal generation on the complementary
\r
1344 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
1345 * the configuration information for TIM module.
\r
1346 * @param OutputChannel: TIM Channel to be disabled.
\r
1347 * This parameter can be one of the following values:
\r
1348 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
1349 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
1350 * @retval HAL status
\r
1352 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
\r
1355 /* Check the parameters */
\r
1356 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
\r
1358 /* Disable the complementary One Pulse output */
\r
1359 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
\r
1361 /* Disable the Main Output */
\r
1362 __HAL_TIM_MOE_DISABLE(htim);
\r
1364 /* Disable the Peripheral */
\r
1365 __HAL_TIM_DISABLE(htim);
\r
1367 /* Return function status */
\r
1372 * @brief Starts the TIM One Pulse signal generation in interrupt mode on the
\r
1373 * complementary channel.
\r
1374 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
1375 * the configuration information for TIM module.
\r
1376 * @param OutputChannel: TIM Channel to be enabled.
\r
1377 * This parameter can be one of the following values:
\r
1378 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
1379 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
1380 * @retval HAL status
\r
1382 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
\r
1384 /* Check the parameters */
\r
1385 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
\r
1387 /* Enable the TIM Capture/Compare 1 interrupt */
\r
1388 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
\r
1390 /* Enable the TIM Capture/Compare 2 interrupt */
\r
1391 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
\r
1393 /* Enable the complementary One Pulse output */
\r
1394 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
\r
1396 /* Enable the Main Output */
\r
1397 __HAL_TIM_MOE_ENABLE(htim);
\r
1399 /* Return function status */
\r
1404 * @brief Stops the TIM One Pulse signal generation in interrupt mode on the
\r
1405 * complementary channel.
\r
1406 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
1407 * the configuration information for TIM module.
\r
1408 * @param OutputChannel: TIM Channel to be disabled.
\r
1409 * This parameter can be one of the following values:
\r
1410 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
1411 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
1412 * @retval HAL status
\r
1414 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
\r
1416 /* Check the parameters */
\r
1417 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
\r
1419 /* Disable the TIM Capture/Compare 1 interrupt */
\r
1420 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
\r
1422 /* Disable the TIM Capture/Compare 2 interrupt */
\r
1423 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
\r
1425 /* Disable the complementary One Pulse output */
\r
1426 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
\r
1428 /* Disable the Main Output */
\r
1429 __HAL_TIM_MOE_DISABLE(htim);
\r
1431 /* Disable the Peripheral */
\r
1432 __HAL_TIM_DISABLE(htim);
\r
1434 /* Return function status */
\r
1442 /** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
\r
1443 * @brief Peripheral Control functions
\r
1446 ==============================================================================
\r
1447 ##### Peripheral Control functions #####
\r
1448 ==============================================================================
\r
1450 This section provides functions allowing to:
\r
1451 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
\r
1452 (+) Configure External Clock source.
\r
1453 (+) Configure Complementary channels, break features and dead time.
\r
1454 (+) Configure Master and the Slave synchronization.
\r
1455 (+) Configure the commutation event in case of use of the Hall sensor interface.
\r
1456 (+) Configure the DMA Burst Mode.
\r
1462 * @brief Configure the TIM commutation event sequence.
\r
1463 * @note This function is mandatory to use the commutation event in order to
\r
1464 * update the configuration at each commutation detection on the TRGI input of the Timer,
\r
1465 * the typical use of this feature is with the use of another Timer(interface Timer)
\r
1466 * configured in Hall sensor interface, this interface Timer will generate the
\r
1467 * commutation at its TRGO output (connected to Timer used in this function) each time
\r
1468 * the TI1 of the Interface Timer detect a commutation at its input TI1.
\r
1469 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
1470 * the configuration information for TIM module.
\r
1471 * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
\r
1472 * This parameter can be one of the following values:
\r
1473 * @arg TIM_TS_ITR0: Internal trigger 0 selected
\r
1474 * @arg TIM_TS_ITR1: Internal trigger 1 selected
\r
1475 * @arg TIM_TS_ITR2: Internal trigger 2 selected
\r
1476 * @arg TIM_TS_ITR3: Internal trigger 3 selected
\r
1477 * @arg TIM_TS_NONE: No trigger is needed
\r
1478 * @param CommutationSource: the Commutation Event source.
\r
1479 * This parameter can be one of the following values:
\r
1480 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
\r
1481 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
\r
1482 * @retval HAL status
\r
1484 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
\r
1486 /* Check the parameters */
\r
1487 assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
\r
1488 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
\r
1492 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
\r
1493 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
\r
1495 /* Select the Input trigger */
\r
1496 htim->Instance->SMCR &= ~TIM_SMCR_TS;
\r
1497 htim->Instance->SMCR |= InputTrigger;
\r
1500 /* Select the Capture Compare preload feature */
\r
1501 htim->Instance->CR2 |= TIM_CR2_CCPC;
\r
1502 /* Select the Commutation event source */
\r
1503 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
\r
1504 htim->Instance->CR2 |= CommutationSource;
\r
1506 __HAL_UNLOCK(htim);
\r
1512 * @brief Configure the TIM commutation event sequence with interrupt.
\r
1513 * @note This function is mandatory to use the commutation event in order to
\r
1514 * update the configuration at each commutation detection on the TRGI input of the Timer,
\r
1515 * the typical use of this feature is with the use of another Timer(interface Timer)
\r
1516 * configured in Hall sensor interface, this interface Timer will generate the
\r
1517 * commutation at its TRGO output (connected to Timer used in this function) each time
\r
1518 * the TI1 of the Interface Timer detect a commutation at its input TI1.
\r
1519 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
1520 * the configuration information for TIM module.
\r
1521 * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
\r
1522 * This parameter can be one of the following values:
\r
1523 * @arg TIM_TS_ITR0: Internal trigger 0 selected
\r
1524 * @arg TIM_TS_ITR1: Internal trigger 1 selected
\r
1525 * @arg TIM_TS_ITR2: Internal trigger 2 selected
\r
1526 * @arg TIM_TS_ITR3: Internal trigger 3 selected
\r
1527 * @arg TIM_TS_NONE: No trigger is needed
\r
1528 * @param CommutationSource: the Commutation Event source.
\r
1529 * This parameter can be one of the following values:
\r
1530 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
\r
1531 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
\r
1532 * @retval HAL status
\r
1534 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
\r
1536 /* Check the parameters */
\r
1537 assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
\r
1538 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
\r
1542 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
\r
1543 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
\r
1545 /* Select the Input trigger */
\r
1546 htim->Instance->SMCR &= ~TIM_SMCR_TS;
\r
1547 htim->Instance->SMCR |= InputTrigger;
\r
1550 /* Select the Capture Compare preload feature */
\r
1551 htim->Instance->CR2 |= TIM_CR2_CCPC;
\r
1552 /* Select the Commutation event source */
\r
1553 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
\r
1554 htim->Instance->CR2 |= CommutationSource;
\r
1556 /* Enable the Commutation Interrupt Request */
\r
1557 __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
\r
1559 __HAL_UNLOCK(htim);
\r
1565 * @brief Configure the TIM commutation event sequence with DMA.
\r
1566 * @note This function is mandatory to use the commutation event in order to
\r
1567 * update the configuration at each commutation detection on the TRGI input of the Timer,
\r
1568 * the typical use of this feature is with the use of another Timer(interface Timer)
\r
1569 * configured in Hall sensor interface, this interface Timer will generate the
\r
1570 * commutation at its TRGO output (connected to Timer used in this function) each time
\r
1571 * the TI1 of the Interface Timer detect a commutation at its input TI1.
\r
1572 * @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set
\r
1573 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
1574 * the configuration information for TIM module.
\r
1575 * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
\r
1576 * This parameter can be one of the following values:
\r
1577 * @arg TIM_TS_ITR0: Internal trigger 0 selected
\r
1578 * @arg TIM_TS_ITR1: Internal trigger 1 selected
\r
1579 * @arg TIM_TS_ITR2: Internal trigger 2 selected
\r
1580 * @arg TIM_TS_ITR3: Internal trigger 3 selected
\r
1581 * @arg TIM_TS_NONE: No trigger is needed
\r
1582 * @param CommutationSource: the Commutation Event source.
\r
1583 * This parameter can be one of the following values:
\r
1584 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
\r
1585 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
\r
1586 * @retval HAL status
\r
1588 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
\r
1590 /* Check the parameters */
\r
1591 assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
\r
1592 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
\r
1596 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
\r
1597 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
\r
1599 /* Select the Input trigger */
\r
1600 htim->Instance->SMCR &= ~TIM_SMCR_TS;
\r
1601 htim->Instance->SMCR |= InputTrigger;
\r
1604 /* Select the Capture Compare preload feature */
\r
1605 htim->Instance->CR2 |= TIM_CR2_CCPC;
\r
1606 /* Select the Commutation event source */
\r
1607 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
\r
1608 htim->Instance->CR2 |= CommutationSource;
\r
1610 /* Enable the Commutation DMA Request */
\r
1611 /* Set the DMA Commutation Callback */
\r
1612 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
\r
1613 /* Set the DMA error callback */
\r
1614 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError;
\r
1616 /* Enable the Commutation DMA Request */
\r
1617 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
\r
1619 __HAL_UNLOCK(htim);
\r
1625 * @brief Initializes the TIM Output Compare Channels according to the specified
\r
1626 * parameters in the TIM_OC_InitTypeDef.
\r
1627 * @param htim: TIM Output Compare handle
\r
1628 * @param sConfig: TIM Output Compare configuration structure
\r
1629 * @param Channel : TIM Channels to configure
\r
1630 * This parameter can be one of the following values:
\r
1631 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
1632 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
1633 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
\r
1634 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
\r
1635 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
\r
1636 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
\r
1637 * @arg TIM_CHANNEL_ALL: all output channels supported by the timer instance selected
\r
1638 * @retval HAL status
\r
1640 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
\r
1642 /* Check the parameters */
\r
1643 assert_param(IS_TIM_CHANNELS(Channel));
\r
1644 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
\r
1645 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
\r
1646 assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
\r
1647 assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
\r
1648 assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
\r
1650 /* Check input state */
\r
1651 __HAL_LOCK(htim);
\r
1653 htim->State = HAL_TIM_STATE_BUSY;
\r
1657 case TIM_CHANNEL_1:
\r
1659 /* Check the parameters */
\r
1660 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
\r
1662 /* Configure the TIM Channel 1 in Output Compare */
\r
1663 TIM_OC1_SetConfig(htim->Instance, sConfig);
\r
1667 case TIM_CHANNEL_2:
\r
1669 /* Check the parameters */
\r
1670 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
\r
1672 /* Configure the TIM Channel 2 in Output Compare */
\r
1673 TIM_OC2_SetConfig(htim->Instance, sConfig);
\r
1677 case TIM_CHANNEL_3:
\r
1679 /* Check the parameters */
\r
1680 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
\r
1682 /* Configure the TIM Channel 3 in Output Compare */
\r
1683 TIM_OC3_SetConfig(htim->Instance, sConfig);
\r
1687 case TIM_CHANNEL_4:
\r
1689 /* Check the parameters */
\r
1690 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
\r
1692 /* Configure the TIM Channel 4 in Output Compare */
\r
1693 TIM_OC4_SetConfig(htim->Instance, sConfig);
\r
1697 case TIM_CHANNEL_5:
\r
1699 /* Check the parameters */
\r
1700 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
\r
1702 /* Configure the TIM Channel 5 in Output Compare */
\r
1703 TIM_OC5_SetConfig(htim->Instance, sConfig);
\r
1707 case TIM_CHANNEL_6:
\r
1709 /* Check the parameters */
\r
1710 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
\r
1712 /* Configure the TIM Channel 6 in Output Compare */
\r
1713 TIM_OC6_SetConfig(htim->Instance, sConfig);
\r
1721 htim->State = HAL_TIM_STATE_READY;
\r
1723 __HAL_UNLOCK(htim);
\r
1729 * @brief Initializes the TIM PWM channels according to the specified
\r
1730 * parameters in the TIM_OC_InitTypeDef.
\r
1731 * @param htim: TIM PWM handle
\r
1732 * @param sConfig: TIM PWM configuration structure
\r
1733 * @param Channel : TIM Channels to be configured
\r
1734 * This parameter can be one of the following values:
\r
1735 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
1736 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
1737 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
\r
1738 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
\r
1739 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
\r
1740 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
\r
1741 * @arg TIM_CHANNEL_ALL: all PWM channels supported by the timer instance selected
\r
1742 * @retval HAL status
\r
1744 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
\r
1745 TIM_OC_InitTypeDef* sConfig,
\r
1748 /* Check the parameters */
\r
1749 assert_param(IS_TIM_CHANNELS(Channel));
\r
1750 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
\r
1751 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
\r
1752 assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
\r
1753 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
\r
1754 assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
\r
1755 assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
\r
1757 /* Check input state */
\r
1760 htim->State = HAL_TIM_STATE_BUSY;
\r
1764 case TIM_CHANNEL_1:
\r
1766 /* Check the parameters */
\r
1767 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
\r
1769 /* Configure the Channel 1 in PWM mode */
\r
1770 TIM_OC1_SetConfig(htim->Instance, sConfig);
\r
1772 /* Set the Preload enable bit for channel1 */
\r
1773 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
\r
1775 /* Configure the Output Fast mode */
\r
1776 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
\r
1777 htim->Instance->CCMR1 |= sConfig->OCFastMode;
\r
1781 case TIM_CHANNEL_2:
\r
1783 /* Check the parameters */
\r
1784 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
\r
1786 /* Configure the Channel 2 in PWM mode */
\r
1787 TIM_OC2_SetConfig(htim->Instance, sConfig);
\r
1789 /* Set the Preload enable bit for channel2 */
\r
1790 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
\r
1792 /* Configure the Output Fast mode */
\r
1793 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
\r
1794 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
\r
1798 case TIM_CHANNEL_3:
\r
1800 /* Check the parameters */
\r
1801 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
\r
1803 /* Configure the Channel 3 in PWM mode */
\r
1804 TIM_OC3_SetConfig(htim->Instance, sConfig);
\r
1806 /* Set the Preload enable bit for channel3 */
\r
1807 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
\r
1809 /* Configure the Output Fast mode */
\r
1810 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
\r
1811 htim->Instance->CCMR2 |= sConfig->OCFastMode;
\r
1815 case TIM_CHANNEL_4:
\r
1817 /* Check the parameters */
\r
1818 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
\r
1820 /* Configure the Channel 4 in PWM mode */
\r
1821 TIM_OC4_SetConfig(htim->Instance, sConfig);
\r
1823 /* Set the Preload enable bit for channel4 */
\r
1824 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
\r
1826 /* Configure the Output Fast mode */
\r
1827 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
\r
1828 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
\r
1832 case TIM_CHANNEL_5:
\r
1834 /* Check the parameters */
\r
1835 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
\r
1837 /* Configure the Channel 5 in PWM mode */
\r
1838 TIM_OC5_SetConfig(htim->Instance, sConfig);
\r
1840 /* Set the Preload enable bit for channel5*/
\r
1841 htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
\r
1843 /* Configure the Output Fast mode */
\r
1844 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
\r
1845 htim->Instance->CCMR3 |= sConfig->OCFastMode;
\r
1849 case TIM_CHANNEL_6:
\r
1851 /* Check the parameters */
\r
1852 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
\r
1854 /* Configure the Channel 5 in PWM mode */
\r
1855 TIM_OC6_SetConfig(htim->Instance, sConfig);
\r
1857 /* Set the Preload enable bit for channel6 */
\r
1858 htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
\r
1860 /* Configure the Output Fast mode */
\r
1861 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
\r
1862 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8;
\r
1870 htim->State = HAL_TIM_STATE_READY;
\r
1872 __HAL_UNLOCK(htim);
\r
1878 * @brief Configures the OCRef clear feature
\r
1879 * @param htim: TIM handle
\r
1880 * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
\r
1881 * contains the OCREF clear feature and parameters for the TIM peripheral.
\r
1882 * @param Channel: specifies the TIM Channel
\r
1883 * This parameter can be one of the following values:
\r
1884 * @arg TIM_Channel_1: TIM Channel 1
\r
1885 * @arg TIM_Channel_2: TIM Channel 2
\r
1886 * @arg TIM_Channel_3: TIM Channel 3
\r
1887 * @arg TIM_Channel_4: TIM Channel 4
\r
1888 * @arg TIM_Channel_5: TIM Channel 5
\r
1889 * @arg TIM_Channel_6: TIM Channel 6
\r
1892 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
\r
1893 TIM_ClearInputConfigTypeDef *sClearInputConfig,
\r
1896 uint32_t tmpsmcr = 0;
\r
1898 /* Check the parameters */
\r
1899 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
\r
1900 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
\r
1902 /* Check input state */
\r
1905 switch (sClearInputConfig->ClearInputSource)
\r
1907 case TIM_CLEARINPUTSOURCE_NONE:
\r
1909 /* Clear the OCREF clear selection bit */
\r
1910 tmpsmcr &= ~TIM_SMCR_OCCS;
\r
1912 /* Clear the ETR Bits */
\r
1913 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
\r
1915 /* Set TIMx_SMCR */
\r
1916 htim->Instance->SMCR = tmpsmcr;
\r
1920 case TIM_CLEARINPUTSOURCE_OCREFCLR:
\r
1922 /* Clear the OCREF clear selection bit */
\r
1923 htim->Instance->SMCR &= ~TIM_SMCR_OCCS;
\r
1927 case TIM_CLEARINPUTSOURCE_ETR:
\r
1929 /* Check the parameters */
\r
1930 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
\r
1931 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
\r
1932 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
\r
1934 TIM_ETR_SetConfig(htim->Instance,
\r
1935 sClearInputConfig->ClearInputPrescaler,
\r
1936 sClearInputConfig->ClearInputPolarity,
\r
1937 sClearInputConfig->ClearInputFilter);
\r
1939 /* Set the OCREF clear selection bit */
\r
1940 htim->Instance->SMCR |= TIM_SMCR_OCCS;
\r
1949 case TIM_CHANNEL_1:
\r
1951 if(sClearInputConfig->ClearInputState != RESET)
\r
1953 /* Enable the Ocref clear feature for Channel 1 */
\r
1954 htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
\r
1958 /* Disable the Ocref clear feature for Channel 1 */
\r
1959 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
\r
1963 case TIM_CHANNEL_2:
\r
1965 if(sClearInputConfig->ClearInputState != RESET)
\r
1967 /* Enable the Ocref clear feature for Channel 2 */
\r
1968 htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
\r
1972 /* Disable the Ocref clear feature for Channel 2 */
\r
1973 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
\r
1977 case TIM_CHANNEL_3:
\r
1979 if(sClearInputConfig->ClearInputState != RESET)
\r
1981 /* Enable the Ocref clear feature for Channel 3 */
\r
1982 htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
\r
1986 /* Disable the Ocref clear feature for Channel 3 */
\r
1987 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
\r
1991 case TIM_CHANNEL_4:
\r
1993 if(sClearInputConfig->ClearInputState != RESET)
\r
1995 /* Enable the Ocref clear feature for Channel 4 */
\r
1996 htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
\r
2000 /* Disable the Ocref clear feature for Channel 4 */
\r
2001 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
\r
2005 case TIM_CHANNEL_5:
\r
2007 if(sClearInputConfig->ClearInputState != RESET)
\r
2009 /* Enable the Ocref clear feature for Channel 1 */
\r
2010 htim->Instance->CCMR3 |= TIM_CCMR3_OC5CE;
\r
2014 /* Disable the Ocref clear feature for Channel 1 */
\r
2015 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5CE;
\r
2019 case TIM_CHANNEL_6:
\r
2021 if(sClearInputConfig->ClearInputState != RESET)
\r
2023 /* Enable the Ocref clear feature for Channel 1 */
\r
2024 htim->Instance->CCMR3 |= TIM_CCMR3_OC6CE;
\r
2028 /* Disable the Ocref clear feature for Channel 1 */
\r
2029 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6CE;
\r
2037 __HAL_UNLOCK(htim);
\r
2043 * @brief Configures the TIM in master mode.
\r
2044 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
2045 * the configuration information for TIM module.
\r
2046 * @param sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that
\r
2047 * contains the selected trigger output (TRGO) and the Master/Slave
\r
2049 * @retval HAL status
\r
2051 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig)
\r
2054 uint32_t tmpsmcr;
\r
2056 /* Check the parameters */
\r
2057 assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));
\r
2058 assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
\r
2059 assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
\r
2061 /* Check input state */
\r
2064 /* Get the TIMx CR2 register value */
\r
2065 tmpcr2 = htim->Instance->CR2;
\r
2067 /* Get the TIMx SMCR register value */
\r
2068 tmpsmcr = htim->Instance->SMCR;
\r
2070 /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
\r
2071 if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
\r
2073 /* Check the parameters */
\r
2074 assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
\r
2076 /* Clear the MMS2 bits */
\r
2077 tmpcr2 &= ~TIM_CR2_MMS2;
\r
2078 /* Select the TRGO2 source*/
\r
2079 tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
\r
2082 /* Reset the MMS Bits */
\r
2083 tmpcr2 &= ~TIM_CR2_MMS;
\r
2084 /* Select the TRGO source */
\r
2085 tmpcr2 |= sMasterConfig->MasterOutputTrigger;
\r
2087 /* Reset the MSM Bit */
\r
2088 tmpsmcr &= ~TIM_SMCR_MSM;
\r
2089 /* Set master mode */
\r
2090 tmpsmcr |= sMasterConfig->MasterSlaveMode;
\r
2092 /* Update TIMx CR2 */
\r
2093 htim->Instance->CR2 = tmpcr2;
\r
2095 /* Update TIMx SMCR */
\r
2096 htim->Instance->SMCR = tmpsmcr;
\r
2098 __HAL_UNLOCK(htim);
\r
2104 * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
\r
2105 * and the AOE(automatic output enable).
\r
2106 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
2107 * the configuration information for TIM module.
\r
2108 * @param sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfig_TypeDef structure that
\r
2109 * contains the BDTR Register configuration information for the TIM peripheral.
\r
2110 * @retval HAL status
\r
2112 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
\r
2113 TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)
\r
2115 uint32_t tmpbdtr = 0;
\r
2117 /* Check the parameters */
\r
2118 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
\r
2119 assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
\r
2120 assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
\r
2121 assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
\r
2122 assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
\r
2123 assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
\r
2124 assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
\r
2125 assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
\r
2126 assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
\r
2127 assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
\r
2128 assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
\r
2129 assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
\r
2131 /* Check input state */
\r
2134 htim->State = HAL_TIM_STATE_BUSY;
\r
2136 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
\r
2137 the OSSI State, the dead time value and the Automatic Output Enable Bit */
\r
2139 /* Clear the BDTR bits */
\r
2140 tmpbdtr &= ~(TIM_BDTR_DTG | TIM_BDTR_LOCK | TIM_BDTR_OSSI |
\r
2141 TIM_BDTR_OSSR | TIM_BDTR_BKE | TIM_BDTR_BKP |
\r
2142 TIM_BDTR_AOE | TIM_BDTR_MOE | TIM_BDTR_BKF |
\r
2143 TIM_BDTR_BK2F | TIM_BDTR_BK2E | TIM_BDTR_BK2P);
\r
2145 /* Set the BDTR bits */
\r
2146 tmpbdtr |= sBreakDeadTimeConfig->DeadTime;
\r
2147 tmpbdtr |= sBreakDeadTimeConfig->LockLevel;
\r
2148 tmpbdtr |= sBreakDeadTimeConfig->OffStateIDLEMode;
\r
2149 tmpbdtr |= sBreakDeadTimeConfig->OffStateRunMode;
\r
2150 tmpbdtr |= sBreakDeadTimeConfig->BreakState;
\r
2151 tmpbdtr |= sBreakDeadTimeConfig->BreakPolarity;
\r
2152 tmpbdtr |= sBreakDeadTimeConfig->AutomaticOutput;
\r
2153 tmpbdtr |= (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT);
\r
2154 tmpbdtr |= (sBreakDeadTimeConfig->Break2Filter << BDTR_BK2F_SHIFT);
\r
2155 tmpbdtr |= sBreakDeadTimeConfig->Break2State;
\r
2156 tmpbdtr |= sBreakDeadTimeConfig->Break2Polarity;
\r
2158 /* Set TIMx_BDTR */
\r
2159 htim->Instance->BDTR = tmpbdtr;
\r
2161 __HAL_UNLOCK(htim);
\r
2167 * @brief Configures the TIM2, TIM5 and TIM11 Remapping input capabilities.
\r
2168 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
2169 * the configuration information for TIM module.
\r
2170 * @param TIM_Remap: specifies the TIM input remapping source.
\r
2171 * This parameter can be one of the following values:
\r
2172 * @arg TIM_TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default)
\r
2173 * @arg TIM_TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trigger output.
\r
2174 * @arg TIM_TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF.
\r
2175 * @arg TIM_TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF.
\r
2176 * @arg TIM_TIM5_GPIO: TIM5 CH4 input is connected to dedicated Timer pin(default)
\r
2177 * @arg TIM_TIM5_LSI: TIM5 CH4 input is connected to LSI clock.
\r
2178 * @arg TIM_TIM5_LSE: TIM5 CH4 input is connected to LSE clock.
\r
2179 * @arg TIM_TIM5_RTC: TIM5 CH4 input is connected to RTC Output event.
\r
2180 * @arg TIM_TIM11_GPIO: TIM11 CH4 input is connected to dedicated Timer pin(default)
\r
2181 * @arg TIM_TIM11_SPDIF: SPDIF Frame synchronous
\r
2182 * @arg TIM_TIM11_HSE: TIM11 CH4 input is connected to HSE_RTC clock
\r
2183 * (HSE divided by a programmable prescaler)
\r
2184 * @arg TIM_TIM11_MCO1: TIM11 CH1 input is connected to MCO1
\r
2185 * @retval HAL status
\r
2187 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
\r
2191 /* Check parameters */
\r
2192 assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
\r
2193 assert_param(IS_TIM_REMAP(Remap));
\r
2195 /* Set the Timer remapping configuration */
\r
2196 htim->Instance->OR = Remap;
\r
2198 htim->State = HAL_TIM_STATE_READY;
\r
2200 __HAL_UNLOCK(htim);
\r
2206 * @brief Group channel 5 and channel 1, 2 or 3
\r
2207 * @param htim: TIM handle.
\r
2208 * @param OCRef: specifies the reference signal(s) the OC5REF is combined with.
\r
2209 * This parameter can be any combination of the following values:
\r
2210 * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
\r
2211 * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
\r
2212 * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
\r
2213 * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
\r
2214 * @retval HAL status
\r
2216 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t OCRef)
\r
2218 /* Check parameters */
\r
2219 assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
\r
2220 assert_param(IS_TIM_GROUPCH5(OCRef));
\r
2222 /* Process Locked */
\r
2225 htim->State = HAL_TIM_STATE_BUSY;
\r
2227 /* Clear GC5Cx bit fields */
\r
2228 htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3|TIM_CCR5_GC5C2|TIM_CCR5_GC5C1);
\r
2230 /* Set GC5Cx bit fields */
\r
2231 htim->Instance->CCR5 |= OCRef;
\r
2233 htim->State = HAL_TIM_STATE_READY;
\r
2235 __HAL_UNLOCK(htim);
\r
2244 /** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
\r
2245 * @brief Extended Callbacks functions
\r
2248 ==============================================================================
\r
2249 ##### Extension Callbacks functions #####
\r
2250 ==============================================================================
\r
2252 This section provides Extension TIM callback functions:
\r
2253 (+) Timer Commutation callback
\r
2254 (+) Timer Break callback
\r
2261 * @brief Hall commutation changed callback in non blocking mode
\r
2262 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
2263 * the configuration information for TIM module.
\r
2266 __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
\r
2268 /* NOTE : This function Should not be modified, when the callback is needed,
\r
2269 the HAL_TIMEx_CommutationCallback could be implemented in the user file
\r
2274 * @brief Hall Break detection callback in non blocking mode
\r
2275 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
2276 * the configuration information for TIM module.
\r
2279 __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
\r
2281 /* NOTE : This function Should not be modified, when the callback is needed,
\r
2282 the HAL_TIMEx_BreakCallback could be implemented in the user file
\r
2290 /** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
\r
2291 * @brief Extended Peripheral State functions
\r
2294 ==============================================================================
\r
2295 ##### Extension Peripheral State functions #####
\r
2296 ==============================================================================
\r
2298 This subsection permits to get in run-time the status of the peripheral
\r
2299 and the data flow.
\r
2306 * @brief Return the TIM Hall Sensor interface state
\r
2307 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
\r
2308 * the configuration information for TIM module.
\r
2309 * @retval HAL state
\r
2311 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
\r
2313 return htim->State;
\r
2321 * @brief TIM DMA Commutation callback.
\r
2322 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
\r
2323 * the configuration information for the specified DMA module.
\r
2326 void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
\r
2328 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
\r
2330 htim->State= HAL_TIM_STATE_READY;
\r
2332 HAL_TIMEx_CommutationCallback(htim);
\r
2336 * @brief Enables or disables the TIM Capture Compare Channel xN.
\r
2337 * @param TIMx to select the TIM peripheral
\r
2338 * @param Channel: specifies the TIM Channel
\r
2339 * This parameter can be one of the following values:
\r
2340 * @arg TIM_Channel_1: TIM Channel 1
\r
2341 * @arg TIM_Channel_2: TIM Channel 2
\r
2342 * @arg TIM_Channel_3: TIM Channel 3
\r
2343 * @param ChannelNState: specifies the TIM Channel CCxNE bit new state.
\r
2344 * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
\r
2347 static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
\r
2351 /* Check the parameters */
\r
2352 assert_param(IS_TIM_ADVANCED_INSTANCE(TIMx));
\r
2353 assert_param(IS_TIM_COMPLEMENTARY_CHANNELS(Channel));
\r
2355 tmp = TIM_CCER_CC1NE << Channel;
\r
2357 /* Reset the CCxNE Bit */
\r
2358 TIMx->CCER &= ~tmp;
\r
2360 /* Set or reset the CCxNE Bit */
\r
2361 TIMx->CCER |= (uint32_t)(ChannelNState << Channel);
\r
2365 * @brief Timer Output Compare 5 configuration
\r
2366 * @param TIMx to select the TIM peripheral
\r
2367 * @param OC_Config: The output configuration structure
\r
2370 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
\r
2372 uint32_t tmpccmrx = 0;
\r
2373 uint32_t tmpccer = 0;
\r
2374 uint32_t tmpcr2 = 0;
\r
2376 /* Disable the output: Reset the CCxE Bit */
\r
2377 TIMx->CCER &= ~TIM_CCER_CC5E;
\r
2379 /* Get the TIMx CCER register value */
\r
2380 tmpccer = TIMx->CCER;
\r
2381 /* Get the TIMx CR2 register value */
\r
2382 tmpcr2 = TIMx->CR2;
\r
2383 /* Get the TIMx CCMR1 register value */
\r
2384 tmpccmrx = TIMx->CCMR3;
\r
2386 /* Reset the Output Compare Mode Bits */
\r
2387 tmpccmrx &= ~(TIM_CCMR3_OC5M);
\r
2388 /* Select the Output Compare Mode */
\r
2389 tmpccmrx |= OC_Config->OCMode;
\r
2391 /* Reset the Output Polarity level */
\r
2392 tmpccer &= ~TIM_CCER_CC5P;
\r
2393 /* Set the Output Compare Polarity */
\r
2394 tmpccer |= (OC_Config->OCPolarity << 16);
\r
2396 if(IS_TIM_BREAK_INSTANCE(TIMx))
\r
2398 /* Reset the Output Compare IDLE State */
\r
2399 tmpcr2 &= ~TIM_CR2_OIS5;
\r
2400 /* Set the Output Idle state */
\r
2401 tmpcr2 |= (OC_Config->OCIdleState << 8);
\r
2403 /* Write to TIMx CR2 */
\r
2404 TIMx->CR2 = tmpcr2;
\r
2406 /* Write to TIMx CCMR3 */
\r
2407 TIMx->CCMR3 = tmpccmrx;
\r
2409 /* Set the Capture Compare Register value */
\r
2410 TIMx->CCR5 = OC_Config->Pulse;
\r
2412 /* Write to TIMx CCER */
\r
2413 TIMx->CCER = tmpccer;
\r
2417 * @brief Timer Output Compare 6 configuration
\r
2418 * @param TIMx to select the TIM peripheral
\r
2419 * @param OC_Config: The output configuration structure
\r
2422 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
\r
2424 uint32_t tmpccmrx = 0;
\r
2425 uint32_t tmpccer = 0;
\r
2426 uint32_t tmpcr2 = 0;
\r
2428 /* Disable the output: Reset the CCxE Bit */
\r
2429 TIMx->CCER &= ~TIM_CCER_CC6E;
\r
2431 /* Get the TIMx CCER register value */
\r
2432 tmpccer = TIMx->CCER;
\r
2433 /* Get the TIMx CR2 register value */
\r
2434 tmpcr2 = TIMx->CR2;
\r
2435 /* Get the TIMx CCMR1 register value */
\r
2436 tmpccmrx = TIMx->CCMR3;
\r
2438 /* Reset the Output Compare Mode Bits */
\r
2439 tmpccmrx &= ~(TIM_CCMR3_OC6M);
\r
2440 /* Select the Output Compare Mode */
\r
2441 tmpccmrx |= (OC_Config->OCMode << 8);
\r
2443 /* Reset the Output Polarity level */
\r
2444 tmpccer &= (uint32_t)~TIM_CCER_CC6P;
\r
2445 /* Set the Output Compare Polarity */
\r
2446 tmpccer |= (OC_Config->OCPolarity << 20);
\r
2448 if(IS_TIM_BREAK_INSTANCE(TIMx))
\r
2450 /* Reset the Output Compare IDLE State */
\r
2451 tmpcr2 &= ~TIM_CR2_OIS6;
\r
2452 /* Set the Output Idle state */
\r
2453 tmpcr2 |= (OC_Config->OCIdleState << 10);
\r
2456 /* Write to TIMx CR2 */
\r
2457 TIMx->CR2 = tmpcr2;
\r
2459 /* Write to TIMx CCMR3 */
\r
2460 TIMx->CCMR3 = tmpccmrx;
\r
2462 /* Set the Capture Compare Register value */
\r
2463 TIMx->CCR6 = OC_Config->Pulse;
\r
2465 /* Write to TIMx CCER */
\r
2466 TIMx->CCER = tmpccer;
\r
2473 #endif /* HAL_TIM_MODULE_ENABLED */
\r
2481 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
\r
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