1 /* File: startup_ARMCM4.S
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2 * Purpose: startup file for Cortex-M4 devices. Should use with
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3 * GCC for ARM Embedded Processors
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5 * Date: 16 August 2013
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7 /* Copyright (c) 2011 - 2013 ARM LIMITED
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10 Redistribution and use in source and binary forms, with or without
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11 modification, are permitted provided that the following conditions are met:
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12 - Redistributions of source code must retain the above copyright
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13 notice, this list of conditions and the following disclaimer.
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14 - Redistributions in binary form must reproduce the above copyright
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15 notice, this list of conditions and the following disclaimer in the
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16 documentation and/or other materials provided with the distribution.
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17 - Neither the name of ARM nor the names of its contributors may be used
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18 to endorse or promote products derived from this software without
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19 specific prior written permission.
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21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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24 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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31 POSSIBILITY OF SUCH DAMAGE.
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32 ---------------------------------------------------------------------------*/
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36 .extern __SRAM_segment_end__
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38 .section .isr_vector,"a",%progbits
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45 .long __SRAM_segment_end__ - 4 /* Top of Stack at top of RAM*/
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46 .long Reset_Handler /* Reset Handler */
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47 .long NMI_Handler /* NMI Handler */
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48 .long HardFault_Handler /* Hard Fault Handler */
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49 .long MemManage_Handler /* MPU Fault Handler */
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50 .long BusFault_Handler /* Bus Fault Handler */
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51 .long UsageFault_Handler /* Usage Fault Handler */
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52 .long 0 /* Reserved */
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53 .long 0 /* Reserved */
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54 .long 0 /* Reserved */
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55 .long 0 /* Reserved */
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56 .long SVC_Handler /* SVCall Handler */
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57 .long DebugMon_Handler /* Debug Monitor Handler */
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58 .long 0 /* Reserved */
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59 .long PendSV_Handler /* PendSV Handler */
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60 .long SysTick_Handler /* SysTick Handler */
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62 /* External interrupts */
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63 .long NVIC_Handler_GIRQ08 // 40h: 0, GIRQ08
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64 .long NVIC_Handler_GIRQ09 // 44h: 1, GIRQ09
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65 .long NVIC_Handler_GIRQ10 // 48h: 2, GIRQ10
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66 .long NVIC_Handler_GIRQ11 // 4Ch: 3, GIRQ11
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67 .long NVIC_Handler_GIRQ12 // 50h: 4, GIRQ12
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68 .long NVIC_Handler_GIRQ13 // 54h: 5, GIRQ13
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69 .long NVIC_Handler_GIRQ14 // 58h: 6, GIRQ14
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70 .long NVIC_Handler_GIRQ15 // 5Ch: 7, GIRQ15
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71 .long NVIC_Handler_GIRQ16 // 60h: 8, GIRQ16
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72 .long NVIC_Handler_GIRQ17 // 64h: 9, GIRQ17
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73 .long NVIC_Handler_GIRQ18 // 68h: 10, GIRQ18
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74 .long NVIC_Handler_GIRQ19 // 6Ch: 11, GIRQ19
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75 .long NVIC_Handler_GIRQ20 // 70h: 12, GIRQ20
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76 .long NVIC_Handler_GIRQ21 // 74h: 13, GIRQ21
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77 .long NVIC_Handler_GIRQ23 // 78h: 14, GIRQ23
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78 .long NVIC_Handler_GIRQ24 // 7Ch: 15, GIRQ24
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79 .long NVIC_Handler_GIRQ25 // 80h: 16, GIRQ25
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80 .long NVIC_Handler_GIRQ26 // 84h: 17, GIRQ26
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81 .long 0 // 88h: 18, RSVD
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82 .long 0 // 8Ch: 19, RSVD
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83 .long NVIC_Handler_I2C0 // 90h: 20, I2C/SMBus 0
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84 .long NVIC_Handler_I2C1 // 94h: 21, I2C/SMBus 1
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85 .long NVIC_Handler_I2C2 // 98h: 22, I2C/SMBus 2
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86 .long NVIC_Handler_I2C3 // 9Ch: 23, I2C/SMBus 3
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87 .long NVIC_Handler_DMA0 // A0h: 24, DMA Channel 0
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88 .long NVIC_Handler_DMA1 // A4h: 25, DMA Channel 1
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89 .long NVIC_Handler_DMA2 // A8h: 26, DMA Channel 2
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90 .long NVIC_Handler_DMA3 // ACh: 27, DMA Channel 3
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91 .long NVIC_Handler_DMA4 // B0h: 28, DMA Channel 4
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92 .long NVIC_Handler_DMA5 // B4h: 29, DMA Channel 5
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93 .long NVIC_Handler_DMA6 // B8h: 30, DMA Channel 6
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94 .long NVIC_Handler_DMA7 // BCh: 31, DMA Channel 7
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95 .long NVIC_Handler_DMA8 // C0h: 32, DMA Channel 8
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96 .long NVIC_Handler_DMA9 // C4h: 33, DMA Channel 9
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97 .long NVIC_Handler_DMA10 // C8h: 34, DMA Channel 10
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98 .long NVIC_Handler_DMA11 // CCh: 35, DMA Channel 11
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99 .long NVIC_Handler_DMA12 // D0h: 36, DMA Channel 12
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100 .long NVIC_Handler_DMA13 // D4h: 37, DMA Channel 13
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101 .long 0 // D8h: 38, Unused
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102 .long 0 // DCh: 39, Unused
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103 .long NVIC_Handler_UART0 // E0h: 40, UART0
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104 .long NVIC_Handler_UART1 // E4h: 41, UART1
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105 .long NVIC_Handler_EMI0 // E8h: 42, EMI0
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106 .long NVIC_Handler_EMI1 // ECh: 43, EMI0
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107 .long NVIC_Handler_EMI2 // F0h: 44, EMI0
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108 .long NVIC_Handler_ACPI_EC0_IBF // F4h: 45, ACPI_EC0_IBF
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109 .long NVIC_Handler_ACPI_EC0_OBF // F8h: 46, ACPI_EC0_OBF
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110 .long NVIC_Handler_ACPI_EC1_IBF // FCh: 47, ACPI_EC1_IBF
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111 .long NVIC_Handler_ACPI_EC1_OBF // 100h: 48, ACPI_EC1_OBF
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112 .long NVIC_Handler_ACPI_EC2_IBF // 104h: 49, ACPI_EC0_IBF
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113 .long NVIC_Handler_ACPI_EC2_OBF // 108h: 50, ACPI_EC0_OBF
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114 .long NVIC_Handler_ACPI_EC3_IBF // 10Ch: 51, ACPI_EC1_IBF
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115 .long NVIC_Handler_ACPI_EC3_OBF // 110h: 52, ACPI_EC1_OBF
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116 .long NVIC_Handler_ACPI_EC4_IBF // 114h: 53, ACPI_EC0_IBF
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117 .long NVIC_Handler_ACPI_EC4_OBF // 118h: 54, ACPI_EC0_OBF
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118 .long NVIC_Handler_PM1_CTL // 11Ch: 55, ACPI_PM1_CTL
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119 .long NVIC_Handler_PM1_EN // 120h: 56, ACPI_PM1_EN
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120 .long NVIC_Handler_PM1_STS // 124h: 57, ACPI_PM1_STS
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121 .long NVIC_Handler_MIF8042_OBF // 128h: 58, MIF8042_OBF
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122 .long NVIC_Handler_MIF8042_IBF // 12Ch: 59, MIF8042_IBF
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123 .long NVIC_Handler_MB_H2EC // 130h: 60, Mailbox Host to EC
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124 .long NVIC_Handler_MB_DATA // 134h: 61, Mailbox Host Data
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125 .long NVIC_Handler_P80A // 138h: 62, Port 80h A
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126 .long NVIC_Handler_P80B // 13Ch: 63, Port 80h B
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127 .long 0 // 140h: 64, Reserved
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128 .long NVIC_Handler_PKE_ERR // 144h: 65, PKE Error
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129 .long NVIC_Handler_PKE_END // 148h: 66, PKE End
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130 .long NVIC_Handler_TRNG // 14Ch: 67, Random Num Gen
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131 .long NVIC_Handler_AES // 150h: 68, AES
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132 .long NVIC_Handler_HASH // 154h: 69, HASH
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133 .long NVIC_Handler_PECI // 158h: 70, PECI
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134 .long NVIC_Handler_TACH0 // 15Ch: 71, TACH0
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135 .long NVIC_Handler_TACH1 // 160h: 72, TACH1
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136 .long NVIC_Handler_TACH2 // 164h: 73, TACH2
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137 .long NVIC_Handler_R2P0_FAIL // 168h: 74, RPM2PWM 0 Fan Fail
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138 .long NVIC_Handler_R2P0_STALL // 16Ch: 75, RPM2PWM 0 Fan Stall
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139 .long NVIC_Handler_R2P1_FAIL // 170h: 76, RPM2PWM 1 Fan Fail
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140 .long NVIC_Handler_R2P1_STALL // 174h: 77, RPM2PWM 1 Fan Stall
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141 .long NVIC_Handler_ADC_SNGL // 178h: 78, ADC_SNGL
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142 .long NVIC_Handler_ADC_RPT // 17Ch: 79, ADC_RPT
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143 .long NVIC_Handler_RCID0 // 180h: 80, RCID 0
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144 .long NVIC_Handler_RCID1 // 184h: 81, RCID 1
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145 .long NVIC_Handler_RCID2 // 188h: 82, RCID 2
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146 .long NVIC_Handler_LED0 // 18Ch: 83, LED0
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147 .long NVIC_Handler_LED1 // 190h: 84, LED1
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148 .long NVIC_Handler_LED2 // 194h: 85, LED2
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149 .long NVIC_Handler_LED3 // 198h: 86, LED2
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150 .long NVIC_Handler_PHOT // 19Ch: 87, ProcHot Monitor
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151 .long NVIC_Handler_PWRGD0 // 1A0h: 88, PowerGuard 0 Status
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152 .long NVIC_Handler_PWRGD1 // 1A4h: 89, PowerGuard 1 Status
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153 .long NVIC_Handler_LPCBERR // 1A8h: 90, LPC Bus Error
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154 .long NVIC_Handler_QMSPI0 // 1ACh: 91, QMSPI 0
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155 .long NVIC_Handler_GPSPI0_TX // 1B0h: 92, GP-SPI0 TX
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156 .long NVIC_Handler_GPSPI0_RX // 1B4h: 93, GP-SPI0 RX
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157 .long NVIC_Handler_GPSPI1_TX // 1B8h: 94, GP-SPI1 TX
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158 .long NVIC_Handler_GPSPI1_RX // 1BCh: 95, GP-SPI1 RX
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159 .long NVIC_Handler_BC0_BUSY // 1C0h: 96, BC-Link0 Busy-Clear
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160 .long NVIC_Handler_BC0_ERR // 1C4h: 97, BC-Link0 Error
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161 .long NVIC_Handler_BC1_BUSY // 1C8h: 98, BC-Link1 Busy-Clear
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162 .long NVIC_Handler_BC1_ERR // 1CCh: 99, BC-Link1 Error
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163 .long NVIC_Handler_PS2_0 // 1D0h: 100, PS2_0
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164 .long NVIC_Handler_PS2_1 // 1D4h: 101, PS2_1
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165 .long NVIC_Handler_PS2_2 // 1D8h: 102, PS2_2
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166 .long NVIC_Handler_ESPI_PC // 1DCh: 103, eSPI Periph Chan
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167 .long NVIC_Handler_ESPI_BM1 // 1E0h: 104, eSPI Bus Master 1
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168 .long NVIC_Handler_ESPI_BM2 // 1E4h: 105, eSPI Bus Master 2
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169 .long NVIC_Handler_ESPI_LTR // 1E8h: 106, eSPI LTR
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170 .long NVIC_Handler_ESPI_OOB_UP // 1ECh: 107, eSPI Bus Master 1
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171 .long NVIC_Handler_ESPI_OOB_DN // 1F0h: 108, eSPI Bus Master 2
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172 .long NVIC_Handler_ESPI_FLASH // 1F4h: 109, eSPI Flash Chan
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173 .long NVIC_Handler_ESPI_RESET // 1F8h: 110, eSPI Reset
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174 .long NVIC_Handler_RTMR // 1FCh: 111, RTOS Timer
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175 .long NVIC_Handler_HTMR0 // 200h: 112, Hibernation Timer 0
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176 .long NVIC_Handler_HTMR1 // 204h: 113, Hibernation Timer 1
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177 .long NVIC_Handler_WK // 208h: 114, Week Alarm
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178 .long NVIC_Handler_WKSUB // 20Ch: 115, Week Alarm, sub week
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179 .long NVIC_Handler_WKSEC // 210h: 116, Week Alarm, one sec
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180 .long NVIC_Handler_WKSUBSEC // 214h: 117, Week Alarm, sub sec
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181 .long NVIC_Handler_SYSPWR // 218h: 118, System Power Present pin
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182 .long NVIC_Handler_RTC // 21Ch: 119, RTC
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183 .long NVIC_Handler_RTC_ALARM // 220h: 120, RTC_ALARM
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184 .long NVIC_Handler_VCI_OVRD_IN // 224h: 121, VCI Override Input
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185 .long NVIC_Handler_VCI_IN0 // 228h: 122, VCI Input 0
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186 .long NVIC_Handler_VCI_IN1 // 22Ch: 123, VCI Input 1
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187 .long NVIC_Handler_VCI_IN2 // 230h: 124, VCI Input 2
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188 .long NVIC_Handler_VCI_IN3 // 234h: 125, VCI Input 3
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189 .long NVIC_Handler_VCI_IN4 // 238h: 126, VCI Input 4
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190 .long NVIC_Handler_VCI_IN5 // 23Ch: 127, VCI Input 5
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191 .long NVIC_Handler_VCI_IN6 // 240h: 128, VCI Input 6
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192 .long NVIC_Handler_PS20A_WAKE // 244h: 129, PS2 Port 0A Wake
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193 .long NVIC_Handler_PS20B_WAKE // 248h: 130, PS2 Port 0B Wake
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194 .long NVIC_Handler_PS21A_WAKE // 24Ch: 131, PS2 Port 1A Wake
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195 .long NVIC_Handler_PS21B_WAKE // 250h: 132, PS2 Port 1B Wake
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196 .long NVIC_Handler_PS21_WAKE // 254h: 133, PS2 Port 1 Wake
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197 .long NVIC_Handler_ENVMON // 258h: 134, Thernal Monitor
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198 .long NVIC_Handler_KEYSCAN // 25Ch: 135, Key Scan
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199 .long NVIC_Handler_BTMR16_0 // 260h: 136, 16-bit Basic Timer 0
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200 .long NVIC_Handler_BTMR16_1 // 264h: 137, 16-bit Basic Timer 1
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201 .long NVIC_Handler_BTMR16_2 // 268h: 138, 16-bit Basic Timer 2
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202 .long NVIC_Handler_BTMR16_3 // 26Ch: 139, 16-bit Basic Timer 3
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203 .long NVIC_Handler_BTMR32_0 // 270h: 140, 32-bit Basic Timer 0
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204 .long NVIC_Handler_BTMR32_1 // 274h: 141, 32-bit Basic Timer 1
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205 .long NVIC_Handler_EVTMR0 // 278h: 142, Event Counter/Timer 0
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206 .long NVIC_Handler_EVTMR1 // 27Ch: 143, Event Counter/Timer 1
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207 .long NVIC_Handler_EVTMR2 // 280h: 144, Event Counter/Timer 2
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208 .long NVIC_Handler_EVTMR3 // 284h: 145, Event Counter/Timer 3
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209 .long NVIC_Handler_CAPTMR // 288h: 146, Capture Timer
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210 .long NVIC_Handler_CAP0 // 28Ch: 147, Capture 0 Event
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211 .long NVIC_Handler_CAP1 // 290h: 148, Capture 1 Event
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212 .long NVIC_Handler_CAP2 // 294h: 149, Capture 2 Event
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213 .long NVIC_Handler_CAP3 // 298h: 150, Capture 3 Event
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214 .long NVIC_Handler_CAP4 // 29Ch: 151, Capture 4 Event
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215 .long NVIC_Handler_CAP5 // 2A0h: 152, Capture 5 Event
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216 .long NVIC_Handler_CMP0 // 2A4h: 153, Compare 0 Event
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217 .long NVIC_Handler_CMP1 // 2A8h: 154, Compare 1 Event
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226 .globl Reset_Handler
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227 .type Reset_Handler, %function
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230 /* Firstly it copies data from read only memory to RAM. There are two schemes
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231 * to copy. One can copy more than one sections. Another can only copy
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232 * one section. The former scheme needs more instructions and read-only
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233 * data to implement than the latter.
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234 * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
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236 /* Single section scheme.
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238 * The ranges of copy from/to are specified by following symbols
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239 * __etext: LMA of start of the section to copy from. Usually end of text
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240 * __data_start__: VMA of start of the section to copy to
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241 * __data_end__: VMA of end of the section to copy to
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243 * All addresses must be aligned to 4 bytes boundary.
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245 ldr sp, =__SRAM_segment_end__
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249 ldr r2, =__data_start__
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250 ldr r3, =__data_end__
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259 /* This part of work usually is done in C library startup code. Otherwise,
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260 * define this macro to enable it in this startup.
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262 * There are two schemes too. One can clear multiple BSS sections. Another
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263 * can only clear one section. The former is more size expensive than the
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266 * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
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267 * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
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270 /* Single BSS section scheme.
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272 * The BSS section is specified by following symbols
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273 * __bss_start__: start of the BSS section.
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274 * __bss_end__: end of the BSS section.
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276 * Both addresses must be aligned to 4 bytes boundary.
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278 ldr r1, =__bss_start__
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279 ldr r2, =__bss_end__
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288 #ifndef __NO_SYSTEM_INIT
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289 /* bl SystemInit */
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295 .size Reset_Handler, . - Reset_Handler
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299 .weak Default_Handler
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300 .type Default_Handler, %function
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303 .size Default_Handler, . - Default_Handler
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305 /* Macro to define default handlers. Default handler
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306 * will be weak symbol and just dead loops. They can be
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307 * overwritten by other handlers */
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308 .macro def_irq_handler handler_name
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309 .weak \handler_name
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310 .set \handler_name, Default_Handler
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313 def_irq_handler NMI_Handler
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314 def_irq_handler HardFault_Handler
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315 def_irq_handler MemManage_Handler
\r
316 def_irq_handler BusFault_Handler
\r
317 def_irq_handler UsageFault_Handler
\r
318 /* def_irq_handler SVC_Handler */
\r
319 def_irq_handler DebugMon_Handler
\r
320 /* def_irq_handler PendSV_Handler */
\r
321 /* def_irq_handler SysTick_Handler */
\r
322 def_irq_handler DEF_IRQHandler
\r
324 def_irq_handler NVIC_Handler_GIRQ08 // 40h: 0, GIRQ08
\r
325 def_irq_handler NVIC_Handler_GIRQ09 // 44h: 1, GIRQ09
\r
326 def_irq_handler NVIC_Handler_GIRQ10 // 48h: 2, GIRQ10
\r
327 def_irq_handler NVIC_Handler_GIRQ11 // 4Ch: 3, GIRQ11
\r
328 def_irq_handler NVIC_Handler_GIRQ12 // 50h: 4, GIRQ12
\r
329 def_irq_handler NVIC_Handler_GIRQ13 // 54h: 5, GIRQ13
\r
330 def_irq_handler NVIC_Handler_GIRQ14 // 58h: 6, GIRQ14
\r
331 def_irq_handler NVIC_Handler_GIRQ15 // 5Ch: 7, GIRQ15
\r
332 def_irq_handler NVIC_Handler_GIRQ16 // 60h: 8, GIRQ16
\r
333 def_irq_handler NVIC_Handler_GIRQ17 // 64h: 9, GIRQ17
\r
334 def_irq_handler NVIC_Handler_GIRQ18 // 68h: 10, GIRQ18
\r
335 def_irq_handler NVIC_Handler_GIRQ19 // 6Ch: 11, GIRQ19
\r
336 def_irq_handler NVIC_Handler_GIRQ20 // 70h: 12, GIRQ20
\r
337 def_irq_handler NVIC_Handler_GIRQ21 // 74h: 13, GIRQ21
\r
338 def_irq_handler NVIC_Handler_GIRQ23 // 78h: 14, GIRQ23
\r
339 def_irq_handler NVIC_Handler_GIRQ24 // 7Ch: 15, GIRQ24
\r
340 def_irq_handler NVIC_Handler_GIRQ25 // 80h: 16, GIRQ25
\r
341 def_irq_handler NVIC_Handler_GIRQ26 // 84h: 17, GIRQ26
\r
342 def_irq_handler NVIC_Handler_I2C0 // 90h: 20, I2C/SMBus 0
\r
343 def_irq_handler NVIC_Handler_I2C1 // 94h: 21, I2C/SMBus 1
\r
344 def_irq_handler NVIC_Handler_I2C2 // 98h: 22, I2C/SMBus 2
\r
345 def_irq_handler NVIC_Handler_I2C3 // 9Ch: 23, I2C/SMBus 3
\r
346 def_irq_handler NVIC_Handler_DMA0 // A0h: 24, DMA Channel 0
\r
347 def_irq_handler NVIC_Handler_DMA1 // A4h: 25, DMA Channel 1
\r
348 def_irq_handler NVIC_Handler_DMA2 // A8h: 26, DMA Channel 2
\r
349 def_irq_handler NVIC_Handler_DMA3 // ACh: 27, DMA Channel 3
\r
350 def_irq_handler NVIC_Handler_DMA4 // B0h: 28, DMA Channel 4
\r
351 def_irq_handler NVIC_Handler_DMA5 // B4h: 29, DMA Channel 5
\r
352 def_irq_handler NVIC_Handler_DMA6 // B8h: 30, DMA Channel 6
\r
353 def_irq_handler NVIC_Handler_DMA7 // BCh: 31, DMA Channel 7
\r
354 def_irq_handler NVIC_Handler_DMA8 // C0h: 32, DMA Channel 8
\r
355 def_irq_handler NVIC_Handler_DMA9 // C4h: 33, DMA Channel 9
\r
356 def_irq_handler NVIC_Handler_DMA10 // C8h: 34, DMA Channel 10
\r
357 def_irq_handler NVIC_Handler_DMA11 // CCh: 35, DMA Channel 11
\r
358 def_irq_handler NVIC_Handler_DMA12 // D0h: 36, DMA Channel 12
\r
359 def_irq_handler NVIC_Handler_DMA13 // D4h: 37, DMA Channel 13
\r
360 def_irq_handler NVIC_Handler_UART0 // E0h: 40, UART0
\r
361 def_irq_handler NVIC_Handler_UART1 // E4h: 41, UART1
\r
362 def_irq_handler NVIC_Handler_EMI0 // E8h: 42, EMI0
\r
363 def_irq_handler NVIC_Handler_EMI1 // ECh: 43, EMI0
\r
364 def_irq_handler NVIC_Handler_EMI2 // F0h: 44, EMI0
\r
365 def_irq_handler NVIC_Handler_ACPI_EC0_IBF // F4h: 45, ACPI_EC0_IBF
\r
366 def_irq_handler NVIC_Handler_ACPI_EC0_OBF // F8h: 46, ACPI_EC0_OBF
\r
367 def_irq_handler NVIC_Handler_ACPI_EC1_IBF // FCh: 47, ACPI_EC1_IBF
\r
368 def_irq_handler NVIC_Handler_ACPI_EC1_OBF // 100h: 48, ACPI_EC1_OBF
\r
369 def_irq_handler NVIC_Handler_ACPI_EC2_IBF // 104h: 49, ACPI_EC0_IBF
\r
370 def_irq_handler NVIC_Handler_ACPI_EC2_OBF // 108h: 50, ACPI_EC0_OBF
\r
371 def_irq_handler NVIC_Handler_ACPI_EC3_IBF // 10Ch: 51, ACPI_EC1_IBF
\r
372 def_irq_handler NVIC_Handler_ACPI_EC3_OBF // 110h: 52, ACPI_EC1_OBF
\r
373 def_irq_handler NVIC_Handler_ACPI_EC4_IBF // 114h: 53, ACPI_EC0_IBF
\r
374 def_irq_handler NVIC_Handler_ACPI_EC4_OBF // 118h: 54, ACPI_EC0_OBF
\r
375 def_irq_handler NVIC_Handler_PM1_CTL // 11Ch: 55, ACPI_PM1_CTL
\r
376 def_irq_handler NVIC_Handler_PM1_EN // 120h: 56, ACPI_PM1_EN
\r
377 def_irq_handler NVIC_Handler_PM1_STS // 124h: 57, ACPI_PM1_STS
\r
378 def_irq_handler NVIC_Handler_MIF8042_OBF // 128h: 58, MIF8042_OBF
\r
379 def_irq_handler NVIC_Handler_MIF8042_IBF // 12Ch: 59, MIF8042_IBF
\r
380 def_irq_handler NVIC_Handler_MB_H2EC // 130h: 60, Mailbox Host to EC
\r
381 def_irq_handler NVIC_Handler_MB_DATA // 134h: 61, Mailbox Host Data
\r
382 def_irq_handler NVIC_Handler_P80A // 138h: 62, Port 80h A
\r
383 def_irq_handler NVIC_Handler_P80B // 13Ch: 63, Port 80h B
\r
384 def_irq_handler NVIC_Handler_PKE_ERR // 144h: 65, PKE Error
\r
385 def_irq_handler NVIC_Handler_PKE_END // 148h: 66, PKE End
\r
386 def_irq_handler NVIC_Handler_TRNG // 14Ch: 67, Random Num Gen
\r
387 def_irq_handler NVIC_Handler_AES // 150h: 68, AES
\r
388 def_irq_handler NVIC_Handler_HASH // 154h: 69, HASH
\r
389 def_irq_handler NVIC_Handler_PECI // 158h: 70, PECI
\r
390 def_irq_handler NVIC_Handler_TACH0 // 15Ch: 71, TACH0
\r
391 def_irq_handler NVIC_Handler_TACH1 // 160h: 72, TACH1
\r
392 def_irq_handler NVIC_Handler_TACH2 // 164h: 73, TACH2
\r
393 def_irq_handler NVIC_Handler_R2P0_FAIL // 168h: 74, RPM2PWM 0 Fan Fail
\r
394 def_irq_handler NVIC_Handler_R2P0_STALL // 16Ch: 75, RPM2PWM 0 Fan Stall
\r
395 def_irq_handler NVIC_Handler_R2P1_FAIL // 170h: 76, RPM2PWM 1 Fan Fail
\r
396 def_irq_handler NVIC_Handler_R2P1_STALL // 174h: 77, RPM2PWM 1 Fan Stall
\r
397 def_irq_handler NVIC_Handler_ADC_SNGL // 178h: 78, ADC_SNGL
\r
398 def_irq_handler NVIC_Handler_ADC_RPT // 17Ch: 79, ADC_RPT
\r
399 def_irq_handler NVIC_Handler_RCID0 // 180h: 80, RCID 0
\r
400 def_irq_handler NVIC_Handler_RCID1 // 184h: 81, RCID 1
\r
401 def_irq_handler NVIC_Handler_RCID2 // 188h: 82, RCID 2
\r
402 def_irq_handler NVIC_Handler_LED0 // 18Ch: 83, LED0
\r
403 def_irq_handler NVIC_Handler_LED1 // 190h: 84, LED1
\r
404 def_irq_handler NVIC_Handler_LED2 // 194h: 85, LED2
\r
405 def_irq_handler NVIC_Handler_LED3 // 198h: 86, LED2
\r
406 def_irq_handler NVIC_Handler_PHOT // 19Ch: 87, ProcHot Monitor
\r
407 def_irq_handler NVIC_Handler_PWRGD0 // 1A0h: 88, PowerGuard 0 Status
\r
408 def_irq_handler NVIC_Handler_PWRGD1 // 1A4h: 89, PowerGuard 1 Status
\r
409 def_irq_handler NVIC_Handler_LPCBERR // 1A8h: 90, LPC Bus Error
\r
410 def_irq_handler NVIC_Handler_QMSPI0 // 1ACh: 91, QMSPI 0
\r
411 def_irq_handler NVIC_Handler_GPSPI0_TX // 1B0h: 92, GP-SPI0 TX
\r
412 def_irq_handler NVIC_Handler_GPSPI0_RX // 1B4h: 93, GP-SPI0 RX
\r
413 def_irq_handler NVIC_Handler_GPSPI1_TX // 1B8h: 94, GP-SPI1 TX
\r
414 def_irq_handler NVIC_Handler_GPSPI1_RX // 1BCh: 95, GP-SPI1 RX
\r
415 def_irq_handler NVIC_Handler_BC0_BUSY // 1C0h: 96, BC-Link0 Busy-Clear
\r
416 def_irq_handler NVIC_Handler_BC0_ERR // 1C4h: 97, BC-Link0 Error
\r
417 def_irq_handler NVIC_Handler_BC1_BUSY // 1C8h: 98, BC-Link1 Busy-Clear
\r
418 def_irq_handler NVIC_Handler_BC1_ERR // 1CCh: 99, BC-Link1 Error
\r
419 def_irq_handler NVIC_Handler_PS2_0 // 1D0h: 100, PS2_0
\r
420 def_irq_handler NVIC_Handler_PS2_1 // 1D4h: 101, PS2_1
\r
421 def_irq_handler NVIC_Handler_PS2_2 // 1D8h: 102, PS2_2
\r
422 def_irq_handler NVIC_Handler_ESPI_PC // 1DCh: 103, eSPI Periph Chan
\r
423 def_irq_handler NVIC_Handler_ESPI_BM1 // 1E0h: 104, eSPI Bus Master 1
\r
424 def_irq_handler NVIC_Handler_ESPI_BM2 // 1E4h: 105, eSPI Bus Master 2
\r
425 def_irq_handler NVIC_Handler_ESPI_LTR // 1E8h: 106, eSPI LTR
\r
426 def_irq_handler NVIC_Handler_ESPI_OOB_UP // 1ECh: 107, eSPI Bus Master 1
\r
427 def_irq_handler NVIC_Handler_ESPI_OOB_DN // 1F0h: 108, eSPI Bus Master 2
\r
428 def_irq_handler NVIC_Handler_ESPI_FLASH // 1F4h: 109, eSPI Flash Chan
\r
429 def_irq_handler NVIC_Handler_ESPI_RESET // 1F8h: 110, eSPI Reset
\r
430 def_irq_handler NVIC_Handler_RTMR // 1FCh: 111, RTOS Timer
\r
431 def_irq_handler NVIC_Handler_HTMR0 // 200h: 112, Hibernation Timer 0
\r
432 def_irq_handler NVIC_Handler_HTMR1 // 204h: 113, Hibernation Timer 1
\r
433 def_irq_handler NVIC_Handler_WK // 208h: 114, Week Alarm
\r
434 def_irq_handler NVIC_Handler_WKSUB // 20Ch: 115, Week Alarm, sub week
\r
435 def_irq_handler NVIC_Handler_WKSEC // 210h: 116, Week Alarm, one sec
\r
436 def_irq_handler NVIC_Handler_WKSUBSEC // 214h: 117, Week Alarm, sub sec
\r
437 def_irq_handler NVIC_Handler_SYSPWR // 218h: 118, System Power Present pin
\r
438 def_irq_handler NVIC_Handler_RTC // 21Ch: 119, RTC
\r
439 def_irq_handler NVIC_Handler_RTC_ALARM // 220h: 120, RTC_ALARM
\r
440 def_irq_handler NVIC_Handler_VCI_OVRD_IN // 224h: 121, VCI Override Input
\r
441 def_irq_handler NVIC_Handler_VCI_IN0 // 228h: 122, VCI Input 0
\r
442 def_irq_handler NVIC_Handler_VCI_IN1 // 22Ch: 123, VCI Input 1
\r
443 def_irq_handler NVIC_Handler_VCI_IN2 // 230h: 124, VCI Input 2
\r
444 def_irq_handler NVIC_Handler_VCI_IN3 // 234h: 125, VCI Input 3
\r
445 def_irq_handler NVIC_Handler_VCI_IN4 // 238h: 126, VCI Input 4
\r
446 def_irq_handler NVIC_Handler_VCI_IN5 // 23Ch: 127, VCI Input 5
\r
447 def_irq_handler NVIC_Handler_VCI_IN6 // 240h: 128, VCI Input 6
\r
448 def_irq_handler NVIC_Handler_PS20A_WAKE // 244h: 129, PS2 Port 0A Wake
\r
449 def_irq_handler NVIC_Handler_PS20B_WAKE // 248h: 130, PS2 Port 0B Wake
\r
450 def_irq_handler NVIC_Handler_PS21A_WAKE // 24Ch: 131, PS2 Port 1A Wake
\r
451 def_irq_handler NVIC_Handler_PS21B_WAKE // 250h: 132, PS2 Port 1B Wake
\r
452 def_irq_handler NVIC_Handler_PS21_WAKE // 254h: 133, PS2 Port 1 Wake
\r
453 def_irq_handler NVIC_Handler_ENVMON // 258h: 134, Thernal Monitor
\r
454 def_irq_handler NVIC_Handler_KEYSCAN // 25Ch: 135, Key Scan
\r
455 def_irq_handler NVIC_Handler_BTMR16_0 // 260h: 136, 16-bit Basic Timer 0
\r
456 def_irq_handler NVIC_Handler_BTMR16_1 // 264h: 137, 16-bit Basic Timer 1
\r
457 def_irq_handler NVIC_Handler_BTMR16_2 // 268h: 138, 16-bit Basic Timer 2
\r
458 def_irq_handler NVIC_Handler_BTMR16_3 // 26Ch: 139, 16-bit Basic Timer 3
\r
459 def_irq_handler NVIC_Handler_BTMR32_0 // 270h: 140, 32-bit Basic Timer 0
\r
460 def_irq_handler NVIC_Handler_BTMR32_1 // 274h: 141, 32-bit Basic Timer 1
\r
461 def_irq_handler NVIC_Handler_EVTMR0 // 278h: 142, Event Counter/Timer 0
\r
462 def_irq_handler NVIC_Handler_EVTMR1 // 27Ch: 143, Event Counter/Timer 1
\r
463 def_irq_handler NVIC_Handler_EVTMR2 // 280h: 144, Event Counter/Timer 2
\r
464 def_irq_handler NVIC_Handler_EVTMR3 // 284h: 145, Event Counter/Timer 3
\r
465 def_irq_handler NVIC_Handler_CAPTMR // 288h: 146, Capture Timer
\r
466 def_irq_handler NVIC_Handler_CAP0 // 28Ch: 147, Capture 0 Event
\r
467 def_irq_handler NVIC_Handler_CAP1 // 290h: 148, Capture 1 Event
\r
468 def_irq_handler NVIC_Handler_CAP2 // 294h: 149, Capture 2 Event
\r
469 def_irq_handler NVIC_Handler_CAP3 // 298h: 150, Capture 3 Event
\r
470 def_irq_handler NVIC_Handler_CAP4 // 29Ch: 151, Capture 4 Event
\r
471 def_irq_handler NVIC_Handler_CAP5 // 2A0h: 152, Capture 5 Event
\r
472 def_irq_handler NVIC_Handler_CMP0 // 2A4h: 153, Compare 0 Event
\r
473 def_irq_handler NVIC_Handler_CMP1 // 2A8h: 154, Compare 1 Event
\r