1 /*****************************************************************************
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2 * © 2015 Microchip Technology Inc. and its subsidiaries.
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3 * You may use this software and any derivatives exclusively with
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4 * Microchip products.
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5 * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
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6 * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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7 * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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8 * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
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9 * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
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10 * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
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11 * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
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12 * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
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13 * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
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14 * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
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15 * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
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16 * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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17 * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
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19 ******************************************************************************
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21 Version Control Information (Perforce)
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22 ******************************************************************************
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24 $DateTime: 2016/09/22 08:03:49 $
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26 Last Change: Updated for tabs
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27 ******************************************************************************/
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28 /** @file pcr_perphl.c
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29 * \brief Power, Clocks, and Resets Peripheral Source file
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32 * This file implements the PCR Peripheral functions
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33 ******************************************************************************/
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39 #include "common_lib.h"
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42 /* ---------------------------------------------------------------------- */
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43 /* Generic functions to program and read 32-bit values from PCR Registers */
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44 /* ---------------------------------------------------------------------- */
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45 /** Writes 32-bit value in the PCR Register
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46 * @param pcr_reg_id - pcr register id
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47 * @param value - 32-bit value
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49 void p_pcr_reg_write(uint8_t pcr_reg_id, uint32_t value)
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51 __IO uint32_t *pPCR_Reg;
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53 pPCR_Reg = (uint32_t *)(PCR_BASE);
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55 pPCR_Reg += pcr_reg_id;
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60 /** Reads 32-bit value from the PCR Register
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61 * @param pcr_reg_id - pcr register id
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62 * @return value - 32-bit value
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64 uint32_t p_pcr_reg_read(uint8_t pcr_reg_id)
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66 __IO uint32_t *pPCR_Reg;
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69 pPCR_Reg = (uint32_t *)(PCR_BASE);
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71 pPCR_Reg += pcr_reg_id;
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78 /* ---------------------------------------------------------------------- */
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79 /* Functions to set, clr and get bits in PCR Registers */
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80 /* ---------------------------------------------------------------------- */
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82 /** Sets bits in a PCR Register
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83 * @param pcr_reg_id - pcr register id
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84 * @param bit_mask - Bit mask of bits to set
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86 void p_pcr_reg_set(uint8_t pcr_reg_id, uint32_t bit_mask)
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88 __IO uint32_t *pPCR_Reg;
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90 pPCR_Reg = (uint32_t *)(PCR_BASE);
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92 pPCR_Reg += pcr_reg_id;
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94 *pPCR_Reg |= bit_mask;
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97 /** Clears bits in a PCR Register
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98 * @param pcr_reg_id - pcr register id
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99 * @param bit_mask - Bit mask of bits to clear
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101 void p_pcr_reg_clr(uint8_t pcr_reg_id, uint32_t bit_mask)
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103 __IO uint32_t *pPCR_Reg;
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105 pPCR_Reg = (uint32_t *)(PCR_BASE);
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107 pPCR_Reg += pcr_reg_id;
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109 *pPCR_Reg &= ~bit_mask;
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112 /** Read bits in a PCR Register
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113 * @param pcr_reg_id - pcr register id
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114 * @param bit_mask - Bit mask of bits to read
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115 * @return value - 32-bit value
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117 uint32_t p_pcr_reg_get(uint8_t pcr_reg_id, uint32_t bit_mask)
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119 __IO uint32_t *pPCR_Reg;
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122 pPCR_Reg = (uint32_t *)(PCR_BASE);
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124 pPCR_Reg += pcr_reg_id;
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126 retVal = (*pPCR_Reg) & bit_mask;
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131 /** Sets or Clears bits in a PCR Register - Helper Function
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132 * @param pcr_reg_id - pcr register id
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133 * @param bit_mask - Bit mask of bits to set or clear
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134 * @param set_clr_flag - Flag to set (1) or clear (0) bits in the PCR Register
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136 void p_pcr_reg_update(uint8_t pcr_reg_id, uint32_t bit_mask, uint8_t set_clr_flag)
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140 p_pcr_reg_set(pcr_reg_id, bit_mask);
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144 p_pcr_reg_clr(pcr_reg_id, bit_mask);
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148 /* ---------------------------------------------------------------------- */
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149 /* Functions to operate on System Sleep Control Register */
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150 /* ---------------------------------------------------------------------- */
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153 /** Writes required sleep mode in System Sleep Control Register
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154 * @param sleep_value - System Sleep control value (Heavy/Light/Sleep All)
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156 void p_pcr_system_sleep_ctrl_write(uint8_t sleep_value)
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158 __IO uint32_t *pPCR_Reg;
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160 /* Check for valid value */
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161 if ((sleep_value == SYSTEM_LIGHT_SLEEP) ||
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162 (sleep_value == SYSTEM_LIGHT_SLEEP) ||
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163 (sleep_value == SYSTEM_LIGHT_SLEEP))
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165 pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_SLEEP_CTRL;
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167 *pPCR_Reg = (sleep_value & 0x7);
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171 /** Reads the System Sleep Control PCR Register
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172 * @return value - byte 0 of the system sleep control PCR register
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174 uint8_t p_pcr_system_sleep_ctrl_read(void)
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176 __IO uint32_t *pPCR_Reg;
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179 pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_SLEEP_CTRL;
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181 retVal = (uint8_t)((*pPCR_Reg) & 0xFF);
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188 /* ---------------------------------------------------------------------- */
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189 /* Function to program to CLK Divide Value */
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190 /* ---------------------------------------------------------------------- */
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192 /** Writes the clock divide value in the Processor Clock Control Register
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193 * @param clk_divide_value - clk divide values, valid values in enum PROCESSOR_CLK_DIVIDE_VALUE
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195 void p_pcr_processor_clk_ctrl_write(uint8_t clk_divide_value)
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197 __IO uint32_t *pPCR_Reg;
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199 /* Check for valid value */
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200 if (((clk_divide_value >= PCR_CPU_CLK_DIVIDE_1) &&
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201 (clk_divide_value <= PCR_CPU_CLK_DIVIDE_4)) ||
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202 (clk_divide_value == PCR_CPU_CLK_DIVIDE_16) ||
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203 (clk_divide_value == PCR_CPU_CLK_DIVIDE_48))
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205 pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PROCESSOR_CLK_CTRL;
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207 *pPCR_Reg = (clk_divide_value & 0xFF);
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212 /** Writes the clock divide value in the Processor Clock Control Register
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214 * @ return value - clk divide value, valid values in enum PROCESSOR_CLK_DIVIDE_VALUE
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216 uint8_t p_pcr_processor_clk_ctrl_read(void)
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218 __IO uint32_t *pPCR_Reg;
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221 pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PROCESSOR_CLK_CTRL;
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223 retVal = ((uint8_t)((*pPCR_Reg) & 0xFF));
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229 /* ---------------------------------------------------------------------- */
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230 /* Function to program the slow clock divide value */
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231 /* ---------------------------------------------------------------------- */
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233 /** Write the slow clock divide value in the Slow Clock Control Register
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234 * @param slow_clk_divide_value - slow clk divide value
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236 void p_pcr_slow_clk_ctrl_write(uint16_t slow_clk_divide_value)
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238 __IO uint32_t *pPCR_Reg;
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240 pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SLOW_CLK_CTRL;
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242 *pPCR_Reg = (slow_clk_divide_value & 0x3FF);
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246 /* ---------------------------------------------------------------------- */
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247 /* Function to read the Oscillator Lock Status */
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248 /* ---------------------------------------------------------------------- */
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250 /** Reads the Oscillator Lock status bit in the Oscillator ID Register
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251 * @return 1 if Oscillator Lock Status bit is set, else 0
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253 uint8_t p_pcr_oscillator_lock_sts_get(void)
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255 __IO uint32_t *pPCR_Reg;
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258 pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_OSCILLATOR_ID;
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261 if (*pPCR_Reg & PCR_OSCILLATOR_LOCK_STATUS_BITMASK)
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271 /** Reads the Oscillator ID Register
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272 * @return oscillator ID value
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274 uint16_t p_pcr_oscillator_id_reg_read(void)
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276 __IO uint32_t *pPCR_Reg;
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279 pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_OSCILLATOR_ID;
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281 retVal = ((uint16_t)((*pPCR_Reg) & 0x1FFu));
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287 /* ---------------------------------------------------------------------- */
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288 /* Functions to read various power status in Power Reset register */
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289 /* ---------------------------------------------------------------------- */
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291 /** Reads the VCC PWRGD Status bit
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292 * in the Power Reset Status Register
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293 * @return 1 if VCC PWRGD Status bit is set, else 0
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295 uint8_t p_pcr_pwr_reset_vcc_pwrdg_sts_get(void)
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297 __IO uint32_t *pPCR_Reg;
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300 pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS;
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303 if (*pPCR_Reg & PCR_PWR_RESET_STS_VCC_PWRGD_RESET_STS_BITMASK)
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311 /** Reads the Host Reset Status bit
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312 * in the Power Reset Status Register
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313 * @return 1 if Host Reset Status bit is set, else 0
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315 uint8_t p_pcr_pwr_reset_host_reset_sts_get(void)
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317 __IO uint32_t *pPCR_Reg;
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320 pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS;
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323 if (*pPCR_Reg & PCR_PWR_RESET_STS_HOST_RESET_STS_BITMASK)
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331 /** Reads the VBAT Reset Status bit
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332 * in the Power Reset Status Register
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333 * @return 1 if VBAT Reset Status bit is set, else 0
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335 uint8_t p_pcr_pwr_reset_vbat_reset_sts_get(void)
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337 __IO uint32_t *pPCR_Reg;
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340 pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS;
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343 if (*pPCR_Reg & PCR_PWR_RESET_STS_VBAT_RESET_STS_BITMASK)
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351 /** Clears the VBAT Reset Status bit
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352 * in the Power Reset Status Register
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354 void p_pcr_pwr_reset_vbat_reset_sts_clr(void)
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356 __IO uint32_t *pPCR_Reg;
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358 pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS;
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361 *pPCR_Reg |= PCR_PWR_RESET_STS_VBAT_RESET_STS_BITMASK;
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365 /** Reads the VTR Reset Status bit
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366 * in the Power Reset Status Register
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367 * @return 1 if VTR Reset Status bit is set, else 0
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369 uint8_t p_pcr_pwr_reset_vtr_reset_sts_get(void)
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371 __IO uint32_t *pPCR_Reg;
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374 pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS;
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377 if (*pPCR_Reg & PCR_PWR_RESET_STS_VTR_RESET_STS_BITMASK)
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385 /** Clears the VTR Reset Status bit
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386 * in the Power Reset Status Register
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388 void p_pcr_pwr_reset_vtr_reset_sts_clr(void)
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390 __IO uint32_t *pPCR_Reg;
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392 pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS;
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395 *pPCR_Reg |= PCR_PWR_RESET_STS_VTR_RESET_STS_BITMASK;
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399 /** Reads the JTAG Reset Status bit
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400 * in the Power Reset Status Register
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401 * @return 1 if JTAG Reset Status bit is set, else 0
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403 uint8_t p_pcr_pwr_reset_jtag_reset_sts_get(void)
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405 __IO uint32_t *pPCR_Reg;
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408 pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS;
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411 if (*pPCR_Reg & PCR_PWR_RESET_STS_JTAG_RESET_STS_BITMASK)
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419 /** Clears the JTAG Reset Status bit
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420 * in the Power Reset Status Register
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422 void p_pcr_pwr_reset_jtag_reset_sts_clr(void)
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424 __IO uint32_t *pPCR_Reg;
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426 pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS;
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429 *pPCR_Reg |= PCR_PWR_RESET_STS_JTAG_RESET_STS_BITMASK;
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433 /** Reads the 32K_ACTIVE status bit
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434 * in the Chip Subsystem Power Reset Status Register
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435 * @return 1 if 32_ACTIVE bit is set, else 0
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437 uint8_t p_pcr_pwr_reset_32K_active_sts_get(void)
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439 __IO uint32_t *pPCR_Reg;
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442 pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS;
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445 if (*pPCR_Reg & PCR_PWR_RESET_STS_32K_ACTIVE_STS_BITMASK)
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453 /** Reads the PCICLK_ACTIVE status bit
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454 * in the Power Reset Status Register
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455 * @return 1 if PCICLK_ACTIVE bit is set, else 0
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457 uint8_t p_pcr_pwr_reset_pciclk_active_sts_get(void)
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459 __IO uint32_t *pPCR_Reg;
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462 pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS;
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465 if (*pPCR_Reg & PCR_PWR_RESET_STS_PCICLK_ACTIVE_STS_BITMASK)
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472 /** Reads the ESPI status bit
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473 * in the Power Reset Status Register
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474 * @return 1 if ESPICLK_ACTIVE bit is set, else 0
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476 uint8_t p_pcr_pwr_reset_espiclk_active_sts_get(void)
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478 __IO uint32_t *pPCR_Reg;
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481 pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS;
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484 if (*pPCR_Reg & PCR_PWR_RESET_STS_ESPICLK_ACTIVE_STS_BITMASK)
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491 /** Reads the Power status reg
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492 * @return Power Status Reg value
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494 uint16_t p_pcr_pwr_reset_sts_get(void)
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496 __IO uint32_t *pPCR_Reg;
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499 pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS;
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501 retVal = (uint16_t)((*pPCR_Reg) & 0xFFF);
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506 /* ---------------------------------------------------------------------- */
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507 /* Functions for Power Reset Control Register */
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508 /* ---------------------------------------------------------------------- */
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510 /** Reads the Power Reset Control Register
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511 * @return Power Reset Control Register value
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513 uint16_t p_pcr_pwr_reset_ctrl_read(void)
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515 __IO uint32_t *pPCR_Reg;
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518 pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_CTRL;
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520 retVal = (uint16_t)((*pPCR_Reg) & 0x1FFUL);
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525 /** Set the PWR_INV bit in the Power Reset Control Register
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526 * @param set_clr value 1 or 0
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529 void p_pcr_pwr_reset_ctrl_pwr_inv_set_clr(uint8_t set_clr)
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531 __IO uint32_t *pPCR_Reg;
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533 pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_CTRL;
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537 *pPCR_Reg |= (PCR_PWR_RESET_CTRL_PWR_INV_BITMASK);
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541 *pPCR_Reg &= ~(PCR_PWR_RESET_CTRL_PWR_INV_BITMASK);
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545 /** Set the HOST RESET SELECT bit in the Power Reset Control Register
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546 * @param set_clr value 1 or 0
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549 void p_pcr_pwr_reset_ctrl_host_rst_set_clr(uint8_t set_clr)
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551 __IO uint32_t *pPCR_Reg;
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553 pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_CTRL;
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557 *pPCR_Reg |= (PCR_PWR_RESET_CTRL_HOST_RST_SELECT_BITMASK);
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561 *pPCR_Reg &= ~(PCR_PWR_RESET_CTRL_HOST_RST_SELECT_BITMASK);
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566 /* ---------------------------------------------------------------------- */
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567 /* Functions for System Reset Register */
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568 /* ---------------------------------------------------------------------- */
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569 /** Set the SOFT_SYS_RESET bit in the System Reset Register
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573 void p_pcr_system_reset_set()
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575 __IO uint32_t *pPCR_Reg;
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577 pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_RESET;
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579 *pPCR_Reg |= (1<<8);
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582 /* ---------------------------------------------------------------------- */
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583 /* Functions for PKE Clock Register */
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584 /* ---------------------------------------------------------------------- */
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585 /** Set the value in PKE CLOCK Register
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586 * @param PKE Clock value
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589 void p_pcr_pke_clock_write(uint8_t pke_clk_val)
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591 __IO uint32_t *pPCR_Reg;
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593 pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_TEST0;
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595 *pPCR_Reg = pke_clk_val;
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598 /** Read the value in PKE CLOCK Register
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600 * @return PKE Clock value
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602 uint8_t p_pcr_pke_clock_read(void)
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604 __IO uint32_t *pPCR_Reg;
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606 pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_TEST0;
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608 return ((uint8_t)(*pPCR_Reg & 0xFF));
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611 /* ---------------------------------------------------------------------- */
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612 /* Functions for Oscillator calibration Register */
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613 /* ---------------------------------------------------------------------- */
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614 /** Set the value in Oscillator calibration Register
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615 * @param Oscillator calibration value
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618 void p_pcr_osc_cal_write(uint8_t osc_cal_val)
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620 __IO uint32_t *pPCR_Reg;
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622 pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_TEST1;
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624 *pPCR_Reg = osc_cal_val;
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627 /** Read the value in Osc cal Register
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629 * @return Osc cal value
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631 uint8_t p_pcr_osc_cal_read(void)
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633 __IO uint32_t *pPCR_Reg;
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635 pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_TEST1;
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637 return ((uint8_t)(*pPCR_Reg & 0xFF));
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640 /* end pcr_perphl.c */
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