2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
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3 * Copyright 2016-2017,2019 NXP
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4 * All rights reserved.
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6 * SPDX-License-Identifier: BSD-3-Clause
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8 /***********************************************************************************************************************
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9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
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10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
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11 **********************************************************************************************************************/
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13 * How to set up clock using clock driver functions:
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15 * 1. Setup clock sources.
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17 * 2. Setup voltage for the fastest of the clock outputs
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19 * 3. Set up wait states of the flash.
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21 * 4. Set up all dividers.
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23 * 5. Set up all selectors to provide selected clocks.
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26 /* clang-format off */
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27 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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29 product: Clocks v7.0
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31 package_id: LPC54018JET180
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33 processor_version: 0.7.1
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34 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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35 /* clang-format on */
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37 #include "fsl_power.h"
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38 #include "fsl_clock.h"
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39 #include "clock_config.h"
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41 /*******************************************************************************
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43 ******************************************************************************/
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45 /*******************************************************************************
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47 ******************************************************************************/
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48 /* System clock frequency. */
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49 extern uint32_t SystemCoreClock;
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51 /*******************************************************************************
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52 ************************ BOARD_InitBootClocks function ************************
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53 ******************************************************************************/
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54 void BOARD_InitBootClocks(void)
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56 BOARD_BootClockPLL180M();
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59 /*******************************************************************************
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60 ******************** Configuration BOARD_BootClockFRO12M **********************
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61 ******************************************************************************/
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62 /* clang-format off */
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63 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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65 name: BOARD_BootClockFRO12M
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67 - {id: FRO12M_clock.outFreq, value: 12 MHz}
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68 - {id: FROHF_clock.outFreq, value: 48 MHz}
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69 - {id: MAIN_clock.outFreq, value: 12 MHz}
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70 - {id: System_clock.outFreq, value: 12 MHz}
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72 - {id: SYSCON.EMCCLKDIV.scale, value: '1', locked: true}
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73 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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74 /* clang-format on */
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76 /*******************************************************************************
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77 * Variables for BOARD_BootClockFRO12M configuration
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78 ******************************************************************************/
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79 /*******************************************************************************
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80 * Code for BOARD_BootClockFRO12M configuration
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81 ******************************************************************************/
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82 void BOARD_BootClockFRO12M(void)
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84 /*!< Set up the clock sources */
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86 POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */
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87 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without
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88 accidentally being below the voltage for current speed */
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89 /*!< Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U)
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90 before calling this API since this API is implemented in ROM code */
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91 CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
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92 POWER_SetVoltageForFreq(
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93 12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
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95 /*!< Set up dividers */
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96 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */
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98 /*!< Set up clock selectors - Attach clocks to the peripheries */
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99 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */
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100 /* Set SystemCoreClock variable. */
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101 SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
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104 /*******************************************************************************
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105 ******************* Configuration BOARD_BootClockFROHF48M *********************
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106 ******************************************************************************/
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107 /* clang-format off */
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108 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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110 name: BOARD_BootClockFROHF48M
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112 - {id: FRO12M_clock.outFreq, value: 12 MHz}
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113 - {id: FROHF_clock.outFreq, value: 48 MHz}
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114 - {id: MAIN_clock.outFreq, value: 48 MHz}
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115 - {id: System_clock.outFreq, value: 48 MHz}
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117 - {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf}
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118 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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119 /* clang-format on */
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121 /*******************************************************************************
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122 * Variables for BOARD_BootClockFROHF48M configuration
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123 ******************************************************************************/
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124 /*******************************************************************************
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125 * Code for BOARD_BootClockFROHF48M configuration
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126 ******************************************************************************/
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127 void BOARD_BootClockFROHF48M(void)
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129 /*!< Set up the clock sources */
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131 POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */
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132 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without
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133 accidentally being below the voltage for current speed */
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134 POWER_SetVoltageForFreq(
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135 48000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
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136 /*!< Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U)
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137 before calling this API since this API is implemented in ROM code */
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138 CLOCK_SetupFROClocking(48000000U); /*!< Set up high frequency FRO output to selected frequency */
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140 /*!< Set up dividers */
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141 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */
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143 /*!< Set up clock selectors - Attach clocks to the peripheries */
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144 CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
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145 /* Set SystemCoreClock variable. */
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146 SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK;
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149 /*******************************************************************************
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150 ******************* Configuration BOARD_BootClockFROHF96M *********************
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151 ******************************************************************************/
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152 /* clang-format off */
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153 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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155 name: BOARD_BootClockFROHF96M
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157 - {id: FRO12M_clock.outFreq, value: 12 MHz}
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158 - {id: FROHF_clock.outFreq, value: 96 MHz}
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159 - {id: MAIN_clock.outFreq, value: 96 MHz}
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160 - {id: System_clock.outFreq, value: 96 MHz}
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162 - {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf}
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164 - {id: SYSCON.fro_hf.outFreq, value: 96 MHz}
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165 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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166 /* clang-format on */
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168 /*******************************************************************************
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169 * Variables for BOARD_BootClockFROHF96M configuration
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170 ******************************************************************************/
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171 /*******************************************************************************
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172 * Code for BOARD_BootClockFROHF96M configuration
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173 ******************************************************************************/
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174 void BOARD_BootClockFROHF96M(void)
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176 /*!< Set up the clock sources */
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178 POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */
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179 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without
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180 accidentally being below the voltage for current speed */
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181 POWER_SetVoltageForFreq(
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182 96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
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183 /*!< Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U)
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184 before calling this API since this API is implemented in ROM code */
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185 CLOCK_SetupFROClocking(96000000U); /*!< Set up high frequency FRO output to selected frequency */
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187 /*!< Set up dividers */
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188 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */
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190 /*!< Set up clock selectors - Attach clocks to the peripheries */
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191 CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
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192 /* Set SystemCoreClock variable. */
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193 SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK;
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196 /*******************************************************************************
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197 ******************** Configuration BOARD_BootClockPLL180M *********************
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198 ******************************************************************************/
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199 /* clang-format off */
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200 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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202 name: BOARD_BootClockPLL180M
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203 called_from_default_init: true
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205 - {id: FRO12M_clock.outFreq, value: 12 MHz}
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206 - {id: FROHF_clock.outFreq, value: 96 MHz}
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207 - {id: MAIN_clock.outFreq, value: 180 MHz}
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208 - {id: SYSPLL_clock.outFreq, value: 180 MHz}
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209 - {id: System_clock.outFreq, value: 180 MHz}
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210 - {id: USB0_clock.outFreq, value: 96 MHz}
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212 - {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL_BYPASS}
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213 - {id: SYSCON.M_MULT.scale, value: '30', locked: true}
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214 - {id: SYSCON.N_DIV.scale, value: '1', locked: true}
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215 - {id: SYSCON.PDEC.scale, value: '2', locked: true}
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216 - {id: SYSCON.USB0CLKSEL.sel, value: SYSCON.fro_hf}
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217 - {id: SYSCON_PDRUNCFG0_PDEN_SYS_PLL_CFG, value: Power_up}
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219 - {id: SYSCON._clk_in.outFreq, value: 12 MHz, enabled: true}
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220 - {id: SYSCON.fro_hf.outFreq, value: 96 MHz}
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221 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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222 /* clang-format on */
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224 /*******************************************************************************
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225 * Variables for BOARD_BootClockPLL180M configuration
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226 ******************************************************************************/
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227 /*******************************************************************************
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228 * Code for BOARD_BootClockPLL180M configuration
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229 ******************************************************************************/
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230 void BOARD_BootClockPLL180M(void)
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232 /*!< Set up the clock sources */
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234 POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */
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235 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without
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236 accidentally being below the voltage for current speed */
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237 POWER_DisablePD(kPDRUNCFG_PD_SYS_OSC); /*!< Enable System Oscillator Power */
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238 SYSCON->SYSOSCCTRL = ((SYSCON->SYSOSCCTRL & ~SYSCON_SYSOSCCTRL_FREQRANGE_MASK) |
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239 SYSCON_SYSOSCCTRL_FREQRANGE(0U)); /*!< Set system oscillator range */
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240 POWER_SetVoltageForFreq(
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241 180000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
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242 /*!< Set up SYS PLL */
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243 const pll_setup_t pllSetup = {
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244 .pllctrl = SYSCON_SYSPLLCTRL_SELI(32U) | SYSCON_SYSPLLCTRL_SELP(16U) | SYSCON_SYSPLLCTRL_SELR(0U),
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245 .pllmdec = (SYSCON_SYSPLLMDEC_MDEC(8191U)),
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246 .pllndec = (SYSCON_SYSPLLNDEC_NDEC(770U)),
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247 .pllpdec = (SYSCON_SYSPLLPDEC_PDEC(98U)),
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248 .pllRate = 180000000U,
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249 .flags = PLL_SETUPFLAG_WAITLOCK | PLL_SETUPFLAG_POWERUP};
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250 CLOCK_AttachClk(kFRO12M_to_SYS_PLL); /*!< Set sys pll clock source*/
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251 CLOCK_SetPLLFreq(&pllSetup); /*!< Configure PLL to the desired value */
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252 /*!< Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U)
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253 before calling this API since this API is implemented in ROM code */
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254 CLOCK_SetupFROClocking(96000000U); /*!< Set up high frequency FRO output to selected frequency */
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256 /*!< Set up dividers */
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257 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */
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258 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 0U, true); /*!< Reset USB0CLKDIV divider counter and halt it */
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259 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); /*!< Set USB0CLKDIV divider to value 1 */
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261 /*!< Set up clock selectors - Attach clocks to the peripheries */
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262 CLOCK_AttachClk(kSYS_PLL_to_MAIN_CLK); /*!< Switch MAIN_CLK to SYS_PLL */
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263 CLOCK_AttachClk(kFRO_HF_to_USB0_CLK); /*!< Switch USB0_CLK to FRO_HF */
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264 SYSCON->MAINCLKSELA =
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265 ((SYSCON->MAINCLKSELA & ~SYSCON_MAINCLKSELA_SEL_MASK) |
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266 SYSCON_MAINCLKSELA_SEL(0U)); /*!< Switch MAINCLKSELA to FRO12M even it is not used for MAINCLKSELB */
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267 /* Set SystemCoreClock variable. */
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268 SystemCoreClock = BOARD_BOOTCLOCKPLL180M_CORE_CLOCK;
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