2 ** ###################################################################
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3 ** Processors: LPC54018JBD208
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6 ** Compilers: GNU C Compiler
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7 ** IAR ANSI C/C++ Compiler for ARM
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8 ** Keil ARM C/C++ Compiler
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9 ** MCUXpresso Compiler
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11 ** Reference manual: LPC540xx/LPC54S0xx User manual Rev.0.8 5 June 2018
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12 ** Version: rev. 1.2, 2017-06-08
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16 ** CMSIS Peripheral Access Layer for LPC54018
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18 ** Copyright 1997-2016 Freescale Semiconductor, Inc.
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19 ** Copyright 2016-2019 NXP
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20 ** All rights reserved.
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22 ** SPDX-License-Identifier: BSD-3-Clause
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24 ** http: www.nxp.com
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25 ** mail: support@nxp.com
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28 ** - rev. 1.0 (2016-08-12)
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30 ** - rev. 1.1 (2016-11-25)
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31 ** Update CANFD and Classic CAN register.
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32 ** Add MAC TIMERSTAMP registers.
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33 ** - rev. 1.2 (2017-06-08)
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34 ** Remove RTC_CTRL_RTC_OSC_BYPASS.
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35 ** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV.
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36 ** Remove RESET and HALT from SYSCON_AHBCLKDIV.
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38 ** ###################################################################
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45 * @brief CMSIS Peripheral Access Layer for LPC54018
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47 * CMSIS Peripheral Access Layer for LPC54018
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50 #ifndef _LPC54018_H_
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51 #define _LPC54018_H_ /**< Symbol preventing repeated inclusion */
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53 /** Memory map major version (memory maps with equal major version number are
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55 #define MCU_MEM_MAP_VERSION 0x0100U
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56 /** Memory map minor version */
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57 #define MCU_MEM_MAP_VERSION_MINOR 0x0002U
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60 /* ----------------------------------------------------------------------------
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61 -- Interrupt vector numbers
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62 ---------------------------------------------------------------------------- */
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65 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
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69 /** Interrupt Number Definitions */
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70 #define NUMBER_OF_INT_VECTORS 73 /**< Number of interrupts in the Vector table */
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73 /* Auxiliary constants */
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74 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
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76 /* Core interrupts */
\r
77 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
\r
78 HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
\r
79 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
\r
80 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
\r
81 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
\r
82 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
\r
83 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
\r
84 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
\r
85 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
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87 /* Device specific interrupts */
\r
88 WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect */
\r
89 DMA0_IRQn = 1, /**< DMA controller */
\r
90 GINT0_IRQn = 2, /**< GPIO group 0 */
\r
91 GINT1_IRQn = 3, /**< GPIO group 1 */
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92 PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */
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93 PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */
\r
94 PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */
\r
95 PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */
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96 UTICK0_IRQn = 8, /**< Micro-tick Timer */
\r
97 MRT0_IRQn = 9, /**< Multi-rate timer */
\r
98 CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */
\r
99 CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */
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100 SCT0_IRQn = 12, /**< SCTimer/PWM */
\r
101 CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */
\r
102 FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) */
\r
103 FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) */
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104 FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) */
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105 FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) */
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106 FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) */
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107 FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM) */
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108 FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM) */
\r
109 FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM) */
\r
110 ADC0_SEQA_IRQn = 22, /**< ADC0 sequence A completion. */
\r
111 ADC0_SEQB_IRQn = 23, /**< ADC0 sequence B completion. */
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112 ADC0_THCMP_IRQn = 24, /**< ADC0 threshold compare and error. */
\r
113 DMIC0_IRQn = 25, /**< Digital microphone and DMIC subsystem */
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114 HWVAD0_IRQn = 26, /**< Hardware Voice Activity Detector */
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115 USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */
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116 USB0_IRQn = 28, /**< USB device */
\r
117 RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */
\r
118 FLEXCOMM10_IRQn = 30, /**< Flexcomm Interface 10 (SPI, FLEXCOMM) */
\r
119 Reserved47_IRQn = 31, /**< Reserved interrupt */
\r
120 PIN_INT4_IRQn = 32, /**< Pin interrupt 4 or pattern match engine slice 4 int */
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121 PIN_INT5_IRQn = 33, /**< Pin interrupt 5 or pattern match engine slice 5 int */
\r
122 PIN_INT6_IRQn = 34, /**< Pin interrupt 6 or pattern match engine slice 6 int */
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123 PIN_INT7_IRQn = 35, /**< Pin interrupt 7 or pattern match engine slice 7 int */
\r
124 CTIMER2_IRQn = 36, /**< Standard counter/timer CTIMER2 */
\r
125 CTIMER4_IRQn = 37, /**< Standard counter/timer CTIMER4 */
\r
126 RIT_IRQn = 38, /**< Repetitive Interrupt Timer */
\r
127 SPIFI0_IRQn = 39, /**< SPI flash interface */
\r
128 FLEXCOMM8_IRQn = 40, /**< Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM) */
\r
129 FLEXCOMM9_IRQn = 41, /**< Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM) */
\r
130 SDIO_IRQn = 42, /**< SD/MMC */
\r
131 CAN0_IRQ0_IRQn = 43, /**< CAN0 interrupt0 */
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132 CAN0_IRQ1_IRQn = 44, /**< CAN0 interrupt1 */
\r
133 CAN1_IRQ0_IRQn = 45, /**< CAN1 interrupt0 */
\r
134 CAN1_IRQ1_IRQn = 46, /**< CAN1 interrupt1 */
\r
135 USB1_IRQn = 47, /**< USB1 interrupt */
\r
136 USB1_NEEDCLK_IRQn = 48, /**< USB1 activity */
\r
137 ETHERNET_IRQn = 49, /**< Ethernet */
\r
138 ETHERNET_PMT_IRQn = 50, /**< Ethernet power management interrupt */
\r
139 ETHERNET_MACLP_IRQn = 51, /**< Ethernet MAC interrupt */
\r
140 Reserved68_IRQn = 52, /**< Reserved interrupt */
\r
141 LCD_IRQn = 53, /**< LCD interrupt */
\r
142 SHA_IRQn = 54, /**< SHA interrupt */
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143 SMARTCARD0_IRQn = 55, /**< Smart card 0 interrupt */
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144 SMARTCARD1_IRQn = 56 /**< Smart card 1 interrupt */
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149 */ /* end of group Interrupt_vector_numbers */
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152 /* ----------------------------------------------------------------------------
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153 -- Cortex M4 Core Configuration
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154 ---------------------------------------------------------------------------- */
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157 * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
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161 #define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */
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162 #define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */
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163 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
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164 #define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
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166 #include "core_cm4.h" /* Core Peripheral Access Layer */
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167 #include "system_LPC54018.h" /* Device specific configuration file */
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171 */ /* end of group Cortex_Core_Configuration */
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174 /* ----------------------------------------------------------------------------
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175 -- Mapping Information
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176 ---------------------------------------------------------------------------- */
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179 * @addtogroup Mapping_Information Mapping Information
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183 /** Mapping Information */
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185 * @addtogroup dma_request
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189 /*******************************************************************************
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191 ******************************************************************************/
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194 * @brief Structure for the DMA hardware request
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196 * Defines the structure for the DMA hardware request collections. The user can configure the
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197 * hardware request to trigger the DMA transfer accordingly. The index
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198 * of the hardware request varies according to the to SoC.
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200 typedef enum _dma_request_source
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202 kDmaRequestFlexcomm0Rx = 0U, /**< Flexcomm Interface 0 RX/I2C Slave */
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203 kDmaRequestFlexcomm0Tx = 1U, /**< Flexcomm Interface 0 TX/I2C Master */
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204 kDmaRequestFlexcomm1Rx = 2U, /**< Flexcomm Interface 1 RX/I2C Slave */
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205 kDmaRequestFlexcomm1Tx = 3U, /**< Flexcomm Interface 1 TX/I2C Master */
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206 kDmaRequestFlexcomm2Rx = 4U, /**< Flexcomm Interface 2 RX/I2C Slave */
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207 kDmaRequestFlexcomm2Tx = 5U, /**< Flexcomm Interface 2 TX/I2C Master */
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208 kDmaRequestFlexcomm3Rx = 6U, /**< Flexcomm Interface 3 RX/I2C Slave */
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209 kDmaRequestFlexcomm3Tx = 7U, /**< Flexcomm Interface 3 TX/I2C Master */
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210 kDmaRequestFlexcomm4Rx = 8U, /**< Flexcomm Interface 4 RX/I2C Slave */
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211 kDmaRequestFlexcomm4Tx = 9U, /**< Flexcomm Interface 4 TX/I2C Master */
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212 kDmaRequestFlexcomm5Rx = 10U, /**< Flexcomm Interface 5 RX/I2C Slave */
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213 kDmaRequestFlexcomm5Tx = 11U, /**< Flexcomm Interface 5 TX/I2C Master */
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214 kDmaRequestFlexcomm6Rx = 12U, /**< Flexcomm Interface 6 RX/I2C Slave */
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215 kDmaRequestFlexcomm6Tx = 13U, /**< Flexcomm Interface 6 TX/I2C Master */
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216 kDmaRequestFlexcomm7Rx = 14U, /**< Flexcomm Interface 7 RX/I2C Slave */
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217 kDmaRequestFlexcomm7Tx = 15U, /**< Flexcomm Interface 7 TX/I2C Master */
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218 kDmaRequestDMIC0 = 16U, /**< Digital microphone interface 0 channel 0 */
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219 kDmaRequestDMIC1 = 17U, /**< Digital microphone interface 0 channel 1 */
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220 kDmaRequestSPIFI = 18U, /**< SPI Flash Interface */
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221 kDmaRequestSHA = 19U, /**< Secure Hash Algorithm */
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222 kDmaRequestFlexcomm8Rx = 20U, /**< Flexcomm Interface 8 RX/I2C Slave */
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223 kDmaRequestFlexcomm8Tx = 21U, /**< Flexcomm Interface 8 TX/I2C Slave */
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224 kDmaRequestFlexcomm9Rx = 22U, /**< Flexcomm Interface 9 RX/I2C Slave */
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225 kDmaRequestFlexcomm9Tx = 23U, /**< Flexcomm Interface 9 TX/I2C Slave */
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226 kDmaRequestSMARTCARD0_RX = 24U, /**< SMARTCARD0 RX */
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227 kDmaRequestSMARTCARD0_TX = 25U, /**< SMARTCARD0 TX */
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228 kDmaRequestSMARTCARD1_RX = 26U, /**< SMARTCARD1 RX */
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229 kDmaRequestSMARTCARD1_TX = 27U, /**< SMARTCARD1 TX */
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230 kDmaRequestFlexcomm10Rx = 28U, /**< Flexcomm Interface 10 RX */
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231 kDmaRequestFlexcomm10Tx = 29U, /**< Flexcomm Interface 10 TX */
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232 } dma_request_source_t;
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239 */ /* end of group Mapping_Information */
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242 /* ----------------------------------------------------------------------------
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243 -- Device Peripheral Access Layer
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244 ---------------------------------------------------------------------------- */
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247 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
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253 ** Start of section using anonymous unions
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256 #if defined(__ARMCC_VERSION)
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257 #if (__ARMCC_VERSION >= 6010050)
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258 #pragma clang diagnostic push
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261 #pragma anon_unions
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263 #elif defined(__GNUC__)
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264 /* anonymous unions are enabled by default */
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265 #elif defined(__IAR_SYSTEMS_ICC__)
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266 #pragma language=extended
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268 #error Not supported compiler type
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271 /* ----------------------------------------------------------------------------
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272 -- ADC Peripheral Access Layer
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273 ---------------------------------------------------------------------------- */
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276 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
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280 /** ADC - Register Layout Typedef */
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282 __IO uint32_t CTRL; /**< ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls., offset: 0x0 */
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283 __IO uint32_t INSEL; /**< Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0., offset: 0x4 */
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284 __IO uint32_t SEQ_CTRL[2]; /**< ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n., array offset: 0x8, array step: 0x4 */
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285 __I uint32_t SEQ_GDAT[2]; /**< ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n., array offset: 0x10, array step: 0x4 */
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286 uint8_t RESERVED_0[8];
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287 __I uint32_t DAT[12]; /**< ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0., array offset: 0x20, array step: 0x4 */
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288 __IO uint32_t THR0_LOW; /**< ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x50 */
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289 __IO uint32_t THR1_LOW; /**< ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x54 */
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290 __IO uint32_t THR0_HIGH; /**< ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x58 */
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291 __IO uint32_t THR1_HIGH; /**< ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x5C */
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292 __IO uint32_t CHAN_THRSEL; /**< ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel, offset: 0x60 */
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293 __IO uint32_t INTEN; /**< ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated., offset: 0x64 */
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294 __IO uint32_t FLAGS; /**< ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers)., offset: 0x68 */
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295 __IO uint32_t STARTUP; /**< ADC Startup register., offset: 0x6C */
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296 __IO uint32_t CALIB; /**< ADC Calibration register., offset: 0x70 */
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299 /* ----------------------------------------------------------------------------
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300 -- ADC Register Masks
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301 ---------------------------------------------------------------------------- */
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304 * @addtogroup ADC_Register_Masks ADC Register Masks
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308 /*! @name CTRL - ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls. */
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310 #define ADC_CTRL_CLKDIV_MASK (0xFFU)
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311 #define ADC_CTRL_CLKDIV_SHIFT (0U)
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312 /*! CLKDIV - In synchronous mode only, the system clock is divided by this value plus one to produce
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313 * the clock for the ADC converter, which should be less than or equal to 72 MHz. Typically,
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314 * software should program the smallest value in this field that yields this maximum clock rate or
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315 * slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may
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316 * be desirable. This field is ignored in the asynchronous operating mode.
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318 #define ADC_CTRL_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CLKDIV_SHIFT)) & ADC_CTRL_CLKDIV_MASK)
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319 #define ADC_CTRL_ASYNMODE_MASK (0x100U)
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320 #define ADC_CTRL_ASYNMODE_SHIFT (8U)
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321 /*! ASYNMODE - Select clock mode.
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322 * 0b0..Synchronous mode. The ADC clock is derived from the system clock based on the divide value selected in
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323 * the CLKDIV field. The ADC clock will be started in a controlled fashion in response to a trigger to
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324 * eliminate any uncertainty in the launching of an ADC conversion in response to any synchronous (on-chip) trigger.
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325 * In Synchronous mode with the SYNCBYPASS bit (in a sequence control register) set, sampling of the ADC
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326 * input and start of conversion will initiate 2 system clocks after the leading edge of a (synchronous) trigger
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328 * 0b1..Asynchronous mode. The ADC clock is based on the output of the ADC clock divider ADCCLKSEL in the SYSCON block.
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330 #define ADC_CTRL_ASYNMODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ASYNMODE_SHIFT)) & ADC_CTRL_ASYNMODE_MASK)
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331 #define ADC_CTRL_RESOL_MASK (0x600U)
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332 #define ADC_CTRL_RESOL_SHIFT (9U)
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333 /*! RESOL - The number of bits of ADC resolution. Accuracy can be reduced to achieve higher
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334 * conversion rates. A single conversion (including one conversion in a burst or sequence) requires the
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335 * selected number of bits of resolution plus 3 ADC clocks. This field must only be altered when
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336 * the ADC is fully idle. Changing it during any kind of ADC operation may have unpredictable
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337 * results. ADC clock frequencies for various resolutions must not exceed: - 5x the system clock rate
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338 * for 12-bit resolution - 4.3x the system clock rate for 10-bit resolution - 3.6x the system
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339 * clock for 8-bit resolution - 3x the bus clock rate for 6-bit resolution
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340 * 0b00..6-bit resolution. An ADC conversion requires 9 ADC clocks, plus any clocks specified by the TSAMP field.
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341 * 0b01..8-bit resolution. An ADC conversion requires 11 ADC clocks, plus any clocks specified by the TSAMP field.
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342 * 0b10..10-bit resolution. An ADC conversion requires 13 ADC clocks, plus any clocks specified by the TSAMP field.
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343 * 0b11..12-bit resolution. An ADC conversion requires 15 ADC clocks, plus any clocks specified by the TSAMP field.
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345 #define ADC_CTRL_RESOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RESOL_SHIFT)) & ADC_CTRL_RESOL_MASK)
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346 #define ADC_CTRL_BYPASSCAL_MASK (0x800U)
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347 #define ADC_CTRL_BYPASSCAL_SHIFT (11U)
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348 /*! BYPASSCAL - Bypass Calibration. This bit may be set to avoid the need to calibrate if offset
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349 * error is not a concern in the application.
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350 * 0b0..Calibrate. The stored calibration value will be applied to the ADC during conversions to compensated for
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351 * offset error. A calibration cycle must be performed each time the chip is powered-up. Re-calibration may
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352 * be warranted periodically - especially if operating conditions have changed.
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353 * 0b1..Bypass calibration. Calibration is not utilized. Less time is required when enabling the ADC -
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354 * particularly following chip power-up. Attempts to launch a calibration cycle are blocked when this bit is set.
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356 #define ADC_CTRL_BYPASSCAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_BYPASSCAL_SHIFT)) & ADC_CTRL_BYPASSCAL_MASK)
\r
357 #define ADC_CTRL_TSAMP_MASK (0x7000U)
\r
358 #define ADC_CTRL_TSAMP_SHIFT (12U)
\r
359 /*! TSAMP - Sample Time. The default sampling period (TSAMP = '000') at the start of each conversion
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360 * is 2.5 ADC clock periods. Depending on a variety of factors, including operating conditions
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361 * and the output impedance of the analog source, longer sampling times may be required. See
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362 * Section 28.7.10. The TSAMP field specifies the number of additional ADC clock cycles, from zero to
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363 * seven, by which the sample period will be extended. The total conversion time will increase by
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364 * the same number of clocks. 000 - The sample period will be the default 2.5 ADC clocks. A
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365 * complete conversion with 12-bits of accuracy will require 15 clocks. 001- The sample period will
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366 * be extended by one ADC clock to a total of 3.5 clock periods. A complete 12-bit conversion will
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367 * require 16 clocks. 010 - The sample period will be extended by two clocks to 4.5 ADC clock
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368 * cycles. A complete 12-bit conversion will require 17 ADC clocks. 111 - The sample period will be
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369 * extended by seven clocks to 9.5 ADC clock cycles. A complete 12-bit conversion will require
\r
372 #define ADC_CTRL_TSAMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_TSAMP_SHIFT)) & ADC_CTRL_TSAMP_MASK)
\r
375 /*! @name INSEL - Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0. */
\r
377 #define ADC_INSEL_SEL_MASK (0x3U)
\r
378 #define ADC_INSEL_SEL_SHIFT (0U)
\r
379 /*! SEL - Selects the input source for channel 0. All other values are reserved.
\r
380 * 0b00..ADC0_IN0 function.
\r
381 * 0b11..Internal temperature sensor.
\r
383 #define ADC_INSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_INSEL_SEL_SHIFT)) & ADC_INSEL_SEL_MASK)
\r
386 /*! @name SEQ_CTRL - ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n. */
\r
388 #define ADC_SEQ_CTRL_CHANNELS_MASK (0xFFFU)
\r
389 #define ADC_SEQ_CTRL_CHANNELS_SHIFT (0U)
\r
390 /*! CHANNELS - Selects which one or more of the ADC channels will be sampled and converted when this
\r
391 * sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be
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392 * included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1
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393 * and so forth. When this conversion sequence is triggered, either by a hardware trigger or via
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394 * software command, ADC conversions will be performed on each enabled channel, in sequence,
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395 * beginning with the lowest-ordered channel. This field can ONLY be changed while SEQA_ENA (bit 31)
\r
396 * is LOW. It is allowed to change this field and set bit 31 in the same write.
\r
398 #define ADC_SEQ_CTRL_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_CHANNELS_SHIFT)) & ADC_SEQ_CTRL_CHANNELS_MASK)
\r
399 #define ADC_SEQ_CTRL_TRIGGER_MASK (0x3F000U)
\r
400 #define ADC_SEQ_CTRL_TRIGGER_SHIFT (12U)
\r
401 /*! TRIGGER - Selects which of the available hardware trigger sources will cause this conversion
\r
402 * sequence to be initiated. Program the trigger input number in this field. See Table 476. In order
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403 * to avoid generating a spurious trigger, it is recommended writing to this field only when
\r
404 * SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.
\r
406 #define ADC_SEQ_CTRL_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGGER_SHIFT)) & ADC_SEQ_CTRL_TRIGGER_MASK)
\r
407 #define ADC_SEQ_CTRL_TRIGPOL_MASK (0x40000U)
\r
408 #define ADC_SEQ_CTRL_TRIGPOL_SHIFT (18U)
\r
409 /*! TRIGPOL - Select the polarity of the selected input trigger for this conversion sequence. In
\r
410 * order to avoid generating a spurious trigger, it is recommended writing to this field only when
\r
411 * SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.
\r
412 * 0b0..Negative edge. A negative edge launches the conversion sequence on the selected trigger input.
\r
413 * 0b1..Positive edge. A positive edge launches the conversion sequence on the selected trigger input.
\r
415 #define ADC_SEQ_CTRL_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGPOL_SHIFT)) & ADC_SEQ_CTRL_TRIGPOL_MASK)
\r
416 #define ADC_SEQ_CTRL_SYNCBYPASS_MASK (0x80000U)
\r
417 #define ADC_SEQ_CTRL_SYNCBYPASS_SHIFT (19U)
\r
418 /*! SYNCBYPASS - Setting this bit allows the hardware trigger input to bypass synchronization
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419 * flip-flop stages and therefore shorten the time between the trigger input signal and the start of a
\r
420 * conversion. There are slightly different criteria for whether or not this bit can be set
\r
421 * depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0):
\r
422 * Synchronization may be bypassed (this bit may be set) if the selected trigger source is already
\r
423 * synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer).
\r
424 * Whether this bit is set or not, a trigger pulse must be maintained for at least one system
\r
425 * clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be
\r
426 * bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse
\r
427 * will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and
\r
428 * on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be
\r
429 * maintained for one system clock period.
\r
430 * 0b0..Enable trigger synchronization. The hardware trigger bypass is not enabled.
\r
431 * 0b1..Bypass trigger synchronization. The hardware trigger bypass is enabled.
\r
433 #define ADC_SEQ_CTRL_SYNCBYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SYNCBYPASS_SHIFT)) & ADC_SEQ_CTRL_SYNCBYPASS_MASK)
\r
434 #define ADC_SEQ_CTRL_START_MASK (0x4000000U)
\r
435 #define ADC_SEQ_CTRL_START_SHIFT (26U)
\r
436 /*! START - Writing a 1 to this field will launch one pass through this conversion sequence. The
\r
437 * behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this
\r
438 * bit if the BURST bit is set. This bit is only set to a 1 momentarily when written to launch a
\r
439 * conversion sequence. It will consequently always read back as a zero.
\r
441 #define ADC_SEQ_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_START_SHIFT)) & ADC_SEQ_CTRL_START_MASK)
\r
442 #define ADC_SEQ_CTRL_BURST_MASK (0x8000000U)
\r
443 #define ADC_SEQ_CTRL_BURST_SHIFT (27U)
\r
444 /*! BURST - Writing a 1 to this bit will cause this conversion sequence to be continuously cycled
\r
445 * through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions
\r
446 * can be halted by clearing this bit. The sequence currently in progress will be completed before
\r
447 * conversions are terminated. Note that a new sequence could begin just before BURST is cleared.
\r
449 #define ADC_SEQ_CTRL_BURST(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_BURST_SHIFT)) & ADC_SEQ_CTRL_BURST_MASK)
\r
450 #define ADC_SEQ_CTRL_SINGLESTEP_MASK (0x10000000U)
\r
451 #define ADC_SEQ_CTRL_SINGLESTEP_SHIFT (28U)
\r
452 /*! SINGLESTEP - When this bit is set, a hardware trigger or a write to the START bit will launch a
\r
453 * single conversion on the next channel in the sequence instead of the default response of
\r
454 * launching an entire sequence of conversions. Once all of the channels comprising a sequence have
\r
455 * been converted, a subsequent trigger will repeat the sequence beginning with the first enabled
\r
456 * channel. Interrupt generation will still occur either after each individual conversion or at
\r
457 * the end of the entire sequence, depending on the state of the MODE bit.
\r
459 #define ADC_SEQ_CTRL_SINGLESTEP(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SINGLESTEP_SHIFT)) & ADC_SEQ_CTRL_SINGLESTEP_MASK)
\r
460 #define ADC_SEQ_CTRL_LOWPRIO_MASK (0x20000000U)
\r
461 #define ADC_SEQ_CTRL_LOWPRIO_SHIFT (29U)
\r
462 /*! LOWPRIO - Set priority for sequence A.
\r
463 * 0b0..Low priority. Any B trigger which occurs while an A conversion sequence is active will be ignored and lost.
\r
464 * 0b1..High priority. Setting this bit to a 1 will permit any enabled B sequence trigger (including a B sequence
\r
465 * software start) to immediately interrupt sequence A and launch a B sequence in it's place. The conversion
\r
466 * currently in progress will be terminated. The A sequence that was interrupted will automatically resume
\r
467 * after the B sequence completes. The channel whose conversion was terminated will be re-sampled and the
\r
468 * conversion sequence will resume from that point.
\r
470 #define ADC_SEQ_CTRL_LOWPRIO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_LOWPRIO_SHIFT)) & ADC_SEQ_CTRL_LOWPRIO_MASK)
\r
471 #define ADC_SEQ_CTRL_MODE_MASK (0x40000000U)
\r
472 #define ADC_SEQ_CTRL_MODE_SHIFT (30U)
\r
473 /*! MODE - Indicates whether the primary method for retrieving conversion results for this sequence
\r
474 * will be accomplished via reading the global data register (SEQA_GDAT) at the end of each
\r
475 * conversion, or the individual channel result registers at the end of the entire sequence. Impacts
\r
476 * when conversion-complete interrupt/DMA trigger for sequence-A will be generated and which
\r
477 * overrun conditions contribute to an overrun interrupt as described below.
\r
478 * 0b0..End of conversion. The sequence A interrupt/DMA trigger will be set at the end of each individual ADC
\r
479 * conversion performed under sequence A. This flag will mirror the DATAVALID bit in the SEQA_GDAT register. The
\r
480 * OVERRUN bit in the SEQA_GDAT register will contribute to generation of an overrun interrupt/DMA trigger
\r
482 * 0b1..End of sequence. The sequence A interrupt/DMA trigger will be set when the entire set of sequence-A
\r
483 * conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in
\r
484 * this mode. The OVERRUN bit in the SEQA_GDAT register will NOT contribute to generation of an overrun
\r
485 * interrupt/DMA trigger since it is assumed this register may not be utilized in this mode.
\r
487 #define ADC_SEQ_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_MODE_SHIFT)) & ADC_SEQ_CTRL_MODE_MASK)
\r
488 #define ADC_SEQ_CTRL_SEQ_ENA_MASK (0x80000000U)
\r
489 #define ADC_SEQ_CTRL_SEQ_ENA_SHIFT (31U)
\r
490 /*! SEQ_ENA - Sequence Enable. In order to avoid spuriously triggering the sequence, care should be
\r
491 * taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state
\r
492 * (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered
\r
493 * immediately upon being enabled. In order to avoid spuriously triggering the sequence, care
\r
494 * should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE
\r
495 * state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be
\r
496 * triggered immediately upon being enabled.
\r
497 * 0b0..Disabled. Sequence n is disabled. Sequence n triggers are ignored. If this bit is cleared while sequence
\r
498 * n is in progress, the sequence will be halted at the end of the current conversion. After the sequence is
\r
499 * re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel.
\r
500 * 0b1..Enabled. Sequence n is enabled.
\r
502 #define ADC_SEQ_CTRL_SEQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SEQ_ENA_SHIFT)) & ADC_SEQ_CTRL_SEQ_ENA_MASK)
\r
505 /* The count of ADC_SEQ_CTRL */
\r
506 #define ADC_SEQ_CTRL_COUNT (2U)
\r
508 /*! @name SEQ_GDAT - ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n. */
\r
510 #define ADC_SEQ_GDAT_RESULT_MASK (0xFFF0U)
\r
511 #define ADC_SEQ_GDAT_RESULT_SHIFT (4U)
\r
512 /*! RESULT - This field contains the 12-bit ADC conversion result from the most recent conversion
\r
513 * performed under conversion sequence associated with this register. The result is a binary
\r
514 * fraction representing the voltage on the currently-selected input channel as it falls within the
\r
515 * range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less
\r
516 * than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input
\r
517 * was close to, equal to, or greater than that on VREFP. DATAVALID = 1 indicates that this
\r
518 * result has not yet been read.
\r
520 #define ADC_SEQ_GDAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_RESULT_SHIFT)) & ADC_SEQ_GDAT_RESULT_MASK)
\r
521 #define ADC_SEQ_GDAT_THCMPRANGE_MASK (0x30000U)
\r
522 #define ADC_SEQ_GDAT_THCMPRANGE_SHIFT (16U)
\r
523 /*! THCMPRANGE - Indicates whether the result of the last conversion performed was above, below or
\r
524 * within the range established by the designated threshold comparison registers (THRn_LOW and
\r
527 #define ADC_SEQ_GDAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPRANGE_SHIFT)) & ADC_SEQ_GDAT_THCMPRANGE_MASK)
\r
528 #define ADC_SEQ_GDAT_THCMPCROSS_MASK (0xC0000U)
\r
529 #define ADC_SEQ_GDAT_THCMPCROSS_SHIFT (18U)
\r
530 /*! THCMPCROSS - Indicates whether the result of the last conversion performed represented a
\r
531 * crossing of the threshold level established by the designated LOW threshold comparison register
\r
532 * (THRn_LOW) and, if so, in what direction the crossing occurred.
\r
534 #define ADC_SEQ_GDAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPCROSS_SHIFT)) & ADC_SEQ_GDAT_THCMPCROSS_MASK)
\r
535 #define ADC_SEQ_GDAT_CHN_MASK (0x3C000000U)
\r
536 #define ADC_SEQ_GDAT_CHN_SHIFT (26U)
\r
537 /*! CHN - These bits contain the channel from which the RESULT bits were converted (e.g. 0000
\r
538 * identifies channel 0, 0001 channel 1, etc.).
\r
540 #define ADC_SEQ_GDAT_CHN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_CHN_SHIFT)) & ADC_SEQ_GDAT_CHN_MASK)
\r
541 #define ADC_SEQ_GDAT_OVERRUN_MASK (0x40000000U)
\r
542 #define ADC_SEQ_GDAT_OVERRUN_SHIFT (30U)
\r
543 /*! OVERRUN - This bit is set if a new conversion result is loaded into the RESULT field before a
\r
544 * previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along
\r
545 * with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun
\r
546 * interrupt/DMA trigger if the MODE bit (in SEQAA_CTRL) for the corresponding sequence is set
\r
547 * to '0' (and if the overrun interrupt is enabled).
\r
549 #define ADC_SEQ_GDAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_OVERRUN_SHIFT)) & ADC_SEQ_GDAT_OVERRUN_MASK)
\r
550 #define ADC_SEQ_GDAT_DATAVALID_MASK (0x80000000U)
\r
551 #define ADC_SEQ_GDAT_DATAVALID_SHIFT (31U)
\r
552 /*! DATAVALID - This bit is set to '1' at the end of each conversion when a new result is loaded
\r
553 * into the RESULT field. It is cleared whenever this register is read. This bit will cause a
\r
554 * conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQA_CTRL) for that
\r
555 * sequence is set to 0 (and if the interrupt is enabled).
\r
557 #define ADC_SEQ_GDAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_DATAVALID_SHIFT)) & ADC_SEQ_GDAT_DATAVALID_MASK)
\r
560 /* The count of ADC_SEQ_GDAT */
\r
561 #define ADC_SEQ_GDAT_COUNT (2U)
\r
563 /*! @name DAT - ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0. */
\r
565 #define ADC_DAT_RESULT_MASK (0xFFF0U)
\r
566 #define ADC_DAT_RESULT_SHIFT (4U)
\r
567 /*! RESULT - This field contains the 12-bit ADC conversion result from the last conversion performed
\r
568 * on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin,
\r
569 * as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on
\r
570 * the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that
\r
571 * the voltage on the input was close to, equal to, or greater than that on VREFP.
\r
573 #define ADC_DAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_RESULT_SHIFT)) & ADC_DAT_RESULT_MASK)
\r
574 #define ADC_DAT_THCMPRANGE_MASK (0x30000U)
\r
575 #define ADC_DAT_THCMPRANGE_SHIFT (16U)
\r
576 /*! THCMPRANGE - Threshold Range Comparison result. 0x0 = In Range: The last completed conversion
\r
577 * was greater than or equal to the value programmed into the designated LOW threshold register
\r
578 * (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold
\r
579 * register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value
\r
580 * programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last
\r
581 * completed conversion was greater than the value programmed into the designated HIGH threshold
\r
582 * register (THRn_HIGH). 0x3 = Reserved.
\r
584 #define ADC_DAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPRANGE_SHIFT)) & ADC_DAT_THCMPRANGE_MASK)
\r
585 #define ADC_DAT_THCMPCROSS_MASK (0xC0000U)
\r
586 #define ADC_DAT_THCMPCROSS_SHIFT (18U)
\r
587 /*! THCMPCROSS - Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The
\r
588 * most recent completed conversion on this channel had the same relationship (above or below) to
\r
589 * the threshold value established by the designated LOW threshold register (THRn_LOW) as did the
\r
590 * previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing
\r
591 * Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the
\r
592 * previous sample on this channel was above the threshold value established by the designated LOW
\r
593 * threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward
\r
594 * Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred
\r
595 * - i.e. the previous sample on this channel was below the threshold value established by the
\r
596 * designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
\r
598 #define ADC_DAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPCROSS_SHIFT)) & ADC_DAT_THCMPCROSS_MASK)
\r
599 #define ADC_DAT_CHANNEL_MASK (0x3C000000U)
\r
600 #define ADC_DAT_CHANNEL_SHIFT (26U)
\r
601 /*! CHANNEL - This field is hard-coded to contain the channel number that this particular register
\r
602 * relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1
\r
605 #define ADC_DAT_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_CHANNEL_SHIFT)) & ADC_DAT_CHANNEL_MASK)
\r
606 #define ADC_DAT_OVERRUN_MASK (0x40000000U)
\r
607 #define ADC_DAT_OVERRUN_SHIFT (30U)
\r
608 /*! OVERRUN - This bit will be set to a 1 if a new conversion on this channel completes and
\r
609 * overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit
\r
610 * is set. This bit is cleared, along with the DONE bit, whenever this register is read or when
\r
611 * the data related to this channel is read from either of the global SEQn_GDAT registers. This
\r
612 * bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if
\r
613 * the overrun interrupt is enabled. While it is allowed to include the same channels in both
\r
614 * conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the
\r
615 * data registers associated with any of the channels that are shared between the two sequences. Any
\r
616 * erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
\r
618 #define ADC_DAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_OVERRUN_SHIFT)) & ADC_DAT_OVERRUN_MASK)
\r
619 #define ADC_DAT_DATAVALID_MASK (0x80000000U)
\r
620 #define ADC_DAT_DATAVALID_SHIFT (31U)
\r
621 /*! DATAVALID - This bit is set to 1 when an ADC conversion on this channel completes. This bit is
\r
622 * cleared whenever this register is read or when the data related to this channel is read from
\r
623 * either of the global SEQn_GDAT registers. While it is allowed to include the same channels in
\r
624 * both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in
\r
625 * the data registers associated with any of the channels that are shared between the two
\r
626 * sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
\r
628 #define ADC_DAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_DATAVALID_SHIFT)) & ADC_DAT_DATAVALID_MASK)
\r
631 /* The count of ADC_DAT */
\r
632 #define ADC_DAT_COUNT (12U)
\r
634 /*! @name THR0_LOW - ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */
\r
636 #define ADC_THR0_LOW_THRLOW_MASK (0xFFF0U)
\r
637 #define ADC_THR0_LOW_THRLOW_SHIFT (4U)
\r
638 /*! THRLOW - Low threshold value against which ADC results will be compared
\r
640 #define ADC_THR0_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_LOW_THRLOW_SHIFT)) & ADC_THR0_LOW_THRLOW_MASK)
\r
643 /*! @name THR1_LOW - ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */
\r
645 #define ADC_THR1_LOW_THRLOW_MASK (0xFFF0U)
\r
646 #define ADC_THR1_LOW_THRLOW_SHIFT (4U)
\r
647 /*! THRLOW - Low threshold value against which ADC results will be compared
\r
649 #define ADC_THR1_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_LOW_THRLOW_SHIFT)) & ADC_THR1_LOW_THRLOW_MASK)
\r
652 /*! @name THR0_HIGH - ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */
\r
654 #define ADC_THR0_HIGH_THRHIGH_MASK (0xFFF0U)
\r
655 #define ADC_THR0_HIGH_THRHIGH_SHIFT (4U)
\r
656 /*! THRHIGH - High threshold value against which ADC results will be compared
\r
658 #define ADC_THR0_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_HIGH_THRHIGH_SHIFT)) & ADC_THR0_HIGH_THRHIGH_MASK)
\r
661 /*! @name THR1_HIGH - ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */
\r
663 #define ADC_THR1_HIGH_THRHIGH_MASK (0xFFF0U)
\r
664 #define ADC_THR1_HIGH_THRHIGH_SHIFT (4U)
\r
665 /*! THRHIGH - High threshold value against which ADC results will be compared
\r
667 #define ADC_THR1_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_HIGH_THRHIGH_SHIFT)) & ADC_THR1_HIGH_THRHIGH_MASK)
\r
670 /*! @name CHAN_THRSEL - ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel */
\r
672 #define ADC_CHAN_THRSEL_CH0_THRSEL_MASK (0x1U)
\r
673 #define ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT (0U)
\r
674 /*! CH0_THRSEL - Threshold select for channel 0.
\r
675 * 0b0..Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers.
\r
676 * 0b1..Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers.
\r
678 #define ADC_CHAN_THRSEL_CH0_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH0_THRSEL_MASK)
\r
679 #define ADC_CHAN_THRSEL_CH1_THRSEL_MASK (0x2U)
\r
680 #define ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT (1U)
\r
681 /*! CH1_THRSEL - Threshold select for channel 1. See description for channel 0.
\r
683 #define ADC_CHAN_THRSEL_CH1_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH1_THRSEL_MASK)
\r
684 #define ADC_CHAN_THRSEL_CH2_THRSEL_MASK (0x4U)
\r
685 #define ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT (2U)
\r
686 /*! CH2_THRSEL - Threshold select for channel 2. See description for channel 0.
\r
688 #define ADC_CHAN_THRSEL_CH2_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH2_THRSEL_MASK)
\r
689 #define ADC_CHAN_THRSEL_CH3_THRSEL_MASK (0x8U)
\r
690 #define ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT (3U)
\r
691 /*! CH3_THRSEL - Threshold select for channel 3. See description for channel 0.
\r
693 #define ADC_CHAN_THRSEL_CH3_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH3_THRSEL_MASK)
\r
694 #define ADC_CHAN_THRSEL_CH4_THRSEL_MASK (0x10U)
\r
695 #define ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT (4U)
\r
696 /*! CH4_THRSEL - Threshold select for channel 4. See description for channel 0.
\r
698 #define ADC_CHAN_THRSEL_CH4_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH4_THRSEL_MASK)
\r
699 #define ADC_CHAN_THRSEL_CH5_THRSEL_MASK (0x20U)
\r
700 #define ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT (5U)
\r
701 /*! CH5_THRSEL - Threshold select for channel 5. See description for channel 0.
\r
703 #define ADC_CHAN_THRSEL_CH5_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH5_THRSEL_MASK)
\r
704 #define ADC_CHAN_THRSEL_CH6_THRSEL_MASK (0x40U)
\r
705 #define ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT (6U)
\r
706 /*! CH6_THRSEL - Threshold select for channel 6. See description for channel 0.
\r
708 #define ADC_CHAN_THRSEL_CH6_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH6_THRSEL_MASK)
\r
709 #define ADC_CHAN_THRSEL_CH7_THRSEL_MASK (0x80U)
\r
710 #define ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT (7U)
\r
711 /*! CH7_THRSEL - Threshold select for channel 7. See description for channel 0.
\r
713 #define ADC_CHAN_THRSEL_CH7_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH7_THRSEL_MASK)
\r
714 #define ADC_CHAN_THRSEL_CH8_THRSEL_MASK (0x100U)
\r
715 #define ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT (8U)
\r
716 /*! CH8_THRSEL - Threshold select for channel 8. See description for channel 0.
\r
718 #define ADC_CHAN_THRSEL_CH8_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH8_THRSEL_MASK)
\r
719 #define ADC_CHAN_THRSEL_CH9_THRSEL_MASK (0x200U)
\r
720 #define ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT (9U)
\r
721 /*! CH9_THRSEL - Threshold select for channel 9. See description for channel 0.
\r
723 #define ADC_CHAN_THRSEL_CH9_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH9_THRSEL_MASK)
\r
724 #define ADC_CHAN_THRSEL_CH10_THRSEL_MASK (0x400U)
\r
725 #define ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT (10U)
\r
726 /*! CH10_THRSEL - Threshold select for channel 10. See description for channel 0.
\r
728 #define ADC_CHAN_THRSEL_CH10_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH10_THRSEL_MASK)
\r
729 #define ADC_CHAN_THRSEL_CH11_THRSEL_MASK (0x800U)
\r
730 #define ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT (11U)
\r
731 /*! CH11_THRSEL - Threshold select for channel 11. See description for channel 0.
\r
733 #define ADC_CHAN_THRSEL_CH11_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH11_THRSEL_MASK)
\r
736 /*! @name INTEN - ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated. */
\r
738 #define ADC_INTEN_SEQA_INTEN_MASK (0x1U)
\r
739 #define ADC_INTEN_SEQA_INTEN_SHIFT (0U)
\r
740 /*! SEQA_INTEN - Sequence A interrupt enable.
\r
741 * 0b0..Disabled. The sequence A interrupt/DMA trigger is disabled.
\r
742 * 0b1..Enabled. The sequence A interrupt/DMA trigger is enabled and will be asserted either upon completion of
\r
743 * each individual conversion performed as part of sequence A, or upon completion of the entire A sequence of
\r
744 * conversions, depending on the MODE bit in the SEQA_CTRL register.
\r
746 #define ADC_INTEN_SEQA_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQA_INTEN_SHIFT)) & ADC_INTEN_SEQA_INTEN_MASK)
\r
747 #define ADC_INTEN_SEQB_INTEN_MASK (0x2U)
\r
748 #define ADC_INTEN_SEQB_INTEN_SHIFT (1U)
\r
749 /*! SEQB_INTEN - Sequence B interrupt enable.
\r
750 * 0b0..Disabled. The sequence B interrupt/DMA trigger is disabled.
\r
751 * 0b1..Enabled. The sequence B interrupt/DMA trigger is enabled and will be asserted either upon completion of
\r
752 * each individual conversion performed as part of sequence B, or upon completion of the entire B sequence of
\r
753 * conversions, depending on the MODE bit in the SEQB_CTRL register.
\r
755 #define ADC_INTEN_SEQB_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQB_INTEN_SHIFT)) & ADC_INTEN_SEQB_INTEN_MASK)
\r
756 #define ADC_INTEN_OVR_INTEN_MASK (0x4U)
\r
757 #define ADC_INTEN_OVR_INTEN_SHIFT (2U)
\r
758 /*! OVR_INTEN - Overrun interrupt enable.
\r
759 * 0b0..Disabled. The overrun interrupt is disabled.
\r
760 * 0b1..Enabled. The overrun interrupt is enabled. Detection of an overrun condition on any of the 12 channel
\r
761 * data registers will cause an overrun interrupt/DMA trigger. In addition, if the MODE bit for a particular
\r
762 * sequence is 0, then an overrun in the global data register for that sequence will also cause this
\r
763 * interrupt/DMA trigger to be asserted.
\r
765 #define ADC_INTEN_OVR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_OVR_INTEN_SHIFT)) & ADC_INTEN_OVR_INTEN_MASK)
\r
766 #define ADC_INTEN_ADCMPINTEN0_MASK (0x18U)
\r
767 #define ADC_INTEN_ADCMPINTEN0_SHIFT (3U)
\r
768 /*! ADCMPINTEN0 - Threshold comparison interrupt enable for channel 0.
\r
770 * 0b01..Outside threshold.
\r
771 * 0b10..Crossing threshold.
\r
774 #define ADC_INTEN_ADCMPINTEN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN0_SHIFT)) & ADC_INTEN_ADCMPINTEN0_MASK)
\r
775 #define ADC_INTEN_ADCMPINTEN1_MASK (0x60U)
\r
776 #define ADC_INTEN_ADCMPINTEN1_SHIFT (5U)
\r
777 /*! ADCMPINTEN1 - Channel 1 threshold comparison interrupt enable. See description for channel 0.
\r
779 #define ADC_INTEN_ADCMPINTEN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN1_SHIFT)) & ADC_INTEN_ADCMPINTEN1_MASK)
\r
780 #define ADC_INTEN_ADCMPINTEN2_MASK (0x180U)
\r
781 #define ADC_INTEN_ADCMPINTEN2_SHIFT (7U)
\r
782 /*! ADCMPINTEN2 - Channel 2 threshold comparison interrupt enable. See description for channel 0.
\r
784 #define ADC_INTEN_ADCMPINTEN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN2_SHIFT)) & ADC_INTEN_ADCMPINTEN2_MASK)
\r
785 #define ADC_INTEN_ADCMPINTEN3_MASK (0x600U)
\r
786 #define ADC_INTEN_ADCMPINTEN3_SHIFT (9U)
\r
787 /*! ADCMPINTEN3 - Channel 3 threshold comparison interrupt enable. See description for channel 0.
\r
789 #define ADC_INTEN_ADCMPINTEN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN3_SHIFT)) & ADC_INTEN_ADCMPINTEN3_MASK)
\r
790 #define ADC_INTEN_ADCMPINTEN4_MASK (0x1800U)
\r
791 #define ADC_INTEN_ADCMPINTEN4_SHIFT (11U)
\r
792 /*! ADCMPINTEN4 - Channel 4 threshold comparison interrupt enable. See description for channel 0.
\r
794 #define ADC_INTEN_ADCMPINTEN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN4_SHIFT)) & ADC_INTEN_ADCMPINTEN4_MASK)
\r
795 #define ADC_INTEN_ADCMPINTEN5_MASK (0x6000U)
\r
796 #define ADC_INTEN_ADCMPINTEN5_SHIFT (13U)
\r
797 /*! ADCMPINTEN5 - Channel 5 threshold comparison interrupt enable. See description for channel 0.
\r
799 #define ADC_INTEN_ADCMPINTEN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN5_SHIFT)) & ADC_INTEN_ADCMPINTEN5_MASK)
\r
800 #define ADC_INTEN_ADCMPINTEN6_MASK (0x18000U)
\r
801 #define ADC_INTEN_ADCMPINTEN6_SHIFT (15U)
\r
802 /*! ADCMPINTEN6 - Channel 6 threshold comparison interrupt enable. See description for channel 0.
\r
804 #define ADC_INTEN_ADCMPINTEN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN6_SHIFT)) & ADC_INTEN_ADCMPINTEN6_MASK)
\r
805 #define ADC_INTEN_ADCMPINTEN7_MASK (0x60000U)
\r
806 #define ADC_INTEN_ADCMPINTEN7_SHIFT (17U)
\r
807 /*! ADCMPINTEN7 - Channel 7 threshold comparison interrupt enable. See description for channel 0.
\r
809 #define ADC_INTEN_ADCMPINTEN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN7_SHIFT)) & ADC_INTEN_ADCMPINTEN7_MASK)
\r
810 #define ADC_INTEN_ADCMPINTEN8_MASK (0x180000U)
\r
811 #define ADC_INTEN_ADCMPINTEN8_SHIFT (19U)
\r
812 /*! ADCMPINTEN8 - Channel 8 threshold comparison interrupt enable. See description for channel 0.
\r
814 #define ADC_INTEN_ADCMPINTEN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN8_SHIFT)) & ADC_INTEN_ADCMPINTEN8_MASK)
\r
815 #define ADC_INTEN_ADCMPINTEN9_MASK (0x600000U)
\r
816 #define ADC_INTEN_ADCMPINTEN9_SHIFT (21U)
\r
817 /*! ADCMPINTEN9 - Channel 9 threshold comparison interrupt enable. See description for channel 0.
\r
819 #define ADC_INTEN_ADCMPINTEN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN9_SHIFT)) & ADC_INTEN_ADCMPINTEN9_MASK)
\r
820 #define ADC_INTEN_ADCMPINTEN10_MASK (0x1800000U)
\r
821 #define ADC_INTEN_ADCMPINTEN10_SHIFT (23U)
\r
822 /*! ADCMPINTEN10 - Channel 10 threshold comparison interrupt enable. See description for channel 0.
\r
824 #define ADC_INTEN_ADCMPINTEN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN10_SHIFT)) & ADC_INTEN_ADCMPINTEN10_MASK)
\r
825 #define ADC_INTEN_ADCMPINTEN11_MASK (0x6000000U)
\r
826 #define ADC_INTEN_ADCMPINTEN11_SHIFT (25U)
\r
827 /*! ADCMPINTEN11 - Channel 21 threshold comparison interrupt enable. See description for channel 0.
\r
829 #define ADC_INTEN_ADCMPINTEN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN11_SHIFT)) & ADC_INTEN_ADCMPINTEN11_MASK)
\r
832 /*! @name FLAGS - ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers). */
\r
834 #define ADC_FLAGS_THCMP0_MASK (0x1U)
\r
835 #define ADC_FLAGS_THCMP0_SHIFT (0U)
\r
836 /*! THCMP0 - Threshold comparison event on Channel 0. Set to 1 upon either an out-of-range result or
\r
837 * a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by
\r
840 #define ADC_FLAGS_THCMP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP0_SHIFT)) & ADC_FLAGS_THCMP0_MASK)
\r
841 #define ADC_FLAGS_THCMP1_MASK (0x2U)
\r
842 #define ADC_FLAGS_THCMP1_SHIFT (1U)
\r
843 /*! THCMP1 - Threshold comparison event on Channel 1. See description for channel 0.
\r
845 #define ADC_FLAGS_THCMP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP1_SHIFT)) & ADC_FLAGS_THCMP1_MASK)
\r
846 #define ADC_FLAGS_THCMP2_MASK (0x4U)
\r
847 #define ADC_FLAGS_THCMP2_SHIFT (2U)
\r
848 /*! THCMP2 - Threshold comparison event on Channel 2. See description for channel 0.
\r
850 #define ADC_FLAGS_THCMP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP2_SHIFT)) & ADC_FLAGS_THCMP2_MASK)
\r
851 #define ADC_FLAGS_THCMP3_MASK (0x8U)
\r
852 #define ADC_FLAGS_THCMP3_SHIFT (3U)
\r
853 /*! THCMP3 - Threshold comparison event on Channel 3. See description for channel 0.
\r
855 #define ADC_FLAGS_THCMP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP3_SHIFT)) & ADC_FLAGS_THCMP3_MASK)
\r
856 #define ADC_FLAGS_THCMP4_MASK (0x10U)
\r
857 #define ADC_FLAGS_THCMP4_SHIFT (4U)
\r
858 /*! THCMP4 - Threshold comparison event on Channel 4. See description for channel 0.
\r
860 #define ADC_FLAGS_THCMP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP4_SHIFT)) & ADC_FLAGS_THCMP4_MASK)
\r
861 #define ADC_FLAGS_THCMP5_MASK (0x20U)
\r
862 #define ADC_FLAGS_THCMP5_SHIFT (5U)
\r
863 /*! THCMP5 - Threshold comparison event on Channel 5. See description for channel 0.
\r
865 #define ADC_FLAGS_THCMP5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP5_SHIFT)) & ADC_FLAGS_THCMP5_MASK)
\r
866 #define ADC_FLAGS_THCMP6_MASK (0x40U)
\r
867 #define ADC_FLAGS_THCMP6_SHIFT (6U)
\r
868 /*! THCMP6 - Threshold comparison event on Channel 6. See description for channel 0.
\r
870 #define ADC_FLAGS_THCMP6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP6_SHIFT)) & ADC_FLAGS_THCMP6_MASK)
\r
871 #define ADC_FLAGS_THCMP7_MASK (0x80U)
\r
872 #define ADC_FLAGS_THCMP7_SHIFT (7U)
\r
873 /*! THCMP7 - Threshold comparison event on Channel 7. See description for channel 0.
\r
875 #define ADC_FLAGS_THCMP7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP7_SHIFT)) & ADC_FLAGS_THCMP7_MASK)
\r
876 #define ADC_FLAGS_THCMP8_MASK (0x100U)
\r
877 #define ADC_FLAGS_THCMP8_SHIFT (8U)
\r
878 /*! THCMP8 - Threshold comparison event on Channel 8. See description for channel 0.
\r
880 #define ADC_FLAGS_THCMP8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP8_SHIFT)) & ADC_FLAGS_THCMP8_MASK)
\r
881 #define ADC_FLAGS_THCMP9_MASK (0x200U)
\r
882 #define ADC_FLAGS_THCMP9_SHIFT (9U)
\r
883 /*! THCMP9 - Threshold comparison event on Channel 9. See description for channel 0.
\r
885 #define ADC_FLAGS_THCMP9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP9_SHIFT)) & ADC_FLAGS_THCMP9_MASK)
\r
886 #define ADC_FLAGS_THCMP10_MASK (0x400U)
\r
887 #define ADC_FLAGS_THCMP10_SHIFT (10U)
\r
888 /*! THCMP10 - Threshold comparison event on Channel 10. See description for channel 0.
\r
890 #define ADC_FLAGS_THCMP10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP10_SHIFT)) & ADC_FLAGS_THCMP10_MASK)
\r
891 #define ADC_FLAGS_THCMP11_MASK (0x800U)
\r
892 #define ADC_FLAGS_THCMP11_SHIFT (11U)
\r
893 /*! THCMP11 - Threshold comparison event on Channel 11. See description for channel 0.
\r
895 #define ADC_FLAGS_THCMP11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP11_SHIFT)) & ADC_FLAGS_THCMP11_MASK)
\r
896 #define ADC_FLAGS_OVERRUN0_MASK (0x1000U)
\r
897 #define ADC_FLAGS_OVERRUN0_SHIFT (12U)
\r
898 /*! OVERRUN0 - Mirrors the OVERRRUN status flag from the result register for ADC channel 0
\r
900 #define ADC_FLAGS_OVERRUN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN0_SHIFT)) & ADC_FLAGS_OVERRUN0_MASK)
\r
901 #define ADC_FLAGS_OVERRUN1_MASK (0x2000U)
\r
902 #define ADC_FLAGS_OVERRUN1_SHIFT (13U)
\r
903 /*! OVERRUN1 - Mirrors the OVERRRUN status flag from the result register for ADC channel 1
\r
905 #define ADC_FLAGS_OVERRUN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN1_SHIFT)) & ADC_FLAGS_OVERRUN1_MASK)
\r
906 #define ADC_FLAGS_OVERRUN2_MASK (0x4000U)
\r
907 #define ADC_FLAGS_OVERRUN2_SHIFT (14U)
\r
908 /*! OVERRUN2 - Mirrors the OVERRRUN status flag from the result register for ADC channel 2
\r
910 #define ADC_FLAGS_OVERRUN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN2_SHIFT)) & ADC_FLAGS_OVERRUN2_MASK)
\r
911 #define ADC_FLAGS_OVERRUN3_MASK (0x8000U)
\r
912 #define ADC_FLAGS_OVERRUN3_SHIFT (15U)
\r
913 /*! OVERRUN3 - Mirrors the OVERRRUN status flag from the result register for ADC channel 3
\r
915 #define ADC_FLAGS_OVERRUN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN3_SHIFT)) & ADC_FLAGS_OVERRUN3_MASK)
\r
916 #define ADC_FLAGS_OVERRUN4_MASK (0x10000U)
\r
917 #define ADC_FLAGS_OVERRUN4_SHIFT (16U)
\r
918 /*! OVERRUN4 - Mirrors the OVERRRUN status flag from the result register for ADC channel 4
\r
920 #define ADC_FLAGS_OVERRUN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN4_SHIFT)) & ADC_FLAGS_OVERRUN4_MASK)
\r
921 #define ADC_FLAGS_OVERRUN5_MASK (0x20000U)
\r
922 #define ADC_FLAGS_OVERRUN5_SHIFT (17U)
\r
923 /*! OVERRUN5 - Mirrors the OVERRRUN status flag from the result register for ADC channel 5
\r
925 #define ADC_FLAGS_OVERRUN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN5_SHIFT)) & ADC_FLAGS_OVERRUN5_MASK)
\r
926 #define ADC_FLAGS_OVERRUN6_MASK (0x40000U)
\r
927 #define ADC_FLAGS_OVERRUN6_SHIFT (18U)
\r
928 /*! OVERRUN6 - Mirrors the OVERRRUN status flag from the result register for ADC channel 6
\r
930 #define ADC_FLAGS_OVERRUN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN6_SHIFT)) & ADC_FLAGS_OVERRUN6_MASK)
\r
931 #define ADC_FLAGS_OVERRUN7_MASK (0x80000U)
\r
932 #define ADC_FLAGS_OVERRUN7_SHIFT (19U)
\r
933 /*! OVERRUN7 - Mirrors the OVERRRUN status flag from the result register for ADC channel 7
\r
935 #define ADC_FLAGS_OVERRUN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN7_SHIFT)) & ADC_FLAGS_OVERRUN7_MASK)
\r
936 #define ADC_FLAGS_OVERRUN8_MASK (0x100000U)
\r
937 #define ADC_FLAGS_OVERRUN8_SHIFT (20U)
\r
938 /*! OVERRUN8 - Mirrors the OVERRRUN status flag from the result register for ADC channel 8
\r
940 #define ADC_FLAGS_OVERRUN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN8_SHIFT)) & ADC_FLAGS_OVERRUN8_MASK)
\r
941 #define ADC_FLAGS_OVERRUN9_MASK (0x200000U)
\r
942 #define ADC_FLAGS_OVERRUN9_SHIFT (21U)
\r
943 /*! OVERRUN9 - Mirrors the OVERRRUN status flag from the result register for ADC channel 9
\r
945 #define ADC_FLAGS_OVERRUN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN9_SHIFT)) & ADC_FLAGS_OVERRUN9_MASK)
\r
946 #define ADC_FLAGS_OVERRUN10_MASK (0x400000U)
\r
947 #define ADC_FLAGS_OVERRUN10_SHIFT (22U)
\r
948 /*! OVERRUN10 - Mirrors the OVERRRUN status flag from the result register for ADC channel 10
\r
950 #define ADC_FLAGS_OVERRUN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN10_SHIFT)) & ADC_FLAGS_OVERRUN10_MASK)
\r
951 #define ADC_FLAGS_OVERRUN11_MASK (0x800000U)
\r
952 #define ADC_FLAGS_OVERRUN11_SHIFT (23U)
\r
953 /*! OVERRUN11 - Mirrors the OVERRRUN status flag from the result register for ADC channel 11
\r
955 #define ADC_FLAGS_OVERRUN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN11_SHIFT)) & ADC_FLAGS_OVERRUN11_MASK)
\r
956 #define ADC_FLAGS_SEQA_OVR_MASK (0x1000000U)
\r
957 #define ADC_FLAGS_SEQA_OVR_SHIFT (24U)
\r
958 /*! SEQA_OVR - Mirrors the global OVERRUN status flag in the SEQA_GDAT register
\r
960 #define ADC_FLAGS_SEQA_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_OVR_SHIFT)) & ADC_FLAGS_SEQA_OVR_MASK)
\r
961 #define ADC_FLAGS_SEQB_OVR_MASK (0x2000000U)
\r
962 #define ADC_FLAGS_SEQB_OVR_SHIFT (25U)
\r
963 /*! SEQB_OVR - Mirrors the global OVERRUN status flag in the SEQB_GDAT register
\r
965 #define ADC_FLAGS_SEQB_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_OVR_SHIFT)) & ADC_FLAGS_SEQB_OVR_MASK)
\r
966 #define ADC_FLAGS_SEQA_INT_MASK (0x10000000U)
\r
967 #define ADC_FLAGS_SEQA_INT_SHIFT (28U)
\r
968 /*! SEQA_INT - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQA_CTRL register is 0,
\r
969 * this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT), which
\r
970 * is set at the end of every ADC conversion performed as part of sequence A. It will be cleared
\r
971 * automatically when the SEQA_GDAT register is read. If the MODE bit in the SEQA_CTRL register
\r
972 * is 1, this flag will be set upon completion of an entire A sequence. In this case it must be
\r
973 * cleared by writing a 1 to this SEQA_INT bit. This interrupt must be enabled in the INTEN
\r
976 #define ADC_FLAGS_SEQA_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_INT_SHIFT)) & ADC_FLAGS_SEQA_INT_MASK)
\r
977 #define ADC_FLAGS_SEQB_INT_MASK (0x20000000U)
\r
978 #define ADC_FLAGS_SEQB_INT_SHIFT (29U)
\r
979 /*! SEQB_INT - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQB_CTRL register is 0,
\r
980 * this flag will mirror the DATAVALID bit in the sequence A global data register (SEQB_GDAT), which
\r
981 * is set at the end of every ADC conversion performed as part of sequence B. It will be cleared
\r
982 * automatically when the SEQB_GDAT register is read. If the MODE bit in the SEQB_CTRL register
\r
983 * is 1, this flag will be set upon completion of an entire B sequence. In this case it must be
\r
984 * cleared by writing a 1 to this SEQB_INT bit. This interrupt must be enabled in the INTEN
\r
987 #define ADC_FLAGS_SEQB_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_INT_SHIFT)) & ADC_FLAGS_SEQB_INT_MASK)
\r
988 #define ADC_FLAGS_THCMP_INT_MASK (0x40000000U)
\r
989 #define ADC_FLAGS_THCMP_INT_SHIFT (30U)
\r
990 /*! THCMP_INT - Threshold Comparison Interrupt. This bit will be set if any of the THCMP flags in
\r
991 * the lower bits of this register are set to 1 (due to an enabled out-of-range or
\r
992 * threshold-crossing event on any channel). Each type of threshold comparison interrupt on each channel must be
\r
993 * individually enabled in the INTEN register to cause this interrupt. This bit will be cleared
\r
994 * when all of the individual threshold flags are cleared via writing 1s to those bits.
\r
996 #define ADC_FLAGS_THCMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP_INT_SHIFT)) & ADC_FLAGS_THCMP_INT_MASK)
\r
997 #define ADC_FLAGS_OVR_INT_MASK (0x80000000U)
\r
998 #define ADC_FLAGS_OVR_INT_SHIFT (31U)
\r
999 /*! OVR_INT - Overrun Interrupt flag. Any overrun bit in any of the individual channel data
\r
1000 * registers will cause this interrupt. In addition, if the MODE bit in either of the SEQn_CTRL registers
\r
1001 * is 0 then the OVERRUN bit in the corresponding SEQn_GDAT register will also cause this
\r
1002 * interrupt. This interrupt must be enabled in the INTEN register. This bit will be cleared when all
\r
1003 * of the individual overrun bits have been cleared via reading the corresponding data registers.
\r
1005 #define ADC_FLAGS_OVR_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVR_INT_SHIFT)) & ADC_FLAGS_OVR_INT_MASK)
\r
1008 /*! @name STARTUP - ADC Startup register. */
\r
1010 #define ADC_STARTUP_ADC_ENA_MASK (0x1U)
\r
1011 #define ADC_STARTUP_ADC_ENA_SHIFT (0U)
\r
1012 /*! ADC_ENA - ADC Enable bit. This bit can only be set to a 1 by software. It is cleared
\r
1013 * automatically whenever the ADC is powered down. This bit must not be set until at least 10 microseconds
\r
1014 * after the ADC is powered up (typically by altering a system-level ADC power control bit).
\r
1016 #define ADC_STARTUP_ADC_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_ENA_SHIFT)) & ADC_STARTUP_ADC_ENA_MASK)
\r
1017 #define ADC_STARTUP_ADC_INIT_MASK (0x2U)
\r
1018 #define ADC_STARTUP_ADC_INIT_SHIFT (1U)
\r
1019 /*! ADC_INIT - ADC Initialization. After enabling the ADC (setting the ADC_ENA bit), the API routine
\r
1020 * will EITHER set this bit or the CALIB bit in the CALIB register, depending on whether or not
\r
1021 * calibration is required. Setting this bit will launch the 'dummy' conversion cycle that is
\r
1022 * required if a calibration is not performed. It will also reload the stored calibration value from
\r
1023 * a previous calibration unless the BYPASSCAL bit is set. This bit should only be set AFTER the
\r
1024 * ADC_ENA bit is set and after the CALIREQD bit is tested to determine whether a calibration or
\r
1025 * an ADC dummy conversion cycle is required. It should not be set during the same write that
\r
1026 * sets the ADC_ENA bit. This bit can only be set to a '1' by software. It is cleared automatically
\r
1027 * when the 'dummy' conversion cycle completes.
\r
1029 #define ADC_STARTUP_ADC_INIT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_INIT_SHIFT)) & ADC_STARTUP_ADC_INIT_MASK)
\r
1032 /*! @name CALIB - ADC Calibration register. */
\r
1034 #define ADC_CALIB_CALIB_MASK (0x1U)
\r
1035 #define ADC_CALIB_CALIB_SHIFT (0U)
\r
1036 /*! CALIB - Calibration request. Setting this bit will launch an ADC calibration cycle. This bit can
\r
1037 * only be set to a '1' by software. It is cleared automatically when the calibration cycle
\r
1040 #define ADC_CALIB_CALIB(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALIB_SHIFT)) & ADC_CALIB_CALIB_MASK)
\r
1041 #define ADC_CALIB_CALREQD_MASK (0x2U)
\r
1042 #define ADC_CALIB_CALREQD_SHIFT (1U)
\r
1043 /*! CALREQD - Calibration required. This read-only bit indicates if calibration is required when
\r
1044 * enabling the ADC. CALREQD will be '1' if no calibration has been run since the chip was
\r
1045 * powered-up and if the BYPASSCAL bit in the CTRL register is low. Software will test this bit to
\r
1046 * determine whether to initiate a calibration cycle or whether to set the ADC_INIT bit (in the STARTUP
\r
1047 * register) to launch the ADC initialization process which includes a 'dummy' conversion cycle.
\r
1048 * Note: A 'dummy' conversion cycle requires approximately 6 ADC clocks as opposed to 81 clocks
\r
1049 * required for calibration.
\r
1051 #define ADC_CALIB_CALREQD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALREQD_SHIFT)) & ADC_CALIB_CALREQD_MASK)
\r
1052 #define ADC_CALIB_CALVALUE_MASK (0x1FCU)
\r
1053 #define ADC_CALIB_CALVALUE_SHIFT (2U)
\r
1054 /*! CALVALUE - Calibration Value. This read-only field displays the calibration value established
\r
1055 * during last calibration cycle. This value is not typically of any use to the user.
\r
1057 #define ADC_CALIB_CALVALUE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALVALUE_SHIFT)) & ADC_CALIB_CALVALUE_MASK)
\r
1063 */ /* end of group ADC_Register_Masks */
\r
1066 /* ADC - Peripheral instance base addresses */
\r
1067 /** Peripheral ADC0 base address */
\r
1068 #define ADC0_BASE (0x400A0000u)
\r
1069 /** Peripheral ADC0 base pointer */
\r
1070 #define ADC0 ((ADC_Type *)ADC0_BASE)
\r
1071 /** Array initializer of ADC peripheral base addresses */
\r
1072 #define ADC_BASE_ADDRS { ADC0_BASE }
\r
1073 /** Array initializer of ADC peripheral base pointers */
\r
1074 #define ADC_BASE_PTRS { ADC0 }
\r
1075 /** Interrupt vectors for the ADC peripheral type */
\r
1076 #define ADC_SEQ_IRQS { ADC0_SEQA_IRQn, ADC0_SEQB_IRQn }
\r
1077 #define ADC_THCMP_IRQS { ADC0_THCMP_IRQn }
\r
1081 */ /* end of group ADC_Peripheral_Access_Layer */
\r
1084 /* ----------------------------------------------------------------------------
\r
1085 -- ASYNC_SYSCON Peripheral Access Layer
\r
1086 ---------------------------------------------------------------------------- */
\r
1089 * @addtogroup ASYNC_SYSCON_Peripheral_Access_Layer ASYNC_SYSCON Peripheral Access Layer
\r
1093 /** ASYNC_SYSCON - Register Layout Typedef */
\r
1095 __IO uint32_t ASYNCPRESETCTRL; /**< Async peripheral reset control, offset: 0x0 */
\r
1096 __O uint32_t ASYNCPRESETCTRLSET; /**< Set bits in ASYNCPRESETCTRL, offset: 0x4 */
\r
1097 __O uint32_t ASYNCPRESETCTRLCLR; /**< Clear bits in ASYNCPRESETCTRL, offset: 0x8 */
\r
1098 uint8_t RESERVED_0[4];
\r
1099 __IO uint32_t ASYNCAPBCLKCTRL; /**< Async peripheral clock control, offset: 0x10 */
\r
1100 __O uint32_t ASYNCAPBCLKCTRLSET; /**< Set bits in ASYNCAPBCLKCTRL, offset: 0x14 */
\r
1101 __O uint32_t ASYNCAPBCLKCTRLCLR; /**< Clear bits in ASYNCAPBCLKCTRL, offset: 0x18 */
\r
1102 uint8_t RESERVED_1[4];
\r
1103 __IO uint32_t ASYNCAPBCLKSELA; /**< Async APB clock source select A, offset: 0x20 */
\r
1104 } ASYNC_SYSCON_Type;
\r
1106 /* ----------------------------------------------------------------------------
\r
1107 -- ASYNC_SYSCON Register Masks
\r
1108 ---------------------------------------------------------------------------- */
\r
1111 * @addtogroup ASYNC_SYSCON_Register_Masks ASYNC_SYSCON Register Masks
\r
1115 /*! @name ASYNCPRESETCTRL - Async peripheral reset control */
\r
1117 #define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK (0x2000U)
\r
1118 #define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT (13U)
\r
1119 /*! CTIMER3 - Standard counter/timer CTIMER3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
\r
1121 #define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK)
\r
1122 #define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK (0x4000U)
\r
1123 #define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT (14U)
\r
1124 /*! CTIMER4 - Standard counter/timer CTIMER4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
\r
1126 #define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK)
\r
1129 /*! @name ASYNCPRESETCTRLSET - Set bits in ASYNCPRESETCTRL */
\r
1131 #define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK (0xFFFFFFFFU)
\r
1132 #define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT (0U)
\r
1133 /*! ARST_SET - Writing ones to this register sets the corresponding bit or bits in the
\r
1134 * ASYNCPRESETCTRL register, if they are implemented. Bits that do not correspond to defined bits in
\r
1135 * ASYNCPRESETCTRL are reserved and only zeroes should be written to them.
\r
1137 #define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK)
\r
1140 /*! @name ASYNCPRESETCTRLCLR - Clear bits in ASYNCPRESETCTRL */
\r
1142 #define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK (0xFFFFFFFFU)
\r
1143 #define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT (0U)
\r
1144 /*! ARST_CLR - Writing ones to this register clears the corresponding bit or bits in the
\r
1145 * ASYNCPRESETCTRL register, if they are implemented. Bits that do not correspond to defined bits in
\r
1146 * ASYNCPRESETCTRL are reserved and only zeroes should be written to them.
\r
1148 #define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK)
\r
1151 /*! @name ASYNCAPBCLKCTRL - Async peripheral clock control */
\r
1153 #define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK (0x2000U)
\r
1154 #define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT (13U)
\r
1155 /*! CTIMER3 - Controls the clock for CTIMER3. 0 = Disable; 1 = Enable.
\r
1157 #define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK)
\r
1158 #define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK (0x4000U)
\r
1159 #define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT (14U)
\r
1160 /*! CTIMER4 - Controls the clock for CTIMER4. 0 = Disable; 1 = Enable.
\r
1162 #define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK)
\r
1165 /*! @name ASYNCAPBCLKCTRLSET - Set bits in ASYNCAPBCLKCTRL */
\r
1167 #define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK (0xFFFFFFFFU)
\r
1168 #define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT (0U)
\r
1169 /*! ACLK_SET - Writing ones to this register sets the corresponding bit or bits in the
\r
1170 * ASYNCAPBCLKCTRL register, if they are implemented. Bits that do not correspond to defined bits in
\r
1171 * ASYNCPRESETCTRL are reserved and only zeroes should be written to them.
\r
1173 #define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK)
\r
1176 /*! @name ASYNCAPBCLKCTRLCLR - Clear bits in ASYNCAPBCLKCTRL */
\r
1178 #define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK (0xFFFFFFFFU)
\r
1179 #define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT (0U)
\r
1180 /*! ACLK_CLR - Writing ones to this register clears the corresponding bit or bits in the
\r
1181 * ASYNCAPBCLKCTRL register, if they are implemented. Bits that do not correspond to defined bits in
\r
1182 * ASYNCAPBCLKCTRL are reserved and only zeroes should be written to them.
\r
1184 #define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK)
\r
1187 /*! @name ASYNCAPBCLKSELA - Async APB clock source select A */
\r
1189 #define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK (0x3U)
\r
1190 #define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT (0U)
\r
1191 /*! SEL - Clock source for asynchronous clock source selector A
\r
1192 * 0b00..Main clock (main_clk)
\r
1193 * 0b01..FRO 12 MHz (fro_12m)
\r
1194 * 0b10..Audio PLL clock.(AUDPLL_BYPASS)
\r
1195 * 0b11..fc6 fclk (fc6_fclk)
\r
1197 #define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK)
\r
1203 */ /* end of group ASYNC_SYSCON_Register_Masks */
\r
1206 /* ASYNC_SYSCON - Peripheral instance base addresses */
\r
1207 /** Peripheral ASYNC_SYSCON base address */
\r
1208 #define ASYNC_SYSCON_BASE (0x40040000u)
\r
1209 /** Peripheral ASYNC_SYSCON base pointer */
\r
1210 #define ASYNC_SYSCON ((ASYNC_SYSCON_Type *)ASYNC_SYSCON_BASE)
\r
1211 /** Array initializer of ASYNC_SYSCON peripheral base addresses */
\r
1212 #define ASYNC_SYSCON_BASE_ADDRS { ASYNC_SYSCON_BASE }
\r
1213 /** Array initializer of ASYNC_SYSCON peripheral base pointers */
\r
1214 #define ASYNC_SYSCON_BASE_PTRS { ASYNC_SYSCON }
\r
1218 */ /* end of group ASYNC_SYSCON_Peripheral_Access_Layer */
\r
1221 /* ----------------------------------------------------------------------------
\r
1222 -- CAN Peripheral Access Layer
\r
1223 ---------------------------------------------------------------------------- */
\r
1226 * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
\r
1230 /** CAN - Register Layout Typedef */
\r
1232 uint8_t RESERVED_0[12];
\r
1233 __IO uint32_t DBTP; /**< Data Bit Timing Prescaler Register, offset: 0xC */
\r
1234 __IO uint32_t TEST; /**< Test Register, offset: 0x10 */
\r
1235 uint8_t RESERVED_1[4];
\r
1236 __IO uint32_t CCCR; /**< CC Control Register, offset: 0x18 */
\r
1237 __IO uint32_t NBTP; /**< Nominal Bit Timing and Prescaler Register, offset: 0x1C */
\r
1238 __IO uint32_t TSCC; /**< Timestamp Counter Configuration, offset: 0x20 */
\r
1239 __I uint32_t TSCV; /**< Timestamp Counter Value, offset: 0x24 */
\r
1240 __IO uint32_t TOCC; /**< Timeout Counter Configuration, offset: 0x28 */
\r
1241 __I uint32_t TOCV; /**< Timeout Counter Value, offset: 0x2C */
\r
1242 uint8_t RESERVED_2[16];
\r
1243 __I uint32_t ECR; /**< Error Counter Register, offset: 0x40 */
\r
1244 __I uint32_t PSR; /**< Protocol Status Register, offset: 0x44 */
\r
1245 __IO uint32_t TDCR; /**< Transmitter Delay Compensator Register, offset: 0x48 */
\r
1246 uint8_t RESERVED_3[4];
\r
1247 __IO uint32_t IR; /**< Interrupt Register, offset: 0x50 */
\r
1248 __IO uint32_t IE; /**< Interrupt Enable, offset: 0x54 */
\r
1249 __IO uint32_t ILS; /**< Interrupt Line Select, offset: 0x58 */
\r
1250 __IO uint32_t ILE; /**< Interrupt Line Enable, offset: 0x5C */
\r
1251 uint8_t RESERVED_4[32];
\r
1252 __IO uint32_t GFC; /**< Global Filter Configuration, offset: 0x80 */
\r
1253 __IO uint32_t SIDFC; /**< Standard ID Filter Configuration, offset: 0x84 */
\r
1254 __IO uint32_t XIDFC; /**< Extended ID Filter Configuration, offset: 0x88 */
\r
1255 uint8_t RESERVED_5[4];
\r
1256 __IO uint32_t XIDAM; /**< Extended ID AND Mask, offset: 0x90 */
\r
1257 __I uint32_t HPMS; /**< High Priority Message Status, offset: 0x94 */
\r
1258 __IO uint32_t NDAT1; /**< New Data 1, offset: 0x98 */
\r
1259 __IO uint32_t NDAT2; /**< New Data 2, offset: 0x9C */
\r
1260 __IO uint32_t RXF0C; /**< Rx FIFO 0 Configuration, offset: 0xA0 */
\r
1261 __I uint32_t RXF0S; /**< Rx FIFO 0 Status, offset: 0xA4 */
\r
1262 __IO uint32_t RXF0A; /**< Rx FIFO 0 Acknowledge, offset: 0xA8 */
\r
1263 __IO uint32_t RXBC; /**< Rx Buffer Configuration, offset: 0xAC */
\r
1264 __IO uint32_t RXF1C; /**< Rx FIFO 1 Configuration, offset: 0xB0 */
\r
1265 __I uint32_t RXF1S; /**< Rx FIFO 1 Status, offset: 0xB4 */
\r
1266 __IO uint32_t RXF1A; /**< Rx FIFO 1 Acknowledge, offset: 0xB8 */
\r
1267 __IO uint32_t RXESC; /**< Rx Buffer and FIFO Element Size Configuration, offset: 0xBC */
\r
1268 __IO uint32_t TXBC; /**< Tx Buffer Configuration, offset: 0xC0 */
\r
1269 __IO uint32_t TXFQS; /**< Tx FIFO/Queue Status, offset: 0xC4 */
\r
1270 __IO uint32_t TXESC; /**< Tx Buffer Element Size Configuration, offset: 0xC8 */
\r
1271 __I uint32_t TXBRP; /**< Tx Buffer Request Pending, offset: 0xCC */
\r
1272 __IO uint32_t TXBAR; /**< Tx Buffer Add Request, offset: 0xD0 */
\r
1273 __IO uint32_t TXBCR; /**< Tx Buffer Cancellation Request, offset: 0xD4 */
\r
1274 __I uint32_t TXBTO; /**< Tx Buffer Transmission Occurred, offset: 0xD8 */
\r
1275 __I uint32_t TXBCF; /**< Tx Buffer Cancellation Finished, offset: 0xDC */
\r
1276 __IO uint32_t TXBTIE; /**< Tx Buffer Transmission Interrupt Enable, offset: 0xE0 */
\r
1277 __IO uint32_t TXBCIE; /**< Tx Buffer Cancellation Finished Interrupt Enable, offset: 0xE4 */
\r
1278 uint8_t RESERVED_6[8];
\r
1279 __IO uint32_t TXEFC; /**< Tx Event FIFO Configuration, offset: 0xF0 */
\r
1280 __I uint32_t TXEFS; /**< Tx Event FIFO Status, offset: 0xF4 */
\r
1281 __IO uint32_t TXEFA; /**< Tx Event FIFO Acknowledge, offset: 0xF8 */
\r
1282 uint8_t RESERVED_7[260];
\r
1283 __IO uint32_t MRBA; /**< CAN Message RAM Base Address, offset: 0x200 */
\r
1284 uint8_t RESERVED_8[508];
\r
1285 __IO uint32_t ETSCC; /**< External Timestamp Counter Configuration, offset: 0x400 */
\r
1286 uint8_t RESERVED_9[508];
\r
1287 __IO uint32_t ETSCV; /**< External Timestamp Counter Value, offset: 0x600 */
\r
1290 /* ----------------------------------------------------------------------------
\r
1291 -- CAN Register Masks
\r
1292 ---------------------------------------------------------------------------- */
\r
1295 * @addtogroup CAN_Register_Masks CAN Register Masks
\r
1299 /*! @name DBTP - Data Bit Timing Prescaler Register */
\r
1301 #define CAN_DBTP_DSJW_MASK (0xFU)
\r
1302 #define CAN_DBTP_DSJW_SHIFT (0U)
\r
1303 /*! DSJW - Data (re)synchronization jump width.
\r
1305 #define CAN_DBTP_DSJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DSJW_SHIFT)) & CAN_DBTP_DSJW_MASK)
\r
1306 #define CAN_DBTP_DTSEG2_MASK (0xF0U)
\r
1307 #define CAN_DBTP_DTSEG2_SHIFT (4U)
\r
1308 /*! DTSEG2 - Data time segment after sample point.
\r
1310 #define CAN_DBTP_DTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG2_SHIFT)) & CAN_DBTP_DTSEG2_MASK)
\r
1311 #define CAN_DBTP_DTSEG1_MASK (0x1F00U)
\r
1312 #define CAN_DBTP_DTSEG1_SHIFT (8U)
\r
1313 /*! DTSEG1 - Data time segment before sample point.
\r
1315 #define CAN_DBTP_DTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG1_SHIFT)) & CAN_DBTP_DTSEG1_MASK)
\r
1316 #define CAN_DBTP_DBRP_MASK (0x1F0000U)
\r
1317 #define CAN_DBTP_DBRP_SHIFT (16U)
\r
1318 /*! DBRP - Data bit rate prescaler.
\r
1320 #define CAN_DBTP_DBRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DBRP_SHIFT)) & CAN_DBTP_DBRP_MASK)
\r
1321 #define CAN_DBTP_TDC_MASK (0x800000U)
\r
1322 #define CAN_DBTP_TDC_SHIFT (23U)
\r
1323 /*! TDC - Transmitter delay compensation.
\r
1325 #define CAN_DBTP_TDC(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_TDC_SHIFT)) & CAN_DBTP_TDC_MASK)
\r
1328 /*! @name TEST - Test Register */
\r
1330 #define CAN_TEST_LBCK_MASK (0x10U)
\r
1331 #define CAN_TEST_LBCK_SHIFT (4U)
\r
1332 /*! LBCK - Loop back mode.
\r
1334 #define CAN_TEST_LBCK(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_LBCK_SHIFT)) & CAN_TEST_LBCK_MASK)
\r
1335 #define CAN_TEST_TX_MASK (0x60U)
\r
1336 #define CAN_TEST_TX_SHIFT (5U)
\r
1337 /*! TX - Control of transmit pin.
\r
1339 #define CAN_TEST_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_TX_SHIFT)) & CAN_TEST_TX_MASK)
\r
1340 #define CAN_TEST_RX_MASK (0x80U)
\r
1341 #define CAN_TEST_RX_SHIFT (7U)
\r
1342 /*! RX - Monitors the actual value of the CAN_RXD.
\r
1344 #define CAN_TEST_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_RX_SHIFT)) & CAN_TEST_RX_MASK)
\r
1347 /*! @name CCCR - CC Control Register */
\r
1349 #define CAN_CCCR_INIT_MASK (0x1U)
\r
1350 #define CAN_CCCR_INIT_SHIFT (0U)
\r
1351 /*! INIT - Initialization.
\r
1353 #define CAN_CCCR_INIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_INIT_SHIFT)) & CAN_CCCR_INIT_MASK)
\r
1354 #define CAN_CCCR_CCE_MASK (0x2U)
\r
1355 #define CAN_CCCR_CCE_SHIFT (1U)
\r
1356 /*! CCE - Configuration change enable.
\r
1358 #define CAN_CCCR_CCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CCE_SHIFT)) & CAN_CCCR_CCE_MASK)
\r
1359 #define CAN_CCCR_ASM_MASK (0x4U)
\r
1360 #define CAN_CCCR_ASM_SHIFT (2U)
\r
1361 /*! ASM - Restricted operational mode.
\r
1363 #define CAN_CCCR_ASM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_ASM_SHIFT)) & CAN_CCCR_ASM_MASK)
\r
1364 #define CAN_CCCR_CSA_MASK (0x8U)
\r
1365 #define CAN_CCCR_CSA_SHIFT (3U)
\r
1366 /*! CSA - Clock Stop Acknowledge.
\r
1368 #define CAN_CCCR_CSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSA_SHIFT)) & CAN_CCCR_CSA_MASK)
\r
1369 #define CAN_CCCR_CSR_MASK (0x10U)
\r
1370 #define CAN_CCCR_CSR_SHIFT (4U)
\r
1371 /*! CSR - Clock Stop Request.
\r
1373 #define CAN_CCCR_CSR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSR_SHIFT)) & CAN_CCCR_CSR_MASK)
\r
1374 #define CAN_CCCR_MON_MASK (0x20U)
\r
1375 #define CAN_CCCR_MON_SHIFT (5U)
\r
1376 /*! MON - Bus monitoring mode.
\r
1378 #define CAN_CCCR_MON(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_MON_SHIFT)) & CAN_CCCR_MON_MASK)
\r
1379 #define CAN_CCCR_DAR_MASK (0x40U)
\r
1380 #define CAN_CCCR_DAR_SHIFT (6U)
\r
1381 /*! DAR - Disable automatic retransmission.
\r
1383 #define CAN_CCCR_DAR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_DAR_SHIFT)) & CAN_CCCR_DAR_MASK)
\r
1384 #define CAN_CCCR_TEST_MASK (0x80U)
\r
1385 #define CAN_CCCR_TEST_SHIFT (7U)
\r
1386 /*! TEST - Test mode enable.
\r
1388 #define CAN_CCCR_TEST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TEST_SHIFT)) & CAN_CCCR_TEST_MASK)
\r
1389 #define CAN_CCCR_FDOE_MASK (0x100U)
\r
1390 #define CAN_CCCR_FDOE_SHIFT (8U)
\r
1391 /*! FDOE - CAN FD operation enable.
\r
1393 #define CAN_CCCR_FDOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_FDOE_SHIFT)) & CAN_CCCR_FDOE_MASK)
\r
1394 #define CAN_CCCR_BRSE_MASK (0x200U)
\r
1395 #define CAN_CCCR_BRSE_SHIFT (9U)
\r
1396 /*! BRSE - When CAN FD operation is disabled, this bit is not evaluated.
\r
1398 #define CAN_CCCR_BRSE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_BRSE_SHIFT)) & CAN_CCCR_BRSE_MASK)
\r
1399 #define CAN_CCCR_PXHD_MASK (0x1000U)
\r
1400 #define CAN_CCCR_PXHD_SHIFT (12U)
\r
1401 /*! PXHD - Protocol exception handling disable.
\r
1403 #define CAN_CCCR_PXHD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_PXHD_SHIFT)) & CAN_CCCR_PXHD_MASK)
\r
1404 #define CAN_CCCR_EFBI_MASK (0x2000U)
\r
1405 #define CAN_CCCR_EFBI_SHIFT (13U)
\r
1406 /*! EFBI - Edge filtering during bus integration.
\r
1408 #define CAN_CCCR_EFBI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_EFBI_SHIFT)) & CAN_CCCR_EFBI_MASK)
\r
1409 #define CAN_CCCR_TXP_MASK (0x4000U)
\r
1410 #define CAN_CCCR_TXP_SHIFT (14U)
\r
1411 /*! TXP - Transmit pause.
\r
1413 #define CAN_CCCR_TXP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TXP_SHIFT)) & CAN_CCCR_TXP_MASK)
\r
1414 #define CAN_CCCR_NISO_MASK (0x8000U)
\r
1415 #define CAN_CCCR_NISO_SHIFT (15U)
\r
1416 /*! NISO - Non ISO operation.
\r
1418 #define CAN_CCCR_NISO(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_NISO_SHIFT)) & CAN_CCCR_NISO_MASK)
\r
1421 /*! @name NBTP - Nominal Bit Timing and Prescaler Register */
\r
1423 #define CAN_NBTP_NTSEG2_MASK (0x7FU)
\r
1424 #define CAN_NBTP_NTSEG2_SHIFT (0U)
\r
1425 /*! NTSEG2 - Nominal time segment after sample point.
\r
1427 #define CAN_NBTP_NTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG2_SHIFT)) & CAN_NBTP_NTSEG2_MASK)
\r
1428 #define CAN_NBTP_NTSEG1_MASK (0xFF00U)
\r
1429 #define CAN_NBTP_NTSEG1_SHIFT (8U)
\r
1430 /*! NTSEG1 - Nominal time segment before sample point.
\r
1432 #define CAN_NBTP_NTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG1_SHIFT)) & CAN_NBTP_NTSEG1_MASK)
\r
1433 #define CAN_NBTP_NBRP_MASK (0x1FF0000U)
\r
1434 #define CAN_NBTP_NBRP_SHIFT (16U)
\r
1435 /*! NBRP - Nominal bit rate prescaler.
\r
1437 #define CAN_NBTP_NBRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NBRP_SHIFT)) & CAN_NBTP_NBRP_MASK)
\r
1438 #define CAN_NBTP_NSJW_MASK (0xFE000000U)
\r
1439 #define CAN_NBTP_NSJW_SHIFT (25U)
\r
1440 /*! NSJW - Nominal (re)synchronization jump width.
\r
1442 #define CAN_NBTP_NSJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NSJW_SHIFT)) & CAN_NBTP_NSJW_MASK)
\r
1445 /*! @name TSCC - Timestamp Counter Configuration */
\r
1447 #define CAN_TSCC_TSS_MASK (0x3U)
\r
1448 #define CAN_TSCC_TSS_SHIFT (0U)
\r
1449 /*! TSS - Timestamp select.
\r
1451 #define CAN_TSCC_TSS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TSS_SHIFT)) & CAN_TSCC_TSS_MASK)
\r
1452 #define CAN_TSCC_TCP_MASK (0xF0000U)
\r
1453 #define CAN_TSCC_TCP_SHIFT (16U)
\r
1454 /*! TCP - Timestamp counter prescaler Configures the timestamp and timeout counters time unit in multiple of CAN bit times.
\r
1456 #define CAN_TSCC_TCP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TCP_SHIFT)) & CAN_TSCC_TCP_MASK)
\r
1459 /*! @name TSCV - Timestamp Counter Value */
\r
1461 #define CAN_TSCV_TSC_MASK (0xFFFFU)
\r
1462 #define CAN_TSCV_TSC_SHIFT (0U)
\r
1463 /*! TSC - Timestamp counter.
\r
1465 #define CAN_TSCV_TSC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCV_TSC_SHIFT)) & CAN_TSCV_TSC_MASK)
\r
1468 /*! @name TOCC - Timeout Counter Configuration */
\r
1470 #define CAN_TOCC_ETOC_MASK (0x1U)
\r
1471 #define CAN_TOCC_ETOC_SHIFT (0U)
\r
1472 /*! ETOC - Enable timeout counter.
\r
1474 #define CAN_TOCC_ETOC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_ETOC_SHIFT)) & CAN_TOCC_ETOC_MASK)
\r
1475 #define CAN_TOCC_TOS_MASK (0x6U)
\r
1476 #define CAN_TOCC_TOS_SHIFT (1U)
\r
1477 /*! TOS - Timeout select.
\r
1479 #define CAN_TOCC_TOS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOS_SHIFT)) & CAN_TOCC_TOS_MASK)
\r
1480 #define CAN_TOCC_TOP_MASK (0xFFFF0000U)
\r
1481 #define CAN_TOCC_TOP_SHIFT (16U)
\r
1482 /*! TOP - Timeout period.
\r
1484 #define CAN_TOCC_TOP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOP_SHIFT)) & CAN_TOCC_TOP_MASK)
\r
1487 /*! @name TOCV - Timeout Counter Value */
\r
1489 #define CAN_TOCV_TOC_MASK (0xFFFFU)
\r
1490 #define CAN_TOCV_TOC_SHIFT (0U)
\r
1491 /*! TOC - Timeout counter.
\r
1493 #define CAN_TOCV_TOC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCV_TOC_SHIFT)) & CAN_TOCV_TOC_MASK)
\r
1496 /*! @name ECR - Error Counter Register */
\r
1498 #define CAN_ECR_TEC_MASK (0xFFU)
\r
1499 #define CAN_ECR_TEC_SHIFT (0U)
\r
1500 /*! TEC - Transmit error counter.
\r
1502 #define CAN_ECR_TEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TEC_SHIFT)) & CAN_ECR_TEC_MASK)
\r
1503 #define CAN_ECR_REC_MASK (0x7F00U)
\r
1504 #define CAN_ECR_REC_SHIFT (8U)
\r
1505 /*! REC - Receive error counter.
\r
1507 #define CAN_ECR_REC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_REC_SHIFT)) & CAN_ECR_REC_MASK)
\r
1508 #define CAN_ECR_RP_MASK (0x8000U)
\r
1509 #define CAN_ECR_RP_SHIFT (15U)
\r
1510 /*! RP - Receive error passive.
\r
1512 #define CAN_ECR_RP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RP_SHIFT)) & CAN_ECR_RP_MASK)
\r
1513 #define CAN_ECR_CEL_MASK (0xFF0000U)
\r
1514 #define CAN_ECR_CEL_SHIFT (16U)
\r
1515 /*! CEL - CAN error logging.
\r
1517 #define CAN_ECR_CEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_CEL_SHIFT)) & CAN_ECR_CEL_MASK)
\r
1520 /*! @name PSR - Protocol Status Register */
\r
1522 #define CAN_PSR_LEC_MASK (0x7U)
\r
1523 #define CAN_PSR_LEC_SHIFT (0U)
\r
1524 /*! LEC - Last error code.
\r
1526 #define CAN_PSR_LEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_LEC_SHIFT)) & CAN_PSR_LEC_MASK)
\r
1527 #define CAN_PSR_ACT_MASK (0x18U)
\r
1528 #define CAN_PSR_ACT_SHIFT (3U)
\r
1529 /*! ACT - Activity.
\r
1531 #define CAN_PSR_ACT(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_ACT_SHIFT)) & CAN_PSR_ACT_MASK)
\r
1532 #define CAN_PSR_EP_MASK (0x20U)
\r
1533 #define CAN_PSR_EP_SHIFT (5U)
\r
1534 /*! EP - Error Passive.
\r
1536 #define CAN_PSR_EP(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EP_SHIFT)) & CAN_PSR_EP_MASK)
\r
1537 #define CAN_PSR_EW_MASK (0x40U)
\r
1538 #define CAN_PSR_EW_SHIFT (6U)
\r
1539 /*! EW - Warning status.
\r
1541 #define CAN_PSR_EW(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EW_SHIFT)) & CAN_PSR_EW_MASK)
\r
1542 #define CAN_PSR_BO_MASK (0x80U)
\r
1543 #define CAN_PSR_BO_SHIFT (7U)
\r
1544 /*! BO - Bus Off Status.
\r
1546 #define CAN_PSR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_BO_SHIFT)) & CAN_PSR_BO_MASK)
\r
1547 #define CAN_PSR_DLEC_MASK (0x700U)
\r
1548 #define CAN_PSR_DLEC_SHIFT (8U)
\r
1549 /*! DLEC - Data phase last error code.
\r
1551 #define CAN_PSR_DLEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_DLEC_SHIFT)) & CAN_PSR_DLEC_MASK)
\r
1552 #define CAN_PSR_RESI_MASK (0x800U)
\r
1553 #define CAN_PSR_RESI_SHIFT (11U)
\r
1554 /*! RESI - ESI flag of the last received CAN FD message.
\r
1556 #define CAN_PSR_RESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RESI_SHIFT)) & CAN_PSR_RESI_MASK)
\r
1557 #define CAN_PSR_RBRS_MASK (0x1000U)
\r
1558 #define CAN_PSR_RBRS_SHIFT (12U)
\r
1559 /*! RBRS - BRS flag of last received CAN FD message.
\r
1561 #define CAN_PSR_RBRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RBRS_SHIFT)) & CAN_PSR_RBRS_MASK)
\r
1562 #define CAN_PSR_RFDF_MASK (0x2000U)
\r
1563 #define CAN_PSR_RFDF_SHIFT (13U)
\r
1564 /*! RFDF - Received a CAN FD message.
\r
1566 #define CAN_PSR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RFDF_SHIFT)) & CAN_PSR_RFDF_MASK)
\r
1567 #define CAN_PSR_PXE_MASK (0x4000U)
\r
1568 #define CAN_PSR_PXE_SHIFT (14U)
\r
1569 /*! PXE - Protocol exception event.
\r
1571 #define CAN_PSR_PXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_PXE_SHIFT)) & CAN_PSR_PXE_MASK)
\r
1572 #define CAN_PSR_TDCV_MASK (0x7F0000U)
\r
1573 #define CAN_PSR_TDCV_SHIFT (16U)
\r
1574 /*! TDCV - Transmitter delay compensation value.
\r
1576 #define CAN_PSR_TDCV(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_TDCV_SHIFT)) & CAN_PSR_TDCV_MASK)
\r
1579 /*! @name TDCR - Transmitter Delay Compensator Register */
\r
1581 #define CAN_TDCR_TDCF_MASK (0x7FU)
\r
1582 #define CAN_TDCR_TDCF_SHIFT (0U)
\r
1583 /*! TDCF - Transmitter delay compensation filter window length.
\r
1585 #define CAN_TDCR_TDCF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCF_SHIFT)) & CAN_TDCR_TDCF_MASK)
\r
1586 #define CAN_TDCR_TDCO_MASK (0x7F00U)
\r
1587 #define CAN_TDCR_TDCO_SHIFT (8U)
\r
1588 /*! TDCO - Transmitter delay compensation offset.
\r
1590 #define CAN_TDCR_TDCO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCO_SHIFT)) & CAN_TDCR_TDCO_MASK)
\r
1593 /*! @name IR - Interrupt Register */
\r
1595 #define CAN_IR_RF0N_MASK (0x1U)
\r
1596 #define CAN_IR_RF0N_SHIFT (0U)
\r
1597 /*! RF0N - Rx FIFO 0 new message.
\r
1599 #define CAN_IR_RF0N(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0N_SHIFT)) & CAN_IR_RF0N_MASK)
\r
1600 #define CAN_IR_RF0W_MASK (0x2U)
\r
1601 #define CAN_IR_RF0W_SHIFT (1U)
\r
1602 /*! RF0W - Rx FIFO 0 watermark reached.
\r
1604 #define CAN_IR_RF0W(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0W_SHIFT)) & CAN_IR_RF0W_MASK)
\r
1605 #define CAN_IR_RF0F_MASK (0x4U)
\r
1606 #define CAN_IR_RF0F_SHIFT (2U)
\r
1607 /*! RF0F - Rx FIFO 0 full.
\r
1609 #define CAN_IR_RF0F(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0F_SHIFT)) & CAN_IR_RF0F_MASK)
\r
1610 #define CAN_IR_RF0L_MASK (0x8U)
\r
1611 #define CAN_IR_RF0L_SHIFT (3U)
\r
1612 /*! RF0L - Rx FIFO 0 message lost.
\r
1614 #define CAN_IR_RF0L(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0L_SHIFT)) & CAN_IR_RF0L_MASK)
\r
1615 #define CAN_IR_RF1N_MASK (0x10U)
\r
1616 #define CAN_IR_RF1N_SHIFT (4U)
\r
1617 /*! RF1N - Rx FIFO 1 new message.
\r
1619 #define CAN_IR_RF1N(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1N_SHIFT)) & CAN_IR_RF1N_MASK)
\r
1620 #define CAN_IR_RF1W_MASK (0x20U)
\r
1621 #define CAN_IR_RF1W_SHIFT (5U)
\r
1622 /*! RF1W - Rx FIFO 1 watermark reached.
\r
1624 #define CAN_IR_RF1W(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1W_SHIFT)) & CAN_IR_RF1W_MASK)
\r
1625 #define CAN_IR_RF1F_MASK (0x40U)
\r
1626 #define CAN_IR_RF1F_SHIFT (6U)
\r
1627 /*! RF1F - Rx FIFO 1 full.
\r
1629 #define CAN_IR_RF1F(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1F_SHIFT)) & CAN_IR_RF1F_MASK)
\r
1630 #define CAN_IR_RF1L_MASK (0x80U)
\r
1631 #define CAN_IR_RF1L_SHIFT (7U)
\r
1632 /*! RF1L - Rx FIFO 1 message lost.
\r
1634 #define CAN_IR_RF1L(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1L_SHIFT)) & CAN_IR_RF1L_MASK)
\r
1635 #define CAN_IR_HPM_MASK (0x100U)
\r
1636 #define CAN_IR_HPM_SHIFT (8U)
\r
1637 /*! HPM - High priority message.
\r
1639 #define CAN_IR_HPM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_HPM_SHIFT)) & CAN_IR_HPM_MASK)
\r
1640 #define CAN_IR_TC_MASK (0x200U)
\r
1641 #define CAN_IR_TC_SHIFT (9U)
\r
1642 /*! TC - Transmission completed.
\r
1644 #define CAN_IR_TC(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TC_SHIFT)) & CAN_IR_TC_MASK)
\r
1645 #define CAN_IR_TCF_MASK (0x400U)
\r
1646 #define CAN_IR_TCF_SHIFT (10U)
\r
1647 /*! TCF - Transmission cancellation finished.
\r
1649 #define CAN_IR_TCF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TCF_SHIFT)) & CAN_IR_TCF_MASK)
\r
1650 #define CAN_IR_TFE_MASK (0x800U)
\r
1651 #define CAN_IR_TFE_SHIFT (11U)
\r
1652 /*! TFE - Tx FIFO empty.
\r
1654 #define CAN_IR_TFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TFE_SHIFT)) & CAN_IR_TFE_MASK)
\r
1655 #define CAN_IR_TEFN_MASK (0x1000U)
\r
1656 #define CAN_IR_TEFN_SHIFT (12U)
\r
1657 /*! TEFN - Tx event FIFO new entry.
\r
1659 #define CAN_IR_TEFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFN_SHIFT)) & CAN_IR_TEFN_MASK)
\r
1660 #define CAN_IR_TEFW_MASK (0x2000U)
\r
1661 #define CAN_IR_TEFW_SHIFT (13U)
\r
1662 /*! TEFW - Tx event FIFO watermark reached.
\r
1664 #define CAN_IR_TEFW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFW_SHIFT)) & CAN_IR_TEFW_MASK)
\r
1665 #define CAN_IR_TEFF_MASK (0x4000U)
\r
1666 #define CAN_IR_TEFF_SHIFT (14U)
\r
1667 /*! TEFF - Tx event FIFO full.
\r
1669 #define CAN_IR_TEFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFF_SHIFT)) & CAN_IR_TEFF_MASK)
\r
1670 #define CAN_IR_TEFL_MASK (0x8000U)
\r
1671 #define CAN_IR_TEFL_SHIFT (15U)
\r
1672 /*! TEFL - Tx event FIFO element lost.
\r
1674 #define CAN_IR_TEFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFL_SHIFT)) & CAN_IR_TEFL_MASK)
\r
1675 #define CAN_IR_TSW_MASK (0x10000U)
\r
1676 #define CAN_IR_TSW_SHIFT (16U)
\r
1677 /*! TSW - Timestamp wraparound.
\r
1679 #define CAN_IR_TSW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TSW_SHIFT)) & CAN_IR_TSW_MASK)
\r
1680 #define CAN_IR_MRAF_MASK (0x20000U)
\r
1681 #define CAN_IR_MRAF_SHIFT (17U)
\r
1682 /*! MRAF - Message RAM access failure.
\r
1684 #define CAN_IR_MRAF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_MRAF_SHIFT)) & CAN_IR_MRAF_MASK)
\r
1685 #define CAN_IR_TOO_MASK (0x40000U)
\r
1686 #define CAN_IR_TOO_SHIFT (18U)
\r
1687 /*! TOO - Timeout occurred.
\r
1689 #define CAN_IR_TOO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TOO_SHIFT)) & CAN_IR_TOO_MASK)
\r
1690 #define CAN_IR_DRX_MASK (0x80000U)
\r
1691 #define CAN_IR_DRX_SHIFT (19U)
\r
1692 /*! DRX - Message stored in dedicated Rx buffer.
\r
1694 #define CAN_IR_DRX(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_DRX_SHIFT)) & CAN_IR_DRX_MASK)
\r
1695 #define CAN_IR_BEC_MASK (0x100000U)
\r
1696 #define CAN_IR_BEC_SHIFT (20U)
\r
1697 /*! BEC - Bit error corrected.
\r
1699 #define CAN_IR_BEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEC_SHIFT)) & CAN_IR_BEC_MASK)
\r
1700 #define CAN_IR_BEU_MASK (0x200000U)
\r
1701 #define CAN_IR_BEU_SHIFT (21U)
\r
1702 /*! BEU - Bit error uncorrected.
\r
1704 #define CAN_IR_BEU(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEU_SHIFT)) & CAN_IR_BEU_MASK)
\r
1705 #define CAN_IR_ELO_MASK (0x400000U)
\r
1706 #define CAN_IR_ELO_SHIFT (22U)
\r
1707 /*! ELO - Error logging overflow.
\r
1709 #define CAN_IR_ELO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_ELO_SHIFT)) & CAN_IR_ELO_MASK)
\r
1710 #define CAN_IR_EP_MASK (0x800000U)
\r
1711 #define CAN_IR_EP_SHIFT (23U)
\r
1712 /*! EP - Error passive.
\r
1714 #define CAN_IR_EP(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_EP_SHIFT)) & CAN_IR_EP_MASK)
\r
1715 #define CAN_IR_EW_MASK (0x1000000U)
\r
1716 #define CAN_IR_EW_SHIFT (24U)
\r
1717 /*! EW - Warning status.
\r
1719 #define CAN_IR_EW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_EW_SHIFT)) & CAN_IR_EW_MASK)
\r
1720 #define CAN_IR_BO_MASK (0x2000000U)
\r
1721 #define CAN_IR_BO_SHIFT (25U)
\r
1722 /*! BO - Bus_Off Status.
\r
1724 #define CAN_IR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BO_SHIFT)) & CAN_IR_BO_MASK)
\r
1725 #define CAN_IR_WDI_MASK (0x4000000U)
\r
1726 #define CAN_IR_WDI_SHIFT (26U)
\r
1727 /*! WDI - Watchdog interrupt.
\r
1729 #define CAN_IR_WDI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_WDI_SHIFT)) & CAN_IR_WDI_MASK)
\r
1730 #define CAN_IR_PEA_MASK (0x8000000U)
\r
1731 #define CAN_IR_PEA_SHIFT (27U)
\r
1732 /*! PEA - Protocol error in arbitration phase.
\r
1734 #define CAN_IR_PEA(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_PEA_SHIFT)) & CAN_IR_PEA_MASK)
\r
1735 #define CAN_IR_PED_MASK (0x10000000U)
\r
1736 #define CAN_IR_PED_SHIFT (28U)
\r
1737 /*! PED - Protocol error in data phase.
\r
1739 #define CAN_IR_PED(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_PED_SHIFT)) & CAN_IR_PED_MASK)
\r
1740 #define CAN_IR_ARA_MASK (0x20000000U)
\r
1741 #define CAN_IR_ARA_SHIFT (29U)
\r
1742 /*! ARA - Access to reserved address.
\r
1744 #define CAN_IR_ARA(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_ARA_SHIFT)) & CAN_IR_ARA_MASK)
\r
1747 /*! @name IE - Interrupt Enable */
\r
1749 #define CAN_IE_RF0NE_MASK (0x1U)
\r
1750 #define CAN_IE_RF0NE_SHIFT (0U)
\r
1751 /*! RF0NE - Rx FIFO 0 new message interrupt enable.
\r
1753 #define CAN_IE_RF0NE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0NE_SHIFT)) & CAN_IE_RF0NE_MASK)
\r
1754 #define CAN_IE_RF0WE_MASK (0x2U)
\r
1755 #define CAN_IE_RF0WE_SHIFT (1U)
\r
1756 /*! RF0WE - Rx FIFO 0 watermark reached interrupt enable.
\r
1758 #define CAN_IE_RF0WE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0WE_SHIFT)) & CAN_IE_RF0WE_MASK)
\r
1759 #define CAN_IE_RF0FE_MASK (0x4U)
\r
1760 #define CAN_IE_RF0FE_SHIFT (2U)
\r
1761 /*! RF0FE - Rx FIFO 0 full interrupt enable.
\r
1763 #define CAN_IE_RF0FE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0FE_SHIFT)) & CAN_IE_RF0FE_MASK)
\r
1764 #define CAN_IE_RF0LE_MASK (0x8U)
\r
1765 #define CAN_IE_RF0LE_SHIFT (3U)
\r
1766 /*! RF0LE - Rx FIFO 0 message lost interrupt enable.
\r
1768 #define CAN_IE_RF0LE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0LE_SHIFT)) & CAN_IE_RF0LE_MASK)
\r
1769 #define CAN_IE_RF1NE_MASK (0x10U)
\r
1770 #define CAN_IE_RF1NE_SHIFT (4U)
\r
1771 /*! RF1NE - Rx FIFO 1 new message interrupt enable.
\r
1773 #define CAN_IE_RF1NE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1NE_SHIFT)) & CAN_IE_RF1NE_MASK)
\r
1774 #define CAN_IE_RF1WE_MASK (0x20U)
\r
1775 #define CAN_IE_RF1WE_SHIFT (5U)
\r
1776 /*! RF1WE - Rx FIFO 1 watermark reached interrupt enable.
\r
1778 #define CAN_IE_RF1WE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1WE_SHIFT)) & CAN_IE_RF1WE_MASK)
\r
1779 #define CAN_IE_RF1FE_MASK (0x40U)
\r
1780 #define CAN_IE_RF1FE_SHIFT (6U)
\r
1781 /*! RF1FE - Rx FIFO 1 full interrupt enable.
\r
1783 #define CAN_IE_RF1FE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1FE_SHIFT)) & CAN_IE_RF1FE_MASK)
\r
1784 #define CAN_IE_RF1LE_MASK (0x80U)
\r
1785 #define CAN_IE_RF1LE_SHIFT (7U)
\r
1786 /*! RF1LE - Rx FIFO 1 message lost interrupt enable.
\r
1788 #define CAN_IE_RF1LE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1LE_SHIFT)) & CAN_IE_RF1LE_MASK)
\r
1789 #define CAN_IE_HPME_MASK (0x100U)
\r
1790 #define CAN_IE_HPME_SHIFT (8U)
\r
1791 /*! HPME - High priority message interrupt enable.
\r
1793 #define CAN_IE_HPME(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_HPME_SHIFT)) & CAN_IE_HPME_MASK)
\r
1794 #define CAN_IE_TCE_MASK (0x200U)
\r
1795 #define CAN_IE_TCE_SHIFT (9U)
\r
1796 /*! TCE - Transmission completed interrupt enable.
\r
1798 #define CAN_IE_TCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCE_SHIFT)) & CAN_IE_TCE_MASK)
\r
1799 #define CAN_IE_TCFE_MASK (0x400U)
\r
1800 #define CAN_IE_TCFE_SHIFT (10U)
\r
1801 /*! TCFE - Transmission cancellation finished interrupt enable.
\r
1803 #define CAN_IE_TCFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCFE_SHIFT)) & CAN_IE_TCFE_MASK)
\r
1804 #define CAN_IE_TFEE_MASK (0x800U)
\r
1805 #define CAN_IE_TFEE_SHIFT (11U)
\r
1806 /*! TFEE - Tx FIFO empty interrupt enable.
\r
1808 #define CAN_IE_TFEE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TFEE_SHIFT)) & CAN_IE_TFEE_MASK)
\r
1809 #define CAN_IE_TEFNE_MASK (0x1000U)
\r
1810 #define CAN_IE_TEFNE_SHIFT (12U)
\r
1811 /*! TEFNE - Tx event FIFO new entry interrupt enable.
\r
1813 #define CAN_IE_TEFNE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFNE_SHIFT)) & CAN_IE_TEFNE_MASK)
\r
1814 #define CAN_IE_TEFWE_MASK (0x2000U)
\r
1815 #define CAN_IE_TEFWE_SHIFT (13U)
\r
1816 /*! TEFWE - Tx event FIFO watermark reached interrupt enable.
\r
1818 #define CAN_IE_TEFWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFWE_SHIFT)) & CAN_IE_TEFWE_MASK)
\r
1819 #define CAN_IE_TEFFE_MASK (0x4000U)
\r
1820 #define CAN_IE_TEFFE_SHIFT (14U)
\r
1821 /*! TEFFE - Tx event FIFO full interrupt enable.
\r
1823 #define CAN_IE_TEFFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFFE_SHIFT)) & CAN_IE_TEFFE_MASK)
\r
1824 #define CAN_IE_TEFLE_MASK (0x8000U)
\r
1825 #define CAN_IE_TEFLE_SHIFT (15U)
\r
1826 /*! TEFLE - Tx event FIFO element lost interrupt enable.
\r
1828 #define CAN_IE_TEFLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFLE_SHIFT)) & CAN_IE_TEFLE_MASK)
\r
1829 #define CAN_IE_TSWE_MASK (0x10000U)
\r
1830 #define CAN_IE_TSWE_SHIFT (16U)
\r
1831 /*! TSWE - Timestamp wraparound interrupt enable.
\r
1833 #define CAN_IE_TSWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TSWE_SHIFT)) & CAN_IE_TSWE_MASK)
\r
1834 #define CAN_IE_MRAFE_MASK (0x20000U)
\r
1835 #define CAN_IE_MRAFE_SHIFT (17U)
\r
1836 /*! MRAFE - Message RAM access failure interrupt enable.
\r
1838 #define CAN_IE_MRAFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_MRAFE_SHIFT)) & CAN_IE_MRAFE_MASK)
\r
1839 #define CAN_IE_TOOE_MASK (0x40000U)
\r
1840 #define CAN_IE_TOOE_SHIFT (18U)
\r
1841 /*! TOOE - Timeout occurred interrupt enable.
\r
1843 #define CAN_IE_TOOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TOOE_SHIFT)) & CAN_IE_TOOE_MASK)
\r
1844 #define CAN_IE_DRXE_MASK (0x80000U)
\r
1845 #define CAN_IE_DRXE_SHIFT (19U)
\r
1846 /*! DRXE - Message stored in dedicated Rx buffer interrupt enable.
\r
1848 #define CAN_IE_DRXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_DRXE_SHIFT)) & CAN_IE_DRXE_MASK)
\r
1849 #define CAN_IE_BECE_MASK (0x100000U)
\r
1850 #define CAN_IE_BECE_SHIFT (20U)
\r
1851 /*! BECE - Bit error corrected interrupt enable.
\r
1853 #define CAN_IE_BECE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BECE_SHIFT)) & CAN_IE_BECE_MASK)
\r
1854 #define CAN_IE_BEUE_MASK (0x200000U)
\r
1855 #define CAN_IE_BEUE_SHIFT (21U)
\r
1856 /*! BEUE - Bit error uncorrected interrupt enable.
\r
1858 #define CAN_IE_BEUE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BEUE_SHIFT)) & CAN_IE_BEUE_MASK)
\r
1859 #define CAN_IE_ELOE_MASK (0x400000U)
\r
1860 #define CAN_IE_ELOE_SHIFT (22U)
\r
1861 /*! ELOE - Error logging overflow interrupt enable.
\r
1863 #define CAN_IE_ELOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_ELOE_SHIFT)) & CAN_IE_ELOE_MASK)
\r
1864 #define CAN_IE_EPE_MASK (0x800000U)
\r
1865 #define CAN_IE_EPE_SHIFT (23U)
\r
1866 /*! EPE - Error passive interrupt enable.
\r
1868 #define CAN_IE_EPE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_EPE_SHIFT)) & CAN_IE_EPE_MASK)
\r
1869 #define CAN_IE_EWE_MASK (0x1000000U)
\r
1870 #define CAN_IE_EWE_SHIFT (24U)
\r
1871 /*! EWE - Warning status interrupt enable.
\r
1873 #define CAN_IE_EWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_EWE_SHIFT)) & CAN_IE_EWE_MASK)
\r
1874 #define CAN_IE_BOE_MASK (0x2000000U)
\r
1875 #define CAN_IE_BOE_SHIFT (25U)
\r
1876 /*! BOE - Bus_Off Status interrupt enable.
\r
1878 #define CAN_IE_BOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BOE_SHIFT)) & CAN_IE_BOE_MASK)
\r
1879 #define CAN_IE_WDIE_MASK (0x4000000U)
\r
1880 #define CAN_IE_WDIE_SHIFT (26U)
\r
1881 /*! WDIE - Watchdog interrupt enable.
\r
1883 #define CAN_IE_WDIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_WDIE_SHIFT)) & CAN_IE_WDIE_MASK)
\r
1884 #define CAN_IE_PEAE_MASK (0x8000000U)
\r
1885 #define CAN_IE_PEAE_SHIFT (27U)
\r
1886 /*! PEAE - Protocol error in arbitration phase interrupt enable.
\r
1888 #define CAN_IE_PEAE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEAE_SHIFT)) & CAN_IE_PEAE_MASK)
\r
1889 #define CAN_IE_PEDE_MASK (0x10000000U)
\r
1890 #define CAN_IE_PEDE_SHIFT (28U)
\r
1891 /*! PEDE - Protocol error in data phase interrupt enable.
\r
1893 #define CAN_IE_PEDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEDE_SHIFT)) & CAN_IE_PEDE_MASK)
\r
1894 #define CAN_IE_ARAE_MASK (0x20000000U)
\r
1895 #define CAN_IE_ARAE_SHIFT (29U)
\r
1896 /*! ARAE - Access to reserved address interrupt enable.
\r
1898 #define CAN_IE_ARAE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_ARAE_SHIFT)) & CAN_IE_ARAE_MASK)
\r
1901 /*! @name ILS - Interrupt Line Select */
\r
1903 #define CAN_ILS_RF0NL_MASK (0x1U)
\r
1904 #define CAN_ILS_RF0NL_SHIFT (0U)
\r
1905 /*! RF0NL - Rx FIFO 0 new message interrupt line.
\r
1907 #define CAN_ILS_RF0NL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0NL_SHIFT)) & CAN_ILS_RF0NL_MASK)
\r
1908 #define CAN_ILS_RF0WL_MASK (0x2U)
\r
1909 #define CAN_ILS_RF0WL_SHIFT (1U)
\r
1910 /*! RF0WL - Rx FIFO 0 watermark reached interrupt line.
\r
1912 #define CAN_ILS_RF0WL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0WL_SHIFT)) & CAN_ILS_RF0WL_MASK)
\r
1913 #define CAN_ILS_RF0FL_MASK (0x4U)
\r
1914 #define CAN_ILS_RF0FL_SHIFT (2U)
\r
1915 /*! RF0FL - Rx FIFO 0 full interrupt line.
\r
1917 #define CAN_ILS_RF0FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0FL_SHIFT)) & CAN_ILS_RF0FL_MASK)
\r
1918 #define CAN_ILS_RF0LL_MASK (0x8U)
\r
1919 #define CAN_ILS_RF0LL_SHIFT (3U)
\r
1920 /*! RF0LL - Rx FIFO 0 message lost interrupt line.
\r
1922 #define CAN_ILS_RF0LL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0LL_SHIFT)) & CAN_ILS_RF0LL_MASK)
\r
1923 #define CAN_ILS_RF1NL_MASK (0x10U)
\r
1924 #define CAN_ILS_RF1NL_SHIFT (4U)
\r
1925 /*! RF1NL - Rx FIFO 1 new message interrupt line.
\r
1927 #define CAN_ILS_RF1NL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1NL_SHIFT)) & CAN_ILS_RF1NL_MASK)
\r
1928 #define CAN_ILS_RF1WL_MASK (0x20U)
\r
1929 #define CAN_ILS_RF1WL_SHIFT (5U)
\r
1930 /*! RF1WL - Rx FIFO 1 watermark reached interrupt line.
\r
1932 #define CAN_ILS_RF1WL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1WL_SHIFT)) & CAN_ILS_RF1WL_MASK)
\r
1933 #define CAN_ILS_RF1FL_MASK (0x40U)
\r
1934 #define CAN_ILS_RF1FL_SHIFT (6U)
\r
1935 /*! RF1FL - Rx FIFO 1 full interrupt line.
\r
1937 #define CAN_ILS_RF1FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1FL_SHIFT)) & CAN_ILS_RF1FL_MASK)
\r
1938 #define CAN_ILS_RF1LL_MASK (0x80U)
\r
1939 #define CAN_ILS_RF1LL_SHIFT (7U)
\r
1940 /*! RF1LL - Rx FIFO 1 message lost interrupt line.
\r
1942 #define CAN_ILS_RF1LL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1LL_SHIFT)) & CAN_ILS_RF1LL_MASK)
\r
1943 #define CAN_ILS_HPML_MASK (0x100U)
\r
1944 #define CAN_ILS_HPML_SHIFT (8U)
\r
1945 /*! HPML - High priority message interrupt line.
\r
1947 #define CAN_ILS_HPML(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_HPML_SHIFT)) & CAN_ILS_HPML_MASK)
\r
1948 #define CAN_ILS_TCL_MASK (0x200U)
\r
1949 #define CAN_ILS_TCL_SHIFT (9U)
\r
1950 /*! TCL - Transmission completed interrupt line.
\r
1952 #define CAN_ILS_TCL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCL_SHIFT)) & CAN_ILS_TCL_MASK)
\r
1953 #define CAN_ILS_TCFL_MASK (0x400U)
\r
1954 #define CAN_ILS_TCFL_SHIFT (10U)
\r
1955 /*! TCFL - Transmission cancellation finished interrupt line.
\r
1957 #define CAN_ILS_TCFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCFL_SHIFT)) & CAN_ILS_TCFL_MASK)
\r
1958 #define CAN_ILS_TFEL_MASK (0x800U)
\r
1959 #define CAN_ILS_TFEL_SHIFT (11U)
\r
1960 /*! TFEL - Tx FIFO empty interrupt line.
\r
1962 #define CAN_ILS_TFEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TFEL_SHIFT)) & CAN_ILS_TFEL_MASK)
\r
1963 #define CAN_ILS_TEFNL_MASK (0x1000U)
\r
1964 #define CAN_ILS_TEFNL_SHIFT (12U)
\r
1965 /*! TEFNL - Tx event FIFO new entry interrupt line.
\r
1967 #define CAN_ILS_TEFNL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFNL_SHIFT)) & CAN_ILS_TEFNL_MASK)
\r
1968 #define CAN_ILS_TEFWL_MASK (0x2000U)
\r
1969 #define CAN_ILS_TEFWL_SHIFT (13U)
\r
1970 /*! TEFWL - Tx event FIFO watermark reached interrupt line.
\r
1972 #define CAN_ILS_TEFWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFWL_SHIFT)) & CAN_ILS_TEFWL_MASK)
\r
1973 #define CAN_ILS_TEFFL_MASK (0x4000U)
\r
1974 #define CAN_ILS_TEFFL_SHIFT (14U)
\r
1975 /*! TEFFL - Tx event FIFO full interrupt line.
\r
1977 #define CAN_ILS_TEFFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFFL_SHIFT)) & CAN_ILS_TEFFL_MASK)
\r
1978 #define CAN_ILS_TEFLL_MASK (0x8000U)
\r
1979 #define CAN_ILS_TEFLL_SHIFT (15U)
\r
1980 /*! TEFLL - Tx event FIFO element lost interrupt line.
\r
1982 #define CAN_ILS_TEFLL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFLL_SHIFT)) & CAN_ILS_TEFLL_MASK)
\r
1983 #define CAN_ILS_TSWL_MASK (0x10000U)
\r
1984 #define CAN_ILS_TSWL_SHIFT (16U)
\r
1985 /*! TSWL - Timestamp wraparound interrupt line.
\r
1987 #define CAN_ILS_TSWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TSWL_SHIFT)) & CAN_ILS_TSWL_MASK)
\r
1988 #define CAN_ILS_MRAFL_MASK (0x20000U)
\r
1989 #define CAN_ILS_MRAFL_SHIFT (17U)
\r
1990 /*! MRAFL - Message RAM access failure interrupt line.
\r
1992 #define CAN_ILS_MRAFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_MRAFL_SHIFT)) & CAN_ILS_MRAFL_MASK)
\r
1993 #define CAN_ILS_TOOL_MASK (0x40000U)
\r
1994 #define CAN_ILS_TOOL_SHIFT (18U)
\r
1995 /*! TOOL - Timeout occurred interrupt line.
\r
1997 #define CAN_ILS_TOOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TOOL_SHIFT)) & CAN_ILS_TOOL_MASK)
\r
1998 #define CAN_ILS_DRXL_MASK (0x80000U)
\r
1999 #define CAN_ILS_DRXL_SHIFT (19U)
\r
2000 /*! DRXL - Message stored in dedicated Rx buffer interrupt line.
\r
2002 #define CAN_ILS_DRXL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_DRXL_SHIFT)) & CAN_ILS_DRXL_MASK)
\r
2003 #define CAN_ILS_BECL_MASK (0x100000U)
\r
2004 #define CAN_ILS_BECL_SHIFT (20U)
\r
2005 /*! BECL - Bit error corrected interrupt line.
\r
2007 #define CAN_ILS_BECL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BECL_SHIFT)) & CAN_ILS_BECL_MASK)
\r
2008 #define CAN_ILS_BEUL_MASK (0x200000U)
\r
2009 #define CAN_ILS_BEUL_SHIFT (21U)
\r
2010 /*! BEUL - Bit error uncorrected interrupt line.
\r
2012 #define CAN_ILS_BEUL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BEUL_SHIFT)) & CAN_ILS_BEUL_MASK)
\r
2013 #define CAN_ILS_ELOL_MASK (0x400000U)
\r
2014 #define CAN_ILS_ELOL_SHIFT (22U)
\r
2015 /*! ELOL - Error logging overflow interrupt line.
\r
2017 #define CAN_ILS_ELOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ELOL_SHIFT)) & CAN_ILS_ELOL_MASK)
\r
2018 #define CAN_ILS_EPL_MASK (0x800000U)
\r
2019 #define CAN_ILS_EPL_SHIFT (23U)
\r
2020 /*! EPL - Error passive interrupt line.
\r
2022 #define CAN_ILS_EPL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EPL_SHIFT)) & CAN_ILS_EPL_MASK)
\r
2023 #define CAN_ILS_EWL_MASK (0x1000000U)
\r
2024 #define CAN_ILS_EWL_SHIFT (24U)
\r
2025 /*! EWL - Warning status interrupt line.
\r
2027 #define CAN_ILS_EWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EWL_SHIFT)) & CAN_ILS_EWL_MASK)
\r
2028 #define CAN_ILS_BOL_MASK (0x2000000U)
\r
2029 #define CAN_ILS_BOL_SHIFT (25U)
\r
2030 /*! BOL - Bus_Off Status interrupt line.
\r
2032 #define CAN_ILS_BOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BOL_SHIFT)) & CAN_ILS_BOL_MASK)
\r
2033 #define CAN_ILS_WDIL_MASK (0x4000000U)
\r
2034 #define CAN_ILS_WDIL_SHIFT (26U)
\r
2035 /*! WDIL - Watchdog interrupt line.
\r
2037 #define CAN_ILS_WDIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_WDIL_SHIFT)) & CAN_ILS_WDIL_MASK)
\r
2038 #define CAN_ILS_PEAL_MASK (0x8000000U)
\r
2039 #define CAN_ILS_PEAL_SHIFT (27U)
\r
2040 /*! PEAL - Protocol error in arbitration phase interrupt line.
\r
2042 #define CAN_ILS_PEAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEAL_SHIFT)) & CAN_ILS_PEAL_MASK)
\r
2043 #define CAN_ILS_PEDL_MASK (0x10000000U)
\r
2044 #define CAN_ILS_PEDL_SHIFT (28U)
\r
2045 /*! PEDL - Protocol error in data phase interrupt line.
\r
2047 #define CAN_ILS_PEDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEDL_SHIFT)) & CAN_ILS_PEDL_MASK)
\r
2048 #define CAN_ILS_ARAL_MASK (0x20000000U)
\r
2049 #define CAN_ILS_ARAL_SHIFT (29U)
\r
2050 /*! ARAL - Access to reserved address interrupt line.
\r
2052 #define CAN_ILS_ARAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ARAL_SHIFT)) & CAN_ILS_ARAL_MASK)
\r
2055 /*! @name ILE - Interrupt Line Enable */
\r
2057 #define CAN_ILE_EINT0_MASK (0x1U)
\r
2058 #define CAN_ILE_EINT0_SHIFT (0U)
\r
2059 /*! EINT0 - Enable interrupt line 0.
\r
2061 #define CAN_ILE_EINT0(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT0_SHIFT)) & CAN_ILE_EINT0_MASK)
\r
2062 #define CAN_ILE_EINT1_MASK (0x2U)
\r
2063 #define CAN_ILE_EINT1_SHIFT (1U)
\r
2064 /*! EINT1 - Enable interrupt line 1.
\r
2066 #define CAN_ILE_EINT1(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT1_SHIFT)) & CAN_ILE_EINT1_MASK)
\r
2069 /*! @name GFC - Global Filter Configuration */
\r
2071 #define CAN_GFC_RRFE_MASK (0x1U)
\r
2072 #define CAN_GFC_RRFE_SHIFT (0U)
\r
2073 /*! RRFE - Reject remote frames extended.
\r
2075 #define CAN_GFC_RRFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFE_SHIFT)) & CAN_GFC_RRFE_MASK)
\r
2076 #define CAN_GFC_RRFS_MASK (0x2U)
\r
2077 #define CAN_GFC_RRFS_SHIFT (1U)
\r
2078 /*! RRFS - Reject remote frames standard.
\r
2080 #define CAN_GFC_RRFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFS_SHIFT)) & CAN_GFC_RRFS_MASK)
\r
2081 #define CAN_GFC_ANFE_MASK (0xCU)
\r
2082 #define CAN_GFC_ANFE_SHIFT (2U)
\r
2083 /*! ANFE - Accept non-matching frames extended.
\r
2085 #define CAN_GFC_ANFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFE_SHIFT)) & CAN_GFC_ANFE_MASK)
\r
2086 #define CAN_GFC_ANFS_MASK (0x30U)
\r
2087 #define CAN_GFC_ANFS_SHIFT (4U)
\r
2088 /*! ANFS - Accept non-matching frames standard.
\r
2090 #define CAN_GFC_ANFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFS_SHIFT)) & CAN_GFC_ANFS_MASK)
\r
2093 /*! @name SIDFC - Standard ID Filter Configuration */
\r
2095 #define CAN_SIDFC_FLSSA_MASK (0xFFFCU)
\r
2096 #define CAN_SIDFC_FLSSA_SHIFT (2U)
\r
2097 /*! FLSSA - Filter list standard start address.
\r
2099 #define CAN_SIDFC_FLSSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_FLSSA_SHIFT)) & CAN_SIDFC_FLSSA_MASK)
\r
2100 #define CAN_SIDFC_LSS_MASK (0xFF0000U)
\r
2101 #define CAN_SIDFC_LSS_SHIFT (16U)
\r
2102 /*! LSS - List size standard 0 = No standard message ID filter.
\r
2104 #define CAN_SIDFC_LSS(x) (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_LSS_SHIFT)) & CAN_SIDFC_LSS_MASK)
\r
2107 /*! @name XIDFC - Extended ID Filter Configuration */
\r
2109 #define CAN_XIDFC_FLESA_MASK (0xFFFCU)
\r
2110 #define CAN_XIDFC_FLESA_SHIFT (2U)
\r
2111 /*! FLESA - Filter list extended start address.
\r
2113 #define CAN_XIDFC_FLESA(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_FLESA_SHIFT)) & CAN_XIDFC_FLESA_MASK)
\r
2114 #define CAN_XIDFC_LSE_MASK (0xFF0000U)
\r
2115 #define CAN_XIDFC_LSE_SHIFT (16U)
\r
2116 /*! LSE - List size extended 0 = No extended message ID filter.
\r
2118 #define CAN_XIDFC_LSE(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_LSE_SHIFT)) & CAN_XIDFC_LSE_MASK)
\r
2121 /*! @name XIDAM - Extended ID AND Mask */
\r
2123 #define CAN_XIDAM_EIDM_MASK (0x1FFFFFFFU)
\r
2124 #define CAN_XIDAM_EIDM_SHIFT (0U)
\r
2125 /*! EIDM - Extended ID mask.
\r
2127 #define CAN_XIDAM_EIDM(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDAM_EIDM_SHIFT)) & CAN_XIDAM_EIDM_MASK)
\r
2130 /*! @name HPMS - High Priority Message Status */
\r
2132 #define CAN_HPMS_BIDX_MASK (0x3FU)
\r
2133 #define CAN_HPMS_BIDX_SHIFT (0U)
\r
2134 /*! BIDX - Buffer index.
\r
2136 #define CAN_HPMS_BIDX(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_BIDX_SHIFT)) & CAN_HPMS_BIDX_MASK)
\r
2137 #define CAN_HPMS_MSI_MASK (0xC0U)
\r
2138 #define CAN_HPMS_MSI_SHIFT (6U)
\r
2139 /*! MSI - Message storage indicator.
\r
2141 #define CAN_HPMS_MSI(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_MSI_SHIFT)) & CAN_HPMS_MSI_MASK)
\r
2142 #define CAN_HPMS_FIDX_MASK (0x7F00U)
\r
2143 #define CAN_HPMS_FIDX_SHIFT (8U)
\r
2144 /*! FIDX - Filter index.
\r
2146 #define CAN_HPMS_FIDX(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FIDX_SHIFT)) & CAN_HPMS_FIDX_MASK)
\r
2147 #define CAN_HPMS_FLST_MASK (0x8000U)
\r
2148 #define CAN_HPMS_FLST_SHIFT (15U)
\r
2149 /*! FLST - Filter list.
\r
2151 #define CAN_HPMS_FLST(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FLST_SHIFT)) & CAN_HPMS_FLST_MASK)
\r
2154 /*! @name NDAT1 - New Data 1 */
\r
2156 #define CAN_NDAT1_ND_MASK (0xFFFFFFFFU)
\r
2157 #define CAN_NDAT1_ND_SHIFT (0U)
\r
2158 /*! ND - New Data.
\r
2160 #define CAN_NDAT1_ND(x) (((uint32_t)(((uint32_t)(x)) << CAN_NDAT1_ND_SHIFT)) & CAN_NDAT1_ND_MASK)
\r
2163 /*! @name NDAT2 - New Data 2 */
\r
2165 #define CAN_NDAT2_ND_MASK (0xFFFFFFFFU)
\r
2166 #define CAN_NDAT2_ND_SHIFT (0U)
\r
2167 /*! ND - New Data.
\r
2169 #define CAN_NDAT2_ND(x) (((uint32_t)(((uint32_t)(x)) << CAN_NDAT2_ND_SHIFT)) & CAN_NDAT2_ND_MASK)
\r
2172 /*! @name RXF0C - Rx FIFO 0 Configuration */
\r
2174 #define CAN_RXF0C_F0SA_MASK (0xFFFCU)
\r
2175 #define CAN_RXF0C_F0SA_SHIFT (2U)
\r
2176 /*! F0SA - Rx FIFO 0 start address.
\r
2178 #define CAN_RXF0C_F0SA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0SA_SHIFT)) & CAN_RXF0C_F0SA_MASK)
\r
2179 #define CAN_RXF0C_F0S_MASK (0x7F0000U)
\r
2180 #define CAN_RXF0C_F0S_SHIFT (16U)
\r
2181 /*! F0S - Rx FIFO 0 size.
\r
2183 #define CAN_RXF0C_F0S(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0S_SHIFT)) & CAN_RXF0C_F0S_MASK)
\r
2184 #define CAN_RXF0C_F0WM_MASK (0x7F000000U)
\r
2185 #define CAN_RXF0C_F0WM_SHIFT (24U)
\r
2186 /*! F0WM - Rx FIFO 0 watermark 0 = Watermark interrupt disabled.
\r
2188 #define CAN_RXF0C_F0WM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0WM_SHIFT)) & CAN_RXF0C_F0WM_MASK)
\r
2189 #define CAN_RXF0C_F0OM_MASK (0x80000000U)
\r
2190 #define CAN_RXF0C_F0OM_SHIFT (31U)
\r
2191 /*! F0OM - FIFO 0 operation mode.
\r
2193 #define CAN_RXF0C_F0OM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0OM_SHIFT)) & CAN_RXF0C_F0OM_MASK)
\r
2196 /*! @name RXF0S - Rx FIFO 0 Status */
\r
2198 #define CAN_RXF0S_F0FL_MASK (0x7FU)
\r
2199 #define CAN_RXF0S_F0FL_SHIFT (0U)
\r
2200 /*! F0FL - Rx FIFO 0 fill level.
\r
2202 #define CAN_RXF0S_F0FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0FL_SHIFT)) & CAN_RXF0S_F0FL_MASK)
\r
2203 #define CAN_RXF0S_F0GI_MASK (0x3F00U)
\r
2204 #define CAN_RXF0S_F0GI_SHIFT (8U)
\r
2205 /*! F0GI - Rx FIFO 0 get index.
\r
2207 #define CAN_RXF0S_F0GI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0GI_SHIFT)) & CAN_RXF0S_F0GI_MASK)
\r
2208 #define CAN_RXF0S_F0PI_MASK (0x3F0000U)
\r
2209 #define CAN_RXF0S_F0PI_SHIFT (16U)
\r
2210 /*! F0PI - Rx FIFO 0 put index.
\r
2212 #define CAN_RXF0S_F0PI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0PI_SHIFT)) & CAN_RXF0S_F0PI_MASK)
\r
2213 #define CAN_RXF0S_F0F_MASK (0x1000000U)
\r
2214 #define CAN_RXF0S_F0F_SHIFT (24U)
\r
2215 /*! F0F - Rx FIFO 0 full.
\r
2217 #define CAN_RXF0S_F0F(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0F_SHIFT)) & CAN_RXF0S_F0F_MASK)
\r
2218 #define CAN_RXF0S_RF0L_MASK (0x2000000U)
\r
2219 #define CAN_RXF0S_RF0L_SHIFT (25U)
\r
2220 /*! RF0L - Rx FIFO 0 message lost.
\r
2222 #define CAN_RXF0S_RF0L(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_RF0L_SHIFT)) & CAN_RXF0S_RF0L_MASK)
\r
2225 /*! @name RXF0A - Rx FIFO 0 Acknowledge */
\r
2227 #define CAN_RXF0A_F0AI_MASK (0x3FU)
\r
2228 #define CAN_RXF0A_F0AI_SHIFT (0U)
\r
2229 /*! F0AI - Rx FIFO 0 acknowledge index.
\r
2231 #define CAN_RXF0A_F0AI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0A_F0AI_SHIFT)) & CAN_RXF0A_F0AI_MASK)
\r
2234 /*! @name RXBC - Rx Buffer Configuration */
\r
2236 #define CAN_RXBC_RBSA_MASK (0xFFFCU)
\r
2237 #define CAN_RXBC_RBSA_SHIFT (2U)
\r
2238 /*! RBSA - Rx buffer start address.
\r
2240 #define CAN_RXBC_RBSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXBC_RBSA_SHIFT)) & CAN_RXBC_RBSA_MASK)
\r
2243 /*! @name RXF1C - Rx FIFO 1 Configuration */
\r
2245 #define CAN_RXF1C_F1SA_MASK (0xFFFCU)
\r
2246 #define CAN_RXF1C_F1SA_SHIFT (2U)
\r
2247 /*! F1SA - Rx FIFO 1 start address.
\r
2249 #define CAN_RXF1C_F1SA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1SA_SHIFT)) & CAN_RXF1C_F1SA_MASK)
\r
2250 #define CAN_RXF1C_F1S_MASK (0x7F0000U)
\r
2251 #define CAN_RXF1C_F1S_SHIFT (16U)
\r
2252 /*! F1S - Rx FIFO 1 size 0 = No Rx FIFO 1.
\r
2254 #define CAN_RXF1C_F1S(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1S_SHIFT)) & CAN_RXF1C_F1S_MASK)
\r
2255 #define CAN_RXF1C_F1WM_MASK (0x7F000000U)
\r
2256 #define CAN_RXF1C_F1WM_SHIFT (24U)
\r
2257 /*! F1WM - Rx FIFO 1 watermark 0 = Watermark interrupt disabled.
\r
2259 #define CAN_RXF1C_F1WM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1WM_SHIFT)) & CAN_RXF1C_F1WM_MASK)
\r
2260 #define CAN_RXF1C_F1OM_MASK (0x80000000U)
\r
2261 #define CAN_RXF1C_F1OM_SHIFT (31U)
\r
2262 /*! F1OM - FIFO 1 operation mode.
\r
2264 #define CAN_RXF1C_F1OM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1OM_SHIFT)) & CAN_RXF1C_F1OM_MASK)
\r
2267 /*! @name RXF1S - Rx FIFO 1 Status */
\r
2269 #define CAN_RXF1S_F1FL_MASK (0x7FU)
\r
2270 #define CAN_RXF1S_F1FL_SHIFT (0U)
\r
2271 /*! F1FL - Rx FIFO 1 fill level.
\r
2273 #define CAN_RXF1S_F1FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1FL_SHIFT)) & CAN_RXF1S_F1FL_MASK)
\r
2274 #define CAN_RXF1S_F1GI_MASK (0x3F00U)
\r
2275 #define CAN_RXF1S_F1GI_SHIFT (8U)
\r
2276 /*! F1GI - Rx FIFO 1 get index.
\r
2278 #define CAN_RXF1S_F1GI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1GI_SHIFT)) & CAN_RXF1S_F1GI_MASK)
\r
2279 #define CAN_RXF1S_F1PI_MASK (0x3F0000U)
\r
2280 #define CAN_RXF1S_F1PI_SHIFT (16U)
\r
2281 /*! F1PI - Rx FIFO 1 put index.
\r
2283 #define CAN_RXF1S_F1PI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1PI_SHIFT)) & CAN_RXF1S_F1PI_MASK)
\r
2284 #define CAN_RXF1S_F1F_MASK (0x1000000U)
\r
2285 #define CAN_RXF1S_F1F_SHIFT (24U)
\r
2286 /*! F1F - Rx FIFO 1 full.
\r
2288 #define CAN_RXF1S_F1F(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1F_SHIFT)) & CAN_RXF1S_F1F_MASK)
\r
2289 #define CAN_RXF1S_RF1L_MASK (0x2000000U)
\r
2290 #define CAN_RXF1S_RF1L_SHIFT (25U)
\r
2291 /*! RF1L - Rx FIFO 1 message lost.
\r
2293 #define CAN_RXF1S_RF1L(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_RF1L_SHIFT)) & CAN_RXF1S_RF1L_MASK)
\r
2296 /*! @name RXF1A - Rx FIFO 1 Acknowledge */
\r
2298 #define CAN_RXF1A_F1AI_MASK (0x3FU)
\r
2299 #define CAN_RXF1A_F1AI_SHIFT (0U)
\r
2300 /*! F1AI - Rx FIFO 1 acknowledge index.
\r
2302 #define CAN_RXF1A_F1AI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1A_F1AI_SHIFT)) & CAN_RXF1A_F1AI_MASK)
\r
2305 /*! @name RXESC - Rx Buffer and FIFO Element Size Configuration */
\r
2307 #define CAN_RXESC_F0DS_MASK (0x7U)
\r
2308 #define CAN_RXESC_F0DS_SHIFT (0U)
\r
2309 /*! F0DS - Rx FIFO 0 data field size.
\r
2311 #define CAN_RXESC_F0DS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F0DS_SHIFT)) & CAN_RXESC_F0DS_MASK)
\r
2312 #define CAN_RXESC_F1DS_MASK (0x70U)
\r
2313 #define CAN_RXESC_F1DS_SHIFT (4U)
\r
2314 /*! F1DS - Rx FIFO 1 data field size.
\r
2316 #define CAN_RXESC_F1DS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F1DS_SHIFT)) & CAN_RXESC_F1DS_MASK)
\r
2317 #define CAN_RXESC_RBDS_MASK (0x700U)
\r
2318 #define CAN_RXESC_RBDS_SHIFT (8U)
\r
2321 #define CAN_RXESC_RBDS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_RBDS_SHIFT)) & CAN_RXESC_RBDS_MASK)
\r
2324 /*! @name TXBC - Tx Buffer Configuration */
\r
2326 #define CAN_TXBC_TBSA_MASK (0xFFFCU)
\r
2327 #define CAN_TXBC_TBSA_SHIFT (2U)
\r
2328 /*! TBSA - Tx buffers start address.
\r
2330 #define CAN_TXBC_TBSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TBSA_SHIFT)) & CAN_TXBC_TBSA_MASK)
\r
2331 #define CAN_TXBC_NDTB_MASK (0x3F0000U)
\r
2332 #define CAN_TXBC_NDTB_SHIFT (16U)
\r
2333 /*! NDTB - Number of dedicated transmit buffers 0 = No dedicated Tx buffers.
\r
2335 #define CAN_TXBC_NDTB(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_NDTB_SHIFT)) & CAN_TXBC_NDTB_MASK)
\r
2336 #define CAN_TXBC_TFQS_MASK (0x3F000000U)
\r
2337 #define CAN_TXBC_TFQS_SHIFT (24U)
\r
2338 /*! TFQS - Transmit FIFO/queue size 0 = No tx FIFO/Queue.
\r
2340 #define CAN_TXBC_TFQS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQS_SHIFT)) & CAN_TXBC_TFQS_MASK)
\r
2341 #define CAN_TXBC_TFQM_MASK (0x40000000U)
\r
2342 #define CAN_TXBC_TFQM_SHIFT (30U)
\r
2343 /*! TFQM - Tx FIFO/queue mode.
\r
2345 #define CAN_TXBC_TFQM(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQM_SHIFT)) & CAN_TXBC_TFQM_MASK)
\r
2348 /*! @name TXFQS - Tx FIFO/Queue Status */
\r
2350 #define CAN_TXFQS_TFGI_MASK (0x1F00U)
\r
2351 #define CAN_TXFQS_TFGI_SHIFT (8U)
\r
2352 /*! TFGI - Tx FIFO get index.
\r
2354 #define CAN_TXFQS_TFGI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFGI_SHIFT)) & CAN_TXFQS_TFGI_MASK)
\r
2355 #define CAN_TXFQS_TFQPI_MASK (0x1F0000U)
\r
2356 #define CAN_TXFQS_TFQPI_SHIFT (16U)
\r
2357 /*! TFQPI - Tx FIFO/queue put index.
\r
2359 #define CAN_TXFQS_TFQPI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQPI_SHIFT)) & CAN_TXFQS_TFQPI_MASK)
\r
2360 #define CAN_TXFQS_TFQF_MASK (0x200000U)
\r
2361 #define CAN_TXFQS_TFQF_SHIFT (21U)
\r
2362 /*! TFQF - Tx FIFO/queue full.
\r
2364 #define CAN_TXFQS_TFQF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQF_SHIFT)) & CAN_TXFQS_TFQF_MASK)
\r
2367 /*! @name TXESC - Tx Buffer Element Size Configuration */
\r
2369 #define CAN_TXESC_TBDS_MASK (0x7U)
\r
2370 #define CAN_TXESC_TBDS_SHIFT (0U)
\r
2371 /*! TBDS - Tx buffer data field size.
\r
2373 #define CAN_TXESC_TBDS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXESC_TBDS_SHIFT)) & CAN_TXESC_TBDS_MASK)
\r
2376 /*! @name TXBRP - Tx Buffer Request Pending */
\r
2378 #define CAN_TXBRP_TRP_MASK (0xFFFFFFFFU)
\r
2379 #define CAN_TXBRP_TRP_SHIFT (0U)
\r
2380 /*! TRP - Transmission request pending.
\r
2382 #define CAN_TXBRP_TRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBRP_TRP_SHIFT)) & CAN_TXBRP_TRP_MASK)
\r
2385 /*! @name TXBAR - Tx Buffer Add Request */
\r
2387 #define CAN_TXBAR_AR_MASK (0xFFFFFFFFU)
\r
2388 #define CAN_TXBAR_AR_SHIFT (0U)
\r
2389 /*! AR - Add request.
\r
2391 #define CAN_TXBAR_AR(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBAR_AR_SHIFT)) & CAN_TXBAR_AR_MASK)
\r
2394 /*! @name TXBCR - Tx Buffer Cancellation Request */
\r
2396 #define CAN_TXBCR_CR_MASK (0xFFFFFFFFU)
\r
2397 #define CAN_TXBCR_CR_SHIFT (0U)
\r
2398 /*! CR - Cancellation request.
\r
2400 #define CAN_TXBCR_CR(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCR_CR_SHIFT)) & CAN_TXBCR_CR_MASK)
\r
2403 /*! @name TXBTO - Tx Buffer Transmission Occurred */
\r
2405 #define CAN_TXBTO_TO_MASK (0xFFFFFFFFU)
\r
2406 #define CAN_TXBTO_TO_SHIFT (0U)
\r
2407 /*! TO - Transmission occurred.
\r
2409 #define CAN_TXBTO_TO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBTO_TO_SHIFT)) & CAN_TXBTO_TO_MASK)
\r
2412 /*! @name TXBCF - Tx Buffer Cancellation Finished */
\r
2414 #define CAN_TXBCF_TO_MASK (0xFFFFFFFFU)
\r
2415 #define CAN_TXBCF_TO_SHIFT (0U)
\r
2416 /*! TO - Cancellation finished.
\r
2418 #define CAN_TXBCF_TO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCF_TO_SHIFT)) & CAN_TXBCF_TO_MASK)
\r
2421 /*! @name TXBTIE - Tx Buffer Transmission Interrupt Enable */
\r
2423 #define CAN_TXBTIE_TIE_MASK (0xFFFFFFFFU)
\r
2424 #define CAN_TXBTIE_TIE_SHIFT (0U)
\r
2425 /*! TIE - Transmission interrupt enable.
\r
2427 #define CAN_TXBTIE_TIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBTIE_TIE_SHIFT)) & CAN_TXBTIE_TIE_MASK)
\r
2430 /*! @name TXBCIE - Tx Buffer Cancellation Finished Interrupt Enable */
\r
2432 #define CAN_TXBCIE_CFIE_MASK (0xFFFFFFFFU)
\r
2433 #define CAN_TXBCIE_CFIE_SHIFT (0U)
\r
2434 /*! CFIE - Cancellation finished interrupt enable.
\r
2436 #define CAN_TXBCIE_CFIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCIE_CFIE_SHIFT)) & CAN_TXBCIE_CFIE_MASK)
\r
2439 /*! @name TXEFC - Tx Event FIFO Configuration */
\r
2441 #define CAN_TXEFC_EFSA_MASK (0xFFFCU)
\r
2442 #define CAN_TXEFC_EFSA_SHIFT (2U)
\r
2443 /*! EFSA - Event FIFO start address.
\r
2445 #define CAN_TXEFC_EFSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFSA_SHIFT)) & CAN_TXEFC_EFSA_MASK)
\r
2446 #define CAN_TXEFC_EFS_MASK (0x3F0000U)
\r
2447 #define CAN_TXEFC_EFS_SHIFT (16U)
\r
2448 /*! EFS - Event FIFO size 0 = Tx event FIFO disabled.
\r
2450 #define CAN_TXEFC_EFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFS_SHIFT)) & CAN_TXEFC_EFS_MASK)
\r
2451 #define CAN_TXEFC_EFWM_MASK (0x3F000000U)
\r
2452 #define CAN_TXEFC_EFWM_SHIFT (24U)
\r
2453 /*! EFWM - Event FIFO watermark 0 = Watermark interrupt disabled.
\r
2455 #define CAN_TXEFC_EFWM(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFWM_SHIFT)) & CAN_TXEFC_EFWM_MASK)
\r
2458 /*! @name TXEFS - Tx Event FIFO Status */
\r
2460 #define CAN_TXEFS_EFFL_MASK (0x3FU)
\r
2461 #define CAN_TXEFS_EFFL_SHIFT (0U)
\r
2462 /*! EFFL - Event FIFO fill level.
\r
2464 #define CAN_TXEFS_EFFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFFL_SHIFT)) & CAN_TXEFS_EFFL_MASK)
\r
2465 #define CAN_TXEFS_EFGI_MASK (0x1F00U)
\r
2466 #define CAN_TXEFS_EFGI_SHIFT (8U)
\r
2467 /*! EFGI - Event FIFO get index.
\r
2469 #define CAN_TXEFS_EFGI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFGI_SHIFT)) & CAN_TXEFS_EFGI_MASK)
\r
2470 #define CAN_TXEFS_EFPI_MASK (0x3F0000U)
\r
2471 #define CAN_TXEFS_EFPI_SHIFT (16U)
\r
2472 /*! EFPI - Event FIFO put index.
\r
2474 #define CAN_TXEFS_EFPI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFPI_SHIFT)) & CAN_TXEFS_EFPI_MASK)
\r
2475 #define CAN_TXEFS_EFF_MASK (0x1000000U)
\r
2476 #define CAN_TXEFS_EFF_SHIFT (24U)
\r
2477 /*! EFF - Event FIFO full.
\r
2479 #define CAN_TXEFS_EFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFF_SHIFT)) & CAN_TXEFS_EFF_MASK)
\r
2480 #define CAN_TXEFS_TEFL_MASK (0x2000000U)
\r
2481 #define CAN_TXEFS_TEFL_SHIFT (25U)
\r
2482 /*! TEFL - Tx event FIFO element lost.
\r
2484 #define CAN_TXEFS_TEFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_TEFL_SHIFT)) & CAN_TXEFS_TEFL_MASK)
\r
2487 /*! @name TXEFA - Tx Event FIFO Acknowledge */
\r
2489 #define CAN_TXEFA_EFAI_MASK (0x1FU)
\r
2490 #define CAN_TXEFA_EFAI_SHIFT (0U)
\r
2491 /*! EFAI - Event FIFO acknowledge index.
\r
2493 #define CAN_TXEFA_EFAI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFA_EFAI_SHIFT)) & CAN_TXEFA_EFAI_MASK)
\r
2496 /*! @name MRBA - CAN Message RAM Base Address */
\r
2498 #define CAN_MRBA_BA_MASK (0xFFFF0000U)
\r
2499 #define CAN_MRBA_BA_SHIFT (16U)
\r
2500 /*! BA - Base address for the message RAM in the chip memory map.
\r
2502 #define CAN_MRBA_BA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MRBA_BA_SHIFT)) & CAN_MRBA_BA_MASK)
\r
2505 /*! @name ETSCC - External Timestamp Counter Configuration */
\r
2507 #define CAN_ETSCC_ETCP_MASK (0x7FFU)
\r
2508 #define CAN_ETSCC_ETCP_SHIFT (0U)
\r
2509 /*! ETCP - External timestamp prescaler value.
\r
2511 #define CAN_ETSCC_ETCP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCP_SHIFT)) & CAN_ETSCC_ETCP_MASK)
\r
2512 #define CAN_ETSCC_ETCE_MASK (0x80000000U)
\r
2513 #define CAN_ETSCC_ETCE_SHIFT (31U)
\r
2514 /*! ETCE - External timestamp counter enable.
\r
2516 #define CAN_ETSCC_ETCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCE_SHIFT)) & CAN_ETSCC_ETCE_MASK)
\r
2519 /*! @name ETSCV - External Timestamp Counter Value */
\r
2521 #define CAN_ETSCV_ETSC_MASK (0xFFFFU)
\r
2522 #define CAN_ETSCV_ETSC_SHIFT (0U)
\r
2523 /*! ETSC - External timestamp counter.
\r
2525 #define CAN_ETSCV_ETSC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCV_ETSC_SHIFT)) & CAN_ETSCV_ETSC_MASK)
\r
2531 */ /* end of group CAN_Register_Masks */
\r
2534 /* CAN - Peripheral instance base addresses */
\r
2535 /** Peripheral CAN0 base address */
\r
2536 #define CAN0_BASE (0x4009D000u)
\r
2537 /** Peripheral CAN0 base pointer */
\r
2538 #define CAN0 ((CAN_Type *)CAN0_BASE)
\r
2539 /** Peripheral CAN1 base address */
\r
2540 #define CAN1_BASE (0x4009E000u)
\r
2541 /** Peripheral CAN1 base pointer */
\r
2542 #define CAN1 ((CAN_Type *)CAN1_BASE)
\r
2543 /** Array initializer of CAN peripheral base addresses */
\r
2544 #define CAN_BASE_ADDRS { CAN0_BASE, CAN1_BASE }
\r
2545 /** Array initializer of CAN peripheral base pointers */
\r
2546 #define CAN_BASE_PTRS { CAN0, CAN1 }
\r
2547 /** Interrupt vectors for the CAN peripheral type */
\r
2548 #define CAN_IRQS { { CAN0_IRQ0_IRQn, CAN0_IRQ1_IRQn }, { CAN1_IRQ0_IRQn, CAN1_IRQ1_IRQn } }
\r
2552 */ /* end of group CAN_Peripheral_Access_Layer */
\r
2555 /* ----------------------------------------------------------------------------
\r
2556 -- CRC Peripheral Access Layer
\r
2557 ---------------------------------------------------------------------------- */
\r
2560 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
\r
2564 /** CRC - Register Layout Typedef */
\r
2566 __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */
\r
2567 __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */
\r
2568 union { /* offset: 0x8 */
\r
2569 __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */
\r
2570 __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */
\r
2574 /* ----------------------------------------------------------------------------
\r
2575 -- CRC Register Masks
\r
2576 ---------------------------------------------------------------------------- */
\r
2579 * @addtogroup CRC_Register_Masks CRC Register Masks
\r
2583 /*! @name MODE - CRC mode register */
\r
2585 #define CRC_MODE_CRC_POLY_MASK (0x3U)
\r
2586 #define CRC_MODE_CRC_POLY_SHIFT (0U)
\r
2587 /*! CRC_POLY - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial
\r
2589 #define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK)
\r
2590 #define CRC_MODE_BIT_RVS_WR_MASK (0x4U)
\r
2591 #define CRC_MODE_BIT_RVS_WR_SHIFT (2U)
\r
2592 /*! BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte)
\r
2594 #define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK)
\r
2595 #define CRC_MODE_CMPL_WR_MASK (0x8U)
\r
2596 #define CRC_MODE_CMPL_WR_SHIFT (3U)
\r
2597 /*! CMPL_WR - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA
\r
2599 #define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK)
\r
2600 #define CRC_MODE_BIT_RVS_SUM_MASK (0x10U)
\r
2601 #define CRC_MODE_BIT_RVS_SUM_SHIFT (4U)
\r
2602 /*! BIT_RVS_SUM - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM
\r
2604 #define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK)
\r
2605 #define CRC_MODE_CMPL_SUM_MASK (0x20U)
\r
2606 #define CRC_MODE_CMPL_SUM_SHIFT (5U)
\r
2607 /*! CMPL_SUM - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM
\r
2609 #define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK)
\r
2612 /*! @name SEED - CRC seed register */
\r
2614 #define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU)
\r
2615 #define CRC_SEED_CRC_SEED_SHIFT (0U)
\r
2616 /*! CRC_SEED - A write access to this register will load CRC seed value to CRC_SUM register with
\r
2617 * selected bit order and 1's complement pre-processes. A write access to this register will
\r
2618 * overrule the CRC calculation in progresses.
\r
2620 #define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK)
\r
2623 /*! @name SUM - CRC checksum register */
\r
2625 #define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU)
\r
2626 #define CRC_SUM_CRC_SUM_SHIFT (0U)
\r
2627 /*! CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes.
\r
2629 #define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK)
\r
2632 /*! @name WR_DATA - CRC data register */
\r
2634 #define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU)
\r
2635 #define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U)
\r
2636 /*! CRC_WR_DATA - Data written to this register will be taken to perform CRC calculation with
\r
2637 * selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and
\r
2638 * accept back-to-back transactions.
\r
2640 #define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK)
\r
2646 */ /* end of group CRC_Register_Masks */
\r
2649 /* CRC - Peripheral instance base addresses */
\r
2650 /** Peripheral CRC_ENGINE base address */
\r
2651 #define CRC_ENGINE_BASE (0x40095000u)
\r
2652 /** Peripheral CRC_ENGINE base pointer */
\r
2653 #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE)
\r
2654 /** Array initializer of CRC peripheral base addresses */
\r
2655 #define CRC_BASE_ADDRS { CRC_ENGINE_BASE }
\r
2656 /** Array initializer of CRC peripheral base pointers */
\r
2657 #define CRC_BASE_PTRS { CRC_ENGINE }
\r
2661 */ /* end of group CRC_Peripheral_Access_Layer */
\r
2664 /* ----------------------------------------------------------------------------
\r
2665 -- CTIMER Peripheral Access Layer
\r
2666 ---------------------------------------------------------------------------- */
\r
2669 * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer
\r
2673 /** CTIMER - Register Layout Typedef */
\r
2675 __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */
\r
2676 __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */
\r
2677 __IO uint32_t TC; /**< Timer Counter, offset: 0x8 */
\r
2678 __IO uint32_t PR; /**< Prescale Register, offset: 0xC */
\r
2679 __IO uint32_t PC; /**< Prescale Counter, offset: 0x10 */
\r
2680 __IO uint32_t MCR; /**< Match Control Register, offset: 0x14 */
\r
2681 __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */
\r
2682 __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */
\r
2683 __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */
\r
2684 __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */
\r
2685 uint8_t RESERVED_0[48];
\r
2686 __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */
\r
2687 __IO uint32_t PWMC; /**< PWM Control Register. The PWMCON enables PWM mode for the external match pins., offset: 0x74 */
\r
2688 __IO uint32_t MSR[4]; /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */
\r
2691 /* ----------------------------------------------------------------------------
\r
2692 -- CTIMER Register Masks
\r
2693 ---------------------------------------------------------------------------- */
\r
2696 * @addtogroup CTIMER_Register_Masks CTIMER Register Masks
\r
2700 /*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
\r
2702 #define CTIMER_IR_MR0INT_MASK (0x1U)
\r
2703 #define CTIMER_IR_MR0INT_SHIFT (0U)
\r
2704 /*! MR0INT - Interrupt flag for match channel 0.
\r
2706 #define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK)
\r
2707 #define CTIMER_IR_MR1INT_MASK (0x2U)
\r
2708 #define CTIMER_IR_MR1INT_SHIFT (1U)
\r
2709 /*! MR1INT - Interrupt flag for match channel 1.
\r
2711 #define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK)
\r
2712 #define CTIMER_IR_MR2INT_MASK (0x4U)
\r
2713 #define CTIMER_IR_MR2INT_SHIFT (2U)
\r
2714 /*! MR2INT - Interrupt flag for match channel 2.
\r
2716 #define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK)
\r
2717 #define CTIMER_IR_MR3INT_MASK (0x8U)
\r
2718 #define CTIMER_IR_MR3INT_SHIFT (3U)
\r
2719 /*! MR3INT - Interrupt flag for match channel 3.
\r
2721 #define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK)
\r
2722 #define CTIMER_IR_CR0INT_MASK (0x10U)
\r
2723 #define CTIMER_IR_CR0INT_SHIFT (4U)
\r
2724 /*! CR0INT - Interrupt flag for capture channel 0 event.
\r
2726 #define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK)
\r
2727 #define CTIMER_IR_CR1INT_MASK (0x20U)
\r
2728 #define CTIMER_IR_CR1INT_SHIFT (5U)
\r
2729 /*! CR1INT - Interrupt flag for capture channel 1 event.
\r
2731 #define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK)
\r
2732 #define CTIMER_IR_CR2INT_MASK (0x40U)
\r
2733 #define CTIMER_IR_CR2INT_SHIFT (6U)
\r
2734 /*! CR2INT - Interrupt flag for capture channel 2 event.
\r
2736 #define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK)
\r
2737 #define CTIMER_IR_CR3INT_MASK (0x80U)
\r
2738 #define CTIMER_IR_CR3INT_SHIFT (7U)
\r
2739 /*! CR3INT - Interrupt flag for capture channel 3 event.
\r
2741 #define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK)
\r
2744 /*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
\r
2746 #define CTIMER_TCR_CEN_MASK (0x1U)
\r
2747 #define CTIMER_TCR_CEN_SHIFT (0U)
\r
2748 /*! CEN - Counter enable.
\r
2749 * 0b0..Disabled.The counters are disabled.
\r
2750 * 0b1..Enabled. The Timer Counter and Prescale Counter are enabled.
\r
2752 #define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK)
\r
2753 #define CTIMER_TCR_CRST_MASK (0x2U)
\r
2754 #define CTIMER_TCR_CRST_SHIFT (1U)
\r
2755 /*! CRST - Counter reset.
\r
2756 * 0b0..Disabled. Do nothing.
\r
2757 * 0b1..Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of
\r
2758 * the APB bus clock. The counters remain reset until TCR[1] is returned to zero.
\r
2760 #define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK)
\r
2763 /*! @name TC - Timer Counter */
\r
2765 #define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU)
\r
2766 #define CTIMER_TC_TCVAL_SHIFT (0U)
\r
2767 /*! TCVAL - Timer counter value.
\r
2769 #define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK)
\r
2772 /*! @name PR - Prescale Register */
\r
2774 #define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU)
\r
2775 #define CTIMER_PR_PRVAL_SHIFT (0U)
\r
2776 /*! PRVAL - Prescale counter value.
\r
2778 #define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK)
\r
2781 /*! @name PC - Prescale Counter */
\r
2783 #define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU)
\r
2784 #define CTIMER_PC_PCVAL_SHIFT (0U)
\r
2785 /*! PCVAL - Prescale counter value.
\r
2787 #define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK)
\r
2790 /*! @name MCR - Match Control Register */
\r
2792 #define CTIMER_MCR_MR0I_MASK (0x1U)
\r
2793 #define CTIMER_MCR_MR0I_SHIFT (0U)
\r
2794 /*! MR0I - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
\r
2796 #define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
\r
2797 #define CTIMER_MCR_MR0R_MASK (0x2U)
\r
2798 #define CTIMER_MCR_MR0R_SHIFT (1U)
\r
2799 /*! MR0R - Reset on MR0: the TC will be reset if MR0 matches it.
\r
2801 #define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK)
\r
2802 #define CTIMER_MCR_MR0S_MASK (0x4U)
\r
2803 #define CTIMER_MCR_MR0S_SHIFT (2U)
\r
2804 /*! MR0S - Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.
\r
2806 #define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK)
\r
2807 #define CTIMER_MCR_MR1I_MASK (0x8U)
\r
2808 #define CTIMER_MCR_MR1I_SHIFT (3U)
\r
2809 /*! MR1I - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.
\r
2811 #define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK)
\r
2812 #define CTIMER_MCR_MR1R_MASK (0x10U)
\r
2813 #define CTIMER_MCR_MR1R_SHIFT (4U)
\r
2814 /*! MR1R - Reset on MR1: the TC will be reset if MR1 matches it.
\r
2816 #define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK)
\r
2817 #define CTIMER_MCR_MR1S_MASK (0x20U)
\r
2818 #define CTIMER_MCR_MR1S_SHIFT (5U)
\r
2819 /*! MR1S - Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.
\r
2821 #define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK)
\r
2822 #define CTIMER_MCR_MR2I_MASK (0x40U)
\r
2823 #define CTIMER_MCR_MR2I_SHIFT (6U)
\r
2824 /*! MR2I - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.
\r
2826 #define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK)
\r
2827 #define CTIMER_MCR_MR2R_MASK (0x80U)
\r
2828 #define CTIMER_MCR_MR2R_SHIFT (7U)
\r
2829 /*! MR2R - Reset on MR2: the TC will be reset if MR2 matches it.
\r
2831 #define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK)
\r
2832 #define CTIMER_MCR_MR2S_MASK (0x100U)
\r
2833 #define CTIMER_MCR_MR2S_SHIFT (8U)
\r
2834 /*! MR2S - Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.
\r
2836 #define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK)
\r
2837 #define CTIMER_MCR_MR3I_MASK (0x200U)
\r
2838 #define CTIMER_MCR_MR3I_SHIFT (9U)
\r
2839 /*! MR3I - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.
\r
2841 #define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK)
\r
2842 #define CTIMER_MCR_MR3R_MASK (0x400U)
\r
2843 #define CTIMER_MCR_MR3R_SHIFT (10U)
\r
2844 /*! MR3R - Reset on MR3: the TC will be reset if MR3 matches it.
\r
2846 #define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK)
\r
2847 #define CTIMER_MCR_MR3S_MASK (0x800U)
\r
2848 #define CTIMER_MCR_MR3S_SHIFT (11U)
\r
2849 /*! MR3S - Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.
\r
2851 #define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK)
\r
2852 #define CTIMER_MCR_MR0RL_MASK (0x1000000U)
\r
2853 #define CTIMER_MCR_MR0RL_SHIFT (24U)
\r
2854 /*! MR0RL - Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero
\r
2855 * (either via a match event or a write to bit 1 of the TCR).
\r
2857 #define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK)
\r
2858 #define CTIMER_MCR_MR1RL_MASK (0x2000000U)
\r
2859 #define CTIMER_MCR_MR1RL_SHIFT (25U)
\r
2860 /*! MR1RL - Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero
\r
2861 * (either via a match event or a write to bit 1 of the TCR).
\r
2863 #define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK)
\r
2864 #define CTIMER_MCR_MR2RL_MASK (0x4000000U)
\r
2865 #define CTIMER_MCR_MR2RL_SHIFT (26U)
\r
2866 /*! MR2RL - Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero
\r
2867 * (either via a match event or a write to bit 1 of the TCR).
\r
2869 #define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK)
\r
2870 #define CTIMER_MCR_MR3RL_MASK (0x8000000U)
\r
2871 #define CTIMER_MCR_MR3RL_SHIFT (27U)
\r
2872 /*! MR3RL - Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero
\r
2873 * (either via a match event or a write to bit 1 of the TCR).
\r
2875 #define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK)
\r
2878 /*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
\r
2880 #define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU)
\r
2881 #define CTIMER_MR_MATCH_SHIFT (0U)
\r
2882 /*! MATCH - Timer counter match value.
\r
2884 #define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK)
\r
2887 /* The count of CTIMER_MR */
\r
2888 #define CTIMER_MR_COUNT (4U)
\r
2890 /*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
\r
2892 #define CTIMER_CCR_CAP0RE_MASK (0x1U)
\r
2893 #define CTIMER_CCR_CAP0RE_SHIFT (0U)
\r
2894 /*! CAP0RE - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with
\r
2895 * the contents of TC. 0 = disabled. 1 = enabled.
\r
2897 #define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK)
\r
2898 #define CTIMER_CCR_CAP0FE_MASK (0x2U)
\r
2899 #define CTIMER_CCR_CAP0FE_SHIFT (1U)
\r
2900 /*! CAP0FE - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with
\r
2901 * the contents of TC. 0 = disabled. 1 = enabled.
\r
2903 #define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK)
\r
2904 #define CTIMER_CCR_CAP0I_MASK (0x4U)
\r
2905 #define CTIMER_CCR_CAP0I_SHIFT (2U)
\r
2906 /*! CAP0I - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt.
\r
2908 #define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
\r
2909 #define CTIMER_CCR_CAP1RE_MASK (0x8U)
\r
2910 #define CTIMER_CCR_CAP1RE_SHIFT (3U)
\r
2911 /*! CAP1RE - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with
\r
2912 * the contents of TC. 0 = disabled. 1 = enabled.
\r
2914 #define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK)
\r
2915 #define CTIMER_CCR_CAP1FE_MASK (0x10U)
\r
2916 #define CTIMER_CCR_CAP1FE_SHIFT (4U)
\r
2917 /*! CAP1FE - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with
\r
2918 * the contents of TC. 0 = disabled. 1 = enabled.
\r
2920 #define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK)
\r
2921 #define CTIMER_CCR_CAP1I_MASK (0x20U)
\r
2922 #define CTIMER_CCR_CAP1I_SHIFT (5U)
\r
2923 /*! CAP1I - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt.
\r
2925 #define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK)
\r
2926 #define CTIMER_CCR_CAP2RE_MASK (0x40U)
\r
2927 #define CTIMER_CCR_CAP2RE_SHIFT (6U)
\r
2928 /*! CAP2RE - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with
\r
2929 * the contents of TC. 0 = disabled. 1 = enabled.
\r
2931 #define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK)
\r
2932 #define CTIMER_CCR_CAP2FE_MASK (0x80U)
\r
2933 #define CTIMER_CCR_CAP2FE_SHIFT (7U)
\r
2934 /*! CAP2FE - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with
\r
2935 * the contents of TC. 0 = disabled. 1 = enabled.
\r
2937 #define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK)
\r
2938 #define CTIMER_CCR_CAP2I_MASK (0x100U)
\r
2939 #define CTIMER_CCR_CAP2I_SHIFT (8U)
\r
2940 /*! CAP2I - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt.
\r
2942 #define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK)
\r
2943 #define CTIMER_CCR_CAP3RE_MASK (0x200U)
\r
2944 #define CTIMER_CCR_CAP3RE_SHIFT (9U)
\r
2945 /*! CAP3RE - Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with
\r
2946 * the contents of TC. 0 = disabled. 1 = enabled.
\r
2948 #define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK)
\r
2949 #define CTIMER_CCR_CAP3FE_MASK (0x400U)
\r
2950 #define CTIMER_CCR_CAP3FE_SHIFT (10U)
\r
2951 /*! CAP3FE - Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with
\r
2952 * the contents of TC. 0 = disabled. 1 = enabled.
\r
2954 #define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK)
\r
2955 #define CTIMER_CCR_CAP3I_MASK (0x800U)
\r
2956 #define CTIMER_CCR_CAP3I_SHIFT (11U)
\r
2957 /*! CAP3I - Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt.
\r
2959 #define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK)
\r
2962 /*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */
\r
2964 #define CTIMER_CR_CAP_MASK (0xFFFFFFFFU)
\r
2965 #define CTIMER_CR_CAP_SHIFT (0U)
\r
2966 /*! CAP - Timer counter capture value.
\r
2968 #define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK)
\r
2971 /* The count of CTIMER_CR */
\r
2972 #define CTIMER_CR_COUNT (4U)
\r
2974 /*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */
\r
2976 #define CTIMER_EMR_EM0_MASK (0x1U)
\r
2977 #define CTIMER_EMR_EM0_SHIFT (0U)
\r
2978 /*! EM0 - External Match 0. This bit reflects the state of output MAT0, whether or not this output
\r
2979 * is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle,
\r
2980 * go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if
\r
2981 * the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
\r
2983 #define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK)
\r
2984 #define CTIMER_EMR_EM1_MASK (0x2U)
\r
2985 #define CTIMER_EMR_EM1_SHIFT (1U)
\r
2986 /*! EM1 - External Match 1. This bit reflects the state of output MAT1, whether or not this output
\r
2987 * is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle,
\r
2988 * go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if
\r
2989 * the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
\r
2991 #define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK)
\r
2992 #define CTIMER_EMR_EM2_MASK (0x4U)
\r
2993 #define CTIMER_EMR_EM2_SHIFT (2U)
\r
2994 /*! EM2 - External Match 2. This bit reflects the state of output MAT2, whether or not this output
\r
2995 * is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle,
\r
2996 * go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if
\r
2997 * the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
\r
2999 #define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK)
\r
3000 #define CTIMER_EMR_EM3_MASK (0x8U)
\r
3001 #define CTIMER_EMR_EM3_SHIFT (3U)
\r
3002 /*! EM3 - External Match 3. This bit reflects the state of output MAT3, whether or not this output
\r
3003 * is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle,
\r
3004 * go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins
\r
3005 * if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
\r
3007 #define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK)
\r
3008 #define CTIMER_EMR_EMC0_MASK (0x30U)
\r
3009 #define CTIMER_EMR_EMC0_SHIFT (4U)
\r
3010 /*! EMC0 - External Match Control 0. Determines the functionality of External Match 0.
\r
3011 * 0b00..Do Nothing.
\r
3012 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out).
\r
3013 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out).
\r
3014 * 0b11..Toggle. Toggle the corresponding External Match bit/output.
\r
3016 #define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK)
\r
3017 #define CTIMER_EMR_EMC1_MASK (0xC0U)
\r
3018 #define CTIMER_EMR_EMC1_SHIFT (6U)
\r
3019 /*! EMC1 - External Match Control 1. Determines the functionality of External Match 1.
\r
3020 * 0b00..Do Nothing.
\r
3021 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out).
\r
3022 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out).
\r
3023 * 0b11..Toggle. Toggle the corresponding External Match bit/output.
\r
3025 #define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK)
\r
3026 #define CTIMER_EMR_EMC2_MASK (0x300U)
\r
3027 #define CTIMER_EMR_EMC2_SHIFT (8U)
\r
3028 /*! EMC2 - External Match Control 2. Determines the functionality of External Match 2.
\r
3029 * 0b00..Do Nothing.
\r
3030 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out).
\r
3031 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out).
\r
3032 * 0b11..Toggle. Toggle the corresponding External Match bit/output.
\r
3034 #define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK)
\r
3035 #define CTIMER_EMR_EMC3_MASK (0xC00U)
\r
3036 #define CTIMER_EMR_EMC3_SHIFT (10U)
\r
3037 /*! EMC3 - External Match Control 3. Determines the functionality of External Match 3.
\r
3038 * 0b00..Do Nothing.
\r
3039 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out).
\r
3040 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out).
\r
3041 * 0b11..Toggle. Toggle the corresponding External Match bit/output.
\r
3043 #define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK)
\r
3046 /*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
\r
3048 #define CTIMER_CTCR_CTMODE_MASK (0x3U)
\r
3049 #define CTIMER_CTCR_CTMODE_SHIFT (0U)
\r
3050 /*! CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment
\r
3051 * Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC
\r
3052 * is incremented when the Prescale Counter matches the Prescale Register.
\r
3053 * 0b00..Timer Mode. Incremented every rising APB bus clock edge.
\r
3054 * 0b01..Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2.
\r
3055 * 0b10..Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2.
\r
3056 * 0b11..Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2.
\r
3058 #define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK)
\r
3059 #define CTIMER_CTCR_CINSEL_MASK (0xCU)
\r
3060 #define CTIMER_CTCR_CINSEL_SHIFT (2U)
\r
3061 /*! CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which
\r
3062 * CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input
\r
3063 * in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be
\r
3064 * programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the
\r
3066 * 0b00..Channel 0. CAPn.0 for CTIMERn
\r
3067 * 0b01..Channel 1. CAPn.1 for CTIMERn
\r
3068 * 0b10..Channel 2. CAPn.2 for CTIMERn
\r
3069 * 0b11..Channel 3. CAPn.3 for CTIMERn
\r
3071 #define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK)
\r
3072 #define CTIMER_CTCR_ENCC_MASK (0x10U)
\r
3073 #define CTIMER_CTCR_ENCC_SHIFT (4U)
\r
3074 /*! ENCC - Setting this bit to 1 enables clearing of the timer and the prescaler when the
\r
3075 * capture-edge event specified in bits 7:5 occurs.
\r
3077 #define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK)
\r
3078 #define CTIMER_CTCR_SELCC_MASK (0xE0U)
\r
3079 #define CTIMER_CTCR_SELCC_SHIFT (5U)
\r
3080 /*! SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the
\r
3081 * timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to
\r
3082 * 0x3 and 0x6 to 0x7 are reserved.
\r
3083 * 0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
\r
3084 * 0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
\r
3085 * 0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
\r
3086 * 0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
\r
3087 * 0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
\r
3088 * 0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
\r
3090 #define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK)
\r
3093 /*! @name PWMC - PWM Control Register. The PWMCON enables PWM mode for the external match pins. */
\r
3095 #define CTIMER_PWMC_PWMEN0_MASK (0x1U)
\r
3096 #define CTIMER_PWMC_PWMEN0_SHIFT (0U)
\r
3097 /*! PWMEN0 - PWM mode enable for channel0.
\r
3098 * 0b0..Match. CTIMERn_MAT0 is controlled by EM0.
\r
3099 * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT0.
\r
3101 #define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK)
\r
3102 #define CTIMER_PWMC_PWMEN1_MASK (0x2U)
\r
3103 #define CTIMER_PWMC_PWMEN1_SHIFT (1U)
\r
3104 /*! PWMEN1 - PWM mode enable for channel1.
\r
3105 * 0b0..Match. CTIMERn_MAT01 is controlled by EM1.
\r
3106 * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT1.
\r
3108 #define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK)
\r
3109 #define CTIMER_PWMC_PWMEN2_MASK (0x4U)
\r
3110 #define CTIMER_PWMC_PWMEN2_SHIFT (2U)
\r
3111 /*! PWMEN2 - PWM mode enable for channel2.
\r
3112 * 0b0..Match. CTIMERn_MAT2 is controlled by EM2.
\r
3113 * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT2.
\r
3115 #define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK)
\r
3116 #define CTIMER_PWMC_PWMEN3_MASK (0x8U)
\r
3117 #define CTIMER_PWMC_PWMEN3_SHIFT (3U)
\r
3118 /*! PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.
\r
3119 * 0b0..Match. CTIMERn_MAT3 is controlled by EM3.
\r
3120 * 0b1..PWM. PWM mode is enabled for CT132Bn_MAT3.
\r
3122 #define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK)
\r
3125 /*! @name MSR - Match Shadow Register */
\r
3127 #define CTIMER_MSR_SHADOWW_MASK (0xFFFFFFFFU)
\r
3128 #define CTIMER_MSR_SHADOWW_SHIFT (0U)
\r
3129 /*! SHADOWW - Timer counter match shadow value.
\r
3131 #define CTIMER_MSR_SHADOWW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_SHADOWW_SHIFT)) & CTIMER_MSR_SHADOWW_MASK)
\r
3134 /* The count of CTIMER_MSR */
\r
3135 #define CTIMER_MSR_COUNT (4U)
\r
3140 */ /* end of group CTIMER_Register_Masks */
\r
3143 /* CTIMER - Peripheral instance base addresses */
\r
3144 /** Peripheral CTIMER0 base address */
\r
3145 #define CTIMER0_BASE (0x40008000u)
\r
3146 /** Peripheral CTIMER0 base pointer */
\r
3147 #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE)
\r
3148 /** Peripheral CTIMER1 base address */
\r
3149 #define CTIMER1_BASE (0x40009000u)
\r
3150 /** Peripheral CTIMER1 base pointer */
\r
3151 #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE)
\r
3152 /** Peripheral CTIMER2 base address */
\r
3153 #define CTIMER2_BASE (0x40028000u)
\r
3154 /** Peripheral CTIMER2 base pointer */
\r
3155 #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE)
\r
3156 /** Peripheral CTIMER3 base address */
\r
3157 #define CTIMER3_BASE (0x40048000u)
\r
3158 /** Peripheral CTIMER3 base pointer */
\r
3159 #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE)
\r
3160 /** Peripheral CTIMER4 base address */
\r
3161 #define CTIMER4_BASE (0x40049000u)
\r
3162 /** Peripheral CTIMER4 base pointer */
\r
3163 #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE)
\r
3164 /** Array initializer of CTIMER peripheral base addresses */
\r
3165 #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE }
\r
3166 /** Array initializer of CTIMER peripheral base pointers */
\r
3167 #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 }
\r
3168 /** Interrupt vectors for the CTIMER peripheral type */
\r
3169 #define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn }
\r
3173 */ /* end of group CTIMER_Peripheral_Access_Layer */
\r
3176 /* ----------------------------------------------------------------------------
\r
3177 -- DMA Peripheral Access Layer
\r
3178 ---------------------------------------------------------------------------- */
\r
3181 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
\r
3185 /** DMA - Register Layout Typedef */
\r
3187 __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */
\r
3188 __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */
\r
3189 __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */
\r
3190 uint8_t RESERVED_0[20];
\r
3191 struct { /* offset: 0x20, array step: 0x5C */
\r
3192 __IO uint32_t ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */
\r
3193 uint8_t RESERVED_0[4];
\r
3194 __O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */
\r
3195 uint8_t RESERVED_1[4];
\r
3196 __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */
\r
3197 uint8_t RESERVED_2[4];
\r
3198 __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */
\r
3199 uint8_t RESERVED_3[4];
\r
3200 __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */
\r
3201 uint8_t RESERVED_4[4];
\r
3202 __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */
\r
3203 uint8_t RESERVED_5[4];
\r
3204 __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */
\r
3205 uint8_t RESERVED_6[4];
\r
3206 __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */
\r
3207 uint8_t RESERVED_7[4];
\r
3208 __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */
\r
3209 uint8_t RESERVED_8[4];
\r
3210 __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */
\r
3211 uint8_t RESERVED_9[4];
\r
3212 __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */
\r
3213 uint8_t RESERVED_10[4];
\r
3214 __O uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */
\r
3216 uint8_t RESERVED_1[900];
\r
3217 struct { /* offset: 0x400, array step: 0x10 */
\r
3218 __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */
\r
3219 __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */
\r
3220 __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */
\r
3221 uint8_t RESERVED_0[4];
\r
3225 /* ----------------------------------------------------------------------------
\r
3226 -- DMA Register Masks
\r
3227 ---------------------------------------------------------------------------- */
\r
3230 * @addtogroup DMA_Register_Masks DMA Register Masks
\r
3234 /*! @name CTRL - DMA control. */
\r
3236 #define DMA_CTRL_ENABLE_MASK (0x1U)
\r
3237 #define DMA_CTRL_ENABLE_SHIFT (0U)
\r
3238 /*! ENABLE - DMA controller master enable.
\r
3239 * 0b0..Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when
\r
3240 * disabled, but does not prevent re-triggering when the DMA controller is re-enabled.
\r
3241 * 0b1..Enabled. The DMA controller is enabled.
\r
3243 #define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK)
\r
3246 /*! @name INTSTAT - Interrupt status. */
\r
3248 #define DMA_INTSTAT_ACTIVEINT_MASK (0x2U)
\r
3249 #define DMA_INTSTAT_ACTIVEINT_SHIFT (1U)
\r
3250 /*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending.
\r
3251 * 0b0..Not pending. No enabled interrupts are pending.
\r
3252 * 0b1..Pending. At least one enabled interrupt is pending.
\r
3254 #define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK)
\r
3255 #define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U)
\r
3256 #define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U)
\r
3257 /*! ACTIVEERRINT - Summarizes whether any error interrupts are pending.
\r
3258 * 0b0..Not pending. No error interrupts are pending.
\r
3259 * 0b1..Pending. At least one error interrupt is pending.
\r
3261 #define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK)
\r
3264 /*! @name SRAMBASE - SRAM address of the channel configuration table. */
\r
3266 #define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U)
\r
3267 #define DMA_SRAMBASE_OFFSET_SHIFT (9U)
\r
3268 /*! OFFSET - Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the
\r
3269 * table must begin on a 512 byte boundary.
\r
3271 #define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK)
\r
3274 /*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */
\r
3276 #define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU)
\r
3277 #define DMA_COMMON_ENABLESET_ENA_SHIFT (0U)
\r
3278 /*! ENA - Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits =
\r
3279 * number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled.
\r
3281 #define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK)
\r
3284 /* The count of DMA_COMMON_ENABLESET */
\r
3285 #define DMA_COMMON_ENABLESET_COUNT (1U)
\r
3287 /*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */
\r
3289 #define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU)
\r
3290 #define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U)
\r
3291 /*! CLR - Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears
\r
3292 * the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits
\r
3295 #define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK)
\r
3298 /* The count of DMA_COMMON_ENABLECLR */
\r
3299 #define DMA_COMMON_ENABLECLR_COUNT (1U)
\r
3301 /*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */
\r
3303 #define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU)
\r
3304 #define DMA_COMMON_ACTIVE_ACT_SHIFT (0U)
\r
3305 /*! ACT - Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits =
\r
3306 * number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active.
\r
3308 #define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK)
\r
3311 /* The count of DMA_COMMON_ACTIVE */
\r
3312 #define DMA_COMMON_ACTIVE_COUNT (1U)
\r
3314 /*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */
\r
3316 #define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU)
\r
3317 #define DMA_COMMON_BUSY_BSY_SHIFT (0U)
\r
3318 /*! BSY - Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits =
\r
3319 * number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy.
\r
3321 #define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK)
\r
3324 /* The count of DMA_COMMON_BUSY */
\r
3325 #define DMA_COMMON_BUSY_COUNT (1U)
\r
3327 /*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */
\r
3329 #define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU)
\r
3330 #define DMA_COMMON_ERRINT_ERR_SHIFT (0U)
\r
3331 /*! ERR - Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of
\r
3332 * bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is
\r
3333 * not active. 1 = error interrupt is active.
\r
3335 #define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK)
\r
3338 /* The count of DMA_COMMON_ERRINT */
\r
3339 #define DMA_COMMON_ERRINT_COUNT (1U)
\r
3341 /*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */
\r
3343 #define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU)
\r
3344 #define DMA_COMMON_INTENSET_INTEN_SHIFT (0U)
\r
3345 /*! INTEN - Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The
\r
3346 * number of bits = number of DMA channels in this device. Other bits are reserved. 0 =
\r
3347 * interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled.
\r
3349 #define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK)
\r
3352 /* The count of DMA_COMMON_INTENSET */
\r
3353 #define DMA_COMMON_INTENSET_COUNT (1U)
\r
3355 /*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */
\r
3357 #define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU)
\r
3358 #define DMA_COMMON_INTENCLR_CLR_SHIFT (0U)
\r
3359 /*! CLR - Writing ones to this register clears corresponding bits in the INTENSET0. Bit n
\r
3360 * corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are
\r
3363 #define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK)
\r
3366 /* The count of DMA_COMMON_INTENCLR */
\r
3367 #define DMA_COMMON_INTENCLR_COUNT (1U)
\r
3369 /*! @name COMMON_INTA - Interrupt A status for all DMA channels. */
\r
3371 #define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU)
\r
3372 #define DMA_COMMON_INTA_IA_SHIFT (0U)
\r
3373 /*! IA - Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of
\r
3374 * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel
\r
3375 * interrupt A is not active. 1 = the DMA channel interrupt A is active.
\r
3377 #define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK)
\r
3380 /* The count of DMA_COMMON_INTA */
\r
3381 #define DMA_COMMON_INTA_COUNT (1U)
\r
3383 /*! @name COMMON_INTB - Interrupt B status for all DMA channels. */
\r
3385 #define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU)
\r
3386 #define DMA_COMMON_INTB_IB_SHIFT (0U)
\r
3387 /*! IB - Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of
\r
3388 * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel
\r
3389 * interrupt B is not active. 1 = the DMA channel interrupt B is active.
\r
3391 #define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK)
\r
3394 /* The count of DMA_COMMON_INTB */
\r
3395 #define DMA_COMMON_INTB_COUNT (1U)
\r
3397 /*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */
\r
3399 #define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU)
\r
3400 #define DMA_COMMON_SETVALID_SV_SHIFT (0U)
\r
3401 /*! SV - SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits
\r
3402 * = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the
\r
3403 * VALIDPENDING control bit for DMA channel n
\r
3405 #define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK)
\r
3408 /* The count of DMA_COMMON_SETVALID */
\r
3409 #define DMA_COMMON_SETVALID_COUNT (1U)
\r
3411 /*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */
\r
3413 #define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU)
\r
3414 #define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U)
\r
3415 /*! TRIG - Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number
\r
3416 * of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 =
\r
3417 * sets the TRIG bit for DMA channel n.
\r
3419 #define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK)
\r
3422 /* The count of DMA_COMMON_SETTRIG */
\r
3423 #define DMA_COMMON_SETTRIG_COUNT (1U)
\r
3425 /*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */
\r
3427 #define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU)
\r
3428 #define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U)
\r
3429 /*! ABORTCTRL - Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect.
\r
3430 * 1 = aborts DMA operations on channel n.
\r
3432 #define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK)
\r
3435 /* The count of DMA_COMMON_ABORT */
\r
3436 #define DMA_COMMON_ABORT_COUNT (1U)
\r
3438 /*! @name CHANNEL_CFG - Configuration register for DMA channel . */
\r
3440 #define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U)
\r
3441 #define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U)
\r
3442 /*! PERIPHREQEN - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory
\r
3443 * move, any peripheral DMA request associated with that channel can be disabled to prevent any
\r
3444 * interaction between the peripheral and the DMA controller.
\r
3445 * 0b0..Disabled. Peripheral DMA requests are disabled.
\r
3446 * 0b1..Enabled. Peripheral DMA requests are enabled.
\r
3448 #define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK)
\r
3449 #define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U)
\r
3450 #define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U)
\r
3451 /*! HWTRIGEN - Hardware Triggering Enable for this channel.
\r
3452 * 0b0..Disabled. Hardware triggering is not used.
\r
3453 * 0b1..Enabled. Use hardware triggering.
\r
3455 #define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK)
\r
3456 #define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U)
\r
3457 #define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U)
\r
3458 /*! TRIGPOL - Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
\r
3459 * 0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
\r
3460 * 0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
\r
3462 #define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK)
\r
3463 #define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U)
\r
3464 #define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U)
\r
3465 /*! TRIGTYPE - Trigger Type. Selects hardware trigger as edge triggered or level triggered.
\r
3466 * 0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
\r
3467 * 0b1..Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER =
\r
3468 * 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the
\r
3469 * trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger
\r
3470 * is, again, asserted. However, the transfer will not be paused until any remaining transfers within the
\r
3471 * current BURSTPOWER length are completed.
\r
3473 #define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK)
\r
3474 #define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U)
\r
3475 #define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U)
\r
3476 /*! TRIGBURST - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
\r
3477 * 0b0..Single transfer. Hardware trigger causes a single transfer.
\r
3478 * 0b1..Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a
\r
3479 * burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a
\r
3480 * hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is
\r
3483 #define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK)
\r
3484 #define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U)
\r
3485 #define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U)
\r
3486 /*! BURSTPOWER - Burst Power is used in two ways. It always selects the address wrap size when
\r
3487 * SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register).
\r
3488 * When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many
\r
3489 * transfers are performed for each DMA trigger. This can be used, for example, with peripherals that
\r
3490 * contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000:
\r
3491 * Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size =
\r
3492 * 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The
\r
3493 * total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even
\r
3494 * multiple of the burst size.
\r
3496 #define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK)
\r
3497 #define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U)
\r
3498 #define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U)
\r
3499 /*! SRCBURSTWRAP - Source Burst Wrap. When enabled, the source data address for the DMA is
\r
3500 * 'wrapped', meaning that the source address range for each burst will be the same. As an example, this
\r
3501 * could be used to read several sequential registers from a peripheral for each DMA burst,
\r
3502 * reading the same registers again for each burst.
\r
3503 * 0b0..Disabled. Source burst wrapping is not enabled for this DMA channel.
\r
3504 * 0b1..Enabled. Source burst wrapping is enabled for this DMA channel.
\r
3506 #define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK)
\r
3507 #define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U)
\r
3508 #define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U)
\r
3509 /*! DSTBURSTWRAP - Destination Burst Wrap. When enabled, the destination data address for the DMA is
\r
3510 * 'wrapped', meaning that the destination address range for each burst will be the same. As an
\r
3511 * example, this could be used to write several sequential registers to a peripheral for each DMA
\r
3512 * burst, writing the same registers again for each burst.
\r
3513 * 0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel.
\r
3514 * 0b1..Enabled. Destination burst wrapping is enabled for this DMA channel.
\r
3516 #define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK)
\r
3517 #define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U)
\r
3518 #define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U)
\r
3519 /*! CHPRIORITY - Priority of this channel when multiple DMA requests are pending. Eight priority
\r
3520 * levels are supported: 0x0 = highest priority. 0x7 = lowest priority.
\r
3522 #define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK)
\r
3525 /* The count of DMA_CHANNEL_CFG */
\r
3526 #define DMA_CHANNEL_CFG_COUNT (32U)
\r
3528 /*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */
\r
3530 #define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U)
\r
3531 #define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U)
\r
3532 /*! VALIDPENDING - Valid pending flag for this channel. This bit is set when a 1 is written to the
\r
3533 * corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
\r
3534 * 0b0..No effect. No effect on DMA operation.
\r
3535 * 0b1..Valid pending.
\r
3537 #define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK)
\r
3538 #define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U)
\r
3539 #define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U)
\r
3540 /*! TRIG - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is
\r
3541 * cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
\r
3542 * 0b0..Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
\r
3543 * 0b1..Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
\r
3545 #define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK)
\r
3548 /* The count of DMA_CHANNEL_CTLSTAT */
\r
3549 #define DMA_CHANNEL_CTLSTAT_COUNT (32U)
\r
3551 /*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */
\r
3553 #define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U)
\r
3554 #define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U)
\r
3555 /*! CFGVALID - Configuration Valid flag. This bit indicates whether the current channel descriptor
\r
3556 * is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
\r
3557 * 0b0..Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
\r
3558 * 0b1..Valid. The current channel descriptor is considered valid.
\r
3560 #define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK)
\r
3561 #define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U)
\r
3562 #define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U)
\r
3563 /*! RELOAD - Indicates whether the channel's control structure will be reloaded when the current
\r
3564 * descriptor is exhausted. Reloading allows ping-pong and linked transfers.
\r
3565 * 0b0..Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
\r
3566 * 0b1..Enabled. Reload the channels' control structure when the current descriptor is exhausted.
\r
3568 #define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK)
\r
3569 #define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U)
\r
3570 #define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U)
\r
3571 /*! SWTRIG - Software Trigger.
\r
3572 * 0b0..Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by
\r
3573 * the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
\r
3574 * 0b1..Set. When written by software, the trigger for this channel is set immediately. This feature should not
\r
3575 * be used with level triggering when TRIGBURST = 0.
\r
3577 #define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK)
\r
3578 #define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U)
\r
3579 #define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U)
\r
3580 /*! CLRTRIG - Clear Trigger.
\r
3581 * 0b0..Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started.
\r
3582 * 0b1..Cleared. The trigger is cleared when this descriptor is exhausted
\r
3584 #define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK)
\r
3585 #define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U)
\r
3586 #define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U)
\r
3587 /*! SETINTA - Set Interrupt flag A for this channel. There is no hardware distinction between
\r
3588 * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By
\r
3589 * convention, interrupt A may be used when only one interrupt flag is needed.
\r
3591 * 0b1..Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
\r
3593 #define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK)
\r
3594 #define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U)
\r
3595 #define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U)
\r
3596 /*! SETINTB - Set Interrupt flag B for this channel. There is no hardware distinction between
\r
3597 * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By
\r
3598 * convention, interrupt A may be used when only one interrupt flag is needed.
\r
3600 * 0b1..Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
\r
3602 #define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK)
\r
3603 #define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U)
\r
3604 #define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U)
\r
3605 /*! WIDTH - Transfer width used for this DMA channel.
\r
3606 * 0b00..8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).
\r
3607 * 0b01..16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).
\r
3608 * 0b10..32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).
\r
3609 * 0b11..Reserved. Reserved setting, do not use.
\r
3611 #define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK)
\r
3612 #define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U)
\r
3613 #define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U)
\r
3614 /*! SRCINC - Determines whether the source address is incremented for each DMA transfer.
\r
3615 * 0b00..No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
\r
3616 * 0b01..1 x width. The source address is incremented by the amount specified by Width for each transfer. This is
\r
3617 * the usual case when the source is memory.
\r
3618 * 0b10..2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
\r
3619 * 0b11..4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
\r
3621 #define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK)
\r
3622 #define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U)
\r
3623 #define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U)
\r
3624 /*! DSTINC - Determines whether the destination address is incremented for each DMA transfer.
\r
3625 * 0b00..No increment. The destination address is not incremented for each transfer. This is the usual case when
\r
3626 * the destination is a peripheral device.
\r
3627 * 0b01..1 x width. The destination address is incremented by the amount specified by Width for each transfer.
\r
3628 * This is the usual case when the destination is memory.
\r
3629 * 0b10..2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
\r
3630 * 0b11..4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
\r
3632 #define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK)
\r
3633 #define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U)
\r
3634 #define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U)
\r
3635 /*! XFERCOUNT - Total number of transfers to be performed, minus 1 encoded. The number of bytes
\r
3636 * transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller
\r
3637 * uses this bit field during transfer to count down. Hence, it cannot be used by software to read
\r
3638 * back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1
\r
3639 * transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of
\r
3640 * 1,024 transfers will be performed.
\r
3642 #define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK)
\r
3645 /* The count of DMA_CHANNEL_XFERCFG */
\r
3646 #define DMA_CHANNEL_XFERCFG_COUNT (32U)
\r
3651 */ /* end of group DMA_Register_Masks */
\r
3654 /* DMA - Peripheral instance base addresses */
\r
3655 /** Peripheral DMA0 base address */
\r
3656 #define DMA0_BASE (0x40082000u)
\r
3657 /** Peripheral DMA0 base pointer */
\r
3658 #define DMA0 ((DMA_Type *)DMA0_BASE)
\r
3659 /** Array initializer of DMA peripheral base addresses */
\r
3660 #define DMA_BASE_ADDRS { DMA0_BASE }
\r
3661 /** Array initializer of DMA peripheral base pointers */
\r
3662 #define DMA_BASE_PTRS { DMA0 }
\r
3663 /** Interrupt vectors for the DMA peripheral type */
\r
3664 #define DMA_IRQS { DMA0_IRQn }
\r
3668 */ /* end of group DMA_Peripheral_Access_Layer */
\r
3671 /* ----------------------------------------------------------------------------
\r
3672 -- DMIC Peripheral Access Layer
\r
3673 ---------------------------------------------------------------------------- */
\r
3676 * @addtogroup DMIC_Peripheral_Access_Layer DMIC Peripheral Access Layer
\r
3680 /** DMIC - Register Layout Typedef */
\r
3682 struct { /* offset: 0x0, array step: 0x100 */
\r
3683 __IO uint32_t OSR; /**< Oversample Rate register 0, array offset: 0x0, array step: 0x100 */
\r
3684 __IO uint32_t DIVHFCLK; /**< DMIC Clock Register 0, array offset: 0x4, array step: 0x100 */
\r
3685 __IO uint32_t PREAC2FSCOEF; /**< Pre-Emphasis Filter Coefficient for 2 FS register, array offset: 0x8, array step: 0x100 */
\r
3686 __IO uint32_t PREAC4FSCOEF; /**< Pre-Emphasis Filter Coefficient for 4 FS register, array offset: 0xC, array step: 0x100 */
\r
3687 __IO uint32_t GAINSHIFT; /**< Decimator Gain Shift register, array offset: 0x10, array step: 0x100 */
\r
3688 uint8_t RESERVED_0[108];
\r
3689 __IO uint32_t FIFO_CTRL; /**< FIFO Control register 0, array offset: 0x80, array step: 0x100 */
\r
3690 __IO uint32_t FIFO_STATUS; /**< FIFO Status register 0, array offset: 0x84, array step: 0x100 */
\r
3691 __IO uint32_t FIFO_DATA; /**< FIFO Data Register 0, array offset: 0x88, array step: 0x100 */
\r
3692 __IO uint32_t PHY_CTRL; /**< PDM Source Configuration register 0, array offset: 0x8C, array step: 0x100 */
\r
3693 __IO uint32_t DC_CTRL; /**< DC Control register 0, array offset: 0x90, array step: 0x100 */
\r
3694 uint8_t RESERVED_1[108];
\r
3696 uint8_t RESERVED_0[3328];
\r
3697 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */
\r
3698 uint8_t RESERVED_1[8];
\r
3699 __IO uint32_t IOCFG; /**< I/O Configuration register, offset: 0xF0C */
\r
3700 __IO uint32_t USE2FS; /**< Use 2FS register, offset: 0xF10 */
\r
3701 uint8_t RESERVED_2[108];
\r
3702 __IO uint32_t HWVADGAIN; /**< HWVAD input gain register, offset: 0xF80 */
\r
3703 __IO uint32_t HWVADHPFS; /**< HWVAD filter control register, offset: 0xF84 */
\r
3704 __IO uint32_t HWVADST10; /**< HWVAD control register, offset: 0xF88 */
\r
3705 __IO uint32_t HWVADRSTT; /**< HWVAD filter reset register, offset: 0xF8C */
\r
3706 __IO uint32_t HWVADTHGN; /**< HWVAD noise estimator gain register, offset: 0xF90 */
\r
3707 __IO uint32_t HWVADTHGS; /**< HWVAD signal estimator gain register, offset: 0xF94 */
\r
3708 __I uint32_t HWVADLOWZ; /**< HWVAD noise envelope estimator register, offset: 0xF98 */
\r
3709 uint8_t RESERVED_3[96];
\r
3710 __I uint32_t ID; /**< Module Identification register, offset: 0xFFC */
\r
3713 /* ----------------------------------------------------------------------------
\r
3714 -- DMIC Register Masks
\r
3715 ---------------------------------------------------------------------------- */
\r
3718 * @addtogroup DMIC_Register_Masks DMIC Register Masks
\r
3722 /*! @name CHANNEL_OSR - Oversample Rate register 0 */
\r
3724 #define DMIC_CHANNEL_OSR_OSR_MASK (0xFFU)
\r
3725 #define DMIC_CHANNEL_OSR_OSR_SHIFT (0U)
\r
3726 /*! OSR - Selects the oversample rate for the related input channel.
\r
3728 #define DMIC_CHANNEL_OSR_OSR(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_OSR_OSR_SHIFT)) & DMIC_CHANNEL_OSR_OSR_MASK)
\r
3731 /* The count of DMIC_CHANNEL_OSR */
\r
3732 #define DMIC_CHANNEL_OSR_COUNT (2U)
\r
3734 /*! @name CHANNEL_DIVHFCLK - DMIC Clock Register 0 */
\r
3736 #define DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK (0xFU)
\r
3737 #define DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT (0U)
\r
3738 /*! PDMDIV - PDM clock divider value. 0 = divide by 1 1 = divide by 2 2 = divide by 3 3 = divide by
\r
3739 * 4 4 = divide by 6 5 = divide by 8 6 = divide by 12 7 = divide by 16 8 = divide by 24 9 =
\r
3740 * divide by 32 10 = divide by 48 11 = divide by 64 12 = divide by 96 13 = divide by 128 others =
\r
3743 #define DMIC_CHANNEL_DIVHFCLK_PDMDIV(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT)) & DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK)
\r
3746 /* The count of DMIC_CHANNEL_DIVHFCLK */
\r
3747 #define DMIC_CHANNEL_DIVHFCLK_COUNT (2U)
\r
3749 /*! @name CHANNEL_PREAC2FSCOEF - Pre-Emphasis Filter Coefficient for 2 FS register */
\r
3751 #define DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK (0x3U)
\r
3752 #define DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT (0U)
\r
3753 /*! COMP - Pre-emphasis filer coefficient for 2 FS mode. 0 = Compensation = 0 1 = Compensation = 16
\r
3754 * 2 = Compensation = 15 3 = Compensation = 13
\r
3756 #define DMIC_CHANNEL_PREAC2FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK)
\r
3759 /* The count of DMIC_CHANNEL_PREAC2FSCOEF */
\r
3760 #define DMIC_CHANNEL_PREAC2FSCOEF_COUNT (2U)
\r
3762 /*! @name CHANNEL_PREAC4FSCOEF - Pre-Emphasis Filter Coefficient for 4 FS register */
\r
3764 #define DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK (0x3U)
\r
3765 #define DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT (0U)
\r
3766 /*! COMP - Pre-emphasis filer coefficient for 4 FS mode. 0 = Compensation = 0 1 = Compensation = 16
\r
3767 * 2 = Compensation = 15 3 = Compensation = 13
\r
3769 #define DMIC_CHANNEL_PREAC4FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK)
\r
3772 /* The count of DMIC_CHANNEL_PREAC4FSCOEF */
\r
3773 #define DMIC_CHANNEL_PREAC4FSCOEF_COUNT (2U)
\r
3775 /*! @name CHANNEL_GAINSHIFT - Decimator Gain Shift register */
\r
3777 #define DMIC_CHANNEL_GAINSHIFT_GAIN_MASK (0x3FU)
\r
3778 #define DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT (0U)
\r
3779 /*! GAIN - Gain control, as a positive or negative (two's complement) number of bits to shift.
\r
3781 #define DMIC_CHANNEL_GAINSHIFT_GAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT)) & DMIC_CHANNEL_GAINSHIFT_GAIN_MASK)
\r
3784 /* The count of DMIC_CHANNEL_GAINSHIFT */
\r
3785 #define DMIC_CHANNEL_GAINSHIFT_COUNT (2U)
\r
3787 /*! @name CHANNEL_FIFO_CTRL - FIFO Control register 0 */
\r
3789 #define DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK (0x1U)
\r
3790 #define DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT (0U)
\r
3791 /*! ENABLE - FIFO enable.
\r
3792 * 0b0..FIFO is not enabled. Enabling a DMIC channel with the FIFO disabled could be useful while data is being
\r
3793 * streamed to the I2S, or in order to avoid a filter settling delay when a channel is re-enabled after a
\r
3794 * period when the data was not needed.
\r
3795 * 0b1..FIFO is enabled. The FIFO must be enabled in order for the CPU or DMA to read data from the DMIC via the FIFODATA register.
\r
3797 #define DMIC_CHANNEL_FIFO_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK)
\r
3798 #define DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK (0x2U)
\r
3799 #define DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT (1U)
\r
3800 /*! RESETN - FIFO reset.
\r
3801 * 0b0..Reset the FIFO.
\r
3802 * 0b1..Normal operation
\r
3804 #define DMIC_CHANNEL_FIFO_CTRL_RESETN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK)
\r
3805 #define DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK (0x4U)
\r
3806 #define DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT (2U)
\r
3807 /*! INTEN - Interrupt enable.
\r
3808 * 0b0..FIFO level interrupts are not enabled.
\r
3809 * 0b1..FIFO level interrupts are enabled.
\r
3811 #define DMIC_CHANNEL_FIFO_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK)
\r
3812 #define DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK (0x8U)
\r
3813 #define DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT (3U)
\r
3814 /*! DMAEN - DMA enable
\r
3815 * 0b0..DMA requests are not enabled.
\r
3816 * 0b1..DMA requests based on FIFO level are enabled.
\r
3818 #define DMIC_CHANNEL_FIFO_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK)
\r
3819 #define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK (0x1F0000U)
\r
3820 #define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT (16U)
\r
3821 /*! TRIGLVL - FIFO trigger level. Selects the data trigger level for interrupt or DMA operation. If
\r
3822 * enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then
\r
3823 * return to the reduced power mode See Section 4.5.66 'Hardware Wake-up control register'. 0 =
\r
3824 * trigger when the FIFO has received one entry (is no longer empty). 1 = trigger when the FIFO has
\r
3825 * received two entries. 15 = trigger when the FIFO has received 16 entries (has become full).
\r
3827 #define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK)
\r
3830 /* The count of DMIC_CHANNEL_FIFO_CTRL */
\r
3831 #define DMIC_CHANNEL_FIFO_CTRL_COUNT (2U)
\r
3833 /*! @name CHANNEL_FIFO_STATUS - FIFO Status register 0 */
\r
3835 #define DMIC_CHANNEL_FIFO_STATUS_INT_MASK (0x1U)
\r
3836 #define DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT (0U)
\r
3837 /*! INT - Interrupt flag. Asserted when FIFO data reaches the level specified in the FIFOCTRL
\r
3838 * register. Writing a one to this bit clears the flag. Remark: note that the bus clock to the DMIC
\r
3839 * subsystem must be running in order for an interrupt to occur.
\r
3841 #define DMIC_CHANNEL_FIFO_STATUS_INT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_INT_MASK)
\r
3842 #define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK (0x2U)
\r
3843 #define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT (1U)
\r
3844 /*! OVERRUN - Overrun flag. Indicates that a FIFO overflow has occurred at some point. Writing a one
\r
3845 * to this bit clears the flag. This flag does not cause an interrupt.
\r
3847 #define DMIC_CHANNEL_FIFO_STATUS_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK)
\r
3848 #define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK (0x4U)
\r
3849 #define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT (2U)
\r
3850 /*! UNDERRUN - Underrun flag. Indicates that a FIFO underflow has occurred at some point. Writing a one to this bit clears the flag.
\r
3852 #define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK)
\r
3855 /* The count of DMIC_CHANNEL_FIFO_STATUS */
\r
3856 #define DMIC_CHANNEL_FIFO_STATUS_COUNT (2U)
\r
3858 /*! @name CHANNEL_FIFO_DATA - FIFO Data Register 0 */
\r
3860 #define DMIC_CHANNEL_FIFO_DATA_DATA_MASK (0xFFFFFFU)
\r
3861 #define DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT (0U)
\r
3862 /*! DATA - Data from the top of the input filter FIFO.
\r
3864 #define DMIC_CHANNEL_FIFO_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT)) & DMIC_CHANNEL_FIFO_DATA_DATA_MASK)
\r
3867 /* The count of DMIC_CHANNEL_FIFO_DATA */
\r
3868 #define DMIC_CHANNEL_FIFO_DATA_COUNT (2U)
\r
3870 /*! @name CHANNEL_PHY_CTRL - PDM Source Configuration register 0 */
\r
3872 #define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK (0x1U)
\r
3873 #define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT (0U)
\r
3874 /*! PHY_FALL - Capture PDM_DATA
\r
3875 * 0b0..Capture PDM_DATA on the rising edge of PDM_CLK.
\r
3876 * 0b1..Capture PDM_DATA on the falling edge of PDM_CLK.
\r
3878 #define DMIC_CHANNEL_PHY_CTRL_PHY_FALL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK)
\r
3879 #define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK (0x2U)
\r
3880 #define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT (1U)
\r
3881 /*! PHY_HALF - Half rate sampling
\r
3882 * 0b0..Standard half rate sampling. The clock to the DMIC is sent at the same rate as the decimator is providing.
\r
3883 * 0b1..Use half rate sampling. The clock to the DMIC is sent at half the rate as the decimator is providing.
\r
3885 #define DMIC_CHANNEL_PHY_CTRL_PHY_HALF(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK)
\r
3888 /* The count of DMIC_CHANNEL_PHY_CTRL */
\r
3889 #define DMIC_CHANNEL_PHY_CTRL_COUNT (2U)
\r
3891 /*! @name CHANNEL_DC_CTRL - DC Control register 0 */
\r
3893 #define DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK (0x3U)
\r
3894 #define DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT (0U)
\r
3895 /*! DCPOLE - DC block filter
\r
3896 * 0b00..Flat response, no filter.
\r
3901 #define DMIC_CHANNEL_DC_CTRL_DCPOLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK)
\r
3902 #define DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK (0xF0U)
\r
3903 #define DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT (4U)
\r
3904 /*! DCGAIN - Fine gain adjustment in the form of a number of bits to downshift.
\r
3906 #define DMIC_CHANNEL_DC_CTRL_DCGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK)
\r
3907 #define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK (0x100U)
\r
3908 #define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT (8U)
\r
3909 /*! SATURATEAT16BIT - Selects 16-bit saturation.
\r
3910 * 0b0..Results roll over if out range and do not saturate.
\r
3911 * 0b1..If the result overflows, it saturates at 0xFFFF for positive overflow and 0x8000 for negative overflow.
\r
3913 #define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT)) & DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK)
\r
3916 /* The count of DMIC_CHANNEL_DC_CTRL */
\r
3917 #define DMIC_CHANNEL_DC_CTRL_COUNT (2U)
\r
3919 /*! @name CHANEN - Channel Enable register */
\r
3921 #define DMIC_CHANEN_EN_CH0_MASK (0x1U)
\r
3922 #define DMIC_CHANEN_EN_CH0_SHIFT (0U)
\r
3923 /*! EN_CH0 - Enable channel 0. When 1, PDM channel 0 is enabled.
\r
3925 #define DMIC_CHANEN_EN_CH0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH0_SHIFT)) & DMIC_CHANEN_EN_CH0_MASK)
\r
3926 #define DMIC_CHANEN_EN_CH1_MASK (0x2U)
\r
3927 #define DMIC_CHANEN_EN_CH1_SHIFT (1U)
\r
3928 /*! EN_CH1 - Enable channel 1. When 1, PDM channel 1 is enabled.
\r
3930 #define DMIC_CHANEN_EN_CH1(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH1_SHIFT)) & DMIC_CHANEN_EN_CH1_MASK)
\r
3933 /*! @name IOCFG - I/O Configuration register */
\r
3935 #define DMIC_IOCFG_CLK_BYPASS0_MASK (0x1U)
\r
3936 #define DMIC_IOCFG_CLK_BYPASS0_SHIFT (0U)
\r
3937 /*! CLK_BYPASS0 - Bypass CLK0. When 1, PDM_DATA1 becomes the clock for PDM channel 0. This provides
\r
3938 * for the possibility of an external codec taking over the PDM bus.
\r
3940 #define DMIC_IOCFG_CLK_BYPASS0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS0_SHIFT)) & DMIC_IOCFG_CLK_BYPASS0_MASK)
\r
3941 #define DMIC_IOCFG_CLK_BYPASS1_MASK (0x2U)
\r
3942 #define DMIC_IOCFG_CLK_BYPASS1_SHIFT (1U)
\r
3943 /*! CLK_BYPASS1 - Bypass CLK1. When 1, PDM_DATA1 becomes the clock for PDM channel 1. This provides
\r
3944 * for the possibility of an external codec taking over the PDM bus.
\r
3946 #define DMIC_IOCFG_CLK_BYPASS1(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS1_SHIFT)) & DMIC_IOCFG_CLK_BYPASS1_MASK)
\r
3947 #define DMIC_IOCFG_STEREO_DATA0_MASK (0x4U)
\r
3948 #define DMIC_IOCFG_STEREO_DATA0_SHIFT (2U)
\r
3949 /*! STEREO_DATA0 - Stereo PDM select. When 1, PDM_DATA0 is routed to both PDM channels in a
\r
3950 * configuration that supports a single stereo digital microphone.
\r
3952 #define DMIC_IOCFG_STEREO_DATA0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_STEREO_DATA0_SHIFT)) & DMIC_IOCFG_STEREO_DATA0_MASK)
\r
3955 /*! @name USE2FS - Use 2FS register */
\r
3957 #define DMIC_USE2FS_USE2FS_MASK (0x1U)
\r
3958 #define DMIC_USE2FS_USE2FS_SHIFT (0U)
\r
3959 /*! USE2FS - Use 2FS register
\r
3960 * 0b0..Use 1FS output for PCM data.
\r
3961 * 0b1..Use 2FS output for PCM data.
\r
3963 #define DMIC_USE2FS_USE2FS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_USE2FS_USE2FS_SHIFT)) & DMIC_USE2FS_USE2FS_MASK)
\r
3966 /*! @name HWVADGAIN - HWVAD input gain register */
\r
3968 #define DMIC_HWVADGAIN_INPUTGAIN_MASK (0xFU)
\r
3969 #define DMIC_HWVADGAIN_INPUTGAIN_SHIFT (0U)
\r
3970 /*! INPUTGAIN - Shift value for input bits 0x00 -10 bits 0x01 -8 bits 0x02 -6 bits 0x03 -4 bits 0x04
\r
3971 * -2 bits 0x05 0 bits (default) 0x06 +2 bits 0x07 +4 bits 0x08 +6 bits 0x09 +8 bits 0x0A +10
\r
3972 * bits 0x0B +12 bits 0x0C +14 bits 0x0D to 0x0F Reserved.
\r
3974 #define DMIC_HWVADGAIN_INPUTGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADGAIN_INPUTGAIN_SHIFT)) & DMIC_HWVADGAIN_INPUTGAIN_MASK)
\r
3977 /*! @name HWVADHPFS - HWVAD filter control register */
\r
3979 #define DMIC_HWVADHPFS_HPFS_MASK (0x3U)
\r
3980 #define DMIC_HWVADHPFS_HPFS_SHIFT (0U)
\r
3981 /*! HPFS - High pass filter
\r
3982 * 0b00..First filter by-pass.
\r
3983 * 0b01..High pass filter with -3dB cut-off at 1750Hz.
\r
3984 * 0b10..High pass filter with -3dB cut-off at 215Hz.
\r
3987 #define DMIC_HWVADHPFS_HPFS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADHPFS_HPFS_SHIFT)) & DMIC_HWVADHPFS_HPFS_MASK)
\r
3990 /*! @name HWVADST10 - HWVAD control register */
\r
3992 #define DMIC_HWVADST10_ST10_MASK (0x1U)
\r
3993 #define DMIC_HWVADST10_ST10_SHIFT (0U)
\r
3994 /*! ST10 - Stage 0
\r
3995 * 0b0..Normal operation, waiting for HWVAD trigger event (stage 0).
\r
3996 * 0b1..Reset internal interrupt flag by writing a '1' pulse.
\r
3998 #define DMIC_HWVADST10_ST10(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADST10_ST10_SHIFT)) & DMIC_HWVADST10_ST10_MASK)
\r
4001 /*! @name HWVADRSTT - HWVAD filter reset register */
\r
4003 #define DMIC_HWVADRSTT_RSTT_MASK (0x1U)
\r
4004 #define DMIC_HWVADRSTT_RSTT_SHIFT (0U)
\r
4005 /*! RSTT - Writing a 1 resets all filter values
\r
4007 #define DMIC_HWVADRSTT_RSTT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADRSTT_RSTT_SHIFT)) & DMIC_HWVADRSTT_RSTT_MASK)
\r
4010 /*! @name HWVADTHGN - HWVAD noise estimator gain register */
\r
4012 #define DMIC_HWVADTHGN_THGN_MASK (0xFU)
\r
4013 #define DMIC_HWVADTHGN_THGN_SHIFT (0U)
\r
4014 /*! THGN - Gain value for the noise estimator. Values 0 to 14. 0 corresponds to a gain of 1.
\r
4016 #define DMIC_HWVADTHGN_THGN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGN_THGN_SHIFT)) & DMIC_HWVADTHGN_THGN_MASK)
\r
4019 /*! @name HWVADTHGS - HWVAD signal estimator gain register */
\r
4021 #define DMIC_HWVADTHGS_THGS_MASK (0xFU)
\r
4022 #define DMIC_HWVADTHGS_THGS_SHIFT (0U)
\r
4023 /*! THGS - Gain value for the signal estimator. Values 0 to 14. 0 corresponds to a gain of 1.
\r
4025 #define DMIC_HWVADTHGS_THGS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGS_THGS_SHIFT)) & DMIC_HWVADTHGS_THGS_MASK)
\r
4028 /*! @name HWVADLOWZ - HWVAD noise envelope estimator register */
\r
4030 #define DMIC_HWVADLOWZ_LOWZ_MASK (0xFFFFU)
\r
4031 #define DMIC_HWVADLOWZ_LOWZ_SHIFT (0U)
\r
4032 /*! LOWZ - Noise envelope estimator value.
\r
4034 #define DMIC_HWVADLOWZ_LOWZ(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADLOWZ_LOWZ_SHIFT)) & DMIC_HWVADLOWZ_LOWZ_MASK)
\r
4037 /*! @name ID - Module Identification register */
\r
4039 #define DMIC_ID_ID_MASK (0xFFFFFFFFU)
\r
4040 #define DMIC_ID_ID_SHIFT (0U)
\r
4041 /*! ID - Indicates module ID and the number of channels in this DMIC interface.
\r
4043 #define DMIC_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DMIC_ID_ID_SHIFT)) & DMIC_ID_ID_MASK)
\r
4049 */ /* end of group DMIC_Register_Masks */
\r
4052 /* DMIC - Peripheral instance base addresses */
\r
4053 /** Peripheral DMIC0 base address */
\r
4054 #define DMIC0_BASE (0x40090000u)
\r
4055 /** Peripheral DMIC0 base pointer */
\r
4056 #define DMIC0 ((DMIC_Type *)DMIC0_BASE)
\r
4057 /** Array initializer of DMIC peripheral base addresses */
\r
4058 #define DMIC_BASE_ADDRS { DMIC0_BASE }
\r
4059 /** Array initializer of DMIC peripheral base pointers */
\r
4060 #define DMIC_BASE_PTRS { DMIC0 }
\r
4061 /** Interrupt vectors for the DMIC peripheral type */
\r
4062 #define DMIC_IRQS { DMIC0_IRQn }
\r
4063 #define DMIC_HWVAD_IRQS { HWVAD0_IRQn }
\r
4067 */ /* end of group DMIC_Peripheral_Access_Layer */
\r
4070 /* ----------------------------------------------------------------------------
\r
4071 -- EMC Peripheral Access Layer
\r
4072 ---------------------------------------------------------------------------- */
\r
4075 * @addtogroup EMC_Peripheral_Access_Layer EMC Peripheral Access Layer
\r
4079 /** EMC - Register Layout Typedef */
\r
4081 __IO uint32_t CONTROL; /**< Controls operation of the memory controller, offset: 0x0 */
\r
4082 __I uint32_t STATUS; /**< Provides EMC status information, offset: 0x4 */
\r
4083 __IO uint32_t CONFIG; /**< Configures operation of the memory controller, offset: 0x8 */
\r
4084 uint8_t RESERVED_0[20];
\r
4085 __IO uint32_t DYNAMICCONTROL; /**< Controls dynamic memory operation, offset: 0x20 */
\r
4086 __IO uint32_t DYNAMICREFRESH; /**< Configures dynamic memory refresh, offset: 0x24 */
\r
4087 __IO uint32_t DYNAMICREADCONFIG; /**< Configures dynamic memory read strategy, offset: 0x28 */
\r
4088 uint8_t RESERVED_1[4];
\r
4089 __IO uint32_t DYNAMICRP; /**< Precharge command period, offset: 0x30 */
\r
4090 __IO uint32_t DYNAMICRAS; /**< Active to precharge command period, offset: 0x34 */
\r
4091 __IO uint32_t DYNAMICSREX; /**< Self-refresh exit time, offset: 0x38 */
\r
4092 __IO uint32_t DYNAMICAPR; /**< Last-data-out to active command time, offset: 0x3C */
\r
4093 __IO uint32_t DYNAMICDAL; /**< Data-in to active command time, offset: 0x40 */
\r
4094 __IO uint32_t DYNAMICWR; /**< Write recovery time, offset: 0x44 */
\r
4095 __IO uint32_t DYNAMICRC; /**< Selects the active to active command period, offset: 0x48 */
\r
4096 __IO uint32_t DYNAMICRFC; /**< Selects the auto-refresh period, offset: 0x4C */
\r
4097 __IO uint32_t DYNAMICXSR; /**< Time for exit self-refresh to active command, offset: 0x50 */
\r
4098 __IO uint32_t DYNAMICRRD; /**< Latency for active bank A to active bank B, offset: 0x54 */
\r
4099 __IO uint32_t DYNAMICMRD; /**< Time for load mode register to active command, offset: 0x58 */
\r
4100 uint8_t RESERVED_2[36];
\r
4101 __IO uint32_t STATICEXTENDEDWAIT; /**< Time for long static memory read and write transfers, offset: 0x80 */
\r
4102 uint8_t RESERVED_3[124];
\r
4103 struct { /* offset: 0x100, array step: 0x20 */
\r
4104 __IO uint32_t DYNAMICCONFIG; /**< Configuration information for EMC_DYCSx, array offset: 0x100, array step: 0x20 */
\r
4105 __IO uint32_t DYNAMICRASCAS; /**< RAS and CAS latencies for EMC_DYCSx, array offset: 0x104, array step: 0x20 */
\r
4106 uint8_t RESERVED_0[24];
\r
4108 uint8_t RESERVED_4[128];
\r
4109 struct { /* offset: 0x200, array step: 0x20 */
\r
4110 __IO uint32_t STATICCONFIG; /**< Configuration for EMC_CSx, array offset: 0x200, array step: 0x20 */
\r
4111 __IO uint32_t STATICWAITWEN; /**< Delay from EMC_CSx to write enable, array offset: 0x204, array step: 0x20 */
\r
4112 __IO uint32_t STATICWAITOEN; /**< Delay from EMC_CSx or address change, whichever is later, to output enable, array offset: 0x208, array step: 0x20 */
\r
4113 __IO uint32_t STATICWAITRD; /**< Delay from EMC_CSx to a read access, array offset: 0x20C, array step: 0x20 */
\r
4114 __IO uint32_t STATICWAITPAGE; /**< Delay for asynchronous page mode sequential accesses for EMC_CSx, array offset: 0x210, array step: 0x20 */
\r
4115 __IO uint32_t STATICWAITWR; /**< Delay from EMC_CSx to a write access, array offset: 0x214, array step: 0x20 */
\r
4116 __IO uint32_t STATICWAITTURN; /**< Number of bus turnaround cycles EMC_CSx, array offset: 0x218, array step: 0x20 */
\r
4117 uint8_t RESERVED_0[4];
\r
4121 /* ----------------------------------------------------------------------------
\r
4122 -- EMC Register Masks
\r
4123 ---------------------------------------------------------------------------- */
\r
4126 * @addtogroup EMC_Register_Masks EMC Register Masks
\r
4130 /*! @name CONTROL - Controls operation of the memory controller */
\r
4132 #define EMC_CONTROL_E_MASK (0x1U)
\r
4133 #define EMC_CONTROL_E_SHIFT (0U)
\r
4134 /*! E - EMC Enable.
\r
4136 #define EMC_CONTROL_E(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_E_SHIFT)) & EMC_CONTROL_E_MASK)
\r
4137 #define EMC_CONTROL_M_MASK (0x2U)
\r
4138 #define EMC_CONTROL_M_SHIFT (1U)
\r
4139 /*! M - Address mirror.
\r
4141 #define EMC_CONTROL_M(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_M_SHIFT)) & EMC_CONTROL_M_MASK)
\r
4142 #define EMC_CONTROL_L_MASK (0x4U)
\r
4143 #define EMC_CONTROL_L_SHIFT (2U)
\r
4144 /*! L - Low-power mode.
\r
4146 #define EMC_CONTROL_L(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_L_SHIFT)) & EMC_CONTROL_L_MASK)
\r
4149 /*! @name STATUS - Provides EMC status information */
\r
4151 #define EMC_STATUS_B_MASK (0x1U)
\r
4152 #define EMC_STATUS_B_SHIFT (0U)
\r
4155 #define EMC_STATUS_B(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_B_SHIFT)) & EMC_STATUS_B_MASK)
\r
4156 #define EMC_STATUS_S_MASK (0x2U)
\r
4157 #define EMC_STATUS_S_SHIFT (1U)
\r
4158 /*! S - Write buffer status.
\r
4160 #define EMC_STATUS_S(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_S_SHIFT)) & EMC_STATUS_S_MASK)
\r
4161 #define EMC_STATUS_SA_MASK (0x4U)
\r
4162 #define EMC_STATUS_SA_SHIFT (2U)
\r
4163 /*! SA - Self-refresh acknowledge.
\r
4165 #define EMC_STATUS_SA(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_SA_SHIFT)) & EMC_STATUS_SA_MASK)
\r
4168 /*! @name CONFIG - Configures operation of the memory controller */
\r
4170 #define EMC_CONFIG_EM_MASK (0x1U)
\r
4171 #define EMC_CONFIG_EM_SHIFT (0U)
\r
4172 /*! EM - Endian mode.
\r
4174 #define EMC_CONFIG_EM(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONFIG_EM_SHIFT)) & EMC_CONFIG_EM_MASK)
\r
4175 #define EMC_CONFIG_CLKR_MASK (0x100U)
\r
4176 #define EMC_CONFIG_CLKR_SHIFT (8U)
\r
4177 /*! CLKR - This bit must contain 0 for proper operation of the EMC.
\r
4179 #define EMC_CONFIG_CLKR(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONFIG_CLKR_SHIFT)) & EMC_CONFIG_CLKR_MASK)
\r
4182 /*! @name DYNAMICCONTROL - Controls dynamic memory operation */
\r
4184 #define EMC_DYNAMICCONTROL_CE_MASK (0x1U)
\r
4185 #define EMC_DYNAMICCONTROL_CE_SHIFT (0U)
\r
4186 /*! CE - Dynamic memory clock enable.
\r
4188 #define EMC_DYNAMICCONTROL_CE(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_CE_SHIFT)) & EMC_DYNAMICCONTROL_CE_MASK)
\r
4189 #define EMC_DYNAMICCONTROL_CS_MASK (0x2U)
\r
4190 #define EMC_DYNAMICCONTROL_CS_SHIFT (1U)
\r
4191 /*! CS - Dynamic memory clock control.
\r
4193 #define EMC_DYNAMICCONTROL_CS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_CS_SHIFT)) & EMC_DYNAMICCONTROL_CS_MASK)
\r
4194 #define EMC_DYNAMICCONTROL_SR_MASK (0x4U)
\r
4195 #define EMC_DYNAMICCONTROL_SR_SHIFT (2U)
\r
4196 /*! SR - Self-refresh request, EMCSREFREQ.
\r
4198 #define EMC_DYNAMICCONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_SR_SHIFT)) & EMC_DYNAMICCONTROL_SR_MASK)
\r
4199 #define EMC_DYNAMICCONTROL_MMC_MASK (0x20U)
\r
4200 #define EMC_DYNAMICCONTROL_MMC_SHIFT (5U)
\r
4201 /*! MMC - Memory clock control.
\r
4203 #define EMC_DYNAMICCONTROL_MMC(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_MMC_SHIFT)) & EMC_DYNAMICCONTROL_MMC_MASK)
\r
4204 #define EMC_DYNAMICCONTROL_I_MASK (0x180U)
\r
4205 #define EMC_DYNAMICCONTROL_I_SHIFT (7U)
\r
4206 /*! I - SDRAM initialization.
\r
4208 #define EMC_DYNAMICCONTROL_I(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_I_SHIFT)) & EMC_DYNAMICCONTROL_I_MASK)
\r
4211 /*! @name DYNAMICREFRESH - Configures dynamic memory refresh */
\r
4213 #define EMC_DYNAMICREFRESH_REFRESH_MASK (0x7FFU)
\r
4214 #define EMC_DYNAMICREFRESH_REFRESH_SHIFT (0U)
\r
4215 /*! REFRESH - Refresh timer.
\r
4217 #define EMC_DYNAMICREFRESH_REFRESH(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICREFRESH_REFRESH_SHIFT)) & EMC_DYNAMICREFRESH_REFRESH_MASK)
\r
4220 /*! @name DYNAMICREADCONFIG - Configures dynamic memory read strategy */
\r
4222 #define EMC_DYNAMICREADCONFIG_RD_MASK (0x3U)
\r
4223 #define EMC_DYNAMICREADCONFIG_RD_SHIFT (0U)
\r
4224 /*! RD - Read data strategy.
\r
4226 #define EMC_DYNAMICREADCONFIG_RD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICREADCONFIG_RD_SHIFT)) & EMC_DYNAMICREADCONFIG_RD_MASK)
\r
4229 /*! @name DYNAMICRP - Precharge command period */
\r
4231 #define EMC_DYNAMICRP_TRP_MASK (0xFU)
\r
4232 #define EMC_DYNAMICRP_TRP_SHIFT (0U)
\r
4233 /*! TRP - Precharge command period.
\r
4235 #define EMC_DYNAMICRP_TRP(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRP_TRP_SHIFT)) & EMC_DYNAMICRP_TRP_MASK)
\r
4238 /*! @name DYNAMICRAS - Active to precharge command period */
\r
4240 #define EMC_DYNAMICRAS_TRAS_MASK (0xFU)
\r
4241 #define EMC_DYNAMICRAS_TRAS_SHIFT (0U)
\r
4242 /*! TRAS - Active to precharge command period.
\r
4244 #define EMC_DYNAMICRAS_TRAS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRAS_TRAS_SHIFT)) & EMC_DYNAMICRAS_TRAS_MASK)
\r
4247 /*! @name DYNAMICSREX - Self-refresh exit time */
\r
4249 #define EMC_DYNAMICSREX_TSREX_MASK (0xFU)
\r
4250 #define EMC_DYNAMICSREX_TSREX_SHIFT (0U)
\r
4251 /*! TSREX - Self-refresh exit time.
\r
4253 #define EMC_DYNAMICSREX_TSREX(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICSREX_TSREX_SHIFT)) & EMC_DYNAMICSREX_TSREX_MASK)
\r
4256 /*! @name DYNAMICAPR - Last-data-out to active command time */
\r
4258 #define EMC_DYNAMICAPR_TAPR_MASK (0xFU)
\r
4259 #define EMC_DYNAMICAPR_TAPR_SHIFT (0U)
\r
4260 /*! TAPR - Last-data-out to active command time.
\r
4262 #define EMC_DYNAMICAPR_TAPR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICAPR_TAPR_SHIFT)) & EMC_DYNAMICAPR_TAPR_MASK)
\r
4265 /*! @name DYNAMICDAL - Data-in to active command time */
\r
4267 #define EMC_DYNAMICDAL_TDAL_MASK (0xFU)
\r
4268 #define EMC_DYNAMICDAL_TDAL_SHIFT (0U)
\r
4269 /*! TDAL - Data-in to active command.
\r
4271 #define EMC_DYNAMICDAL_TDAL(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICDAL_TDAL_SHIFT)) & EMC_DYNAMICDAL_TDAL_MASK)
\r
4274 /*! @name DYNAMICWR - Write recovery time */
\r
4276 #define EMC_DYNAMICWR_TWR_MASK (0xFU)
\r
4277 #define EMC_DYNAMICWR_TWR_SHIFT (0U)
\r
4278 /*! TWR - Write recovery time.
\r
4280 #define EMC_DYNAMICWR_TWR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICWR_TWR_SHIFT)) & EMC_DYNAMICWR_TWR_MASK)
\r
4283 /*! @name DYNAMICRC - Selects the active to active command period */
\r
4285 #define EMC_DYNAMICRC_TRC_MASK (0x1FU)
\r
4286 #define EMC_DYNAMICRC_TRC_SHIFT (0U)
\r
4287 /*! TRC - Active to active command period.
\r
4289 #define EMC_DYNAMICRC_TRC(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRC_TRC_SHIFT)) & EMC_DYNAMICRC_TRC_MASK)
\r
4292 /*! @name DYNAMICRFC - Selects the auto-refresh period */
\r
4294 #define EMC_DYNAMICRFC_TRFC_MASK (0x1FU)
\r
4295 #define EMC_DYNAMICRFC_TRFC_SHIFT (0U)
\r
4296 /*! TRFC - Auto-refresh period and auto-refresh to active command period.
\r
4298 #define EMC_DYNAMICRFC_TRFC(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRFC_TRFC_SHIFT)) & EMC_DYNAMICRFC_TRFC_MASK)
\r
4301 /*! @name DYNAMICXSR - Time for exit self-refresh to active command */
\r
4303 #define EMC_DYNAMICXSR_TXSR_MASK (0x1FU)
\r
4304 #define EMC_DYNAMICXSR_TXSR_SHIFT (0U)
\r
4305 /*! TXSR - Exit self-refresh to active command time.
\r
4307 #define EMC_DYNAMICXSR_TXSR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICXSR_TXSR_SHIFT)) & EMC_DYNAMICXSR_TXSR_MASK)
\r
4310 /*! @name DYNAMICRRD - Latency for active bank A to active bank B */
\r
4312 #define EMC_DYNAMICRRD_TRRD_MASK (0xFU)
\r
4313 #define EMC_DYNAMICRRD_TRRD_SHIFT (0U)
\r
4314 /*! TRRD - Active bank A to active bank B latency 0x0 - 0xE = n + 1 clock cycles.
\r
4316 #define EMC_DYNAMICRRD_TRRD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRRD_TRRD_SHIFT)) & EMC_DYNAMICRRD_TRRD_MASK)
\r
4319 /*! @name DYNAMICMRD - Time for load mode register to active command */
\r
4321 #define EMC_DYNAMICMRD_TMRD_MASK (0xFU)
\r
4322 #define EMC_DYNAMICMRD_TMRD_SHIFT (0U)
\r
4323 /*! TMRD - Load mode register to active command time.
\r
4325 #define EMC_DYNAMICMRD_TMRD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICMRD_TMRD_SHIFT)) & EMC_DYNAMICMRD_TMRD_MASK)
\r
4328 /*! @name STATICEXTENDEDWAIT - Time for long static memory read and write transfers */
\r
4330 #define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_MASK (0x3FFU)
\r
4331 #define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_SHIFT (0U)
\r
4332 /*! EXTENDEDWAIT - Extended wait time out.
\r
4334 #define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_SHIFT)) & EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_MASK)
\r
4337 /*! @name DYNAMIC_DYNAMICCONFIG - Configuration information for EMC_DYCSx */
\r
4339 #define EMC_DYNAMIC_DYNAMICCONFIG_MD_MASK (0x18U)
\r
4340 #define EMC_DYNAMIC_DYNAMICCONFIG_MD_SHIFT (3U)
\r
4341 /*! MD - Memory device.
\r
4343 #define EMC_DYNAMIC_DYNAMICCONFIG_MD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_MD_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_MD_MASK)
\r
4344 #define EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK (0x1F80U)
\r
4345 #define EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT (7U)
\r
4346 /*! AM0 - See Table 933.
\r
4348 #define EMC_DYNAMIC_DYNAMICCONFIG_AM0(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK)
\r
4349 #define EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK (0x4000U)
\r
4350 #define EMC_DYNAMIC_DYNAMICCONFIG_AM1_SHIFT (14U)
\r
4351 /*! AM1 - See Table 933.
\r
4353 #define EMC_DYNAMIC_DYNAMICCONFIG_AM1(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_AM1_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK)
\r
4354 #define EMC_DYNAMIC_DYNAMICCONFIG_B_MASK (0x80000U)
\r
4355 #define EMC_DYNAMIC_DYNAMICCONFIG_B_SHIFT (19U)
\r
4356 /*! B - Buffer enable.
\r
4358 #define EMC_DYNAMIC_DYNAMICCONFIG_B(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_B_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_B_MASK)
\r
4359 #define EMC_DYNAMIC_DYNAMICCONFIG_P_MASK (0x100000U)
\r
4360 #define EMC_DYNAMIC_DYNAMICCONFIG_P_SHIFT (20U)
\r
4361 /*! P - Write protect.
\r
4363 #define EMC_DYNAMIC_DYNAMICCONFIG_P(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_P_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_P_MASK)
\r
4366 /* The count of EMC_DYNAMIC_DYNAMICCONFIG */
\r
4367 #define EMC_DYNAMIC_DYNAMICCONFIG_COUNT (4U)
\r
4369 /*! @name DYNAMIC_DYNAMICRASCAS - RAS and CAS latencies for EMC_DYCSx */
\r
4371 #define EMC_DYNAMIC_DYNAMICRASCAS_RAS_MASK (0x3U)
\r
4372 #define EMC_DYNAMIC_DYNAMICRASCAS_RAS_SHIFT (0U)
\r
4373 /*! RAS - RAS latency (active to read/write delay).
\r
4375 #define EMC_DYNAMIC_DYNAMICRASCAS_RAS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICRASCAS_RAS_SHIFT)) & EMC_DYNAMIC_DYNAMICRASCAS_RAS_MASK)
\r
4376 #define EMC_DYNAMIC_DYNAMICRASCAS_CAS_MASK (0x300U)
\r
4377 #define EMC_DYNAMIC_DYNAMICRASCAS_CAS_SHIFT (8U)
\r
4378 /*! CAS - CAS latency.
\r
4380 #define EMC_DYNAMIC_DYNAMICRASCAS_CAS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICRASCAS_CAS_SHIFT)) & EMC_DYNAMIC_DYNAMICRASCAS_CAS_MASK)
\r
4383 /* The count of EMC_DYNAMIC_DYNAMICRASCAS */
\r
4384 #define EMC_DYNAMIC_DYNAMICRASCAS_COUNT (4U)
\r
4386 /*! @name STATIC_STATICCONFIG - Configuration for EMC_CSx */
\r
4388 #define EMC_STATIC_STATICCONFIG_MW_MASK (0x3U)
\r
4389 #define EMC_STATIC_STATICCONFIG_MW_SHIFT (0U)
\r
4390 /*! MW - Memory width.
\r
4392 #define EMC_STATIC_STATICCONFIG_MW(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_MW_SHIFT)) & EMC_STATIC_STATICCONFIG_MW_MASK)
\r
4393 #define EMC_STATIC_STATICCONFIG_PM_MASK (0x8U)
\r
4394 #define EMC_STATIC_STATICCONFIG_PM_SHIFT (3U)
\r
4395 /*! PM - Page mode.
\r
4397 #define EMC_STATIC_STATICCONFIG_PM(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PM_SHIFT)) & EMC_STATIC_STATICCONFIG_PM_MASK)
\r
4398 #define EMC_STATIC_STATICCONFIG_PC_MASK (0x40U)
\r
4399 #define EMC_STATIC_STATICCONFIG_PC_SHIFT (6U)
\r
4400 /*! PC - Chip select polarity.
\r
4402 #define EMC_STATIC_STATICCONFIG_PC(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PC_SHIFT)) & EMC_STATIC_STATICCONFIG_PC_MASK)
\r
4403 #define EMC_STATIC_STATICCONFIG_PB_MASK (0x80U)
\r
4404 #define EMC_STATIC_STATICCONFIG_PB_SHIFT (7U)
\r
4405 /*! PB - Byte lane state.
\r
4407 #define EMC_STATIC_STATICCONFIG_PB(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PB_SHIFT)) & EMC_STATIC_STATICCONFIG_PB_MASK)
\r
4408 #define EMC_STATIC_STATICCONFIG_EW_MASK (0x100U)
\r
4409 #define EMC_STATIC_STATICCONFIG_EW_SHIFT (8U)
\r
4410 /*! EW - Extended wait (EW) uses the EMCStaticExtendedWait register to time both the read and write
\r
4411 * transfers rather than the EMCStaticWaitRd and EMCStaticWaitWr registers.
\r
4413 #define EMC_STATIC_STATICCONFIG_EW(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_EW_SHIFT)) & EMC_STATIC_STATICCONFIG_EW_MASK)
\r
4414 #define EMC_STATIC_STATICCONFIG_B_MASK (0x80000U)
\r
4415 #define EMC_STATIC_STATICCONFIG_B_SHIFT (19U)
\r
4416 /*! B - Buffer enable [2].
\r
4418 #define EMC_STATIC_STATICCONFIG_B(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_B_SHIFT)) & EMC_STATIC_STATICCONFIG_B_MASK)
\r
4419 #define EMC_STATIC_STATICCONFIG_P_MASK (0x100000U)
\r
4420 #define EMC_STATIC_STATICCONFIG_P_SHIFT (20U)
\r
4421 /*! P - Write protect.
\r
4423 #define EMC_STATIC_STATICCONFIG_P(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_P_SHIFT)) & EMC_STATIC_STATICCONFIG_P_MASK)
\r
4426 /* The count of EMC_STATIC_STATICCONFIG */
\r
4427 #define EMC_STATIC_STATICCONFIG_COUNT (4U)
\r
4429 /*! @name STATIC_STATICWAITWEN - Delay from EMC_CSx to write enable */
\r
4431 #define EMC_STATIC_STATICWAITWEN_WAITWEN_MASK (0xFU)
\r
4432 #define EMC_STATIC_STATICWAITWEN_WAITWEN_SHIFT (0U)
\r
4433 /*! WAITWEN - Wait write enable.
\r
4435 #define EMC_STATIC_STATICWAITWEN_WAITWEN(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITWEN_WAITWEN_SHIFT)) & EMC_STATIC_STATICWAITWEN_WAITWEN_MASK)
\r
4438 /* The count of EMC_STATIC_STATICWAITWEN */
\r
4439 #define EMC_STATIC_STATICWAITWEN_COUNT (4U)
\r
4441 /*! @name STATIC_STATICWAITOEN - Delay from EMC_CSx or address change, whichever is later, to output enable */
\r
4443 #define EMC_STATIC_STATICWAITOEN_WAITOEN_MASK (0xFU)
\r
4444 #define EMC_STATIC_STATICWAITOEN_WAITOEN_SHIFT (0U)
\r
4445 /*! WAITOEN - Wait output enable.
\r
4447 #define EMC_STATIC_STATICWAITOEN_WAITOEN(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITOEN_WAITOEN_SHIFT)) & EMC_STATIC_STATICWAITOEN_WAITOEN_MASK)
\r
4450 /* The count of EMC_STATIC_STATICWAITOEN */
\r
4451 #define EMC_STATIC_STATICWAITOEN_COUNT (4U)
\r
4453 /*! @name STATIC_STATICWAITRD - Delay from EMC_CSx to a read access */
\r
4455 #define EMC_STATIC_STATICWAITRD_WAITRD_MASK (0x1FU)
\r
4456 #define EMC_STATIC_STATICWAITRD_WAITRD_SHIFT (0U)
\r
4459 #define EMC_STATIC_STATICWAITRD_WAITRD(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITRD_WAITRD_SHIFT)) & EMC_STATIC_STATICWAITRD_WAITRD_MASK)
\r
4462 /* The count of EMC_STATIC_STATICWAITRD */
\r
4463 #define EMC_STATIC_STATICWAITRD_COUNT (4U)
\r
4465 /*! @name STATIC_STATICWAITPAGE - Delay for asynchronous page mode sequential accesses for EMC_CSx */
\r
4467 #define EMC_STATIC_STATICWAITPAGE_WAITPAGE_MASK (0x1FU)
\r
4468 #define EMC_STATIC_STATICWAITPAGE_WAITPAGE_SHIFT (0U)
\r
4469 /*! WAITPAGE - Asynchronous page mode read after the first read wait states.
\r
4471 #define EMC_STATIC_STATICWAITPAGE_WAITPAGE(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITPAGE_WAITPAGE_SHIFT)) & EMC_STATIC_STATICWAITPAGE_WAITPAGE_MASK)
\r
4474 /* The count of EMC_STATIC_STATICWAITPAGE */
\r
4475 #define EMC_STATIC_STATICWAITPAGE_COUNT (4U)
\r
4477 /*! @name STATIC_STATICWAITWR - Delay from EMC_CSx to a write access */
\r
4479 #define EMC_STATIC_STATICWAITWR_WAITWR_MASK (0x1FU)
\r
4480 #define EMC_STATIC_STATICWAITWR_WAITWR_SHIFT (0U)
\r
4481 /*! WAITWR - Write wait states.
\r
4483 #define EMC_STATIC_STATICWAITWR_WAITWR(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITWR_WAITWR_SHIFT)) & EMC_STATIC_STATICWAITWR_WAITWR_MASK)
\r
4486 /* The count of EMC_STATIC_STATICWAITWR */
\r
4487 #define EMC_STATIC_STATICWAITWR_COUNT (4U)
\r
4489 /*! @name STATIC_STATICWAITTURN - Number of bus turnaround cycles EMC_CSx */
\r
4491 #define EMC_STATIC_STATICWAITTURN_WAITTURN_MASK (0xFU)
\r
4492 #define EMC_STATIC_STATICWAITTURN_WAITTURN_SHIFT (0U)
\r
4493 /*! WAITTURN - Bus turn-around cycles.
\r
4495 #define EMC_STATIC_STATICWAITTURN_WAITTURN(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITTURN_WAITTURN_SHIFT)) & EMC_STATIC_STATICWAITTURN_WAITTURN_MASK)
\r
4498 /* The count of EMC_STATIC_STATICWAITTURN */
\r
4499 #define EMC_STATIC_STATICWAITTURN_COUNT (4U)
\r
4504 */ /* end of group EMC_Register_Masks */
\r
4507 /* EMC - Peripheral instance base addresses */
\r
4508 /** Peripheral EMC base address */
\r
4509 #define EMC_BASE (0x40081000u)
\r
4510 /** Peripheral EMC base pointer */
\r
4511 #define EMC ((EMC_Type *)EMC_BASE)
\r
4512 /** Array initializer of EMC peripheral base addresses */
\r
4513 #define EMC_BASE_ADDRS { EMC_BASE }
\r
4514 /** Array initializer of EMC peripheral base pointers */
\r
4515 #define EMC_BASE_PTRS { EMC }
\r
4519 */ /* end of group EMC_Peripheral_Access_Layer */
\r
4522 /* ----------------------------------------------------------------------------
\r
4523 -- ENET Peripheral Access Layer
\r
4524 ---------------------------------------------------------------------------- */
\r
4527 * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
\r
4531 /** ENET - Register Layout Typedef */
\r
4533 __IO uint32_t MAC_CONFIG; /**< MAC configuration register, offset: 0x0 */
\r
4534 __IO uint32_t MAC_EXT_CONFIG; /**< , offset: 0x4 */
\r
4535 __IO uint32_t MAC_FRAME_FILTER; /**< MAC frame filter register, offset: 0x8 */
\r
4536 __IO uint32_t MAC_WD_TIMEROUT; /**< MAC watchdog Timeout register, offset: 0xC */
\r
4537 uint8_t RESERVED_0[64];
\r
4538 __IO uint32_t MAC_VLAN_TAG; /**< MAC vlan tag register, offset: 0x50 */
\r
4539 uint8_t RESERVED_1[28];
\r
4540 __IO uint32_t MAC_TX_FLOW_CTRL_Q[2]; /**< Transmit flow control register, array offset: 0x70, array step: 0x4 */
\r
4541 uint8_t RESERVED_2[24];
\r
4542 __IO uint32_t MAC_RX_FLOW_CTRL; /**< Receive flow control register, offset: 0x90 */
\r
4543 uint8_t RESERVED_3[4];
\r
4544 __IO uint32_t MAC_TXQ_PRIO_MAP; /**< , offset: 0x98 */
\r
4545 uint8_t RESERVED_4[4];
\r
4546 __IO uint32_t MAC_RXQ_CTRL[3]; /**< Receive Queue Control 0 register 0x0000, array offset: 0xA0, array step: 0x4 */
\r
4547 uint8_t RESERVED_5[4];
\r
4548 __I uint32_t MAC_INTR_STAT; /**< Interrupt status register 0x0000, offset: 0xB0 */
\r
4549 __IO uint32_t MAC_INTR_EN; /**< Interrupt enable register 0x0000, offset: 0xB4 */
\r
4550 __I uint32_t MAC_RXTX_STAT; /**< Receive Transmit Status register, offset: 0xB8 */
\r
4551 uint8_t RESERVED_6[4];
\r
4552 __IO uint32_t MAC_PMT_CRTL_STAT; /**< , offset: 0xC0 */
\r
4553 __IO uint32_t MAC_RWAKE_FRFLT; /**< Remote wake-up frame filter, offset: 0xC4 */
\r
4554 uint8_t RESERVED_7[8];
\r
4555 __IO uint32_t MAC_LPI_CTRL_STAT; /**< LPI Control and Status Register, offset: 0xD0 */
\r
4556 __IO uint32_t MAC_LPI_TIMER_CTRL; /**< LPI Timers Control register, offset: 0xD4 */
\r
4557 __IO uint32_t MAC_LPI_ENTR_TIMR; /**< LPI entry Timer register, offset: 0xD8 */
\r
4558 __IO uint32_t MAC_1US_TIC_COUNTR; /**< , offset: 0xDC */
\r
4559 uint8_t RESERVED_8[48];
\r
4560 __I uint32_t MAC_VERSION; /**< MAC version register, offset: 0x110 */
\r
4561 __I uint32_t MAC_DBG; /**< MAC debug register, offset: 0x114 */
\r
4562 uint8_t RESERVED_9[4];
\r
4563 __I uint32_t MAC_HW_FEAT[3]; /**< MAC hardware feature register 0x0201, array offset: 0x11C, array step: 0x4 */
\r
4564 uint8_t RESERVED_10[216];
\r
4565 __IO uint32_t MAC_MDIO_ADDR; /**< MIDO address Register, offset: 0x200 */
\r
4566 __IO uint32_t MAC_MDIO_DATA; /**< MDIO Data register, offset: 0x204 */
\r
4567 uint8_t RESERVED_11[248];
\r
4568 __IO uint32_t MAC_ADDR_HIGH; /**< MAC address0 high register, offset: 0x300 */
\r
4569 __IO uint32_t MAC_ADDR_LOW; /**< MAC address0 low register, offset: 0x304 */
\r
4570 uint8_t RESERVED_12[2040];
\r
4571 __IO uint32_t MAC_TIMESTAMP_CTRL; /**< Time stamp control register, offset: 0xB00 */
\r
4572 __IO uint32_t MAC_SUB_SCND_INCR; /**< Sub-second increment register, offset: 0xB04 */
\r
4573 __I uint32_t MAC_SYS_TIME_SCND; /**< System time seconds register, offset: 0xB08 */
\r
4574 __I uint32_t MAC_SYS_TIME_NSCND; /**< System time nanoseconds register, offset: 0xB0C */
\r
4575 __IO uint32_t MAC_SYS_TIME_SCND_UPD; /**< , offset: 0xB10 */
\r
4576 __IO uint32_t MAC_SYS_TIME_NSCND_UPD; /**< , offset: 0xB14 */
\r
4577 __IO uint32_t MAC_SYS_TIMESTMP_ADDEND; /**< Time stamp addend register, offset: 0xB18 */
\r
4578 __IO uint32_t MAC_SYS_TIME_HWORD_SCND; /**< , offset: 0xB1C */
\r
4579 __I uint32_t MAC_SYS_TIMESTMP_STAT; /**< Time stamp status register, offset: 0xB20 */
\r
4580 uint8_t RESERVED_13[12];
\r
4581 __I uint32_t MAC_TX_TIMESTAMP_STATUS_NANOSECONDS; /**< Tx timestamp status nanoseconds, offset: 0xB30 */
\r
4582 __I uint32_t MAC_TX_TIMESTAMP_STATUS_SECONDS; /**< Tx timestamp status seconds, offset: 0xB34 */
\r
4583 uint8_t RESERVED_14[32];
\r
4584 __IO uint32_t MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND; /**< Timestamp ingress correction, offset: 0xB58 */
\r
4585 __IO uint32_t MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND; /**< Timestamp egress correction, offset: 0xB5C */
\r
4586 uint8_t RESERVED_15[160];
\r
4587 __IO uint32_t MTL_OP_MODE; /**< MTL Operation Mode Register, offset: 0xC00 */
\r
4588 uint8_t RESERVED_16[28];
\r
4589 __I uint32_t MTL_INTR_STAT; /**< MTL Interrupt Status register, offset: 0xC20 */
\r
4590 uint8_t RESERVED_17[12];
\r
4591 __IO uint32_t MTL_RXQ_DMA_MAP; /**< MTL Receive Queue and DMA Channel Mapping register, offset: 0xC30 */
\r
4592 uint8_t RESERVED_18[204];
\r
4593 struct { /* offset: 0xD00, array step: 0x40 */
\r
4594 __IO uint32_t MTL_TXQX_OP_MODE; /**< MTL TxQx Operation Mode register, array offset: 0xD00, array step: 0x40 */
\r
4595 __I uint32_t MTL_TXQX_UNDRFLW; /**< MTL TxQx Underflow register, array offset: 0xD04, array step: 0x40 */
\r
4596 __I uint32_t MTL_TXQX_DBG; /**< MTL TxQx Debug register, array offset: 0xD08, array step: 0x40 */
\r
4597 uint8_t RESERVED_0[4];
\r
4598 __IO uint32_t MTL_TXQX_ETS_CTRL; /**< MTL TxQx ETS control register, only TxQ1 support, array offset: 0xD10, array step: 0x40 */
\r
4599 __I uint32_t MTL_TXQX_ETS_STAT; /**< MTL TxQx ETS Status register, array offset: 0xD14, array step: 0x40 */
\r
4600 __IO uint32_t MTL_TXQX_QNTM_WGHT; /**< , array offset: 0xD18, array step: 0x40 */
\r
4601 __IO uint32_t MTL_TXQX_SNDSLP_CRDT; /**< MTL TxQx SendSlopCredit register, only TxQ1 support, array offset: 0xD1C, array step: 0x40 */
\r
4602 __IO uint32_t MTL_TXQX_HI_CRDT; /**< MTL TxQx hiCredit register, only TxQ1 support, array offset: 0xD20, array step: 0x40 */
\r
4603 __IO uint32_t MTL_TXQX_LO_CRDT; /**< MTL TxQx loCredit register, only TxQ1 support, array offset: 0xD24, array step: 0x40 */
\r
4604 uint8_t RESERVED_1[4];
\r
4605 __IO uint32_t MTL_TXQX_INTCTRL_STAT; /**< , array offset: 0xD2C, array step: 0x40 */
\r
4606 __IO uint32_t MTL_RXQX_OP_MODE; /**< MTL RxQx Operation Mode register, array offset: 0xD30, array step: 0x40 */
\r
4607 __I uint32_t MTL_RXQX_MISSPKT_OVRFLW_CNT; /**< MTL RxQx Missed Packet Overflow Counter register, array offset: 0xD34, array step: 0x40 */
\r
4608 __I uint32_t MTL_RXQX_DBG; /**< MTL RxQx Debug register, array offset: 0xD38, array step: 0x40 */
\r
4609 __IO uint32_t MTL_RXQX_CTRL; /**< MTL RxQx Control register, array offset: 0xD3C, array step: 0x40 */
\r
4611 uint8_t RESERVED_19[640];
\r
4612 __IO uint32_t DMA_MODE; /**< DMA mode register, offset: 0x1000 */
\r
4613 __IO uint32_t DMA_SYSBUS_MODE; /**< DMA System Bus mode, offset: 0x1004 */
\r
4614 __IO uint32_t DMA_INTR_STAT; /**< DMA Interrupt status, offset: 0x1008 */
\r
4615 __I uint32_t DMA_DBG_STAT; /**< DMA Debug Status, offset: 0x100C */
\r
4616 uint8_t RESERVED_20[240];
\r
4617 struct { /* offset: 0x1100, array step: 0x80 */
\r
4618 __IO uint32_t DMA_CHX_CTRL; /**< DMA Channelx Control, array offset: 0x1100, array step: 0x80 */
\r
4619 __IO uint32_t DMA_CHX_TX_CTRL; /**< DMA Channelx Transmit Control, array offset: 0x1104, array step: 0x80 */
\r
4620 __IO uint32_t DMA_CHX_RX_CTRL; /**< DMA Channelx Receive Control, array offset: 0x1108, array step: 0x80 */
\r
4621 uint8_t RESERVED_0[8];
\r
4622 __IO uint32_t DMA_CHX_TXDESC_LIST_ADDR; /**< , array offset: 0x1114, array step: 0x80 */
\r
4623 uint8_t RESERVED_1[4];
\r
4624 __IO uint32_t DMA_CHX_RXDESC_LIST_ADDR; /**< , array offset: 0x111C, array step: 0x80 */
\r
4625 __IO uint32_t DMA_CHX_TXDESC_TAIL_PTR; /**< , array offset: 0x1120, array step: 0x80 */
\r
4626 uint8_t RESERVED_2[4];
\r
4627 __IO uint32_t DMA_CHX_RXDESC_TAIL_PTR; /**< , array offset: 0x1128, array step: 0x80 */
\r
4628 __IO uint32_t DMA_CHX_TXDESC_RING_LENGTH; /**< , array offset: 0x112C, array step: 0x80 */
\r
4629 __IO uint32_t DMA_CHX_RXDESC_RING_LENGTH; /**< Channelx Rx descriptor Ring Length, array offset: 0x1130, array step: 0x80 */
\r
4630 __IO uint32_t DMA_CHX_INT_EN; /**< Channelx Interrupt Enable, array offset: 0x1134, array step: 0x80 */
\r
4631 __IO uint32_t DMA_CHX_RX_INT_WDTIMER; /**< Receive Interrupt Watchdog Timer, array offset: 0x1138, array step: 0x80 */
\r
4632 __IO uint32_t DMA_CHX_SLOT_FUNC_CTRL_STAT; /**< Slot Function Control and Status, array offset: 0x113C, array step: 0x80 */
\r
4633 uint8_t RESERVED_3[4];
\r
4634 __I uint32_t DMA_CHX_CUR_HST_TXDESC; /**< Channelx Current Host Transmit descriptor, array offset: 0x1144, array step: 0x80 */
\r
4635 uint8_t RESERVED_4[4];
\r
4636 __I uint32_t DMA_CHX_CUR_HST_RXDESC; /**< , array offset: 0x114C, array step: 0x80 */
\r
4637 uint8_t RESERVED_5[4];
\r
4638 __I uint32_t DMA_CHX_CUR_HST_TXBUF; /**< , array offset: 0x1154, array step: 0x80 */
\r
4639 uint8_t RESERVED_6[4];
\r
4640 __I uint32_t DMA_CHX_CUR_HST_RXBUF; /**< Channelx Current Application Receive Buffer Address, array offset: 0x115C, array step: 0x80 */
\r
4641 __IO uint32_t DMA_CHX_STAT; /**< Channelx DMA status register, array offset: 0x1160, array step: 0x80 */
\r
4642 uint8_t RESERVED_7[8];
\r
4643 __IO uint32_t DMA_CHX_MISS_FRAME_CNT; /**< Channelx missed frame count., array offset: 0x116C, array step: 0x80 */
\r
4644 uint8_t RESERVED_8[16];
\r
4648 /* ----------------------------------------------------------------------------
\r
4649 -- ENET Register Masks
\r
4650 ---------------------------------------------------------------------------- */
\r
4653 * @addtogroup ENET_Register_Masks ENET Register Masks
\r
4657 /*! @name MAC_CONFIG - MAC configuration register */
\r
4659 #define ENET_MAC_CONFIG_RE_MASK (0x1U)
\r
4660 #define ENET_MAC_CONFIG_RE_SHIFT (0U)
\r
4661 /*! RE - Receiver Enable When this bit is set, the receiver state machine of the MAC is enabled for
\r
4662 * receiving frames from the MII.
\r
4664 #define ENET_MAC_CONFIG_RE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_RE_SHIFT)) & ENET_MAC_CONFIG_RE_MASK)
\r
4665 #define ENET_MAC_CONFIG_TE_MASK (0x2U)
\r
4666 #define ENET_MAC_CONFIG_TE_SHIFT (1U)
\r
4667 /*! TE - Transmitter Enable When this bit is set, the transmit state machine of the MAC is enabled for transmission on the MII.
\r
4669 #define ENET_MAC_CONFIG_TE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_TE_SHIFT)) & ENET_MAC_CONFIG_TE_MASK)
\r
4670 #define ENET_MAC_CONFIG_PRELEN_MASK (0xCU)
\r
4671 #define ENET_MAC_CONFIG_PRELEN_SHIFT (2U)
\r
4672 /*! PRELEN - Preamble Length for Transmit packets These bits control the number of preamble bytes
\r
4673 * that are added to the beginning of every Tx packet.
\r
4675 #define ENET_MAC_CONFIG_PRELEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_PRELEN_SHIFT)) & ENET_MAC_CONFIG_PRELEN_MASK)
\r
4676 #define ENET_MAC_CONFIG_DC_MASK (0x10U)
\r
4677 #define ENET_MAC_CONFIG_DC_SHIFT (4U)
\r
4678 /*! DC - Deferral Check When this bit is set, the deferral check function is enabled in the MAC.
\r
4680 #define ENET_MAC_CONFIG_DC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DC_SHIFT)) & ENET_MAC_CONFIG_DC_MASK)
\r
4681 #define ENET_MAC_CONFIG_BL_MASK (0x60U)
\r
4682 #define ENET_MAC_CONFIG_BL_SHIFT (5U)
\r
4683 /*! BL - Back-Off Limit The Back-Off limit determines the random integer number (r) of slot time
\r
4684 * delays (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) the MAC waits before
\r
4685 * rescheduling a transmission attempt during retries after a collision.
\r
4687 #define ENET_MAC_CONFIG_BL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_BL_SHIFT)) & ENET_MAC_CONFIG_BL_MASK)
\r
4688 #define ENET_MAC_CONFIG_DR_MASK (0x100U)
\r
4689 #define ENET_MAC_CONFIG_DR_SHIFT (8U)
\r
4690 /*! DR - Disable Retry When this bit is set, the MAC will attempt only one transmission.
\r
4692 #define ENET_MAC_CONFIG_DR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DR_SHIFT)) & ENET_MAC_CONFIG_DR_MASK)
\r
4693 #define ENET_MAC_CONFIG_DCRS_MASK (0x200U)
\r
4694 #define ENET_MAC_CONFIG_DCRS_SHIFT (9U)
\r
4695 /*! DCRS - Disable Carrier Sense During Transmission When this bit is set, the MAC transmitter
\r
4696 * ignores the MII CRS signal during packet transmission in the half-duplex mode.
\r
4698 #define ENET_MAC_CONFIG_DCRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DCRS_SHIFT)) & ENET_MAC_CONFIG_DCRS_MASK)
\r
4699 #define ENET_MAC_CONFIG_DO_MASK (0x400U)
\r
4700 #define ENET_MAC_CONFIG_DO_SHIFT (10U)
\r
4701 /*! DO - Disable Receive Own When this bit is set, the MAC disables the reception of frames when the
\r
4702 * gmii_txen_o is asserted in Half-Duplex mode.
\r
4704 #define ENET_MAC_CONFIG_DO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DO_SHIFT)) & ENET_MAC_CONFIG_DO_MASK)
\r
4705 #define ENET_MAC_CONFIG_ECRSFD_MASK (0x800U)
\r
4706 #define ENET_MAC_CONFIG_ECRSFD_SHIFT (11U)
\r
4707 /*! ECRSFD - Enable Carrier Sense Before Transmission in Full-Duplex Mode When this bit is set, the
\r
4708 * MAC transmitter checks the CRS signal before packet transmission in the full-duplex mode.
\r
4710 #define ENET_MAC_CONFIG_ECRSFD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_ECRSFD_SHIFT)) & ENET_MAC_CONFIG_ECRSFD_MASK)
\r
4711 #define ENET_MAC_CONFIG_LM_MASK (0x1000U)
\r
4712 #define ENET_MAC_CONFIG_LM_SHIFT (12U)
\r
4713 /*! LM - Loopback Mode When this bit is set, the MAC operates in loopback mode at MII.
\r
4715 #define ENET_MAC_CONFIG_LM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_LM_SHIFT)) & ENET_MAC_CONFIG_LM_MASK)
\r
4716 #define ENET_MAC_CONFIG_DM_MASK (0x2000U)
\r
4717 #define ENET_MAC_CONFIG_DM_SHIFT (13U)
\r
4718 /*! DM - Duplex Mode When this bit is set, the MAC operates in a Full-Duplex mode where it can
\r
4719 * transmit and receive simultaneously.
\r
4721 #define ENET_MAC_CONFIG_DM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DM_SHIFT)) & ENET_MAC_CONFIG_DM_MASK)
\r
4722 #define ENET_MAC_CONFIG_FES_MASK (0x4000U)
\r
4723 #define ENET_MAC_CONFIG_FES_SHIFT (14U)
\r
4724 /*! FES - Speed Indicates the speed in Fast Ethernet (MII) mode: This bit is reserved (RO) by
\r
4725 * default and is enabled only when RMII/SMII is enabled during configuration.
\r
4727 #define ENET_MAC_CONFIG_FES(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_FES_SHIFT)) & ENET_MAC_CONFIG_FES_MASK)
\r
4728 #define ENET_MAC_CONFIG_PS_MASK (0x8000U)
\r
4729 #define ENET_MAC_CONFIG_PS_SHIFT (15U)
\r
4730 /*! PS - Portselect.
\r
4732 #define ENET_MAC_CONFIG_PS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_PS_SHIFT)) & ENET_MAC_CONFIG_PS_MASK)
\r
4733 #define ENET_MAC_CONFIG_JE_MASK (0x10000U)
\r
4734 #define ENET_MAC_CONFIG_JE_SHIFT (16U)
\r
4735 /*! JE - Jumbo Frame Enable When this bit is set, MAC allows Jumbo frames of 9,018 bytes (9,022
\r
4736 * bytes for tagged frames) without reporting a giant frame error in the receive frame status.
\r
4738 #define ENET_MAC_CONFIG_JE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_JE_SHIFT)) & ENET_MAC_CONFIG_JE_MASK)
\r
4739 #define ENET_MAC_CONFIG_JD_MASK (0x20000U)
\r
4740 #define ENET_MAC_CONFIG_JD_SHIFT (17U)
\r
4741 /*! JD - Jabber Disable When this bit is set, the MAC disables the jabber timer on the transmitter,
\r
4742 * and can transfer frames of up to 16,384 bytes.
\r
4744 #define ENET_MAC_CONFIG_JD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_JD_SHIFT)) & ENET_MAC_CONFIG_JD_MASK)
\r
4745 #define ENET_MAC_CONFIG_BE_MASK (0x40000U)
\r
4746 #define ENET_MAC_CONFIG_BE_SHIFT (18U)
\r
4747 /*! BE - Packet Burst Enable When this bit is set, the MAC allows packet bursting during
\r
4748 * transmission in the MII half-duplex mode.
\r
4750 #define ENET_MAC_CONFIG_BE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_BE_SHIFT)) & ENET_MAC_CONFIG_BE_MASK)
\r
4751 #define ENET_MAC_CONFIG_WD_MASK (0x80000U)
\r
4752 #define ENET_MAC_CONFIG_WD_SHIFT (19U)
\r
4753 /*! WD - Watchdog Disable When this bit is set, the MAC disables the watchdog timer on the receiver,
\r
4754 * and can receive frames of up to 16,384 bytes.
\r
4756 #define ENET_MAC_CONFIG_WD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_WD_SHIFT)) & ENET_MAC_CONFIG_WD_MASK)
\r
4757 #define ENET_MAC_CONFIG_ACS_MASK (0x100000U)
\r
4758 #define ENET_MAC_CONFIG_ACS_SHIFT (20U)
\r
4759 /*! ACS - Automatic Pad or CRC Stripping When this bit is set, the MAC strips the Pad or FCS field
\r
4760 * on the incoming packets only if the value of the length field is less than 1,536 bytes.
\r
4762 #define ENET_MAC_CONFIG_ACS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_ACS_SHIFT)) & ENET_MAC_CONFIG_ACS_MASK)
\r
4763 #define ENET_MAC_CONFIG_CST_MASK (0x200000U)
\r
4764 #define ENET_MAC_CONFIG_CST_SHIFT (21U)
\r
4765 /*! CST - CRC stripping for Type packets When this bit is set, the last four bytes (FCS) of all
\r
4766 * packets of Ether type (type field greater than 1,536) are stripped and dropped before forwarding
\r
4767 * the packet to the application.
\r
4769 #define ENET_MAC_CONFIG_CST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_CST_SHIFT)) & ENET_MAC_CONFIG_CST_MASK)
\r
4770 #define ENET_MAC_CONFIG_S2KP_MASK (0x400000U)
\r
4771 #define ENET_MAC_CONFIG_S2KP_SHIFT (22U)
\r
4772 /*! S2KP - IEEE 802.
\r
4774 #define ENET_MAC_CONFIG_S2KP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_S2KP_SHIFT)) & ENET_MAC_CONFIG_S2KP_MASK)
\r
4775 #define ENET_MAC_CONFIG_GPSLCE_MASK (0x800000U)
\r
4776 #define ENET_MAC_CONFIG_GPSLCE_SHIFT (23U)
\r
4777 /*! GPSLCE - Giant Packet Size Limit Control Enable When this bit is set, the MAC considers the
\r
4778 * value in GPSL field in MAC Ext Configuration register to declare a received packet as Giant packet.
\r
4780 #define ENET_MAC_CONFIG_GPSLCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_GPSLCE_SHIFT)) & ENET_MAC_CONFIG_GPSLCE_MASK)
\r
4781 #define ENET_MAC_CONFIG_IPG_MASK (0x7000000U)
\r
4782 #define ENET_MAC_CONFIG_IPG_SHIFT (24U)
\r
4783 /*! IPG - Inter-Packet Gap These bits control the minimum IPG between packets during transmission.
\r
4785 #define ENET_MAC_CONFIG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_IPG_SHIFT)) & ENET_MAC_CONFIG_IPG_MASK)
\r
4786 #define ENET_MAC_CONFIG_IPC_MASK (0x8000000U)
\r
4787 #define ENET_MAC_CONFIG_IPC_SHIFT (27U)
\r
4788 /*! IPC - Checksum Offload When set, this bit enables the IPv4 header checksum checking and IPv4 or
\r
4789 * IPv6 TCP, UDP, or ICMP payload checksum checking.
\r
4791 #define ENET_MAC_CONFIG_IPC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_IPC_SHIFT)) & ENET_MAC_CONFIG_IPC_MASK)
\r
4794 /*! @name MAC_EXT_CONFIG - */
\r
4796 #define ENET_MAC_EXT_CONFIG_GPSL_MASK (0x3FFFU)
\r
4797 #define ENET_MAC_EXT_CONFIG_GPSL_SHIFT (0U)
\r
4798 /*! GPSL - Giant Packet Size Limit If the received packet size is greater than the value programmed
\r
4799 * in this field in units of bytes, the MAC declares the received packet as Giant packet.
\r
4801 #define ENET_MAC_EXT_CONFIG_GPSL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_GPSL_SHIFT)) & ENET_MAC_EXT_CONFIG_GPSL_MASK)
\r
4802 #define ENET_MAC_EXT_CONFIG_DCRCC_MASK (0x10000U)
\r
4803 #define ENET_MAC_EXT_CONFIG_DCRCC_SHIFT (16U)
\r
4804 /*! DCRCC - Disable CRC Checking for Received Packets When this bit is set, the MAC receiver does
\r
4805 * not check the CRC field in the received packets.
\r
4807 #define ENET_MAC_EXT_CONFIG_DCRCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_DCRCC_SHIFT)) & ENET_MAC_EXT_CONFIG_DCRCC_MASK)
\r
4808 #define ENET_MAC_EXT_CONFIG_SPEN_MASK (0x20000U)
\r
4809 #define ENET_MAC_EXT_CONFIG_SPEN_SHIFT (17U)
\r
4810 /*! SPEN - Slow Protocol Detection Enable When this bit is set, MAC processes the Slow Protocol
\r
4811 * packets (Ether Type 0x8809) and provides the Rx status.
\r
4813 #define ENET_MAC_EXT_CONFIG_SPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_SPEN_SHIFT)) & ENET_MAC_EXT_CONFIG_SPEN_MASK)
\r
4814 #define ENET_MAC_EXT_CONFIG_USP_MASK (0x40000U)
\r
4815 #define ENET_MAC_EXT_CONFIG_USP_SHIFT (18U)
\r
4816 /*! USP - Unicast Slow Protocol Packet Detect When this bit is set, the MAC detects the Slow
\r
4817 * Protocol packets with unicast address of the station specified in the MAC Address High Table 747 and
\r
4818 * MAC Address Low Table 748 registers.
\r
4820 #define ENET_MAC_EXT_CONFIG_USP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_USP_SHIFT)) & ENET_MAC_EXT_CONFIG_USP_MASK)
\r
4823 /*! @name MAC_FRAME_FILTER - MAC frame filter register */
\r
4825 #define ENET_MAC_FRAME_FILTER_PR_MASK (0x1U)
\r
4826 #define ENET_MAC_FRAME_FILTER_PR_SHIFT (0U)
\r
4827 /*! PR - Promiscuous Mode When this bit is set, the Address Filter module passes all incoming frames
\r
4828 * regardless of its destination or source address.
\r
4830 #define ENET_MAC_FRAME_FILTER_PR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PR_SHIFT)) & ENET_MAC_FRAME_FILTER_PR_MASK)
\r
4831 #define ENET_MAC_FRAME_FILTER_DAIF_MASK (0x8U)
\r
4832 #define ENET_MAC_FRAME_FILTER_DAIF_SHIFT (3U)
\r
4833 /*! DAIF - DA Inverse Filtering When this bit is set, the Address Check block operates in inverse
\r
4834 * filtering mode for the DA address comparison for both unicast and multicast frames.
\r
4836 #define ENET_MAC_FRAME_FILTER_DAIF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_DAIF_SHIFT)) & ENET_MAC_FRAME_FILTER_DAIF_MASK)
\r
4837 #define ENET_MAC_FRAME_FILTER_PM_MASK (0x10U)
\r
4838 #define ENET_MAC_FRAME_FILTER_PM_SHIFT (4U)
\r
4839 /*! PM - Pass All Multicast When set, this bit indicates that all received frames with a multicast
\r
4840 * destination address (first bit in the destination address field is '1') are passed.
\r
4842 #define ENET_MAC_FRAME_FILTER_PM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PM_SHIFT)) & ENET_MAC_FRAME_FILTER_PM_MASK)
\r
4843 #define ENET_MAC_FRAME_FILTER_DBF_MASK (0x20U)
\r
4844 #define ENET_MAC_FRAME_FILTER_DBF_SHIFT (5U)
\r
4845 /*! DBF - Disable Broadcast Frames When this bit is set, the AFM module filters all incoming broadcast frames.
\r
4847 #define ENET_MAC_FRAME_FILTER_DBF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_DBF_SHIFT)) & ENET_MAC_FRAME_FILTER_DBF_MASK)
\r
4848 #define ENET_MAC_FRAME_FILTER_PCF_MASK (0xC0U)
\r
4849 #define ENET_MAC_FRAME_FILTER_PCF_SHIFT (6U)
\r
4850 /*! PCF - Pass Control Frames These bits control the forwarding of all control frames (including
\r
4851 * unicast and multicast PAUSE frames).
\r
4853 #define ENET_MAC_FRAME_FILTER_PCF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PCF_SHIFT)) & ENET_MAC_FRAME_FILTER_PCF_MASK)
\r
4854 #define ENET_MAC_FRAME_FILTER_SAIF_MASK (0x100U)
\r
4855 #define ENET_MAC_FRAME_FILTER_SAIF_SHIFT (8U)
\r
4856 /*! SAIF - SA Inverse Filtering When this bit is set, the Address Check block operates in the
\r
4857 * inverse filtering mode for SA address comparison.
\r
4859 #define ENET_MAC_FRAME_FILTER_SAIF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_SAIF_SHIFT)) & ENET_MAC_FRAME_FILTER_SAIF_MASK)
\r
4860 #define ENET_MAC_FRAME_FILTER_SAF_MASK (0x200U)
\r
4861 #define ENET_MAC_FRAME_FILTER_SAF_SHIFT (9U)
\r
4862 /*! SAF - Source Address Filter Enable When this bit is set, the MAC compares the SA field of the
\r
4863 * received packets with the values programmed in the enabled SA registers.
\r
4865 #define ENET_MAC_FRAME_FILTER_SAF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_SAF_SHIFT)) & ENET_MAC_FRAME_FILTER_SAF_MASK)
\r
4866 #define ENET_MAC_FRAME_FILTER_RA_MASK (0x80000000U)
\r
4867 #define ENET_MAC_FRAME_FILTER_RA_SHIFT (31U)
\r
4868 /*! RA - Receive all When this bit is set, the MAC Receiver module passes to the Application all
\r
4869 * frames received irrespective of whether they pass the address filter.
\r
4871 #define ENET_MAC_FRAME_FILTER_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_RA_SHIFT)) & ENET_MAC_FRAME_FILTER_RA_MASK)
\r
4874 /*! @name MAC_WD_TIMEROUT - MAC watchdog Timeout register */
\r
4876 #define ENET_MAC_WD_TIMEROUT_WTO_MASK (0xFU)
\r
4877 #define ENET_MAC_WD_TIMEROUT_WTO_SHIFT (0U)
\r
4878 /*! WTO - Watchdog Timeout When the PWE bit is set and the WD bit of the MAC Configuration register
\r
4879 * Table 722 is reset, this field is used as watchdog timeout for a received packet.
\r
4881 #define ENET_MAC_WD_TIMEROUT_WTO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_WD_TIMEROUT_WTO_SHIFT)) & ENET_MAC_WD_TIMEROUT_WTO_MASK)
\r
4882 #define ENET_MAC_WD_TIMEROUT_PWE_MASK (0x100U)
\r
4883 #define ENET_MAC_WD_TIMEROUT_PWE_SHIFT (8U)
\r
4884 /*! PWE - Programmable Watchdog Enable When this bit is set and the WD bit of the MAC Configuration
\r
4885 * register Table 722 is reset, the WTO field is used as watchdog timeout for a received packet.
\r
4887 #define ENET_MAC_WD_TIMEROUT_PWE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_WD_TIMEROUT_PWE_SHIFT)) & ENET_MAC_WD_TIMEROUT_PWE_MASK)
\r
4890 /*! @name MAC_VLAN_TAG - MAC vlan tag register */
\r
4892 #define ENET_MAC_VLAN_TAG_VL_MASK (0xFFFFU)
\r
4893 #define ENET_MAC_VLAN_TAG_VL_SHIFT (0U)
\r
4894 /*! VL - VLAN Tag Identifier for Receive Packets.
\r
4896 #define ENET_MAC_VLAN_TAG_VL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VL_SHIFT)) & ENET_MAC_VLAN_TAG_VL_MASK)
\r
4897 #define ENET_MAC_VLAN_TAG_ETV_MASK (0x10000U)
\r
4898 #define ENET_MAC_VLAN_TAG_ETV_SHIFT (16U)
\r
4899 /*! ETV - Enable 12-Bit VLAN Tag Comparison.
\r
4901 #define ENET_MAC_VLAN_TAG_ETV(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ETV_SHIFT)) & ENET_MAC_VLAN_TAG_ETV_MASK)
\r
4902 #define ENET_MAC_VLAN_TAG_VTIM_MASK (0x20000U)
\r
4903 #define ENET_MAC_VLAN_TAG_VTIM_SHIFT (17U)
\r
4904 /*! VTIM - VLAN Tag Inverse Match Enable.
\r
4906 #define ENET_MAC_VLAN_TAG_VTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VTIM_SHIFT)) & ENET_MAC_VLAN_TAG_VTIM_MASK)
\r
4907 #define ENET_MAC_VLAN_TAG_ESVL_MASK (0x40000U)
\r
4908 #define ENET_MAC_VLAN_TAG_ESVL_SHIFT (18U)
\r
4909 /*! ESVL - Enable S-VLAN.
\r
4911 #define ENET_MAC_VLAN_TAG_ESVL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ESVL_SHIFT)) & ENET_MAC_VLAN_TAG_ESVL_MASK)
\r
4912 #define ENET_MAC_VLAN_TAG_ERSVLM_MASK (0x80000U)
\r
4913 #define ENET_MAC_VLAN_TAG_ERSVLM_SHIFT (19U)
\r
4914 /*! ERSVLM - Enable Receive S-VLAN Match.
\r
4916 #define ENET_MAC_VLAN_TAG_ERSVLM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ERSVLM_SHIFT)) & ENET_MAC_VLAN_TAG_ERSVLM_MASK)
\r
4917 #define ENET_MAC_VLAN_TAG_DOVLTC_MASK (0x100000U)
\r
4918 #define ENET_MAC_VLAN_TAG_DOVLTC_SHIFT (20U)
\r
4919 /*! DOVLTC - Disable VLAN Type Check.
\r
4921 #define ENET_MAC_VLAN_TAG_DOVLTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_DOVLTC_SHIFT)) & ENET_MAC_VLAN_TAG_DOVLTC_MASK)
\r
4922 #define ENET_MAC_VLAN_TAG_EVLS_MASK (0x600000U)
\r
4923 #define ENET_MAC_VLAN_TAG_EVLS_SHIFT (21U)
\r
4924 /*! EVLS - Enable VLAN Tag Stripping on Receive.
\r
4926 #define ENET_MAC_VLAN_TAG_EVLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EVLS_SHIFT)) & ENET_MAC_VLAN_TAG_EVLS_MASK)
\r
4927 #define ENET_MAC_VLAN_TAG_EVLRXS_MASK (0x1000000U)
\r
4928 #define ENET_MAC_VLAN_TAG_EVLRXS_SHIFT (24U)
\r
4929 /*! EVLRXS - Enable VLAN Tag in Rx status.
\r
4931 #define ENET_MAC_VLAN_TAG_EVLRXS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EVLRXS_SHIFT)) & ENET_MAC_VLAN_TAG_EVLRXS_MASK)
\r
4932 #define ENET_MAC_VLAN_TAG_VTHM_MASK (0x2000000U)
\r
4933 #define ENET_MAC_VLAN_TAG_VTHM_SHIFT (25U)
\r
4934 /*! VTHM - Disable VLAN Type Check.
\r
4936 #define ENET_MAC_VLAN_TAG_VTHM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VTHM_SHIFT)) & ENET_MAC_VLAN_TAG_VTHM_MASK)
\r
4937 #define ENET_MAC_VLAN_TAG_EDVLP_MASK (0x4000000U)
\r
4938 #define ENET_MAC_VLAN_TAG_EDVLP_SHIFT (26U)
\r
4939 /*! EDVLP - Enable Double VLAN Processing.
\r
4941 #define ENET_MAC_VLAN_TAG_EDVLP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EDVLP_SHIFT)) & ENET_MAC_VLAN_TAG_EDVLP_MASK)
\r
4942 #define ENET_MAC_VLAN_TAG_ERIVLT_MASK (0x8000000U)
\r
4943 #define ENET_MAC_VLAN_TAG_ERIVLT_SHIFT (27U)
\r
4944 /*! ERIVLT - Enable Inner VLAN Tag.
\r
4946 #define ENET_MAC_VLAN_TAG_ERIVLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ERIVLT_SHIFT)) & ENET_MAC_VLAN_TAG_ERIVLT_MASK)
\r
4947 #define ENET_MAC_VLAN_TAG_EIVLS_MASK (0x30000000U)
\r
4948 #define ENET_MAC_VLAN_TAG_EIVLS_SHIFT (28U)
\r
4949 /*! EIVLS - Enable Inner VLAN Tag Stripping on Receive.
\r
4951 #define ENET_MAC_VLAN_TAG_EIVLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EIVLS_SHIFT)) & ENET_MAC_VLAN_TAG_EIVLS_MASK)
\r
4952 #define ENET_MAC_VLAN_TAG_EIVLRXS_MASK (0x80000000U)
\r
4953 #define ENET_MAC_VLAN_TAG_EIVLRXS_SHIFT (31U)
\r
4954 /*! EIVLRXS - Enable Inner VLAN Tag in Rx Status.
\r
4956 #define ENET_MAC_VLAN_TAG_EIVLRXS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EIVLRXS_SHIFT)) & ENET_MAC_VLAN_TAG_EIVLRXS_MASK)
\r
4959 /*! @name MAC_TX_FLOW_CTRL_Q - Transmit flow control register */
\r
4961 #define ENET_MAC_TX_FLOW_CTRL_Q_FCB_MASK (0x1U)
\r
4962 #define ENET_MAC_TX_FLOW_CTRL_Q_FCB_SHIFT (0U)
\r
4963 /*! FCB - Flow Control Busy/Backpressure Activate This register field can be read by the application
\r
4964 * (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is
\r
4965 * cleared to 0 by the core (Self Clear).
\r
4967 #define ENET_MAC_TX_FLOW_CTRL_Q_FCB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_FCB_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_FCB_MASK)
\r
4968 #define ENET_MAC_TX_FLOW_CTRL_Q_TFE_MASK (0x2U)
\r
4969 #define ENET_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT (1U)
\r
4970 /*! TFE - Transmit Flow Control Enable In Full-Duplex mode, when this bit is set, the MAC enables
\r
4971 * the flow control operation to transmit Pause frames.
\r
4973 #define ENET_MAC_TX_FLOW_CTRL_Q_TFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_TFE_MASK)
\r
4974 #define ENET_MAC_TX_FLOW_CTRL_Q_PLT_MASK (0x70U)
\r
4975 #define ENET_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT (4U)
\r
4976 /*! PLT - Pause Low Threshold This field configures the threshold of the PAUSE timer at which the
\r
4977 * input flow control signal is checked for automatic retransmission of PAUSE Frame.
\r
4979 #define ENET_MAC_TX_FLOW_CTRL_Q_PLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_PLT_MASK)
\r
4980 #define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK (0x80U)
\r
4981 #define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT (7U)
\r
4982 /*! DZPQ - Disable Zero-Quanta Pause When set, this bit disables the automatic generation of
\r
4983 * Zero-Quanta Pause Control frames on the deassertion of the flow-control signal from the FIFO layer.
\r
4985 #define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK)
\r
4986 #define ENET_MAC_TX_FLOW_CTRL_Q_PT_MASK (0xFFFF0000U)
\r
4987 #define ENET_MAC_TX_FLOW_CTRL_Q_PT_SHIFT (16U)
\r
4988 /*! PT - Pause time This field holds the value to be used in the Pause Time field in the transmit control frame.
\r
4990 #define ENET_MAC_TX_FLOW_CTRL_Q_PT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_PT_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_PT_MASK)
\r
4993 /* The count of ENET_MAC_TX_FLOW_CTRL_Q */
\r
4994 #define ENET_MAC_TX_FLOW_CTRL_Q_COUNT (2U)
\r
4996 /*! @name MAC_RX_FLOW_CTRL - Receive flow control register */
\r
4998 #define ENET_MAC_RX_FLOW_CTRL_RFE_MASK (0x1U)
\r
4999 #define ENET_MAC_RX_FLOW_CTRL_RFE_SHIFT (0U)
\r
5000 /*! RFE - Receive Flow Control Enable When this bit is set and the MAC is operating in full-duplex
\r
5001 * mode, the MAC decodes the received Pause packet and disables its transmitter for a specified
\r
5004 #define ENET_MAC_RX_FLOW_CTRL_RFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_FLOW_CTRL_RFE_SHIFT)) & ENET_MAC_RX_FLOW_CTRL_RFE_MASK)
\r
5005 #define ENET_MAC_RX_FLOW_CTRL_UP_MASK (0x2U)
\r
5006 #define ENET_MAC_RX_FLOW_CTRL_UP_SHIFT (1U)
\r
5007 /*! UP - Unicast Pause Packet Detect A pause packet is processed when it has the unique multicast
\r
5008 * address specified in the IEEE 802.
\r
5010 #define ENET_MAC_RX_FLOW_CTRL_UP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_FLOW_CTRL_UP_SHIFT)) & ENET_MAC_RX_FLOW_CTRL_UP_MASK)
\r
5013 /*! @name MAC_TXQ_PRIO_MAP - */
\r
5015 #define ENET_MAC_TXQ_PRIO_MAP_PSTQ0_MASK (0xFFU)
\r
5016 #define ENET_MAC_TXQ_PRIO_MAP_PSTQ0_SHIFT (0U)
\r
5017 /*! PSTQ0 - Priorities Selected in Transmit Queue 0 This field holds the priorities assigned to Tx Queue 0 by the software.
\r
5019 #define ENET_MAC_TXQ_PRIO_MAP_PSTQ0(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TXQ_PRIO_MAP_PSTQ0_SHIFT)) & ENET_MAC_TXQ_PRIO_MAP_PSTQ0_MASK)
\r
5020 #define ENET_MAC_TXQ_PRIO_MAP_PSTQ1_MASK (0xFF00U)
\r
5021 #define ENET_MAC_TXQ_PRIO_MAP_PSTQ1_SHIFT (8U)
\r
5022 /*! PSTQ1 - Priorities Selected in Transmit Queue 1 This bit is similar to the PSTQ0 bit.
\r
5024 #define ENET_MAC_TXQ_PRIO_MAP_PSTQ1(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TXQ_PRIO_MAP_PSTQ1_SHIFT)) & ENET_MAC_TXQ_PRIO_MAP_PSTQ1_MASK)
\r
5027 /*! @name MAC_RXQ_CTRL - Receive Queue Control 0 register 0x0000 */
\r
5029 #define ENET_MAC_RXQ_CTRL_AVCPQ_MASK (0x7U)
\r
5030 #define ENET_MAC_RXQ_CTRL_AVCPQ_SHIFT (0U)
\r
5031 /*! AVCPQ - AV Untagged Control Packets Queue.
\r
5033 #define ENET_MAC_RXQ_CTRL_AVCPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_AVCPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_AVCPQ_MASK)
\r
5034 #define ENET_MAC_RXQ_CTRL_PSRQ0_MASK (0xFFU)
\r
5035 #define ENET_MAC_RXQ_CTRL_PSRQ0_SHIFT (0U)
\r
5036 /*! PSRQ0 - Priorities Selected in the Receive Queue 0.
\r
5038 #define ENET_MAC_RXQ_CTRL_PSRQ0(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ0_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ0_MASK)
\r
5039 #define ENET_MAC_RXQ_CTRL_RXQ0EN_MASK (0x3U)
\r
5040 #define ENET_MAC_RXQ_CTRL_RXQ0EN_SHIFT (0U)
\r
5041 /*! RXQ0EN - Receive Queue 0 Enable.
\r
5043 #define ENET_MAC_RXQ_CTRL_RXQ0EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_RXQ0EN_SHIFT)) & ENET_MAC_RXQ_CTRL_RXQ0EN_MASK)
\r
5044 #define ENET_MAC_RXQ_CTRL_RXQ1EN_MASK (0xCU)
\r
5045 #define ENET_MAC_RXQ_CTRL_RXQ1EN_SHIFT (2U)
\r
5046 /*! RXQ1EN - Receive Queue 1 Enable.
\r
5048 #define ENET_MAC_RXQ_CTRL_RXQ1EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_RXQ1EN_SHIFT)) & ENET_MAC_RXQ_CTRL_RXQ1EN_MASK)
\r
5049 #define ENET_MAC_RXQ_CTRL_AVPTPQ_MASK (0x70U)
\r
5050 #define ENET_MAC_RXQ_CTRL_AVPTPQ_SHIFT (4U)
\r
5051 /*! AVPTPQ - AV PTP Packets Queue.
\r
5053 #define ENET_MAC_RXQ_CTRL_AVPTPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_AVPTPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_AVPTPQ_MASK)
\r
5054 #define ENET_MAC_RXQ_CTRL_PSRQ1_MASK (0xFF00U)
\r
5055 #define ENET_MAC_RXQ_CTRL_PSRQ1_SHIFT (8U)
\r
5056 /*! PSRQ1 - Priorities Selected in the Receive Queue 1.
\r
5058 #define ENET_MAC_RXQ_CTRL_PSRQ1(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ1_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ1_MASK)
\r
5059 #define ENET_MAC_RXQ_CTRL_UPQ_MASK (0x7000U)
\r
5060 #define ENET_MAC_RXQ_CTRL_UPQ_SHIFT (12U)
\r
5061 /*! UPQ - Untagged Packet Queue.
\r
5063 #define ENET_MAC_RXQ_CTRL_UPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_UPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_UPQ_MASK)
\r
5064 #define ENET_MAC_RXQ_CTRL_MCBCQ_MASK (0x70000U)
\r
5065 #define ENET_MAC_RXQ_CTRL_MCBCQ_SHIFT (16U)
\r
5066 /*! MCBCQ - Multicast and Broadcast Queue.
\r
5068 #define ENET_MAC_RXQ_CTRL_MCBCQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_MCBCQ_SHIFT)) & ENET_MAC_RXQ_CTRL_MCBCQ_MASK)
\r
5069 #define ENET_MAC_RXQ_CTRL_PSRQ2_MASK (0xFF0000U)
\r
5070 #define ENET_MAC_RXQ_CTRL_PSRQ2_SHIFT (16U)
\r
5071 /*! PSRQ2 - Priorities Selected in the Receive Queue 2.
\r
5073 #define ENET_MAC_RXQ_CTRL_PSRQ2(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ2_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ2_MASK)
\r
5074 #define ENET_MAC_RXQ_CTRL_MCBCQEN_MASK (0x100000U)
\r
5075 #define ENET_MAC_RXQ_CTRL_MCBCQEN_SHIFT (20U)
\r
5076 /*! MCBCQEN - Multicast and Broadcast Queue Enable.
\r
5078 #define ENET_MAC_RXQ_CTRL_MCBCQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_MCBCQEN_SHIFT)) & ENET_MAC_RXQ_CTRL_MCBCQEN_MASK)
\r
5079 #define ENET_MAC_RXQ_CTRL_PSRQ3_MASK (0xFF000000U)
\r
5080 #define ENET_MAC_RXQ_CTRL_PSRQ3_SHIFT (24U)
\r
5081 /*! PSRQ3 - Priorities Selected in the Receive Queue 3.
\r
5083 #define ENET_MAC_RXQ_CTRL_PSRQ3(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ3_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ3_MASK)
\r
5086 /* The count of ENET_MAC_RXQ_CTRL */
\r
5087 #define ENET_MAC_RXQ_CTRL_COUNT (3U)
\r
5089 /*! @name MAC_INTR_STAT - Interrupt status register 0x0000 */
\r
5091 #define ENET_MAC_INTR_STAT_PHYIS_MASK (0x8U)
\r
5092 #define ENET_MAC_INTR_STAT_PHYIS_SHIFT (3U)
\r
5093 /*! PHYIS - PHY Interrupt.
\r
5095 #define ENET_MAC_INTR_STAT_PHYIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_PHYIS_SHIFT)) & ENET_MAC_INTR_STAT_PHYIS_MASK)
\r
5096 #define ENET_MAC_INTR_STAT_PMTIS_MASK (0x10U)
\r
5097 #define ENET_MAC_INTR_STAT_PMTIS_SHIFT (4U)
\r
5098 /*! PMTIS - PMT Interrupt Status.
\r
5100 #define ENET_MAC_INTR_STAT_PMTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_PMTIS_SHIFT)) & ENET_MAC_INTR_STAT_PMTIS_MASK)
\r
5101 #define ENET_MAC_INTR_STAT_LPIIS_MASK (0x20U)
\r
5102 #define ENET_MAC_INTR_STAT_LPIIS_SHIFT (5U)
\r
5103 /*! LPIIS - LPI Interrupt Status.
\r
5105 #define ENET_MAC_INTR_STAT_LPIIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_LPIIS_SHIFT)) & ENET_MAC_INTR_STAT_LPIIS_MASK)
\r
5106 #define ENET_MAC_INTR_STAT_TSIS_MASK (0x1000U)
\r
5107 #define ENET_MAC_INTR_STAT_TSIS_SHIFT (12U)
\r
5108 /*! TSIS - Timestamp interrupt status.
\r
5110 #define ENET_MAC_INTR_STAT_TSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_TSIS_SHIFT)) & ENET_MAC_INTR_STAT_TSIS_MASK)
\r
5111 #define ENET_MAC_INTR_STAT_TXSTSIS_MASK (0x2000U)
\r
5112 #define ENET_MAC_INTR_STAT_TXSTSIS_SHIFT (13U)
\r
5113 /*! TXSTSIS - Transmit Status Interrupt.
\r
5115 #define ENET_MAC_INTR_STAT_TXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_TXSTSIS_SHIFT)) & ENET_MAC_INTR_STAT_TXSTSIS_MASK)
\r
5116 #define ENET_MAC_INTR_STAT_RXSTSIS_MASK (0x4000U)
\r
5117 #define ENET_MAC_INTR_STAT_RXSTSIS_SHIFT (14U)
\r
5118 /*! RXSTSIS - Receive Status Interrupt.
\r
5120 #define ENET_MAC_INTR_STAT_RXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_RXSTSIS_SHIFT)) & ENET_MAC_INTR_STAT_RXSTSIS_MASK)
\r
5123 /*! @name MAC_INTR_EN - Interrupt enable register 0x0000 */
\r
5125 #define ENET_MAC_INTR_EN_PHYIE_MASK (0x8U)
\r
5126 #define ENET_MAC_INTR_EN_PHYIE_SHIFT (3U)
\r
5127 /*! PHYIE - PHY Interrupt Enable.
\r
5129 #define ENET_MAC_INTR_EN_PHYIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_PHYIE_SHIFT)) & ENET_MAC_INTR_EN_PHYIE_MASK)
\r
5130 #define ENET_MAC_INTR_EN_PMTIE_MASK (0x10U)
\r
5131 #define ENET_MAC_INTR_EN_PMTIE_SHIFT (4U)
\r
5132 /*! PMTIE - PMT Interrupt Enable.
\r
5134 #define ENET_MAC_INTR_EN_PMTIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_PMTIE_SHIFT)) & ENET_MAC_INTR_EN_PMTIE_MASK)
\r
5135 #define ENET_MAC_INTR_EN_LPIIE_MASK (0x20U)
\r
5136 #define ENET_MAC_INTR_EN_LPIIE_SHIFT (5U)
\r
5137 /*! LPIIE - LPI Interrupt Enable.
\r
5139 #define ENET_MAC_INTR_EN_LPIIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_LPIIE_SHIFT)) & ENET_MAC_INTR_EN_LPIIE_MASK)
\r
5140 #define ENET_MAC_INTR_EN_TSIE_MASK (0x1000U)
\r
5141 #define ENET_MAC_INTR_EN_TSIE_SHIFT (12U)
\r
5142 /*! TSIE - Timestamp Interrupt Enable.
\r
5144 #define ENET_MAC_INTR_EN_TSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_TSIE_SHIFT)) & ENET_MAC_INTR_EN_TSIE_MASK)
\r
5145 #define ENET_MAC_INTR_EN_TXSTSIE_MASK (0x2000U)
\r
5146 #define ENET_MAC_INTR_EN_TXSTSIE_SHIFT (13U)
\r
5147 /*! TXSTSIE - Transmit Status Interrupt Enable.
\r
5149 #define ENET_MAC_INTR_EN_TXSTSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_TXSTSIE_SHIFT)) & ENET_MAC_INTR_EN_TXSTSIE_MASK)
\r
5150 #define ENET_MAC_INTR_EN_RXSTSIS_MASK (0x4000U)
\r
5151 #define ENET_MAC_INTR_EN_RXSTSIS_SHIFT (14U)
\r
5152 /*! RXSTSIS - Receive Status Interrupt Enable.
\r
5154 #define ENET_MAC_INTR_EN_RXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_RXSTSIS_SHIFT)) & ENET_MAC_INTR_EN_RXSTSIS_MASK)
\r
5157 /*! @name MAC_RXTX_STAT - Receive Transmit Status register */
\r
5159 #define ENET_MAC_RXTX_STAT_TJT_MASK (0x1U)
\r
5160 #define ENET_MAC_RXTX_STAT_TJT_SHIFT (0U)
\r
5161 /*! TJT - PHY Interrupt Enable When this bit is set, it enables the assertion of the interrupt
\r
5162 * signal because of the setting of PHYIS bit in MAC Interrupt Status register Table 731.
\r
5164 #define ENET_MAC_RXTX_STAT_TJT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_TJT_SHIFT)) & ENET_MAC_RXTX_STAT_TJT_MASK)
\r
5165 #define ENET_MAC_RXTX_STAT_NCARR_MASK (0x2U)
\r
5166 #define ENET_MAC_RXTX_STAT_NCARR_SHIFT (1U)
\r
5167 /*! NCARR - No Carrier When the DTXSTS bit is set in the MTL Operation Mode register Table 758, this
\r
5168 * bit indicates that the carrier signal from the PHY is not present at the end of preamble
\r
5171 #define ENET_MAC_RXTX_STAT_NCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_NCARR_SHIFT)) & ENET_MAC_RXTX_STAT_NCARR_MASK)
\r
5172 #define ENET_MAC_RXTX_STAT_LCARR_MASK (0x4U)
\r
5173 #define ENET_MAC_RXTX_STAT_LCARR_SHIFT (2U)
\r
5174 /*! LCARR - Loss of Carrier When the DTXSTS bit is set in the MTL Operation Mode register Table 758,
\r
5175 * this bit indicates that the loss of carrier occurred during packet transmission, that is, the
\r
5176 * PHY Carrier signal was inactive for one or more transmission clock periods during packet
\r
5179 #define ENET_MAC_RXTX_STAT_LCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_LCARR_SHIFT)) & ENET_MAC_RXTX_STAT_LCARR_MASK)
\r
5180 #define ENET_MAC_RXTX_STAT_EXDEF_MASK (0x8U)
\r
5181 #define ENET_MAC_RXTX_STAT_EXDEF_SHIFT (3U)
\r
5182 /*! EXDEF - Excessive Deferral When the DTXSTS bit is set in the MTL Operation Mode register Table
\r
5183 * 758 and the DC bit is set in the MAC Configuration register Table 758, this bit indicates that
\r
5184 * the transmission ended because of excessive deferral of over 24,288 bit times (155,680 when
\r
5185 * Jumbo packet is enabled).
\r
5187 #define ENET_MAC_RXTX_STAT_EXDEF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_EXDEF_SHIFT)) & ENET_MAC_RXTX_STAT_EXDEF_MASK)
\r
5188 #define ENET_MAC_RXTX_STAT_LCOL_MASK (0x10U)
\r
5189 #define ENET_MAC_RXTX_STAT_LCOL_SHIFT (4U)
\r
5190 /*! LCOL - Late Collision When the DTXSTS bit is set in the MTL Operation Mode register Table 758,
\r
5191 * this bit indicates that the packet transmission aborted because a collision occurred after the
\r
5192 * collision window (64 bytes including Preamble in MII mode).
\r
5194 #define ENET_MAC_RXTX_STAT_LCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_LCOL_SHIFT)) & ENET_MAC_RXTX_STAT_LCOL_MASK)
\r
5195 #define ENET_MAC_RXTX_STAT_EXCOL_MASK (0x20U)
\r
5196 #define ENET_MAC_RXTX_STAT_EXCOL_SHIFT (5U)
\r
5197 /*! EXCOL - Excessive Collisions When the DTXSTS bit is set in the MTL Operation Mode register Table
\r
5198 * 758, this bit indicates that the transmission aborted after 16 successive collisions while
\r
5199 * attempting to transmit the current packet.
\r
5201 #define ENET_MAC_RXTX_STAT_EXCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_EXCOL_SHIFT)) & ENET_MAC_RXTX_STAT_EXCOL_MASK)
\r
5202 #define ENET_MAC_RXTX_STAT_RWT_MASK (0x100U)
\r
5203 #define ENET_MAC_RXTX_STAT_RWT_SHIFT (8U)
\r
5204 /*! RWT - Receive Watchdog Timeout This bit is set when a packet with length greater than 2,048
\r
5205 * bytes is received (10,240 bytes when Jumbo Packet mode is enabled) and the WD bit is reset in the
\r
5206 * MAC Configuration register Table 722.
\r
5208 #define ENET_MAC_RXTX_STAT_RWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_RWT_SHIFT)) & ENET_MAC_RXTX_STAT_RWT_MASK)
\r
5211 /*! @name MAC_PMT_CRTL_STAT - */
\r
5213 #define ENET_MAC_PMT_CRTL_STAT_PWRDWN_MASK (0x1U)
\r
5214 #define ENET_MAC_PMT_CRTL_STAT_PWRDWN_SHIFT (0U)
\r
5215 /*! PWRDWN - Transmit LPI Entry When this bit is set, it indicates that the MAC Transmitter has
\r
5216 * entered the LPI state because of the setting of the LPIEN bit.
\r
5218 #define ENET_MAC_PMT_CRTL_STAT_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_PWRDWN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_PWRDWN_MASK)
\r
5219 #define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_MASK (0x2U)
\r
5220 #define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_SHIFT (1U)
\r
5221 /*! MGKPKTEN - Magic Packet Enable.
\r
5223 #define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_MASK)
\r
5224 #define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_MASK (0x4U)
\r
5225 #define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_SHIFT (2U)
\r
5226 /*! RWKPKTEN - Remote Wake-Up Packet Enable When this bit is set, a power management event is
\r
5227 * generated when the MAC receives a remote wake-up packet.
\r
5229 #define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_MASK)
\r
5230 #define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_MASK (0x20U)
\r
5231 #define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_SHIFT (5U)
\r
5232 /*! MGKPRCVD - Magic Packet Received.
\r
5234 #define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_MASK)
\r
5235 #define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_MASK (0x40U)
\r
5236 #define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_SHIFT (6U)
\r
5237 /*! RWKPRCVD - Remote Wake-Up Packet Received.
\r
5239 #define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_MASK)
\r
5240 #define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_MASK (0x200U)
\r
5241 #define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_SHIFT (9U)
\r
5242 /*! GLBLUCAST - Global Unicast When this bit set, any unicast packet filtered by the MAC (DAF)
\r
5243 * address recognition is detected as a remote wake-up packet.
\r
5245 #define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_MASK)
\r
5246 #define ENET_MAC_PMT_CRTL_STAT_RWKPFE_MASK (0x400U)
\r
5247 #define ENET_MAC_PMT_CRTL_STAT_RWKPFE_SHIFT (10U)
\r
5248 /*! RWKPFE - Remote Wake-up Packet Forwarding Enable When this bit is set along with RWKPKTEN, the
\r
5249 * MAC receiver drops all received frames until it receives the expected wake-up frame.
\r
5251 #define ENET_MAC_PMT_CRTL_STAT_RWKPFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPFE_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPFE_MASK)
\r
5252 #define ENET_MAC_PMT_CRTL_STAT_RWKPTR_MASK (0x1F000000U)
\r
5253 #define ENET_MAC_PMT_CRTL_STAT_RWKPTR_SHIFT (24U)
\r
5254 /*! RWKPTR - Remote Wake-up FIFO Pointer This field gives the current value (0 to 7) of the Remote
\r
5255 * Wake-up Packet Filter register pointer.
\r
5257 #define ENET_MAC_PMT_CRTL_STAT_RWKPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPTR_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPTR_MASK)
\r
5258 #define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_MASK (0x80000000U)
\r
5259 #define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_SHIFT (31U)
\r
5260 /*! RWKFILTRST - Remote Wake-Up Packet Filter Register Pointer Reset When this bit is set, the
\r
5261 * remote wake-up packet filter register pointer is reset to 3'b000.
\r
5263 #define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_MASK)
\r
5266 /*! @name MAC_RWAKE_FRFLT - Remote wake-up frame filter */
\r
5268 #define ENET_MAC_RWAKE_FRFLT_ADDR_MASK (0xFFFFFFFFU)
\r
5269 #define ENET_MAC_RWAKE_FRFLT_ADDR_SHIFT (0U)
\r
5270 /*! ADDR - WKUPFMFILTER address.
\r
5272 #define ENET_MAC_RWAKE_FRFLT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RWAKE_FRFLT_ADDR_SHIFT)) & ENET_MAC_RWAKE_FRFLT_ADDR_MASK)
\r
5275 /*! @name MAC_LPI_CTRL_STAT - LPI Control and Status Register */
\r
5277 #define ENET_MAC_LPI_CTRL_STAT_TLPIEN_MASK (0x1U)
\r
5278 #define ENET_MAC_LPI_CTRL_STAT_TLPIEN_SHIFT (0U)
\r
5279 /*! TLPIEN - Transmit LPI Entry When this bit is set, it indicates that the MAC Transmitter has
\r
5280 * entered the LPI state because of the setting of the LPIEN bit.
\r
5282 #define ENET_MAC_LPI_CTRL_STAT_TLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIEN_MASK)
\r
5283 #define ENET_MAC_LPI_CTRL_STAT_TLPIEX_MASK (0x2U)
\r
5284 #define ENET_MAC_LPI_CTRL_STAT_TLPIEX_SHIFT (1U)
\r
5285 /*! TLPIEX - Transmit LPI Exit When this bit is set, it indicates that the MAC transmitter exited
\r
5286 * the LPI state after the application cleared the LPIEN bit and the LPI TW Timer has expired.
\r
5288 #define ENET_MAC_LPI_CTRL_STAT_TLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIEX_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIEX_MASK)
\r
5289 #define ENET_MAC_LPI_CTRL_STAT_RLPIEN_MASK (0x4U)
\r
5290 #define ENET_MAC_LPI_CTRL_STAT_RLPIEN_SHIFT (2U)
\r
5291 /*! RLPIEN - Receive LPI Entry When this bit is set, it indicates that the MAC Receiver has received
\r
5292 * an LPI pattern and entered the LPI state.
\r
5294 #define ENET_MAC_LPI_CTRL_STAT_RLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIEN_MASK)
\r
5295 #define ENET_MAC_LPI_CTRL_STAT_RLPIEX_MASK (0x8U)
\r
5296 #define ENET_MAC_LPI_CTRL_STAT_RLPIEX_SHIFT (3U)
\r
5297 /*! RLPIEX - Receive LPI Exit When this bit is set, it indicates that the MAC Receiver has stopped
\r
5298 * receiving the LPI pattern on the MII interface, exited the LPI state, and resumed the normal
\r
5301 #define ENET_MAC_LPI_CTRL_STAT_RLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIEX_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIEX_MASK)
\r
5302 #define ENET_MAC_LPI_CTRL_STAT_TLPIST_MASK (0x100U)
\r
5303 #define ENET_MAC_LPI_CTRL_STAT_TLPIST_SHIFT (8U)
\r
5304 /*! TLPIST - Transmit LPI State When this bit is set, it indicates that the MAC is transmitting the LPI pattern on the MII interface.
\r
5306 #define ENET_MAC_LPI_CTRL_STAT_TLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIST_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIST_MASK)
\r
5307 #define ENET_MAC_LPI_CTRL_STAT_RLPIST_MASK (0x200U)
\r
5308 #define ENET_MAC_LPI_CTRL_STAT_RLPIST_SHIFT (9U)
\r
5309 /*! RLPIST - Receive LPI State When this bit is set, it indicates that the MAC is receiving the LPI pattern on the MII interface.
\r
5311 #define ENET_MAC_LPI_CTRL_STAT_RLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIST_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIST_MASK)
\r
5312 #define ENET_MAC_LPI_CTRL_STAT_LPIEN_MASK (0x10000U)
\r
5313 #define ENET_MAC_LPI_CTRL_STAT_LPIEN_SHIFT (16U)
\r
5314 /*! LPIEN - LPI Enable When this bit is set, it instructs the MAC Transmitter to enter the LPI state.
\r
5316 #define ENET_MAC_LPI_CTRL_STAT_LPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPIEN_MASK)
\r
5317 #define ENET_MAC_LPI_CTRL_STAT_PLS_MASK (0x20000U)
\r
5318 #define ENET_MAC_LPI_CTRL_STAT_PLS_SHIFT (17U)
\r
5319 /*! PLS - PHY Link Status This bit indicates the link status of the PHY.
\r
5321 #define ENET_MAC_LPI_CTRL_STAT_PLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_PLS_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_PLS_MASK)
\r
5322 #define ENET_MAC_LPI_CTRL_STAT_LPITXA_MASK (0x80000U)
\r
5323 #define ENET_MAC_LPI_CTRL_STAT_LPITXA_SHIFT (19U)
\r
5324 /*! LPITXA - LPI Tx Automate This bit controls the behavior of the MAC when it is entering or coming
\r
5325 * out of the LPI mode on the Transmit side.
\r
5327 #define ENET_MAC_LPI_CTRL_STAT_LPITXA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPITXA_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPITXA_MASK)
\r
5328 #define ENET_MAC_LPI_CTRL_STAT_LPIATE_MASK (0x100000U)
\r
5329 #define ENET_MAC_LPI_CTRL_STAT_LPIATE_SHIFT (20U)
\r
5330 /*! LPIATE - LPI Timer Enable This bit controls the automatic entry of the MAC Transmitter into and exit out of the LPI state.
\r
5332 #define ENET_MAC_LPI_CTRL_STAT_LPIATE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPIATE_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPIATE_MASK)
\r
5333 #define ENET_MAC_LPI_CTRL_STAT_LPITCSE_MASK (0x200000U)
\r
5334 #define ENET_MAC_LPI_CTRL_STAT_LPITCSE_SHIFT (21U)
\r
5335 /*! LPITCSE - LPI Tx Clock Stop Enable When this bit is set, the MAC asserts LPI Tx Clock Gating
\r
5336 * Control signal high after it enters Tx LPI mode to indicate that the Tx clock to MAC can be
\r
5339 #define ENET_MAC_LPI_CTRL_STAT_LPITCSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPITCSE_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPITCSE_MASK)
\r
5342 /*! @name MAC_LPI_TIMER_CTRL - LPI Timers Control register */
\r
5344 #define ENET_MAC_LPI_TIMER_CTRL_TWT_MASK (0xFFFFU)
\r
5345 #define ENET_MAC_LPI_TIMER_CTRL_TWT_SHIFT (0U)
\r
5346 /*! TWT - LPI TW Timer This field specifies the minimum time (in microseconds) for which the MAC
\r
5347 * waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal
\r
5350 #define ENET_MAC_LPI_TIMER_CTRL_TWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_TIMER_CTRL_TWT_SHIFT)) & ENET_MAC_LPI_TIMER_CTRL_TWT_MASK)
\r
5351 #define ENET_MAC_LPI_TIMER_CTRL_LST_MASK (0x3FF0000U)
\r
5352 #define ENET_MAC_LPI_TIMER_CTRL_LST_SHIFT (16U)
\r
5353 /*! LST - LPI LS Timer This field specifies the minimum time (in milliseconds) for which the link
\r
5354 * status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY.
\r
5356 #define ENET_MAC_LPI_TIMER_CTRL_LST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_TIMER_CTRL_LST_SHIFT)) & ENET_MAC_LPI_TIMER_CTRL_LST_MASK)
\r
5359 /*! @name MAC_LPI_ENTR_TIMR - LPI entry Timer register */
\r
5361 #define ENET_MAC_LPI_ENTR_TIMR_LPIET_MASK (0xFFFF8U)
\r
5362 #define ENET_MAC_LPI_ENTR_TIMR_LPIET_SHIFT (3U)
\r
5363 /*! LPIET - LPI Entry Timer This field specifies the time in microseconds the MAC will wait to enter
\r
5364 * LPI mode, after it has transmitted all the frames.
\r
5366 #define ENET_MAC_LPI_ENTR_TIMR_LPIET(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_ENTR_TIMR_LPIET_SHIFT)) & ENET_MAC_LPI_ENTR_TIMR_LPIET_MASK)
\r
5369 /*! @name MAC_1US_TIC_COUNTR - */
\r
5371 #define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_MASK (0xFFFU)
\r
5372 #define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_SHIFT (0U)
\r
5373 /*! TIC_1US_CNTR - 1US TIC Counter The application must program this counter so that the number of clock cycles of CSR clock is 1us.
\r
5375 #define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_SHIFT)) & ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_MASK)
\r
5378 /*! @name MAC_VERSION - MAC version register */
\r
5380 #define ENET_MAC_VERSION_SNPVER_MASK (0xFFU)
\r
5381 #define ENET_MAC_VERSION_SNPVER_SHIFT (0U)
\r
5382 /*! SNPVER - NXP defined version.
\r
5384 #define ENET_MAC_VERSION_SNPVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VERSION_SNPVER_SHIFT)) & ENET_MAC_VERSION_SNPVER_MASK)
\r
5385 #define ENET_MAC_VERSION_USERVER_MASK (0xFF00U)
\r
5386 #define ENET_MAC_VERSION_USERVER_SHIFT (8U)
\r
5387 /*! USERVER - User defined version.
\r
5389 #define ENET_MAC_VERSION_USERVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VERSION_USERVER_SHIFT)) & ENET_MAC_VERSION_USERVER_MASK)
\r
5392 /*! @name MAC_DBG - MAC debug register */
\r
5394 #define ENET_MAC_DBG_REPESTS_MASK (0x1U)
\r
5395 #define ENET_MAC_DBG_REPESTS_SHIFT (0U)
\r
5396 /*! REPESTS - MAC MII Receive Protocol Engine Status When this bit is set, it indicates that the MAC
\r
5397 * MII receive protocol engine is actively receiving data, and it is not in the Idle state.
\r
5399 #define ENET_MAC_DBG_REPESTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_REPESTS_SHIFT)) & ENET_MAC_DBG_REPESTS_MASK)
\r
5400 #define ENET_MAC_DBG_RFCFCSTS_MASK (0x6U)
\r
5401 #define ENET_MAC_DBG_RFCFCSTS_SHIFT (1U)
\r
5402 /*! RFCFCSTS - MAC Receive Packet Controller FIFO Status When this bit is set, this field indicates
\r
5403 * the active state of the small FIFO Read and Write controllers of the MAC Receive Packet
\r
5404 * Controller module.
\r
5406 #define ENET_MAC_DBG_RFCFCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_RFCFCSTS_SHIFT)) & ENET_MAC_DBG_RFCFCSTS_MASK)
\r
5407 #define ENET_MAC_DBG_TPESTS_MASK (0x10000U)
\r
5408 #define ENET_MAC_DBG_TPESTS_SHIFT (16U)
\r
5409 /*! TPESTS - MAC MII Transmit Protocol Engine Status When this bit is set, it indicates that the MAC
\r
5410 * or MII transmit protocol engine is actively transmitting data, and it is not in the Idle
\r
5413 #define ENET_MAC_DBG_TPESTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_TPESTS_SHIFT)) & ENET_MAC_DBG_TPESTS_MASK)
\r
5414 #define ENET_MAC_DBG_TFCSTS_MASK (0x60000U)
\r
5415 #define ENET_MAC_DBG_TFCSTS_SHIFT (17U)
\r
5416 /*! TFCSTS - MAC Transmit Packet Controller Status This field indicates the state of the MAC Transmit Packet Controller module.
\r
5418 #define ENET_MAC_DBG_TFCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_TFCSTS_SHIFT)) & ENET_MAC_DBG_TFCSTS_MASK)
\r
5421 /*! @name MAC_HW_FEAT - MAC hardware feature register 0x0201 */
\r
5423 #define ENET_MAC_HW_FEAT_MIISEL_MASK (0x1U)
\r
5424 #define ENET_MAC_HW_FEAT_MIISEL_SHIFT (0U)
\r
5425 /*! MIISEL - 10 or 100 Mbps Support.
\r
5427 #define ENET_MAC_HW_FEAT_MIISEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MIISEL_SHIFT)) & ENET_MAC_HW_FEAT_MIISEL_MASK)
\r
5428 #define ENET_MAC_HW_FEAT_RXFIFOSIZE_MASK (0x1FU)
\r
5429 #define ENET_MAC_HW_FEAT_RXFIFOSIZE_SHIFT (0U)
\r
5430 /*! RXFIFOSIZE - MTL Receive FIFO Size.
\r
5432 #define ENET_MAC_HW_FEAT_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXFIFOSIZE_SHIFT)) & ENET_MAC_HW_FEAT_RXFIFOSIZE_MASK)
\r
5433 #define ENET_MAC_HW_FEAT_RXQCNT_MASK (0xFU)
\r
5434 #define ENET_MAC_HW_FEAT_RXQCNT_SHIFT (0U)
\r
5435 /*! RXQCNT - Number of MTL Receive Queues.
\r
5437 #define ENET_MAC_HW_FEAT_RXQCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXQCNT_SHIFT)) & ENET_MAC_HW_FEAT_RXQCNT_MASK)
\r
5438 #define ENET_MAC_HW_FEAT_HDSEL_MASK (0x4U)
\r
5439 #define ENET_MAC_HW_FEAT_HDSEL_SHIFT (2U)
\r
5440 /*! HDSEL - Half-duplex Support.
\r
5442 #define ENET_MAC_HW_FEAT_HDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_HDSEL_SHIFT)) & ENET_MAC_HW_FEAT_HDSEL_MASK)
\r
5443 #define ENET_MAC_HW_FEAT_VLHASH_MASK (0x10U)
\r
5444 #define ENET_MAC_HW_FEAT_VLHASH_SHIFT (4U)
\r
5445 /*! VLHASH - Hash Table Based Filtering option.
\r
5447 #define ENET_MAC_HW_FEAT_VLHASH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_VLHASH_SHIFT)) & ENET_MAC_HW_FEAT_VLHASH_MASK)
\r
5448 #define ENET_MAC_HW_FEAT_SMASEL_MASK (0x20U)
\r
5449 #define ENET_MAC_HW_FEAT_SMASEL_SHIFT (5U)
\r
5450 /*! SMASEL - SMA (MDIO) Interface.
\r
5452 #define ENET_MAC_HW_FEAT_SMASEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_SMASEL_SHIFT)) & ENET_MAC_HW_FEAT_SMASEL_MASK)
\r
5453 #define ENET_MAC_HW_FEAT_RWKSEL_MASK (0x40U)
\r
5454 #define ENET_MAC_HW_FEAT_RWKSEL_SHIFT (6U)
\r
5455 /*! RWKSEL - PMT Remote Wake-up Packet Detection.
\r
5457 #define ENET_MAC_HW_FEAT_RWKSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RWKSEL_SHIFT)) & ENET_MAC_HW_FEAT_RWKSEL_MASK)
\r
5458 #define ENET_MAC_HW_FEAT_TXFIFOSIZE_MASK (0x7C0U)
\r
5459 #define ENET_MAC_HW_FEAT_TXFIFOSIZE_SHIFT (6U)
\r
5460 /*! TXFIFOSIZE - MTL Transmit FIFO Size.
\r
5462 #define ENET_MAC_HW_FEAT_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXFIFOSIZE_SHIFT)) & ENET_MAC_HW_FEAT_TXFIFOSIZE_MASK)
\r
5463 #define ENET_MAC_HW_FEAT_TXQCNT_MASK (0x3C0U)
\r
5464 #define ENET_MAC_HW_FEAT_TXQCNT_SHIFT (6U)
\r
5465 /*! TXQCNT - Number of MTL Transmit Queues.
\r
5467 #define ENET_MAC_HW_FEAT_TXQCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXQCNT_SHIFT)) & ENET_MAC_HW_FEAT_TXQCNT_MASK)
\r
5468 #define ENET_MAC_HW_FEAT_MGKSEL_MASK (0x80U)
\r
5469 #define ENET_MAC_HW_FEAT_MGKSEL_SHIFT (7U)
\r
5470 /*! MGKSEL - PMT magic packet detection.
\r
5472 #define ENET_MAC_HW_FEAT_MGKSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MGKSEL_SHIFT)) & ENET_MAC_HW_FEAT_MGKSEL_MASK)
\r
5473 #define ENET_MAC_HW_FEAT_MMCSEL_MASK (0x100U)
\r
5474 #define ENET_MAC_HW_FEAT_MMCSEL_SHIFT (8U)
\r
5475 /*! MMCSEL - RMON Module Enable.
\r
5477 #define ENET_MAC_HW_FEAT_MMCSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MMCSEL_SHIFT)) & ENET_MAC_HW_FEAT_MMCSEL_MASK)
\r
5478 #define ENET_MAC_HW_FEAT_ARPOFFSEL_MASK (0x200U)
\r
5479 #define ENET_MAC_HW_FEAT_ARPOFFSEL_SHIFT (9U)
\r
5480 /*! ARPOFFSEL - ARP Offload Enabled.
\r
5482 #define ENET_MAC_HW_FEAT_ARPOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ARPOFFSEL_SHIFT)) & ENET_MAC_HW_FEAT_ARPOFFSEL_MASK)
\r
5483 #define ENET_MAC_HW_FEAT_OSTEN_MASK (0x800U)
\r
5484 #define ENET_MAC_HW_FEAT_OSTEN_SHIFT (11U)
\r
5485 /*! OSTEN - One-Step Timestamping Feature.
\r
5487 #define ENET_MAC_HW_FEAT_OSTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_OSTEN_SHIFT)) & ENET_MAC_HW_FEAT_OSTEN_MASK)
\r
5488 #define ENET_MAC_HW_FEAT_PTOEN_MASK (0x1000U)
\r
5489 #define ENET_MAC_HW_FEAT_PTOEN_SHIFT (12U)
\r
5490 /*! PTOEN - PTP OffLoad Feature.
\r
5492 #define ENET_MAC_HW_FEAT_PTOEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_PTOEN_SHIFT)) & ENET_MAC_HW_FEAT_PTOEN_MASK)
\r
5493 #define ENET_MAC_HW_FEAT_RXCHCNT_MASK (0xF000U)
\r
5494 #define ENET_MAC_HW_FEAT_RXCHCNT_SHIFT (12U)
\r
5495 /*! RXCHCNT - Number of DMA Receive Channels.
\r
5497 #define ENET_MAC_HW_FEAT_RXCHCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXCHCNT_SHIFT)) & ENET_MAC_HW_FEAT_RXCHCNT_MASK)
\r
5498 #define ENET_MAC_HW_FEAT_TSSEL_MASK (0x1000U)
\r
5499 #define ENET_MAC_HW_FEAT_TSSEL_SHIFT (12U)
\r
5500 /*! TSSEL - IEEE 1588-2008 Timestamp support .
\r
5502 #define ENET_MAC_HW_FEAT_TSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSSEL_SHIFT)) & ENET_MAC_HW_FEAT_TSSEL_MASK)
\r
5503 #define ENET_MAC_HW_FEAT_ADVTHWORD_MASK (0x2000U)
\r
5504 #define ENET_MAC_HW_FEAT_ADVTHWORD_SHIFT (13U)
\r
5505 /*! ADVTHWORD - IEEE 1588 High Word Register Feature.
\r
5507 #define ENET_MAC_HW_FEAT_ADVTHWORD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ADVTHWORD_SHIFT)) & ENET_MAC_HW_FEAT_ADVTHWORD_MASK)
\r
5508 #define ENET_MAC_HW_FEAT_EEESEL_MASK (0x2000U)
\r
5509 #define ENET_MAC_HW_FEAT_EEESEL_SHIFT (13U)
\r
5510 /*! EEESEL - Energy Efficient Ethernet Support .
\r
5512 #define ENET_MAC_HW_FEAT_EEESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_EEESEL_SHIFT)) & ENET_MAC_HW_FEAT_EEESEL_MASK)
\r
5513 #define ENET_MAC_HW_FEAT_ADDR64_MASK (0xC000U)
\r
5514 #define ENET_MAC_HW_FEAT_ADDR64_SHIFT (14U)
\r
5515 /*! ADDR64 - Address width.
\r
5517 #define ENET_MAC_HW_FEAT_ADDR64(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ADDR64_SHIFT)) & ENET_MAC_HW_FEAT_ADDR64_MASK)
\r
5518 #define ENET_MAC_HW_FEAT_TXCOESEL_MASK (0x4000U)
\r
5519 #define ENET_MAC_HW_FEAT_TXCOESEL_SHIFT (14U)
\r
5520 /*! TXCOESEL - Transmit Checksum Offload Support.
\r
5522 #define ENET_MAC_HW_FEAT_TXCOESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXCOESEL_SHIFT)) & ENET_MAC_HW_FEAT_TXCOESEL_MASK)
\r
5523 #define ENET_MAC_HW_FEAT_DCBEN_MASK (0x10000U)
\r
5524 #define ENET_MAC_HW_FEAT_DCBEN_SHIFT (16U)
\r
5525 /*! DCBEN - Data Center Bridging feature.
\r
5527 #define ENET_MAC_HW_FEAT_DCBEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_DCBEN_SHIFT)) & ENET_MAC_HW_FEAT_DCBEN_MASK)
\r
5528 #define ENET_MAC_HW_FEAT_RXCOESEL_MASK (0x10000U)
\r
5529 #define ENET_MAC_HW_FEAT_RXCOESEL_SHIFT (16U)
\r
5530 /*! RXCOESEL - Receive Checksum Offload Support.
\r
5532 #define ENET_MAC_HW_FEAT_RXCOESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXCOESEL_SHIFT)) & ENET_MAC_HW_FEAT_RXCOESEL_MASK)
\r
5533 #define ENET_MAC_HW_FEAT_SPEN_MASK (0x20000U)
\r
5534 #define ENET_MAC_HW_FEAT_SPEN_SHIFT (17U)
\r
5535 /*! SPEN - Split Header Structure feature.
\r
5537 #define ENET_MAC_HW_FEAT_SPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_SPEN_SHIFT)) & ENET_MAC_HW_FEAT_SPEN_MASK)
\r
5538 #define ENET_MAC_HW_FEAT_TSOEN_MASK (0x40000U)
\r
5539 #define ENET_MAC_HW_FEAT_TSOEN_SHIFT (18U)
\r
5540 /*! TSOEN - TCP Segment Offload Feature.
\r
5542 #define ENET_MAC_HW_FEAT_TSOEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSOEN_SHIFT)) & ENET_MAC_HW_FEAT_TSOEN_MASK)
\r
5543 #define ENET_MAC_HW_FEAT_TXCHCNT_MASK (0x3C0000U)
\r
5544 #define ENET_MAC_HW_FEAT_TXCHCNT_SHIFT (18U)
\r
5545 /*! TXCHCNT - Number of DMA Transmit Channels.
\r
5547 #define ENET_MAC_HW_FEAT_TXCHCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXCHCNT_SHIFT)) & ENET_MAC_HW_FEAT_TXCHCNT_MASK)
\r
5548 #define ENET_MAC_HW_FEAT_DBGMEMA_MASK (0x80000U)
\r
5549 #define ENET_MAC_HW_FEAT_DBGMEMA_SHIFT (19U)
\r
5550 /*! DBGMEMA - DMA Debug Register Feature.
\r
5552 #define ENET_MAC_HW_FEAT_DBGMEMA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_DBGMEMA_SHIFT)) & ENET_MAC_HW_FEAT_DBGMEMA_MASK)
\r
5553 #define ENET_MAC_HW_FEAT_AVSEL_MASK (0x100000U)
\r
5554 #define ENET_MAC_HW_FEAT_AVSEL_SHIFT (20U)
\r
5555 /*! AVSEL - Audio Video Bridging Feature.
\r
5557 #define ENET_MAC_HW_FEAT_AVSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_AVSEL_SHIFT)) & ENET_MAC_HW_FEAT_AVSEL_MASK)
\r
5558 #define ENET_MAC_HW_FEAT_LPMODEEN_MASK (0x800000U)
\r
5559 #define ENET_MAC_HW_FEAT_LPMODEEN_SHIFT (23U)
\r
5560 /*! LPMODEEN - Low Power Mode Feature Support .
\r
5562 #define ENET_MAC_HW_FEAT_LPMODEEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_LPMODEEN_SHIFT)) & ENET_MAC_HW_FEAT_LPMODEEN_MASK)
\r
5563 #define ENET_MAC_HW_FEAT_HASHTBLSZ_MASK (0x3000000U)
\r
5564 #define ENET_MAC_HW_FEAT_HASHTBLSZ_SHIFT (24U)
\r
5565 /*! HASHTBLSZ - Hash Table Size.
\r
5567 #define ENET_MAC_HW_FEAT_HASHTBLSZ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_HASHTBLSZ_SHIFT)) & ENET_MAC_HW_FEAT_HASHTBLSZ_MASK)
\r
5568 #define ENET_MAC_HW_FEAT_PPSOUTNUM_MASK (0x7000000U)
\r
5569 #define ENET_MAC_HW_FEAT_PPSOUTNUM_SHIFT (24U)
\r
5570 /*! PPSOUTNUM - Number of PPS Outputs.
\r
5572 #define ENET_MAC_HW_FEAT_PPSOUTNUM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_PPSOUTNUM_SHIFT)) & ENET_MAC_HW_FEAT_PPSOUTNUM_MASK)
\r
5573 #define ENET_MAC_HW_FEAT_TSSTSSEL_MASK (0x6000000U)
\r
5574 #define ENET_MAC_HW_FEAT_TSSTSSEL_SHIFT (25U)
\r
5575 /*! TSSTSSEL - Timestamp System Time Source.
\r
5577 #define ENET_MAC_HW_FEAT_TSSTSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSSTSSEL_SHIFT)) & ENET_MAC_HW_FEAT_TSSTSSEL_MASK)
\r
5578 #define ENET_MAC_HW_FEAT_L3_L4_FILTER_MASK (0x78000000U)
\r
5579 #define ENET_MAC_HW_FEAT_L3_L4_FILTER_SHIFT (27U)
\r
5580 /*! L3_L4_FILTER - Total Number of L3 and L4 Filters .
\r
5582 #define ENET_MAC_HW_FEAT_L3_L4_FILTER(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_L3_L4_FILTER_SHIFT)) & ENET_MAC_HW_FEAT_L3_L4_FILTER_MASK)
\r
5583 #define ENET_MAC_HW_FEAT_ACTPHYSEL_MASK (0x70000000U)
\r
5584 #define ENET_MAC_HW_FEAT_ACTPHYSEL_SHIFT (28U)
\r
5585 /*! ACTPHYSEL - Active PHY Selected.
\r
5587 #define ENET_MAC_HW_FEAT_ACTPHYSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ACTPHYSEL_SHIFT)) & ENET_MAC_HW_FEAT_ACTPHYSEL_MASK)
\r
5588 #define ENET_MAC_HW_FEAT_AUXSNAPNUM_MASK (0x70000000U)
\r
5589 #define ENET_MAC_HW_FEAT_AUXSNAPNUM_SHIFT (28U)
\r
5590 /*! AUXSNAPNUM - Number of Auxiliary Snapshot Inputs.
\r
5592 #define ENET_MAC_HW_FEAT_AUXSNAPNUM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_AUXSNAPNUM_SHIFT)) & ENET_MAC_HW_FEAT_AUXSNAPNUM_MASK)
\r
5595 /* The count of ENET_MAC_HW_FEAT */
\r
5596 #define ENET_MAC_HW_FEAT_COUNT (3U)
\r
5598 /*! @name MAC_MDIO_ADDR - MIDO address Register */
\r
5600 #define ENET_MAC_MDIO_ADDR_MB_MASK (0x1U)
\r
5601 #define ENET_MAC_MDIO_ADDR_MB_SHIFT (0U)
\r
5602 /*! MB - MII busy.
\r
5604 #define ENET_MAC_MDIO_ADDR_MB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_MB_SHIFT)) & ENET_MAC_MDIO_ADDR_MB_MASK)
\r
5605 #define ENET_MAC_MDIO_ADDR_MOC_MASK (0xCU)
\r
5606 #define ENET_MAC_MDIO_ADDR_MOC_SHIFT (2U)
\r
5607 /*! MOC - MII Operation Command.
\r
5609 #define ENET_MAC_MDIO_ADDR_MOC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_MOC_SHIFT)) & ENET_MAC_MDIO_ADDR_MOC_MASK)
\r
5610 #define ENET_MAC_MDIO_ADDR_CR_MASK (0xF00U)
\r
5611 #define ENET_MAC_MDIO_ADDR_CR_SHIFT (8U)
\r
5612 /*! CR - CSR Clock Range.
\r
5614 #define ENET_MAC_MDIO_ADDR_CR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_CR_SHIFT)) & ENET_MAC_MDIO_ADDR_CR_MASK)
\r
5615 #define ENET_MAC_MDIO_ADDR_NTC_MASK (0x7000U)
\r
5616 #define ENET_MAC_MDIO_ADDR_NTC_SHIFT (12U)
\r
5617 /*! NTC - Number of Training Clocks This field controls the number of trailing clock cycles
\r
5618 * generated on MDC after the end of transmission of MDIO frame.
\r
5620 #define ENET_MAC_MDIO_ADDR_NTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_NTC_SHIFT)) & ENET_MAC_MDIO_ADDR_NTC_MASK)
\r
5621 #define ENET_MAC_MDIO_ADDR_RDA_MASK (0x1F0000U)
\r
5622 #define ENET_MAC_MDIO_ADDR_RDA_SHIFT (16U)
\r
5623 /*! RDA - Register/Device Address These bits select the PHY register in selected PHY device.
\r
5625 #define ENET_MAC_MDIO_ADDR_RDA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_RDA_SHIFT)) & ENET_MAC_MDIO_ADDR_RDA_MASK)
\r
5626 #define ENET_MAC_MDIO_ADDR_PA_MASK (0x3E00000U)
\r
5627 #define ENET_MAC_MDIO_ADDR_PA_SHIFT (21U)
\r
5628 /*! PA - Physical Layer Address This field indicates which PHY devices (out of 32 devices) the MAC is accessing.
\r
5630 #define ENET_MAC_MDIO_ADDR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_PA_SHIFT)) & ENET_MAC_MDIO_ADDR_PA_MASK)
\r
5631 #define ENET_MAC_MDIO_ADDR_BTB_MASK (0x4000000U)
\r
5632 #define ENET_MAC_MDIO_ADDR_BTB_SHIFT (26U)
\r
5633 /*! BTB - Back to Back transactions When this bit is set and the NTC has value greater than 0, then
\r
5634 * the MAC will inform the completion of a read or write command at the end of frame transfer
\r
5635 * (before the trailing clocks are transmitted).
\r
5637 #define ENET_MAC_MDIO_ADDR_BTB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_BTB_SHIFT)) & ENET_MAC_MDIO_ADDR_BTB_MASK)
\r
5638 #define ENET_MAC_MDIO_ADDR_PSE_MASK (0x8000000U)
\r
5639 #define ENET_MAC_MDIO_ADDR_PSE_SHIFT (27U)
\r
5640 /*! PSE - Preamble Suppression Enable When this bit is set, the SMA will suppress the 32-bit
\r
5641 * preamble and transmit MDIO frames with only 1 preamble bit.
\r
5643 #define ENET_MAC_MDIO_ADDR_PSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_PSE_SHIFT)) & ENET_MAC_MDIO_ADDR_PSE_MASK)
\r
5646 /*! @name MAC_MDIO_DATA - MDIO Data register */
\r
5648 #define ENET_MAC_MDIO_DATA_MD_MASK (0xFFFFU)
\r
5649 #define ENET_MAC_MDIO_DATA_MD_SHIFT (0U)
\r
5650 /*! MD - MII Data This field contains the 16-bit data value read from the PHY after a Management
\r
5651 * Read operation or the 16-bit data value to be written to the PHY before a Management Write
\r
5654 #define ENET_MAC_MDIO_DATA_MD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_DATA_MD_SHIFT)) & ENET_MAC_MDIO_DATA_MD_MASK)
\r
5657 /*! @name MAC_ADDR_HIGH - MAC address0 high register */
\r
5659 #define ENET_MAC_ADDR_HIGH_A47_32_MASK (0xFFFFU)
\r
5660 #define ENET_MAC_ADDR_HIGH_A47_32_SHIFT (0U)
\r
5661 /*! A47_32 - MAC Address0 [47:32] This field contains the upper 16 bits (47:32) of the 6-byte first MAC address.
\r
5663 #define ENET_MAC_ADDR_HIGH_A47_32(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_A47_32_SHIFT)) & ENET_MAC_ADDR_HIGH_A47_32_MASK)
\r
5664 #define ENET_MAC_ADDR_HIGH_DCS_MASK (0x10000U)
\r
5665 #define ENET_MAC_ADDR_HIGH_DCS_SHIFT (16U)
\r
5666 /*! DCS - DMA Channel Select This field contains the DMA Channel number to which the Rx packet whose
\r
5667 * DA matches the MAC Address content is routed.
\r
5669 #define ENET_MAC_ADDR_HIGH_DCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_DCS_SHIFT)) & ENET_MAC_ADDR_HIGH_DCS_MASK)
\r
5670 #define ENET_MAC_ADDR_HIGH_AE_MASK (0x80000000U)
\r
5671 #define ENET_MAC_ADDR_HIGH_AE_SHIFT (31U)
\r
5672 /*! AE - Address Enable.
\r
5674 #define ENET_MAC_ADDR_HIGH_AE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_AE_SHIFT)) & ENET_MAC_ADDR_HIGH_AE_MASK)
\r
5677 /*! @name MAC_ADDR_LOW - MAC address0 low register */
\r
5679 #define ENET_MAC_ADDR_LOW_A31_0_MASK (0xFFFFFFFFU)
\r
5680 #define ENET_MAC_ADDR_LOW_A31_0_SHIFT (0U)
\r
5681 /*! A31_0 - MAC Address0 [31:0] This field contains the lower 32 bits of the 6-byte first MAC address.
\r
5683 #define ENET_MAC_ADDR_LOW_A31_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_LOW_A31_0_SHIFT)) & ENET_MAC_ADDR_LOW_A31_0_MASK)
\r
5686 /*! @name MAC_TIMESTAMP_CTRL - Time stamp control register */
\r
5688 #define ENET_MAC_TIMESTAMP_CTRL_TSENA_MASK (0x1U)
\r
5689 #define ENET_MAC_TIMESTAMP_CTRL_TSENA_SHIFT (0U)
\r
5690 /*! TSENA - Enable Timestamp When this bit is set, the timestamp is added for Transmit and Receive packets.
\r
5692 #define ENET_MAC_TIMESTAMP_CTRL_TSENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENA_MASK)
\r
5693 #define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_MASK (0x2U)
\r
5694 #define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_SHIFT (1U)
\r
5695 /*! TSCFUPDT - Fine or Coarse Timestamp Update When this bit is set, the Fine method is used to update system timestamp.
\r
5697 #define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_MASK)
\r
5698 #define ENET_MAC_TIMESTAMP_CTRL_TSINIT_MASK (0x4U)
\r
5699 #define ENET_MAC_TIMESTAMP_CTRL_TSINIT_SHIFT (2U)
\r
5700 /*! TSINIT - Initialize Timestamp When this bit is set, the system time is initialized (overwritten)
\r
5701 * with the value specified in the MAC Register 80 (System Time Seconds Update.
\r
5703 #define ENET_MAC_TIMESTAMP_CTRL_TSINIT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSINIT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSINIT_MASK)
\r
5704 #define ENET_MAC_TIMESTAMP_CTRL_TSUPDT_MASK (0x8U)
\r
5705 #define ENET_MAC_TIMESTAMP_CTRL_TSUPDT_SHIFT (3U)
\r
5706 /*! TSUPDT - Update Timestamp When this bit is set, the system time is updated (added or subtracted)
\r
5707 * with the value specified in MAC System Time Seconds Update Table 753 and MAC System Time
\r
5708 * Nanoseconds Update Table 754.
\r
5710 #define ENET_MAC_TIMESTAMP_CTRL_TSUPDT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSUPDT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSUPDT_MASK)
\r
5711 #define ENET_MAC_TIMESTAMP_CTRL_TSTRIG_MASK (0x10U)
\r
5712 #define ENET_MAC_TIMESTAMP_CTRL_TSTRIG_SHIFT (4U)
\r
5713 /*! TSTRIG - Enable Timestamp Interrupt Trigger When this bit is set, the timestamp interrupt is
\r
5714 * generated when the System Time becomes greater than the value written in the Target Time register.
\r
5716 #define ENET_MAC_TIMESTAMP_CTRL_TSTRIG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSTRIG_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSTRIG_MASK)
\r
5717 #define ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK (0x20U)
\r
5718 #define ENET_MAC_TIMESTAMP_CTRL_TADDREG_SHIFT (5U)
\r
5719 /*! TADDREG - Update Addend Register When this bit is set, the content of the Timestamp Addend
\r
5720 * register is updated in the PTP block for fine correction.
\r
5722 #define ENET_MAC_TIMESTAMP_CTRL_TADDREG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TADDREG_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK)
\r
5723 #define ENET_MAC_TIMESTAMP_CTRL_TSENALL_MASK (0x100U)
\r
5724 #define ENET_MAC_TIMESTAMP_CTRL_TSENALL_SHIFT (8U)
\r
5725 /*! TSENALL - Enable Timestamp for All Packets When this bit is set, the timestamp snapshot is
\r
5726 * enabled for all packets received by the MAC.
\r
5728 #define ENET_MAC_TIMESTAMP_CTRL_TSENALL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENALL_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENALL_MASK)
\r
5729 #define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK (0x200U)
\r
5730 #define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_SHIFT (9U)
\r
5731 /*! TSCTRLSSR - Timestamp Digital or Binary Rollover Control When this bit is set, the Timestamp Low
\r
5732 * register rolls over after 0x3B9AC9FF value (that is, 1 nanosecond accuracy) and increments
\r
5733 * the timestamp (High) seconds.
\r
5735 #define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK)
\r
5736 #define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_MASK (0x400U)
\r
5737 #define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_SHIFT (10U)
\r
5738 /*! TSVER2ENA - Enable PTP Packet Processing for Version 2 Format When this bit is set, the IEEE
\r
5739 * 1588 version 2 format is used to process the PTP packets.
\r
5741 #define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_MASK)
\r
5742 #define ENET_MAC_TIMESTAMP_CTRL_TSIPENA_MASK (0x800U)
\r
5743 #define ENET_MAC_TIMESTAMP_CTRL_TSIPENA_SHIFT (11U)
\r
5744 /*! TSIPENA - Enable Processing of PTP over Ethernet Packets When this bit is set, the MAC receiver
\r
5745 * processes the PTP packets encapsulated directly in the Ethernet packets.
\r
5747 #define ENET_MAC_TIMESTAMP_CTRL_TSIPENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPENA_MASK)
\r
5748 #define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_MASK (0x1000U)
\r
5749 #define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_SHIFT (12U)
\r
5750 /*! TSIPV6ENA - Enable Processing of PTP Packets Sent over 1Pv6-UDP When this bit is set, the MAC
\r
5751 * receiver processes the PTP packets encapsulated in IPv6-UDP packets.
\r
5753 #define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_MASK)
\r
5754 #define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_MASK (0x2000U)
\r
5755 #define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_SHIFT (13U)
\r
5756 /*! TSIPV4ENA - Enable Processing of PTP Packets Sent over IPv4-UDP When this bit is set, the MAC
\r
5757 * receiver processes the PTP packets encapsulated in IPv4-UDP packets.
\r
5759 #define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_MASK)
\r
5760 #define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_MASK (0x4000U)
\r
5761 #define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_SHIFT (14U)
\r
5762 /*! TSEVTENA - Enable Timestamp Snapshot for Event Messages When this bit is set, the timestamp
\r
5763 * snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp).
\r
5765 #define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_MASK)
\r
5766 #define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_MASK (0x8000U)
\r
5767 #define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_SHIFT (15U)
\r
5768 /*! TSMSTRENA - Enable Snapshot for Messages Relevant to Master When this bit is set, the snapshot
\r
5769 * is taken only for the messages that are relevant to the master node.
\r
5771 #define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_MASK)
\r
5772 #define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_MASK (0x30000U)
\r
5773 #define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_SHIFT (16U)
\r
5774 /*! SNAPTYPSEL - Select PTP packets for Taking Snapshots These bits, along with Bits 15 and 14,
\r
5775 * decide the set of PTP packet types for which snapshot needs to be taken.
\r
5777 #define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_MASK)
\r
5778 #define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_MASK (0x40000U)
\r
5779 #define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_SHIFT (18U)
\r
5780 /*! TSENMACADDR - Enable MAC Address for PTP Packet Filtering When this bit is set, the DA MAC
\r
5781 * address (that matches any MAC Address register) is used to filter the PTP packets when PTP is
\r
5782 * directly sent over Ethernet.
\r
5784 #define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_MASK)
\r
5785 #define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_MASK (0x1000000U)
\r
5786 #define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_SHIFT (24U)
\r
5787 /*! TXTTSSTSM - Transmit Timestamp Status Mode When this bit is set, the MAC overwrites the earlier
\r
5788 * transmit timestamp status even if it is not read by the software.
\r
5790 #define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_MASK)
\r
5791 #define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_MASK (0x10000000U)
\r
5792 #define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_SHIFT (28U)
\r
5793 /*! AV8021ASMEN - AV 802.
\r
5795 #define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_MASK)
\r
5798 /*! @name MAC_SUB_SCND_INCR - Sub-second increment register */
\r
5800 #define ENET_MAC_SUB_SCND_INCR_SSINC_MASK (0xFF0000U)
\r
5801 #define ENET_MAC_SUB_SCND_INCR_SSINC_SHIFT (16U)
\r
5802 /*! SSINC - Sub-second increment value.
\r
5804 #define ENET_MAC_SUB_SCND_INCR_SSINC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SUB_SCND_INCR_SSINC_SHIFT)) & ENET_MAC_SUB_SCND_INCR_SSINC_MASK)
\r
5807 /*! @name MAC_SYS_TIME_SCND - System time seconds register */
\r
5809 #define ENET_MAC_SYS_TIME_SCND_TSS_MASK (0xFFFFFFFFU)
\r
5810 #define ENET_MAC_SYS_TIME_SCND_TSS_SHIFT (0U)
\r
5811 /*! TSS - Time stamp second The value in this field indicates the current value in seconds of the
\r
5812 * System Time maintained by the MAC.
\r
5814 #define ENET_MAC_SYS_TIME_SCND_TSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_SCND_TSS_SHIFT)) & ENET_MAC_SYS_TIME_SCND_TSS_MASK)
\r
5817 /*! @name MAC_SYS_TIME_NSCND - System time nanoseconds register */
\r
5819 #define ENET_MAC_SYS_TIME_NSCND_TSSS_MASK (0x7FFFFFFFU)
\r
5820 #define ENET_MAC_SYS_TIME_NSCND_TSSS_SHIFT (0U)
\r
5821 /*! TSSS - Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0.
\r
5823 #define ENET_MAC_SYS_TIME_NSCND_TSSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_TSSS_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_TSSS_MASK)
\r
5826 /*! @name MAC_SYS_TIME_SCND_UPD - */
\r
5828 #define ENET_MAC_SYS_TIME_SCND_UPD_TSS_MASK (0xFFFFFFFFU)
\r
5829 #define ENET_MAC_SYS_TIME_SCND_UPD_TSS_SHIFT (0U)
\r
5830 /*! TSS - Time stamp second The value in this field indicates the time, in seconds, to be initialized or added to the system time.
\r
5832 #define ENET_MAC_SYS_TIME_SCND_UPD_TSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_SCND_UPD_TSS_SHIFT)) & ENET_MAC_SYS_TIME_SCND_UPD_TSS_MASK)
\r
5835 /*! @name MAC_SYS_TIME_NSCND_UPD - */
\r
5837 #define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_MASK (0x7FFFFFFFU)
\r
5838 #define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_SHIFT (0U)
\r
5839 /*! TSSS - Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0.
\r
5841 #define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_MASK)
\r
5842 #define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_MASK (0x80000000U)
\r
5843 #define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_SHIFT (31U)
\r
5844 /*! ADDSUB - Add or subtract time When this bit is set, the time value is subtracted with the contents of the update register.
\r
5846 #define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_MASK)
\r
5849 /*! @name MAC_SYS_TIMESTMP_ADDEND - Time stamp addend register */
\r
5851 #define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_MASK (0xFFFFFFFFU)
\r
5852 #define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_SHIFT (0U)
\r
5853 /*! TSAR - Time stamp addend This register indicates the 32-bit time value to be added to the
\r
5854 * Accumulator register to achieve time synchronization.
\r
5856 #define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_SHIFT)) & ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_MASK)
\r
5859 /*! @name MAC_SYS_TIME_HWORD_SCND - */
\r
5861 #define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_MASK (0xFFFFU)
\r
5862 #define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_SHIFT (0U)
\r
5863 /*! TSHWR - Time stamp higher word Contains the most significant 16-bits of the Time stamp seconds value.
\r
5865 #define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_SHIFT)) & ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_MASK)
\r
5868 /*! @name MAC_SYS_TIMESTMP_STAT - Time stamp status register */
\r
5870 #define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_MASK (0x1U)
\r
5871 #define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_SHIFT (0U)
\r
5872 /*! TSSOVF - Time stamp seconds overflow When set, indicates that the seconds value of the Time
\r
5873 * stamp has overflowed beyond 0xFFFF_FFFF.
\r
5875 #define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_SHIFT)) & ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_MASK)
\r
5878 /*! @name MAC_TX_TIMESTAMP_STATUS_NANOSECONDS - Tx timestamp status nanoseconds */
\r
5880 #define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_MASK (0x7FFFFFFFU)
\r
5881 #define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_SHIFT (0U)
\r
5882 /*! TXTSSTSLO - Transmit timestamp status low.
\r
5884 #define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_MASK)
\r
5885 #define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_MASK (0x80000000U)
\r
5886 #define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_SHIFT (31U)
\r
5887 /*! TXTSSTSMIS - Transmit timestamp status missed.
\r
5889 #define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_MASK)
\r
5892 /*! @name MAC_TX_TIMESTAMP_STATUS_SECONDS - Tx timestamp status seconds */
\r
5894 #define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_MASK (0xFFFFFFFFU)
\r
5895 #define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_SHIFT (0U)
\r
5896 /*! TXTSSTSHI - Transmit timestamp status high.
\r
5898 #define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_MASK)
\r
5901 /*! @name MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND - Timestamp ingress correction */
\r
5903 #define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK (0xFFFFFFFFU)
\r
5904 #define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT (0U)
\r
5905 /*! TSIC - Transmit ingress correction.
\r
5907 #define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT)) & ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK)
\r
5910 /*! @name MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND - Timestamp egress correction */
\r
5912 #define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK (0xFFFFFFFFU)
\r
5913 #define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT (0U)
\r
5914 /*! TSEC - Transmit egress correction.
\r
5916 #define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT)) & ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK)
\r
5919 /*! @name MTL_OP_MODE - MTL Operation Mode Register */
\r
5921 #define ENET_MTL_OP_MODE_DTXSTS_MASK (0x2U)
\r
5922 #define ENET_MTL_OP_MODE_DTXSTS_SHIFT (1U)
\r
5923 /*! DTXSTS - Drop Transmit Status When this bit is set, the Tx packet status received from the MAC is dropped in the MTL.
\r
5925 #define ENET_MTL_OP_MODE_DTXSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_DTXSTS_SHIFT)) & ENET_MTL_OP_MODE_DTXSTS_MASK)
\r
5926 #define ENET_MTL_OP_MODE_RAA_MASK (0x4U)
\r
5927 #define ENET_MTL_OP_MODE_RAA_SHIFT (2U)
\r
5928 /*! RAA - Receive Arbitration Algorithm This field is used to select the arbitration algorithm for the Rx side.
\r
5930 #define ENET_MTL_OP_MODE_RAA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_RAA_SHIFT)) & ENET_MTL_OP_MODE_RAA_MASK)
\r
5931 #define ENET_MTL_OP_MODE_SCHALG_MASK (0x60U)
\r
5932 #define ENET_MTL_OP_MODE_SCHALG_SHIFT (5U)
\r
5933 /*! SCHALG - Tx Scheduling Algorithm This field indicates the algorithm for Tx scheduling: 0x00: WRR
\r
5934 * algorithm 0x1: Reserved 0x2: Reserved 0x3: Strict priority algorithm.
\r
5936 #define ENET_MTL_OP_MODE_SCHALG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_SCHALG_SHIFT)) & ENET_MTL_OP_MODE_SCHALG_MASK)
\r
5937 #define ENET_MTL_OP_MODE_CNTPRST_MASK (0x100U)
\r
5938 #define ENET_MTL_OP_MODE_CNTPRST_SHIFT (8U)
\r
5939 /*! CNTPRST - Counters Preset When this bit is set, MTL TxQ0 Underflow register (Table 762) and
\r
5940 * MTL_TxQ1_Underflow (Table 762) registers are initialized/preset to 0x7F0.
\r
5942 #define ENET_MTL_OP_MODE_CNTPRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_CNTPRST_SHIFT)) & ENET_MTL_OP_MODE_CNTPRST_MASK)
\r
5943 #define ENET_MTL_OP_MODE_CNTCLR_MASK (0x200U)
\r
5944 #define ENET_MTL_OP_MODE_CNTCLR_SHIFT (9U)
\r
5945 /*! CNTCLR - Counters Reset When this bit is set, all counters are reset.
\r
5947 #define ENET_MTL_OP_MODE_CNTCLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_CNTCLR_SHIFT)) & ENET_MTL_OP_MODE_CNTCLR_MASK)
\r
5950 /*! @name MTL_INTR_STAT - MTL Interrupt Status register */
\r
5952 #define ENET_MTL_INTR_STAT_Q0IS_MASK (0x1U)
\r
5953 #define ENET_MTL_INTR_STAT_Q0IS_SHIFT (0U)
\r
5954 /*! Q0IS - Queue 0 Interrupt status This bit indicates that there is an interrupt from Queue 0.
\r
5956 #define ENET_MTL_INTR_STAT_Q0IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_INTR_STAT_Q0IS_SHIFT)) & ENET_MTL_INTR_STAT_Q0IS_MASK)
\r
5957 #define ENET_MTL_INTR_STAT_Q1IS_MASK (0x2U)
\r
5958 #define ENET_MTL_INTR_STAT_Q1IS_SHIFT (1U)
\r
5959 /*! Q1IS - Queue 1 Interrupt status This bit indicates that there is an interrupt from Queue 1.
\r
5961 #define ENET_MTL_INTR_STAT_Q1IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_INTR_STAT_Q1IS_SHIFT)) & ENET_MTL_INTR_STAT_Q1IS_MASK)
\r
5964 /*! @name MTL_RXQ_DMA_MAP - MTL Receive Queue and DMA Channel Mapping register */
\r
5966 #define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_MASK (0x1U)
\r
5967 #define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_SHIFT (0U)
\r
5968 /*! Q0MDMACH - Queue 0 Mapped to DMA Channel This field controls the routing of the packet received
\r
5969 * in Queue 0 to the DMA channel: 0: DMA Channel 0 1: DMA Channel 1 This field is valid when the
\r
5970 * Q0DDMACH field is reset.
\r
5972 #define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_MASK)
\r
5973 #define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_MASK (0x10U)
\r
5974 #define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_SHIFT (4U)
\r
5975 /*! Q0DDMACH - Queue 0 Enabled for DA-based DMA Channel Selection When set, this bit indicates that
\r
5976 * the packets received in Queue 0 are routed to a particular DMA channel as decided in the MAC
\r
5977 * Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the
\r
5978 * Ethernet DA address.
\r
5980 #define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_MASK)
\r
5981 #define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_MASK (0x100U)
\r
5982 #define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_SHIFT (8U)
\r
5983 /*! Q1MDMACH - Queue 1 Mapped to DMA Channel This field controls the routing of the received packet
\r
5984 * in Queue 1 to the DMA channel: 0: DMA Channel 0 1: DMA Channel 1 This field is valid when the
\r
5985 * Q1DDMACH field is reset.
\r
5987 #define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_MASK)
\r
5988 #define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_MASK (0x1000U)
\r
5989 #define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_SHIFT (12U)
\r
5990 /*! Q1DDMACH - Queue 1 Enabled for DA-based DMA Channel Selection When set, this bit indicates that
\r
5991 * the packets received in Queue 1 are routed to a particular DMA channel as decided in the MAC
\r
5992 * Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the
\r
5993 * Ethernet DA address.
\r
5995 #define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_MASK)
\r
5998 /*! @name MTL_QUEUE_MTL_TXQX_OP_MODE - MTL TxQx Operation Mode register */
\r
6000 #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_MASK (0x1U)
\r
6001 #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_SHIFT (0U)
\r
6002 /*! FTQ - Flush Transmit Queue When this bit is set, the Tx queue controller logic is reset to its default values.
\r
6004 #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_MASK)
\r
6005 #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_MASK (0x2U)
\r
6006 #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_SHIFT (1U)
\r
6007 /*! TSF - Transmit Store and Forward When this bit is set, the transmission starts when a full packet resides in the MTL Tx queue.
\r
6009 #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_MASK)
\r
6010 #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_MASK (0xCU)
\r
6011 #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_SHIFT (2U)
\r
6012 /*! TXQEN - Transmit Queue Enable This field is used to enable/disable the transmit queue 0.
\r
6014 #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_MASK)
\r
6015 #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_MASK (0x70U)
\r
6016 #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_SHIFT (4U)
\r
6017 /*! TTC - Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue.
\r
6019 #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_MASK)
\r
6020 #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_MASK (0x70000U)
\r
6021 #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_SHIFT (16U)
\r
6022 /*! TQS - Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes.
\r
6024 #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_MASK)
\r
6027 /* The count of ENET_MTL_QUEUE_MTL_TXQX_OP_MODE */
\r
6028 #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_COUNT (2U)
\r
6030 /*! @name MTL_QUEUE_MTL_TXQX_UNDRFLW - MTL TxQx Underflow register */
\r
6032 #define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK (0x7FFU)
\r
6033 #define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT (0U)
\r
6034 /*! UFFRMCNT - Underflow Packet Counter This field indicates the number of packets aborted by the
\r
6035 * controller because of Tx Queue Underflow.
\r
6037 #define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK)
\r
6038 #define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK (0x800U)
\r
6039 #define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT (11U)
\r
6040 /*! UFCNTOVF - Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue
\r
6041 * Underflow Packet Counter field overflows, that is, it has crossed the maximum count.
\r
6043 #define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK)
\r
6046 /* The count of ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW */
\r
6047 #define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_COUNT (2U)
\r
6049 /*! @name MTL_QUEUE_MTL_TXQX_DBG - MTL TxQx Debug register */
\r
6051 #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_MASK (0x1U)
\r
6052 #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_SHIFT (0U)
\r
6053 /*! TXQPAUSED - Transmit Queue in Pause When this bit is high and the Rx flow control is enabled, it
\r
6054 * indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because
\r
6055 * of the following: - Reception of the PFC packet for the priorities assigned to the Tx Queue
\r
6056 * when PFC is enabled - Reception of 802.
\r
6058 #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_MASK)
\r
6059 #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_MASK (0x6U)
\r
6060 #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_SHIFT (1U)
\r
6061 /*! TRCSTS - MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read
\r
6062 * Controller: 00: Idle state 01: Read state (transferring data to the MAC transmitter) 10:
\r
6063 * Waiting for pending Tx Status from the MAC transmitter 11: Flushing the Tx queue because of the
\r
6064 * Packet Abort request from the MAC.
\r
6066 #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_MASK)
\r
6067 #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_MASK (0x8U)
\r
6068 #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_SHIFT (3U)
\r
6069 /*! TWCSTS - MTL Tx Queue Write Controller Status When high, this bit indicates that the MTL Tx
\r
6070 * Queue Write Controller is active, and it is transferring the data to the Tx Queue.
\r
6072 #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_MASK)
\r
6073 #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_MASK (0x10U)
\r
6074 #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_SHIFT (4U)
\r
6075 /*! TXQSTS - MTL Tx Queue Not Empty Status When this bit is high, it indicates that the MTL Tx Queue
\r
6076 * is not empty and some data is left for transmission.
\r
6078 #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_MASK)
\r
6079 #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_MASK (0x20U)
\r
6080 #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_SHIFT (5U)
\r
6081 /*! TXSTSFSTS - MTL Tx Status FIFO Full Status When high, this bit indicates that the MTL Tx Status FIFO is full.
\r
6083 #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_MASK)
\r
6084 #define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_MASK (0x70000U)
\r
6085 #define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_SHIFT (16U)
\r
6086 /*! PTXQ - Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue.
\r
6088 #define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_MASK)
\r
6089 #define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_MASK (0x700000U)
\r
6090 #define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_SHIFT (20U)
\r
6091 /*! STSXSTSF - Number of Status Words in Tx Status FIFO of Queue This field indicates the current
\r
6092 * number of status in the Tx Status FIFO of this queue.
\r
6094 #define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_MASK)
\r
6097 /* The count of ENET_MTL_QUEUE_MTL_TXQX_DBG */
\r
6098 #define ENET_MTL_QUEUE_MTL_TXQX_DBG_COUNT (2U)
\r
6100 /*! @name MTL_QUEUE_MTL_TXQX_ETS_CTRL - MTL TxQx ETS control register, only TxQ1 support */
\r
6102 #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_MASK (0x4U)
\r
6103 #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_SHIFT (2U)
\r
6104 /*! AVALG - AV Algorithm.
\r
6106 #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_MASK)
\r
6107 #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_MASK (0x8U)
\r
6108 #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_SHIFT (3U)
\r
6109 /*! CC - Credit Control.
\r
6111 #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_MASK)
\r
6112 #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_MASK (0x70U)
\r
6113 #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_SHIFT (4U)
\r
6114 /*! SLC - Credit Control.
\r
6116 #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_MASK)
\r
6119 /* The count of ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL */
\r
6120 #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_COUNT (2U)
\r
6122 /*! @name MTL_QUEUE_MTL_TXQX_ETS_STAT - MTL TxQx ETS Status register */
\r
6124 #define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_MASK (0xFFFFFFU)
\r
6125 #define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_SHIFT (0U)
\r
6126 /*! ABS - Average Bits per Slot.
\r
6128 #define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_MASK)
\r
6131 /* The count of ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT */
\r
6132 #define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_COUNT (2U)
\r
6134 /*! @name MTL_QUEUE_MTL_TXQX_QNTM_WGHT - */
\r
6136 #define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_MASK (0x1FFFFFU)
\r
6137 #define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT (0U)
\r
6138 /*! ISCQW - Average Bits per Slot.
\r
6140 #define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_MASK)
\r
6143 /* The count of ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT */
\r
6144 #define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_COUNT (2U)
\r
6146 /*! @name MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT - MTL TxQx SendSlopCredit register, only TxQ1 support */
\r
6148 #define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_MASK (0x3FFFU)
\r
6149 #define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT (0U)
\r
6150 /*! SSC - sendSlopeCredit.
\r
6152 #define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_MASK)
\r
6155 /* The count of ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT */
\r
6156 #define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_COUNT (2U)
\r
6158 /*! @name MTL_QUEUE_MTL_TXQX_HI_CRDT - MTL TxQx hiCredit register, only TxQ1 support */
\r
6160 #define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_MASK (0x1FFFFFFFU)
\r
6161 #define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_SHIFT (0U)
\r
6162 /*! HC - hiCredit.
\r
6164 #define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_MASK)
\r
6167 /* The count of ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT */
\r
6168 #define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_COUNT (2U)
\r
6170 /*! @name MTL_QUEUE_MTL_TXQX_LO_CRDT - MTL TxQx loCredit register, only TxQ1 support */
\r
6172 #define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_MASK (0x1FFFFFFFU)
\r
6173 #define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_SHIFT (0U)
\r
6174 /*! LC - loCredit.
\r
6176 #define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_MASK)
\r
6179 /* The count of ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT */
\r
6180 #define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_COUNT (2U)
\r
6182 /*! @name MTL_QUEUE_MTL_TXQX_INTCTRL_STAT - */
\r
6184 #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK (0x1U)
\r
6185 #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT (0U)
\r
6186 /*! TXUNFIS - Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue
\r
6187 * had an underflow while transmitting the packet.
\r
6189 #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK)
\r
6190 #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK (0x2U)
\r
6191 #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT (1U)
\r
6192 /*! ABPSIS - Average Bits Per Slot Interrupt Status When set, this bit indicates that the MAC has updated the ABS value.
\r
6194 #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK)
\r
6195 #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK (0x100U)
\r
6196 #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT (8U)
\r
6197 /*! TXUIE - Transmit Queue Underflow Interrupt Enable When this bit is set, the Transmit Queue Underflow interrupt is enabled.
\r
6199 #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK)
\r
6200 #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK (0x200U)
\r
6201 #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT (9U)
\r
6202 /*! ABPSIE - Average Bits Per Slot Interrupt Enable When this bit is set, the MAC asserts the
\r
6203 * interrupt when the average bits per slot status is updated.
\r
6205 #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK)
\r
6206 #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK (0x10000U)
\r
6207 #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT (16U)
\r
6208 /*! RXOVFIS - Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had
\r
6209 * an overflow while receiving the packet.
\r
6211 #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK)
\r
6212 #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK (0x1000000U)
\r
6213 #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT (24U)
\r
6214 /*! RXOIE - Receive Queue Overflow Interrupt Enable When this bit is set, the Receive Queue Overflow interrupt is enabled.
\r
6216 #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK)
\r
6219 /* The count of ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT */
\r
6220 #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_COUNT (2U)
\r
6222 /*! @name MTL_QUEUE_MTL_RXQX_OP_MODE - MTL RxQx Operation Mode register */
\r
6224 #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_MASK (0x3U)
\r
6225 #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_SHIFT (0U)
\r
6226 /*! RTC - Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue
\r
6227 * (in bytes): 00: 64 01: 32 10: 96 11: 128 The packet received is transferred to the
\r
6228 * application or DMA when the packet size within the MTL Rx queue is larger than the threshold.
\r
6230 #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_MASK)
\r
6231 #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_MASK (0x8U)
\r
6232 #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_SHIFT (3U)
\r
6233 /*! FUP - Forward Undersized Good Packets When this bit is set, the Rx queue forwards the undersized
\r
6234 * good packets (packets with no error and length less than 64 bytes), including pad-bytes and
\r
6237 #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_MASK)
\r
6238 #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_MASK (0x10U)
\r
6239 #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_SHIFT (4U)
\r
6240 /*! FEP - Forward Error Packets When this bit is reset, the Rx queue drops packets with error status
\r
6241 * (CRC error, Mll_ER, watchdog timeout, or overflow).
\r
6243 #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_MASK)
\r
6244 #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_MASK (0x20U)
\r
6245 #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_SHIFT (5U)
\r
6246 /*! RSF - Receive Queue Store and Forward When this bit is set, the ethernet block on this chip
\r
6247 * reads a packet from the Rx queue only after the complete packet has been written to it, ignoring
\r
6248 * the RTC field of this register.
\r
6250 #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_MASK)
\r
6251 #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK (0x40U)
\r
6252 #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT (6U)
\r
6253 /*! DIS_TCP_EF - Disable Dropping of TCP/IP Checksum Error Packets When this bit is set, the MAC
\r
6254 * does not drop the packets which only have the errors detected by the Receive Checksum Offload
\r
6257 #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK)
\r
6258 #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_MASK (0x700000U)
\r
6259 #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_SHIFT (20U)
\r
6260 /*! RQS - This field indicates the size of the allocated Receive queues in blocks of 256 bytes.
\r
6262 #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_MASK)
\r
6265 /* The count of ENET_MTL_QUEUE_MTL_RXQX_OP_MODE */
\r
6266 #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_COUNT (2U)
\r
6268 /*! @name MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT - MTL RxQx Missed Packet Overflow Counter register */
\r
6270 #define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK (0x7FFU)
\r
6271 #define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT (0U)
\r
6272 /*! OVFPKTCNT - Overflow Packet Counter This field indicates the number of packets discarded by the
\r
6273 * Ethernet block because of Receive queue overflow.
\r
6275 #define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK)
\r
6276 #define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK (0x800U)
\r
6277 #define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT (11U)
\r
6278 /*! OVFCNTOVF - Overflow Counter Overflow Bit When set, this bit indicates that the Rx Queue
\r
6279 * Overflow Packet Counter field crossed the maximum limit.
\r
6281 #define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK)
\r
6284 /* The count of ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT */
\r
6285 #define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_COUNT (2U)
\r
6287 /*! @name MTL_QUEUE_MTL_RXQX_DBG - MTL RxQx Debug register */
\r
6289 #define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_MASK (0x1U)
\r
6290 #define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_SHIFT (0U)
\r
6291 /*! RWCSTS - MTL Rx Queue Write Controller Active Status When high, this bit indicates that the MTL
\r
6292 * Rx queue Write controller is active, and it is transferring a received packet to the Rx Queue.
\r
6294 #define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_MASK)
\r
6295 #define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_MASK (0x6U)
\r
6296 #define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_SHIFT (1U)
\r
6297 /*! RRCSTS - MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read
\r
6298 * controller: 00: Idle state 01: Reading packet data 10: Reading packet status (or timestamp) 11:
\r
6299 * Flushing the packet data and status.
\r
6301 #define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_MASK)
\r
6302 #define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_MASK (0x30U)
\r
6303 #define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_SHIFT (4U)
\r
6304 /*! RXQSTS - MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx
\r
6305 * Queue: 0x0: Rx Queue empty 0x1: Rx Queue fill-level below flow-control deactivate threshold
\r
6306 * 0x2: Rx Queue fill-level above flow-control activate threshold 0x3: Rx Queue full.
\r
6308 #define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_MASK)
\r
6309 #define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_MASK (0x3FFF0000U)
\r
6310 #define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_SHIFT (16U)
\r
6311 /*! PRXQ - Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue.
\r
6313 #define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_MASK)
\r
6316 /* The count of ENET_MTL_QUEUE_MTL_RXQX_DBG */
\r
6317 #define ENET_MTL_QUEUE_MTL_RXQX_DBG_COUNT (2U)
\r
6319 /*! @name MTL_QUEUE_MTL_RXQX_CTRL - MTL RxQx Control register */
\r
6321 #define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_MASK (0x7U)
\r
6322 #define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT (0U)
\r
6323 /*! RXQ_WEGT - Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0.
\r
6325 #define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_MASK)
\r
6326 #define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK (0x8U)
\r
6327 #define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT (3U)
\r
6328 /*! RXQ_FRM_ARBIT - Receive Queue Packet Arbitration When this bit is set, the The ethernet block
\r
6329 * drives the packet data to the ARI interface such that the entire packet data of
\r
6330 * currently-selected queue is transmitted before switching to other queue.
\r
6332 #define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK)
\r
6335 /* The count of ENET_MTL_QUEUE_MTL_RXQX_CTRL */
\r
6336 #define ENET_MTL_QUEUE_MTL_RXQX_CTRL_COUNT (2U)
\r
6338 /*! @name DMA_MODE - DMA mode register */
\r
6340 #define ENET_DMA_MODE_SWR_MASK (0x1U)
\r
6341 #define ENET_DMA_MODE_SWR_SHIFT (0U)
\r
6342 /*! SWR - Software Reset When this bit is set, the MAC and the OMA controller reset the logic and
\r
6343 * all internal registers of the OMA, MTL, and MAC.
\r
6345 #define ENET_DMA_MODE_SWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_SWR_SHIFT)) & ENET_DMA_MODE_SWR_MASK)
\r
6346 #define ENET_DMA_MODE_DA_MASK (0x2U)
\r
6347 #define ENET_DMA_MODE_DA_SHIFT (1U)
\r
6348 /*! DA - DMA Tx or Rx Arbitration Scheme This bit specifies the arbitration scheme between the
\r
6349 * Transmit and Receive paths of all channels: The Tx path has priority over the Rx path when the TXPR
\r
6352 #define ENET_DMA_MODE_DA(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_DA_SHIFT)) & ENET_DMA_MODE_DA_MASK)
\r
6353 #define ENET_DMA_MODE_TAA_MASK (0x1CU)
\r
6354 #define ENET_DMA_MODE_TAA_SHIFT (2U)
\r
6355 /*! TAA - Transmit Arbitration Algorithm This field is used to select the arbitration algorithm for
\r
6356 * the Transmit side when multiple Tx DMAs are selected.
\r
6358 #define ENET_DMA_MODE_TAA(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_TAA_SHIFT)) & ENET_DMA_MODE_TAA_MASK)
\r
6359 #define ENET_DMA_MODE_TXPR_MASK (0x800U)
\r
6360 #define ENET_DMA_MODE_TXPR_SHIFT (11U)
\r
6361 /*! TXPR - Transmit Priority When set, this bit indicates that the Tx DMA has higher priority than
\r
6362 * the Rx DMA during arbitration for the system-side bus.
\r
6364 #define ENET_DMA_MODE_TXPR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_TXPR_SHIFT)) & ENET_DMA_MODE_TXPR_MASK)
\r
6365 #define ENET_DMA_MODE_PR_MASK (0x7000U)
\r
6366 #define ENET_DMA_MODE_PR_SHIFT (12U)
\r
6367 /*! PR - Priority Ratio These bits control the priority ratio in weighted round-robin arbitration between the Rx DMA and Tx DMA.
\r
6369 #define ENET_DMA_MODE_PR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_PR_SHIFT)) & ENET_DMA_MODE_PR_MASK)
\r
6372 /*! @name DMA_SYSBUS_MODE - DMA System Bus mode */
\r
6374 #define ENET_DMA_SYSBUS_MODE_FB_MASK (0x1U)
\r
6375 #define ENET_DMA_SYSBUS_MODE_FB_SHIFT (0U)
\r
6376 /*! FB - Fixed Burst Length When this bit is set to 1, the AHB master will initiate burst transfers
\r
6377 * of specified length (INCRx or SINGLE).
\r
6379 #define ENET_DMA_SYSBUS_MODE_FB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_FB_SHIFT)) & ENET_DMA_SYSBUS_MODE_FB_MASK)
\r
6380 #define ENET_DMA_SYSBUS_MODE_AAL_MASK (0x1000U)
\r
6381 #define ENET_DMA_SYSBUS_MODE_AAL_SHIFT (12U)
\r
6382 /*! AAL - Address-Aligned Beats When this bit is set to 1, the AHB master performs address-aligned
\r
6383 * burst transfers on Read and Write channels.
\r
6385 #define ENET_DMA_SYSBUS_MODE_AAL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_AAL_SHIFT)) & ENET_DMA_SYSBUS_MODE_AAL_MASK)
\r
6386 #define ENET_DMA_SYSBUS_MODE_MB_MASK (0x4000U)
\r
6387 #define ENET_DMA_SYSBUS_MODE_MB_SHIFT (14U)
\r
6388 /*! MB - Mixed Burst When this bit is set high and the FB bit is low, the AHB master performs
\r
6389 * undefined bursts transfers (INCR) for burst length of 16 or more.
\r
6391 #define ENET_DMA_SYSBUS_MODE_MB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_MB_SHIFT)) & ENET_DMA_SYSBUS_MODE_MB_MASK)
\r
6392 #define ENET_DMA_SYSBUS_MODE_RB_MASK (0x8000U)
\r
6393 #define ENET_DMA_SYSBUS_MODE_RB_SHIFT (15U)
\r
6394 /*! RB - Rebuild INCRx Burst When this bit is set high and the AHB master gets SPLIT, RETRY, or
\r
6395 * EarlyBurst Termination (EBT) response, the AHB master interface rebuilds the pending beats of any
\r
6396 * initiated burst transfer with INCRx and SINGLEtransfers.
\r
6398 #define ENET_DMA_SYSBUS_MODE_RB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_RB_SHIFT)) & ENET_DMA_SYSBUS_MODE_RB_MASK)
\r
6401 /*! @name DMA_INTR_STAT - DMA Interrupt status */
\r
6403 #define ENET_DMA_INTR_STAT_DC0IS_MASK (0x1U)
\r
6404 #define ENET_DMA_INTR_STAT_DC0IS_SHIFT (0U)
\r
6405 /*! DC0IS - DMA Channel 0 Interrupt Status This bit indicates an interrupt event in DMA Channel 0.
\r
6407 #define ENET_DMA_INTR_STAT_DC0IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_DC0IS_SHIFT)) & ENET_DMA_INTR_STAT_DC0IS_MASK)
\r
6408 #define ENET_DMA_INTR_STAT_DC1IS_MASK (0x2U)
\r
6409 #define ENET_DMA_INTR_STAT_DC1IS_SHIFT (1U)
\r
6410 /*! DC1IS - DMA Channel 1 Interrupt Status This bit indicates an interrupt event in DMA Channel 1.
\r
6412 #define ENET_DMA_INTR_STAT_DC1IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_DC1IS_SHIFT)) & ENET_DMA_INTR_STAT_DC1IS_MASK)
\r
6413 #define ENET_DMA_INTR_STAT_MTLIS_MASK (0x10000U)
\r
6414 #define ENET_DMA_INTR_STAT_MTLIS_SHIFT (16U)
\r
6415 /*! MTLIS - MTL Interrupt Status This bit indicates an interrupt event in the MTL.
\r
6417 #define ENET_DMA_INTR_STAT_MTLIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_MTLIS_SHIFT)) & ENET_DMA_INTR_STAT_MTLIS_MASK)
\r
6418 #define ENET_DMA_INTR_STAT_MACIS_MASK (0x20000U)
\r
6419 #define ENET_DMA_INTR_STAT_MACIS_SHIFT (17U)
\r
6420 /*! MACIS - MAC Interrupt Status This bit indicates an interrupt event in the MAC.
\r
6422 #define ENET_DMA_INTR_STAT_MACIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_MACIS_SHIFT)) & ENET_DMA_INTR_STAT_MACIS_MASK)
\r
6425 /*! @name DMA_DBG_STAT - DMA Debug Status */
\r
6427 #define ENET_DMA_DBG_STAT_AHSTS_MASK (0x1U)
\r
6428 #define ENET_DMA_DBG_STAT_AHSTS_SHIFT (0U)
\r
6429 /*! AHSTS - AHB Master Status When high, this bit indicates that the AHB master FSMs are in the non-idle state.
\r
6431 #define ENET_DMA_DBG_STAT_AHSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_AHSTS_SHIFT)) & ENET_DMA_DBG_STAT_AHSTS_MASK)
\r
6432 #define ENET_DMA_DBG_STAT_RPS0_MASK (0xF00U)
\r
6433 #define ENET_DMA_DBG_STAT_RPS0_SHIFT (8U)
\r
6434 /*! RPS0 - DMA Channel 0 Receive Process State This field indicates the Rx DMA FSM state for Channel
\r
6435 * 0: 0x0: Stopped (Reset or Stop Receive Command issued) 0x1: Running (Fetching Rx Transfer )
\r
6436 * 0x2: Reserved 0x3: Running (Waiting for Rx packet) 0x4: Suspended (Rx Unavailable) 0x5: Running
\r
6437 * (Closing the Rx) 0x6: Timestamp write state 0x7: Running (Transferring the received packet
\r
6438 * data from the Rx buffer to the system memory) This field does not generate an interrupt.
\r
6440 #define ENET_DMA_DBG_STAT_RPS0(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_RPS0_SHIFT)) & ENET_DMA_DBG_STAT_RPS0_MASK)
\r
6441 #define ENET_DMA_DBG_STAT_TPS0_MASK (0xF000U)
\r
6442 #define ENET_DMA_DBG_STAT_TPS0_SHIFT (12U)
\r
6443 /*! TPS0 - DMA Channel 0 Transmit Process State This field indicates the Tx DMA FSM state for
\r
6444 * Channel 0: 000: Stopped (Reset or Stop Transmit Command issued) 0x1: Running (Fetching Tx Transfer)
\r
6445 * 0x2: Running (Waiting for status) 0x3: Running (Reading Data from system memory buffer and
\r
6446 * queuing it to the Tx buffer (Tx FIFO)) 0x4: Timestamp write state 0x5: Reserved for future use
\r
6447 * 0x6: Suspended (Tx Unavailable or Tx Buffer Underflow) 0x7: Running (Closing Tx ) This field
\r
6448 * does not generate an interrupt.
\r
6450 #define ENET_DMA_DBG_STAT_TPS0(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_TPS0_SHIFT)) & ENET_DMA_DBG_STAT_TPS0_MASK)
\r
6451 #define ENET_DMA_DBG_STAT_RPS1_MASK (0xF0000U)
\r
6452 #define ENET_DMA_DBG_STAT_RPS1_SHIFT (16U)
\r
6453 /*! RPS1 - DMA Channel 1 Receive Process State This field indicates the Rx DMA FSM state for Channel 1.
\r
6455 #define ENET_DMA_DBG_STAT_RPS1(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_RPS1_SHIFT)) & ENET_DMA_DBG_STAT_RPS1_MASK)
\r
6456 #define ENET_DMA_DBG_STAT_TPS1_MASK (0xF00000U)
\r
6457 #define ENET_DMA_DBG_STAT_TPS1_SHIFT (20U)
\r
6458 /*! TPS1 - DMA Channel 1 Transmit Process State This field indicates the Tx DMA FSM state for Channel 1.
\r
6460 #define ENET_DMA_DBG_STAT_TPS1(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_TPS1_SHIFT)) & ENET_DMA_DBG_STAT_TPS1_MASK)
\r
6463 /*! @name DMA_CH_DMA_CHX_CTRL - DMA Channelx Control */
\r
6465 #define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_MASK (0x10000U)
\r
6466 #define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_SHIFT (16U)
\r
6467 /*! PBLx8 - 8xPBL mode When this bit is set, the PBL value programmed in Bits[21:16] in DMA Channel
\r
6468 * Transmit Control Table 780 is multiplied eight times.
\r
6470 #define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_SHIFT)) & ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_MASK)
\r
6471 #define ENET_DMA_CH_DMA_CHX_CTRL_DSL_MASK (0x1C0000U)
\r
6472 #define ENET_DMA_CH_DMA_CHX_CTRL_DSL_SHIFT (18U)
\r
6473 /*! DSL - Skip Length This bit specifies the Word, Dword, or Lword number (depending on the 32- bit,
\r
6474 * 64-bit, or 128-bit bus) to skip between two unchained s.
\r
6476 #define ENET_DMA_CH_DMA_CHX_CTRL_DSL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CTRL_DSL_SHIFT)) & ENET_DMA_CH_DMA_CHX_CTRL_DSL_MASK)
\r
6479 /* The count of ENET_DMA_CH_DMA_CHX_CTRL */
\r
6480 #define ENET_DMA_CH_DMA_CHX_CTRL_COUNT (2U)
\r
6482 /*! @name DMA_CH_DMA_CHX_TX_CTRL - DMA Channelx Transmit Control */
\r
6484 #define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK (0x1U)
\r
6485 #define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_SHIFT (0U)
\r
6486 /*! ST - Start or Stop Transmission Command When this bit is set, transmission is placed in the Running state.
\r
6488 #define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK)
\r
6489 #define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_MASK (0xEU)
\r
6490 #define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_SHIFT (1U)
\r
6491 /*! TCW - Transmit Channel Weight This field indicates the weight assigned to the corresponding Transmit channel.
\r
6493 #define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_MASK)
\r
6494 #define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_MASK (0x10U)
\r
6495 #define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_SHIFT (4U)
\r
6496 /*! OSF - Operate on Second Frame When this bit is set, it instructs the DMA to process the second
\r
6497 * packet of the Transmit data even before the status for the first packet is obtained.
\r
6499 #define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_MASK)
\r
6500 #define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_MASK (0x3F0000U)
\r
6501 #define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_SHIFT (16U)
\r
6502 /*! TxPBL - Transmit Programmable Burst Length These bits indicate the maximum number of beats to be
\r
6503 * transferred in one DMA data transfer.
\r
6505 #define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_MASK)
\r
6508 /* The count of ENET_DMA_CH_DMA_CHX_TX_CTRL */
\r
6509 #define ENET_DMA_CH_DMA_CHX_TX_CTRL_COUNT (2U)
\r
6511 /*! @name DMA_CH_DMA_CHX_RX_CTRL - DMA Channelx Receive Control */
\r
6513 #define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_MASK (0x1U)
\r
6514 #define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_SHIFT (0U)
\r
6515 /*! SR - Start or Stop Receive When this bit is set, the DMA tries to acquire the from the receive
\r
6516 * list and processes the incoming packets.
\r
6518 #define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_MASK)
\r
6519 #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_MASK (0x7FF8U)
\r
6520 #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_SHIFT (3U)
\r
6521 /*! RBSZ - Receive Buffer size This field indicates the size of the Rx buffers specified in bytes.
\r
6523 #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_MASK)
\r
6524 #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_MASK (0x3F0000U)
\r
6525 #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_SHIFT (16U)
\r
6526 /*! RxPBL - Receive Programmable Burst Length These bits indicate the maximum number of beats to be
\r
6527 * transferred in one DMA data transfer.
\r
6529 #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_MASK)
\r
6530 #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_MASK (0x80000000U)
\r
6531 #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_SHIFT (31U)
\r
6532 /*! RPF - DMA Rx Channel 0 Packet Flush When this bit is set to 1, the DMA will automatically flush
\r
6533 * the packet from the Rx Queues destined to DMA Rx Channel 0 when the DMA Rx Channel 0 is
\r
6534 * stopped after a system bus error has occurred.
\r
6536 #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_MASK)
\r
6539 /* The count of ENET_DMA_CH_DMA_CHX_RX_CTRL */
\r
6540 #define ENET_DMA_CH_DMA_CHX_RX_CTRL_COUNT (2U)
\r
6542 /*! @name DMA_CH_DMA_CHX_TXDESC_LIST_ADDR - */
\r
6544 #define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_MASK (0xFFFFFFFCU)
\r
6545 #define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_SHIFT (2U)
\r
6546 /*! STL - Start of transmit list This field contains the base address of the first in the Transmit list.
\r
6548 #define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_MASK)
\r
6551 /* The count of ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR */
\r
6552 #define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_COUNT (2U)
\r
6554 /*! @name DMA_CH_DMA_CHX_RXDESC_LIST_ADDR - */
\r
6556 #define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_MASK (0xFFFFFFFCU)
\r
6557 #define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_SHIFT (2U)
\r
6558 /*! SRL - Start of receive list This field contains the base address of the First in the Receive list.
\r
6560 #define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_MASK)
\r
6563 /* The count of ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR */
\r
6564 #define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_COUNT (2U)
\r
6566 /*! @name DMA_CH_DMA_CHX_TXDESC_TAIL_PTR - */
\r
6568 #define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK (0xFFFFFFFCU)
\r
6569 #define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT (2U)
\r
6570 /*! TDTP - Transmit Tail Pointer This field contains the tail pointer for the Tx ring.
\r
6572 #define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK)
\r
6575 /* The count of ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR */
\r
6576 #define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_COUNT (2U)
\r
6578 /*! @name DMA_CH_DMA_CHX_RXDESC_TAIL_PTR - */
\r
6580 #define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK (0xFFFFFFFCU)
\r
6581 #define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT (2U)
\r
6582 /*! RDTP - Receive Tail Pointer This field contains the tail pointer for the Rx ring.
\r
6584 #define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK)
\r
6587 /* The count of ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR */
\r
6588 #define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_COUNT (2U)
\r
6590 /*! @name DMA_CH_DMA_CHX_TXDESC_RING_LENGTH - */
\r
6592 #define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK (0x3FFU)
\r
6593 #define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT (0U)
\r
6594 /*! TDRL - Transmit Ring Length This field sets the maximum number of Tx descriptors in the circular ring.
\r
6596 #define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK)
\r
6599 /* The count of ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH */
\r
6600 #define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_COUNT (2U)
\r
6602 /*! @name DMA_CH_DMA_CHX_RXDESC_RING_LENGTH - Channelx Rx descriptor Ring Length */
\r
6604 #define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK (0x3FFU)
\r
6605 #define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_SHIFT (0U)
\r
6606 /*! RDRL - Receive Ring Length This register sets the maximum number of Rx descriptors in the circular ring.
\r
6608 #define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK)
\r
6611 /* The count of ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH */
\r
6612 #define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_COUNT (2U)
\r
6614 /*! @name DMA_CH_DMA_CHX_INT_EN - Channelx Interrupt Enable */
\r
6616 #define ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK (0x1U)
\r
6617 #define ENET_DMA_CH_DMA_CHX_INT_EN_TIE_SHIFT (0U)
\r
6618 /*! TIE - Transmit interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit
\r
6619 * 16 in this register), Transmit Interrupt is enabled.
\r
6621 #define ENET_DMA_CH_DMA_CHX_INT_EN_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK)
\r
6622 #define ENET_DMA_CH_DMA_CHX_INT_EN_TSE_MASK (0x2U)
\r
6623 #define ENET_DMA_CH_DMA_CHX_INT_EN_TSE_SHIFT (1U)
\r
6624 /*! TSE - Transmit stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit
\r
6625 * 15 in this register), Transmission Stopped Interrupt is enabled.
\r
6627 #define ENET_DMA_CH_DMA_CHX_INT_EN_TSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TSE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TSE_MASK)
\r
6628 #define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_MASK (0x4U)
\r
6629 #define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_SHIFT (2U)
\r
6630 /*! TBUE - Transmit buffer unavailable enable When this bit is set with Normal Interrupt Summary
\r
6631 * Enable (bit 16 in this register), Transmit Buffer Unavailable Interrupt is enabled.
\r
6633 #define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_MASK)
\r
6634 #define ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK (0x40U)
\r
6635 #define ENET_DMA_CH_DMA_CHX_INT_EN_RIE_SHIFT (6U)
\r
6636 /*! RIE - Receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16
\r
6637 * in this register), Receive Interrupt is enabled.
\r
6639 #define ENET_DMA_CH_DMA_CHX_INT_EN_RIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK)
\r
6640 #define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_MASK (0x80U)
\r
6641 #define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_SHIFT (7U)
\r
6642 /*! RBUE - Receive buffer unavailable enable When this bit is set with Abnormal Interrupt Summary
\r
6643 * Enable (bit 15 in this register), Receive Buffer Unavailable Interrupt is enabled.
\r
6645 #define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_MASK)
\r
6646 #define ENET_DMA_CH_DMA_CHX_INT_EN_RSE_MASK (0x100U)
\r
6647 #define ENET_DMA_CH_DMA_CHX_INT_EN_RSE_SHIFT (8U)
\r
6648 /*! RSE - Received stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit
\r
6649 * 15 in this register), Receive Stopped Interrupt is enabled.
\r
6651 #define ENET_DMA_CH_DMA_CHX_INT_EN_RSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RSE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RSE_MASK)
\r
6652 #define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_MASK (0x200U)
\r
6653 #define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_SHIFT (9U)
\r
6654 /*! RWTE - Receive watchdog timeout enable When this bit is set with Abnormal Interrupt Summary
\r
6655 * Enable (bit 15 in this register), the Receive Watchdog Timeout Interrupt is enabled.
\r
6657 #define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_MASK)
\r
6658 #define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_MASK (0x400U)
\r
6659 #define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_SHIFT (10U)
\r
6660 /*! ETIE - Early transmit interrupt enable When this bit is set with an Abnormal Interrupt Summary
\r
6661 * Enable (bit 15 in this register), Early Transmit Interrupt is enabled.
\r
6663 #define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_MASK)
\r
6664 #define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_MASK (0x800U)
\r
6665 #define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_SHIFT (11U)
\r
6666 /*! ERIE - Early receive interrupt enable When this bit is set with Normal Interrupt Summary Enable
\r
6667 * (bit 16 in this register), Early Receive Interrupt is enabled.
\r
6669 #define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_MASK)
\r
6670 #define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_MASK (0x1000U)
\r
6671 #define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_SHIFT (12U)
\r
6672 /*! FBEE - Fatal bus error enable When this bit is set with Abnormal Interrupt Summary Enable (bit
\r
6673 * 15 in this register), the Fatal Bus Error Interrupt is enabled.
\r
6675 #define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_MASK)
\r
6676 #define ENET_DMA_CH_DMA_CHX_INT_EN_AIE_MASK (0x4000U)
\r
6677 #define ENET_DMA_CH_DMA_CHX_INT_EN_AIE_SHIFT (14U)
\r
6678 /*! AIE - Abnormal interrupt summary enable When this bit is set, an Abnormal Interrupt summary is enabled.
\r
6680 #define ENET_DMA_CH_DMA_CHX_INT_EN_AIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_AIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_AIE_MASK)
\r
6681 #define ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK (0x8000U)
\r
6682 #define ENET_DMA_CH_DMA_CHX_INT_EN_NIE_SHIFT (15U)
\r
6683 /*! NIE - Normal interrupt summary enable When this bit is set, a normal interrupt is enabled.
\r
6685 #define ENET_DMA_CH_DMA_CHX_INT_EN_NIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_NIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK)
\r
6688 /* The count of ENET_DMA_CH_DMA_CHX_INT_EN */
\r
6689 #define ENET_DMA_CH_DMA_CHX_INT_EN_COUNT (2U)
\r
6691 /*! @name DMA_CH_DMA_CHX_RX_INT_WDTIMER - Receive Interrupt Watchdog Timer */
\r
6693 #define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_MASK (0xFFU)
\r
6694 #define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_SHIFT (0U)
\r
6695 /*! RIWT - Receive Interrupt Watchdog Timer Count Indicates the number of system clock cycles
\r
6696 * multiplied by 256 for which the watchdog timer is set.
\r
6698 #define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_MASK)
\r
6701 /* The count of ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER */
\r
6702 #define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_COUNT (2U)
\r
6704 /*! @name DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT - Slot Function Control and Status */
\r
6706 #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK (0x1U)
\r
6707 #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT (0U)
\r
6708 /*! ESC - Enable Slot Comparison When set, this bit enables the checking of the slot numbers
\r
6709 * programmed in the Tx descriptor with the current reference given in the RSN field.
\r
6711 #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK)
\r
6712 #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK (0x2U)
\r
6713 #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT (1U)
\r
6714 /*! ASC - Advance Slot Check When set, this bit enables the D MA to fetch the data from the buffer
\r
6715 * when the slot number (SLOTNUM) programmed in the Tx descriptor is equal to the reference slot
\r
6716 * number given in the RSN field or, ahead of the reference slot number by up to two slots This
\r
6717 * bit is applicable only when the ESC bit is set.
\r
6719 #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK)
\r
6720 #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK (0xF0000U)
\r
6721 #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT (16U)
\r
6722 /*! RSN - Reference Slot Number This field gives the current value of the reference slot number in the DMA.
\r
6724 #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK)
\r
6727 /* The count of ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT */
\r
6728 #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_COUNT (2U)
\r
6730 /*! @name DMA_CH_DMA_CHX_CUR_HST_TXDESC - Channelx Current Host Transmit descriptor */
\r
6732 #define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_MASK (0xFFFFFFFFU)
\r
6733 #define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_SHIFT (0U)
\r
6734 /*! HTD - Host Transmit descriptor Address Pointer Cleared on Reset.
\r
6736 #define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_MASK)
\r
6739 /* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC */
\r
6740 #define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_COUNT (2U)
\r
6742 /*! @name DMA_CH_DMA_CHX_CUR_HST_RXDESC - */
\r
6744 #define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_MASK (0xFFFFFFFFU)
\r
6745 #define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_SHIFT (0U)
\r
6746 /*! HRD - Host Receive descriptor Address Pointer Cleared on Reset.
\r
6748 #define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_MASK)
\r
6751 /* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC */
\r
6752 #define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_COUNT (2U)
\r
6754 /*! @name DMA_CH_DMA_CHX_CUR_HST_TXBUF - */
\r
6756 #define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_MASK (0xFFFFFFFFU)
\r
6757 #define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_SHIFT (0U)
\r
6758 /*! HTB - Host Transmit Buffer Address Pointer Cleared on Reset.
\r
6760 #define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_MASK)
\r
6763 /* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF */
\r
6764 #define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_COUNT (2U)
\r
6766 /*! @name DMA_CH_DMA_CHX_CUR_HST_RXBUF - Channelx Current Application Receive Buffer Address */
\r
6768 #define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_MASK (0xFFFFFFFFU)
\r
6769 #define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_SHIFT (0U)
\r
6770 /*! HRB - Host Receive Buffer Address Pointer Cleared on Reset.
\r
6772 #define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_MASK)
\r
6775 /* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF */
\r
6776 #define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_COUNT (2U)
\r
6778 /*! @name DMA_CH_DMA_CHX_STAT - Channelx DMA status register */
\r
6780 #define ENET_DMA_CH_DMA_CHX_STAT_TI_MASK (0x1U)
\r
6781 #define ENET_DMA_CH_DMA_CHX_STAT_TI_SHIFT (0U)
\r
6782 /*! TI - Transmit Interrupt This bit indicates that the packet transmission is complete.
\r
6784 #define ENET_DMA_CH_DMA_CHX_STAT_TI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TI_MASK)
\r
6785 #define ENET_DMA_CH_DMA_CHX_STAT_TPS_MASK (0x2U)
\r
6786 #define ENET_DMA_CH_DMA_CHX_STAT_TPS_SHIFT (1U)
\r
6787 /*! TPS - Transmit Process Stopped This bit is set when the transmission is stopped.
\r
6789 #define ENET_DMA_CH_DMA_CHX_STAT_TPS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TPS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TPS_MASK)
\r
6790 #define ENET_DMA_CH_DMA_CHX_STAT_TBU_MASK (0x4U)
\r
6791 #define ENET_DMA_CH_DMA_CHX_STAT_TBU_SHIFT (2U)
\r
6792 /*! TBU - Transmit Buffer Unavailable This bit indicates that the application owns the next
\r
6793 * descriptor in the transmit list, and the DMA cannot acquire it.
\r
6795 #define ENET_DMA_CH_DMA_CHX_STAT_TBU(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TBU_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TBU_MASK)
\r
6796 #define ENET_DMA_CH_DMA_CHX_STAT_RI_MASK (0x40U)
\r
6797 #define ENET_DMA_CH_DMA_CHX_STAT_RI_SHIFT (6U)
\r
6798 /*! RI - Receive Interrupt This bit indicates that the packet reception is complete.
\r
6800 #define ENET_DMA_CH_DMA_CHX_STAT_RI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RI_MASK)
\r
6801 #define ENET_DMA_CH_DMA_CHX_STAT_RBU_MASK (0x80U)
\r
6802 #define ENET_DMA_CH_DMA_CHX_STAT_RBU_SHIFT (7U)
\r
6803 /*! RBU - Receive Buffer Unavailable This bit indicates that the application owns the next in the
\r
6804 * receive list, and the DMA cannot acquire it.
\r
6806 #define ENET_DMA_CH_DMA_CHX_STAT_RBU(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RBU_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RBU_MASK)
\r
6807 #define ENET_DMA_CH_DMA_CHX_STAT_RPS_MASK (0x100U)
\r
6808 #define ENET_DMA_CH_DMA_CHX_STAT_RPS_SHIFT (8U)
\r
6809 /*! RPS - Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state.
\r
6811 #define ENET_DMA_CH_DMA_CHX_STAT_RPS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RPS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RPS_MASK)
\r
6812 #define ENET_DMA_CH_DMA_CHX_STAT_RWT_MASK (0x200U)
\r
6813 #define ENET_DMA_CH_DMA_CHX_STAT_RWT_SHIFT (9U)
\r
6814 /*! RWT - Receive Watchdog time out This bit is asserted when a packet with length greater than
\r
6815 * 2,048 bytes (10,240 bytes when Jumbo Packet mode is enabled) is received.
\r
6817 #define ENET_DMA_CH_DMA_CHX_STAT_RWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RWT_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RWT_MASK)
\r
6818 #define ENET_DMA_CH_DMA_CHX_STAT_ETI_MASK (0x400U)
\r
6819 #define ENET_DMA_CH_DMA_CHX_STAT_ETI_SHIFT (10U)
\r
6820 /*! ETI - Early Transmit Interrupt This bit indicates that the packet to be transmitted is fully transferred to the MTL Tx FIFO.
\r
6822 #define ENET_DMA_CH_DMA_CHX_STAT_ETI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_ETI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_ETI_MASK)
\r
6823 #define ENET_DMA_CH_DMA_CHX_STAT_ERI_MASK (0x800U)
\r
6824 #define ENET_DMA_CH_DMA_CHX_STAT_ERI_SHIFT (11U)
\r
6825 /*! ERI - Early Receive Interrupt This bit indicates that the DMA filled the first data buffer of the packet.
\r
6827 #define ENET_DMA_CH_DMA_CHX_STAT_ERI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_ERI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_ERI_MASK)
\r
6828 #define ENET_DMA_CH_DMA_CHX_STAT_FBE_MASK (0x1000U)
\r
6829 #define ENET_DMA_CH_DMA_CHX_STAT_FBE_SHIFT (12U)
\r
6830 /*! FBE - Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field).
\r
6832 #define ENET_DMA_CH_DMA_CHX_STAT_FBE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_FBE_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_FBE_MASK)
\r
6833 #define ENET_DMA_CH_DMA_CHX_STAT_AIS_MASK (0x4000U)
\r
6834 #define ENET_DMA_CH_DMA_CHX_STAT_AIS_SHIFT (14U)
\r
6835 /*! AIS - Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the
\r
6836 * following when the corresponding interrupt bits are enabled in the DMA Channel Interrupt Enable
\r
6837 * register Table 778: Bit 1: Transmit Process Stopped Bit 7: Receive Buffer Unavailable Bit 8:
\r
6838 * Receive Process Stopped Bit 10: Ear1y Transmit Interrupt Bit 12: Fatal Bus Error Only unmasked
\r
6839 * bits affect the Abnormal Interrupt Summary bit.
\r
6841 #define ENET_DMA_CH_DMA_CHX_STAT_AIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_AIS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_AIS_MASK)
\r
6842 #define ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK (0x8000U)
\r
6843 #define ENET_DMA_CH_DMA_CHX_STAT_NIS_SHIFT (15U)
\r
6844 /*! NIS - Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the
\r
6845 * following bits when the corresponding interrupt bits are enabled in the DMA Channel Interrupt
\r
6846 * Enable register Table 778: Bit 0: Transmit Interrupt Bit 2: Transmit Buffer Unavailable Bit 6:
\r
6847 * Receive Interrupt Bit 11: Early Receive Interrupt Only unmasked bits (interrupts for which
\r
6848 * interrupt enable is set in DMA Channel Interrupt Enable register Table 778) affect the Normal
\r
6849 * Interrupt Summary bit.
\r
6851 #define ENET_DMA_CH_DMA_CHX_STAT_NIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_NIS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK)
\r
6852 #define ENET_DMA_CH_DMA_CHX_STAT_EB_MASK (0x70000U)
\r
6853 #define ENET_DMA_CH_DMA_CHX_STAT_EB_SHIFT (16U)
\r
6854 /*! EB - DMA Error Bits This field indicates the type of error that caused a Bus Error.
\r
6856 #define ENET_DMA_CH_DMA_CHX_STAT_EB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_EB_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_EB_MASK)
\r
6859 /* The count of ENET_DMA_CH_DMA_CHX_STAT */
\r
6860 #define ENET_DMA_CH_DMA_CHX_STAT_COUNT (2U)
\r
6862 /*! @name DMA_CH_DMA_CHX_MISS_FRAME_CNT - Channelx missed frame count. */
\r
6864 #define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFC_MASK (0x7FFU)
\r
6865 #define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFC_SHIFT (0U)
\r
6866 /*! MFC - Dropped packet counters.
\r
6868 #define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFC_SHIFT)) & ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFC_MASK)
\r
6869 #define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFCO_MASK (0x8000U)
\r
6870 #define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFCO_SHIFT (15U)
\r
6871 /*! MFCO - Overflow status of the MFC counter.
\r
6873 #define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFCO(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFCO_SHIFT)) & ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_MFCO_MASK)
\r
6876 /* The count of ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT */
\r
6877 #define ENET_DMA_CH_DMA_CHX_MISS_FRAME_CNT_COUNT (2U)
\r
6882 */ /* end of group ENET_Register_Masks */
\r
6885 /* ENET - Peripheral instance base addresses */
\r
6886 /** Peripheral ENET base address */
\r
6887 #define ENET_BASE (0x40092000u)
\r
6888 /** Peripheral ENET base pointer */
\r
6889 #define ENET ((ENET_Type *)ENET_BASE)
\r
6890 /** Array initializer of ENET peripheral base addresses */
\r
6891 #define ENET_BASE_ADDRS { ENET_BASE }
\r
6892 /** Array initializer of ENET peripheral base pointers */
\r
6893 #define ENET_BASE_PTRS { ENET }
\r
6894 /** Interrupt vectors for the ENET peripheral type */
\r
6895 #define ENET_IRQS { ETHERNET_IRQn }
\r
6896 #define ENET_PMT_IRQS { ETHERNET_PMT_IRQn }
\r
6897 #define ENET_MACLP_IRQS { ETHERNET_MACLP_IRQn }
\r
6901 */ /* end of group ENET_Peripheral_Access_Layer */
\r
6904 /* ----------------------------------------------------------------------------
\r
6905 -- FLEXCOMM Peripheral Access Layer
\r
6906 ---------------------------------------------------------------------------- */
\r
6909 * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer
\r
6913 /** FLEXCOMM - Register Layout Typedef */
\r
6915 uint8_t RESERVED_0[4088];
\r
6916 __IO uint32_t PSELID; /**< Peripheral Select and Flexcomm ID register., offset: 0xFF8 */
\r
6917 __I uint32_t PID; /**< Peripheral identification register., offset: 0xFFC */
\r
6920 /* ----------------------------------------------------------------------------
\r
6921 -- FLEXCOMM Register Masks
\r
6922 ---------------------------------------------------------------------------- */
\r
6925 * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks
\r
6929 /*! @name PSELID - Peripheral Select and Flexcomm ID register. */
\r
6931 #define FLEXCOMM_PSELID_PERSEL_MASK (0x7U)
\r
6932 #define FLEXCOMM_PSELID_PERSEL_SHIFT (0U)
\r
6933 /*! PERSEL - Peripheral Select. This field is writable by software.
\r
6934 * 0b000..No peripheral selected.
\r
6935 * 0b001..USART function selected.
\r
6936 * 0b010..SPI function selected.
\r
6937 * 0b011..I2C function selected.
\r
6938 * 0b100..I2S transmit function selected.
\r
6939 * 0b101..I2S receive function selected.
\r
6943 #define FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK)
\r
6944 #define FLEXCOMM_PSELID_LOCK_MASK (0x8U)
\r
6945 #define FLEXCOMM_PSELID_LOCK_SHIFT (3U)
\r
6946 /*! LOCK - Lock the peripheral select. This field is writable by software.
\r
6947 * 0b0..Peripheral select can be changed by software.
\r
6948 * 0b1..Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset.
\r
6950 #define FLEXCOMM_PSELID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK)
\r
6951 #define FLEXCOMM_PSELID_USARTPRESENT_MASK (0x10U)
\r
6952 #define FLEXCOMM_PSELID_USARTPRESENT_SHIFT (4U)
\r
6953 /*! USARTPRESENT - USART present indicator. This field is Read-only.
\r
6954 * 0b0..This Flexcomm does not include the USART function.
\r
6955 * 0b1..This Flexcomm includes the USART function.
\r
6957 #define FLEXCOMM_PSELID_USARTPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK)
\r
6958 #define FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U)
\r
6959 #define FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U)
\r
6960 /*! SPIPRESENT - SPI present indicator. This field is Read-only.
\r
6961 * 0b0..This Flexcomm does not include the SPI function.
\r
6962 * 0b1..This Flexcomm includes the SPI function.
\r
6964 #define FLEXCOMM_PSELID_SPIPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK)
\r
6965 #define FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U)
\r
6966 #define FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U)
\r
6967 /*! I2CPRESENT - I2C present indicator. This field is Read-only.
\r
6968 * 0b0..This Flexcomm does not include the I2C function.
\r
6969 * 0b1..This Flexcomm includes the I2C function.
\r
6971 #define FLEXCOMM_PSELID_I2CPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK)
\r
6972 #define FLEXCOMM_PSELID_I2SPRESENT_MASK (0x80U)
\r
6973 #define FLEXCOMM_PSELID_I2SPRESENT_SHIFT (7U)
\r
6974 /*! I2SPRESENT - I 2S present indicator. This field is Read-only.
\r
6975 * 0b0..This Flexcomm does not include the I2S function.
\r
6976 * 0b1..This Flexcomm includes the I2S function.
\r
6978 #define FLEXCOMM_PSELID_I2SPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK)
\r
6979 #define FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U)
\r
6980 #define FLEXCOMM_PSELID_ID_SHIFT (12U)
\r
6981 /*! ID - Flexcomm ID.
\r
6983 #define FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK)
\r
6986 /*! @name PID - Peripheral identification register. */
\r
6988 #define FLEXCOMM_PID_Minor_Rev_MASK (0xF00U)
\r
6989 #define FLEXCOMM_PID_Minor_Rev_SHIFT (8U)
\r
6990 /*! Minor_Rev - Minor revision of module implementation.
\r
6992 #define FLEXCOMM_PID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Minor_Rev_SHIFT)) & FLEXCOMM_PID_Minor_Rev_MASK)
\r
6993 #define FLEXCOMM_PID_Major_Rev_MASK (0xF000U)
\r
6994 #define FLEXCOMM_PID_Major_Rev_SHIFT (12U)
\r
6995 /*! Major_Rev - Major revision of module implementation.
\r
6997 #define FLEXCOMM_PID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Major_Rev_SHIFT)) & FLEXCOMM_PID_Major_Rev_MASK)
\r
6998 #define FLEXCOMM_PID_ID_MASK (0xFFFF0000U)
\r
6999 #define FLEXCOMM_PID_ID_SHIFT (16U)
\r
7000 /*! ID - Module identifier for the selected function.
\r
7002 #define FLEXCOMM_PID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK)
\r
7008 */ /* end of group FLEXCOMM_Register_Masks */
\r
7011 /* FLEXCOMM - Peripheral instance base addresses */
\r
7012 /** Peripheral FLEXCOMM0 base address */
\r
7013 #define FLEXCOMM0_BASE (0x40086000u)
\r
7014 /** Peripheral FLEXCOMM0 base pointer */
\r
7015 #define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE)
\r
7016 /** Peripheral FLEXCOMM1 base address */
\r
7017 #define FLEXCOMM1_BASE (0x40087000u)
\r
7018 /** Peripheral FLEXCOMM1 base pointer */
\r
7019 #define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE)
\r
7020 /** Peripheral FLEXCOMM2 base address */
\r
7021 #define FLEXCOMM2_BASE (0x40088000u)
\r
7022 /** Peripheral FLEXCOMM2 base pointer */
\r
7023 #define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE)
\r
7024 /** Peripheral FLEXCOMM3 base address */
\r
7025 #define FLEXCOMM3_BASE (0x40089000u)
\r
7026 /** Peripheral FLEXCOMM3 base pointer */
\r
7027 #define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE)
\r
7028 /** Peripheral FLEXCOMM4 base address */
\r
7029 #define FLEXCOMM4_BASE (0x4008A000u)
\r
7030 /** Peripheral FLEXCOMM4 base pointer */
\r
7031 #define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE)
\r
7032 /** Peripheral FLEXCOMM5 base address */
\r
7033 #define FLEXCOMM5_BASE (0x40096000u)
\r
7034 /** Peripheral FLEXCOMM5 base pointer */
\r
7035 #define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE)
\r
7036 /** Peripheral FLEXCOMM6 base address */
\r
7037 #define FLEXCOMM6_BASE (0x40097000u)
\r
7038 /** Peripheral FLEXCOMM6 base pointer */
\r
7039 #define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE)
\r
7040 /** Peripheral FLEXCOMM7 base address */
\r
7041 #define FLEXCOMM7_BASE (0x40098000u)
\r
7042 /** Peripheral FLEXCOMM7 base pointer */
\r
7043 #define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE)
\r
7044 /** Peripheral FLEXCOMM8 base address */
\r
7045 #define FLEXCOMM8_BASE (0x40099000u)
\r
7046 /** Peripheral FLEXCOMM8 base pointer */
\r
7047 #define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE)
\r
7048 /** Peripheral FLEXCOMM9 base address */
\r
7049 #define FLEXCOMM9_BASE (0x4009A000u)
\r
7050 /** Peripheral FLEXCOMM9 base pointer */
\r
7051 #define FLEXCOMM9 ((FLEXCOMM_Type *)FLEXCOMM9_BASE)
\r
7052 /** Peripheral FLEXCOMM10 base address */
\r
7053 #define FLEXCOMM10_BASE (0x4009F000u)
\r
7054 /** Peripheral FLEXCOMM10 base pointer */
\r
7055 #define FLEXCOMM10 ((FLEXCOMM_Type *)FLEXCOMM10_BASE)
\r
7056 /** Array initializer of FLEXCOMM peripheral base addresses */
\r
7057 #define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE, FLEXCOMM9_BASE, FLEXCOMM10_BASE }
\r
7058 /** Array initializer of FLEXCOMM peripheral base pointers */
\r
7059 #define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, FLEXCOMM9, FLEXCOMM10 }
\r
7060 /** Interrupt vectors for the FLEXCOMM peripheral type */
\r
7061 #define FLEXCOMM_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn, FLEXCOMM10_IRQn }
\r
7065 */ /* end of group FLEXCOMM_Peripheral_Access_Layer */
\r
7068 /* ----------------------------------------------------------------------------
\r
7069 -- GINT Peripheral Access Layer
\r
7070 ---------------------------------------------------------------------------- */
\r
7073 * @addtogroup GINT_Peripheral_Access_Layer GINT Peripheral Access Layer
\r
7077 /** GINT - Register Layout Typedef */
\r
7079 __IO uint32_t CTRL; /**< GPIO grouped interrupt control register, offset: 0x0 */
\r
7080 uint8_t RESERVED_0[28];
\r
7081 __IO uint32_t PORT_POL[2]; /**< GPIO grouped interrupt port 0 polarity register, array offset: 0x20, array step: 0x4 */
\r
7082 uint8_t RESERVED_1[24];
\r
7083 __IO uint32_t PORT_ENA[2]; /**< GPIO grouped interrupt port 0 enable register, array offset: 0x40, array step: 0x4 */
\r
7086 /* ----------------------------------------------------------------------------
\r
7087 -- GINT Register Masks
\r
7088 ---------------------------------------------------------------------------- */
\r
7091 * @addtogroup GINT_Register_Masks GINT Register Masks
\r
7095 /*! @name CTRL - GPIO grouped interrupt control register */
\r
7097 #define GINT_CTRL_INT_MASK (0x1U)
\r
7098 #define GINT_CTRL_INT_SHIFT (0U)
\r
7099 /*! INT - Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect.
\r
7100 * 0b0..No request. No interrupt request is pending.
\r
7101 * 0b1..Request active. Interrupt request is active.
\r
7103 #define GINT_CTRL_INT(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK)
\r
7104 #define GINT_CTRL_COMB_MASK (0x2U)
\r
7105 #define GINT_CTRL_COMB_SHIFT (1U)
\r
7106 /*! COMB - Combine enabled inputs for group interrupt
\r
7107 * 0b0..Or. OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity).
\r
7108 * 0b1..And. AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity).
\r
7110 #define GINT_CTRL_COMB(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK)
\r
7111 #define GINT_CTRL_TRIG_MASK (0x4U)
\r
7112 #define GINT_CTRL_TRIG_SHIFT (2U)
\r
7113 /*! TRIG - Group interrupt trigger
\r
7114 * 0b0..Edge-triggered.
\r
7115 * 0b1..Level-triggered.
\r
7117 #define GINT_CTRL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK)
\r
7120 /*! @name PORT_POL - GPIO grouped interrupt port 0 polarity register */
\r
7122 #define GINT_PORT_POL_POL_MASK (0xFFFFFFFFU)
\r
7123 #define GINT_PORT_POL_POL_SHIFT (0U)
\r
7124 /*! POL - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n
\r
7125 * of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to
\r
7126 * the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin
\r
7127 * contributes to the group interrupt.
\r
7129 #define GINT_PORT_POL_POL(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK)
\r
7132 /* The count of GINT_PORT_POL */
\r
7133 #define GINT_PORT_POL_COUNT (2U)
\r
7135 /*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */
\r
7137 #define GINT_PORT_ENA_ENA_MASK (0xFFFFFFFFU)
\r
7138 #define GINT_PORT_ENA_ENA_SHIFT (0U)
\r
7139 /*! ENA - Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the
\r
7140 * port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is
\r
7141 * enabled and contributes to the grouped interrupt.
\r
7143 #define GINT_PORT_ENA_ENA(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK)
\r
7146 /* The count of GINT_PORT_ENA */
\r
7147 #define GINT_PORT_ENA_COUNT (2U)
\r
7152 */ /* end of group GINT_Register_Masks */
\r
7155 /* GINT - Peripheral instance base addresses */
\r
7156 /** Peripheral GINT0 base address */
\r
7157 #define GINT0_BASE (0x40002000u)
\r
7158 /** Peripheral GINT0 base pointer */
\r
7159 #define GINT0 ((GINT_Type *)GINT0_BASE)
\r
7160 /** Peripheral GINT1 base address */
\r
7161 #define GINT1_BASE (0x40003000u)
\r
7162 /** Peripheral GINT1 base pointer */
\r
7163 #define GINT1 ((GINT_Type *)GINT1_BASE)
\r
7164 /** Array initializer of GINT peripheral base addresses */
\r
7165 #define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE }
\r
7166 /** Array initializer of GINT peripheral base pointers */
\r
7167 #define GINT_BASE_PTRS { GINT0, GINT1 }
\r
7168 /** Interrupt vectors for the GINT peripheral type */
\r
7169 #define GINT_IRQS { GINT0_IRQn, GINT1_IRQn }
\r
7173 */ /* end of group GINT_Peripheral_Access_Layer */
\r
7176 /* ----------------------------------------------------------------------------
\r
7177 -- GPIO Peripheral Access Layer
\r
7178 ---------------------------------------------------------------------------- */
\r
7181 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
\r
7185 /** GPIO - Register Layout Typedef */
\r
7187 __IO uint8_t B[6][32]; /**< Byte pin registers for all port 0 and 1 GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */
\r
7188 uint8_t RESERVED_0[3904];
\r
7189 __IO uint32_t W[6][32]; /**< Word pin registers for all port 0 and 1 GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */
\r
7190 uint8_t RESERVED_1[3328];
\r
7191 __IO uint32_t DIR[6]; /**< Direction registers, array offset: 0x2000, array step: 0x4 */
\r
7192 uint8_t RESERVED_2[104];
\r
7193 __IO uint32_t MASK[6]; /**< Mask register, array offset: 0x2080, array step: 0x4 */
\r
7194 uint8_t RESERVED_3[104];
\r
7195 __IO uint32_t PIN[6]; /**< Port pin register, array offset: 0x2100, array step: 0x4 */
\r
7196 uint8_t RESERVED_4[104];
\r
7197 __IO uint32_t MPIN[6]; /**< Masked port register, array offset: 0x2180, array step: 0x4 */
\r
7198 uint8_t RESERVED_5[104];
\r
7199 __IO uint32_t SET[6]; /**< Write: Set register for port Read: output bits for port, array offset: 0x2200, array step: 0x4 */
\r
7200 uint8_t RESERVED_6[104];
\r
7201 __O uint32_t CLR[6]; /**< Clear port, array offset: 0x2280, array step: 0x4 */
\r
7202 uint8_t RESERVED_7[104];
\r
7203 __O uint32_t NOT[6]; /**< Toggle port, array offset: 0x2300, array step: 0x4 */
\r
7204 uint8_t RESERVED_8[104];
\r
7205 __O uint32_t DIRSET[6]; /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */
\r
7206 uint8_t RESERVED_9[104];
\r
7207 __O uint32_t DIRCLR[6]; /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */
\r
7208 uint8_t RESERVED_10[104];
\r
7209 __O uint32_t DIRNOT[6]; /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */
\r
7212 /* ----------------------------------------------------------------------------
\r
7213 -- GPIO Register Masks
\r
7214 ---------------------------------------------------------------------------- */
\r
7217 * @addtogroup GPIO_Register_Masks GPIO Register Masks
\r
7221 /*! @name B - Byte pin registers for all port 0 and 1 GPIO pins */
\r
7223 #define GPIO_B_PBYTE_MASK (0x1U)
\r
7224 #define GPIO_B_PBYTE_SHIFT (0U)
\r
7225 /*! PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function,
\r
7226 * except that pins configured as analog I/O always read as 0. One register for each port pin.
\r
7227 * Supported pins depends on the specific device and package. Write: loads the pin's output bit.
\r
7228 * One register for each port pin. Supported pins depends on the specific device and package.
\r
7230 #define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK)
\r
7233 /* The count of GPIO_B */
\r
7234 #define GPIO_B_COUNT (6U)
\r
7236 /* The count of GPIO_B */
\r
7237 #define GPIO_B_COUNT2 (32U)
\r
7239 /*! @name W - Word pin registers for all port 0 and 1 GPIO pins */
\r
7241 #define GPIO_W_PWORD_MASK (0xFFFFFFFFU)
\r
7242 #define GPIO_W_PWORD_SHIFT (0U)
\r
7243 /*! PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is
\r
7244 * HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be
\r
7245 * read. Writing any value other than 0 will set the output bit. One register for each port pin.
\r
7246 * Supported pins depends on the specific device and package.
\r
7248 #define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK)
\r
7251 /* The count of GPIO_W */
\r
7252 #define GPIO_W_COUNT (6U)
\r
7254 /* The count of GPIO_W */
\r
7255 #define GPIO_W_COUNT2 (32U)
\r
7257 /*! @name DIR - Direction registers */
\r
7259 #define GPIO_DIR_DIRP_MASK (0xFFFFFFFFU)
\r
7260 #define GPIO_DIR_DIRP_SHIFT (0U)
\r
7261 /*! DIRP - Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported
\r
7262 * pins depends on the specific device and package. 0 = input. 1 = output.
\r
7264 #define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK)
\r
7267 /* The count of GPIO_DIR */
\r
7268 #define GPIO_DIR_COUNT (6U)
\r
7270 /*! @name MASK - Mask register */
\r
7272 #define GPIO_MASK_MASKP_MASK (0xFFFFFFFFU)
\r
7273 #define GPIO_MASK_MASKP_SHIFT (0U)
\r
7274 /*! MASKP - Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 =
\r
7275 * PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 =
\r
7276 * Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit
\r
7279 #define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK)
\r
7282 /* The count of GPIO_MASK */
\r
7283 #define GPIO_MASK_COUNT (6U)
\r
7285 /*! @name PIN - Port pin register */
\r
7287 #define GPIO_PIN_PORT_MASK (0xFFFFFFFFU)
\r
7288 #define GPIO_PIN_PORT_SHIFT (0U)
\r
7289 /*! PORT - Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported
\r
7290 * pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit.
\r
7291 * 1 = Read: pin is high; write: set output bit.
\r
7293 #define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK)
\r
7296 /* The count of GPIO_PIN */
\r
7297 #define GPIO_PIN_COUNT (6U)
\r
7299 /*! @name MPIN - Masked port register */
\r
7301 #define GPIO_MPIN_MPORTP_MASK (0xFFFFFFFFU)
\r
7302 #define GPIO_MPIN_MPORTP_SHIFT (0U)
\r
7303 /*! MPORTP - Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
\r
7304 * the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK
\r
7305 * register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1
\r
7306 * = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit
\r
7307 * if the corresponding bit in the MASK register is 0.
\r
7309 #define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK)
\r
7312 /* The count of GPIO_MPIN */
\r
7313 #define GPIO_MPIN_COUNT (6U)
\r
7315 /*! @name SET - Write: Set register for port Read: output bits for port */
\r
7317 #define GPIO_SET_SETP_MASK (0xFFFFFFFFU)
\r
7318 #define GPIO_SET_SETP_SHIFT (0U)
\r
7319 /*! SETP - Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
\r
7320 * the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output
\r
7321 * bit; write: set output bit.
\r
7323 #define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK)
\r
7326 /* The count of GPIO_SET */
\r
7327 #define GPIO_SET_COUNT (6U)
\r
7329 /*! @name CLR - Clear port */
\r
7331 #define GPIO_CLR_CLRP_MASK (0xFFFFFFFFU)
\r
7332 #define GPIO_CLR_CLRP_SHIFT (0U)
\r
7333 /*! CLRP - Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the
\r
7334 * specific device and package. 0 = No operation. 1 = Clear output bit.
\r
7336 #define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK)
\r
7339 /* The count of GPIO_CLR */
\r
7340 #define GPIO_CLR_COUNT (6U)
\r
7342 /*! @name NOT - Toggle port */
\r
7344 #define GPIO_NOT_NOTP_MASK (0xFFFFFFFFU)
\r
7345 #define GPIO_NOT_NOTP_SHIFT (0U)
\r
7346 /*! NOTP - Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the
\r
7347 * specific device and package. 0 = no operation. 1 = Toggle output bit.
\r
7349 #define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK)
\r
7352 /* The count of GPIO_NOT */
\r
7353 #define GPIO_NOT_COUNT (6U)
\r
7355 /*! @name DIRSET - Set pin direction bits for port */
\r
7357 #define GPIO_DIRSET_DIRSETP_MASK (0x1FFFFFFFU)
\r
7358 #define GPIO_DIRSET_DIRSETP_SHIFT (0U)
\r
7359 /*! DIRSETP - Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
\r
7360 * the specific device and package. 0 = No operation. 1 = Set direction bit.
\r
7362 #define GPIO_DIRSET_DIRSETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK)
\r
7365 /* The count of GPIO_DIRSET */
\r
7366 #define GPIO_DIRSET_COUNT (6U)
\r
7368 /*! @name DIRCLR - Clear pin direction bits for port */
\r
7370 #define GPIO_DIRCLR_DIRCLRP_MASK (0x1FFFFFFFU)
\r
7371 #define GPIO_DIRCLR_DIRCLRP_SHIFT (0U)
\r
7372 /*! DIRCLRP - Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
\r
7373 * the specific device and package. 0 = No operation. 1 = Clear direction bit.
\r
7375 #define GPIO_DIRCLR_DIRCLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK)
\r
7378 /* The count of GPIO_DIRCLR */
\r
7379 #define GPIO_DIRCLR_COUNT (6U)
\r
7381 /*! @name DIRNOT - Toggle pin direction bits for port */
\r
7383 #define GPIO_DIRNOT_DIRNOTP_MASK (0x1FFFFFFFU)
\r
7384 #define GPIO_DIRNOT_DIRNOTP_SHIFT (0U)
\r
7385 /*! DIRNOTP - Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends
\r
7386 * on the specific device and package. 0 = no operation. 1 = Toggle direction bit.
\r
7388 #define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK)
\r
7391 /* The count of GPIO_DIRNOT */
\r
7392 #define GPIO_DIRNOT_COUNT (6U)
\r
7397 */ /* end of group GPIO_Register_Masks */
\r
7400 /* GPIO - Peripheral instance base addresses */
\r
7401 /** Peripheral GPIO base address */
\r
7402 #define GPIO_BASE (0x4008C000u)
\r
7403 /** Peripheral GPIO base pointer */
\r
7404 #define GPIO ((GPIO_Type *)GPIO_BASE)
\r
7405 /** Array initializer of GPIO peripheral base addresses */
\r
7406 #define GPIO_BASE_ADDRS { GPIO_BASE }
\r
7407 /** Array initializer of GPIO peripheral base pointers */
\r
7408 #define GPIO_BASE_PTRS { GPIO }
\r
7412 */ /* end of group GPIO_Peripheral_Access_Layer */
\r
7415 /* ----------------------------------------------------------------------------
\r
7416 -- I2C Peripheral Access Layer
\r
7417 ---------------------------------------------------------------------------- */
\r
7420 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
\r
7424 /** I2C - Register Layout Typedef */
\r
7426 uint8_t RESERVED_0[2048];
\r
7427 __IO uint32_t CFG; /**< Configuration for shared functions., offset: 0x800 */
\r
7428 __IO uint32_t STAT; /**< Status register for Master, Slave, and Monitor functions., offset: 0x804 */
\r
7429 __IO uint32_t INTENSET; /**< Interrupt Enable Set and read register., offset: 0x808 */
\r
7430 __O uint32_t INTENCLR; /**< Interrupt Enable Clear register., offset: 0x80C */
\r
7431 __IO uint32_t TIMEOUT; /**< Time-out value register., offset: 0x810 */
\r
7432 __IO uint32_t CLKDIV; /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x814 */
\r
7433 __I uint32_t INTSTAT; /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x818 */
\r
7434 uint8_t RESERVED_1[4];
\r
7435 __IO uint32_t MSTCTL; /**< Master control register., offset: 0x820 */
\r
7436 __IO uint32_t MSTTIME; /**< Master timing configuration., offset: 0x824 */
\r
7437 __IO uint32_t MSTDAT; /**< Combined Master receiver and transmitter data register., offset: 0x828 */
\r
7438 uint8_t RESERVED_2[20];
\r
7439 __IO uint32_t SLVCTL; /**< Slave control register., offset: 0x840 */
\r
7440 __IO uint32_t SLVDAT; /**< Combined Slave receiver and transmitter data register., offset: 0x844 */
\r
7441 __IO uint32_t SLVADR[4]; /**< Slave address register., array offset: 0x848, array step: 0x4 */
\r
7442 __IO uint32_t SLVQUAL0; /**< Slave Qualification for address 0., offset: 0x858 */
\r
7443 uint8_t RESERVED_3[36];
\r
7444 __I uint32_t MONRXDAT; /**< Monitor receiver data register., offset: 0x880 */
\r
7445 uint8_t RESERVED_4[1912];
\r
7446 __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */
\r
7449 /* ----------------------------------------------------------------------------
\r
7450 -- I2C Register Masks
\r
7451 ---------------------------------------------------------------------------- */
\r
7454 * @addtogroup I2C_Register_Masks I2C Register Masks
\r
7458 /*! @name CFG - Configuration for shared functions. */
\r
7460 #define I2C_CFG_MSTEN_MASK (0x1U)
\r
7461 #define I2C_CFG_MSTEN_SHIFT (0U)
\r
7462 /*! MSTEN - Master Enable. When disabled, configurations settings for the Master function are not
\r
7463 * changed, but the Master function is internally reset.
\r
7464 * 0b0..Disabled. The I2C Master function is disabled.
\r
7465 * 0b1..Enabled. The I2C Master function is enabled.
\r
7467 #define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK)
\r
7468 #define I2C_CFG_SLVEN_MASK (0x2U)
\r
7469 #define I2C_CFG_SLVEN_SHIFT (1U)
\r
7470 /*! SLVEN - Slave Enable. When disabled, configurations settings for the Slave function are not
\r
7471 * changed, but the Slave function is internally reset.
\r
7472 * 0b0..Disabled. The I2C slave function is disabled.
\r
7473 * 0b1..Enabled. The I2C slave function is enabled.
\r
7475 #define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK)
\r
7476 #define I2C_CFG_MONEN_MASK (0x4U)
\r
7477 #define I2C_CFG_MONEN_SHIFT (2U)
\r
7478 /*! MONEN - Monitor Enable. When disabled, configurations settings for the Monitor function are not
\r
7479 * changed, but the Monitor function is internally reset.
\r
7480 * 0b0..Disabled. The I2C Monitor function is disabled.
\r
7481 * 0b1..Enabled. The I2C Monitor function is enabled.
\r
7483 #define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK)
\r
7484 #define I2C_CFG_TIMEOUTEN_MASK (0x8U)
\r
7485 #define I2C_CFG_TIMEOUTEN_SHIFT (3U)
\r
7486 /*! TIMEOUTEN - I2C bus Time-out Enable. When disabled, the time-out function is internally reset.
\r
7487 * 0b0..Disabled. Time-out function is disabled.
\r
7488 * 0b1..Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause
\r
7489 * interrupts if they are enabled. Typically, only one time-out will be used in a system.
\r
7491 #define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK)
\r
7492 #define I2C_CFG_MONCLKSTR_MASK (0x10U)
\r
7493 #define I2C_CFG_MONCLKSTR_SHIFT (4U)
\r
7494 /*! MONCLKSTR - Monitor function Clock Stretching.
\r
7495 * 0b0..Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able
\r
7496 * to read data provided by the Monitor function before it is overwritten. This mode may be used when
\r
7497 * non-invasive monitoring is critical.
\r
7498 * 0b1..Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can
\r
7499 * read all incoming data supplied by the Monitor function.
\r
7501 #define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK)
\r
7502 #define I2C_CFG_HSCAPABLE_MASK (0x20U)
\r
7503 #define I2C_CFG_HSCAPABLE_SHIFT (5U)
\r
7504 /*! HSCAPABLE - High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive
\r
7505 * and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies
\r
7506 * to all functions: Master, Slave, and Monitor.
\r
7507 * 0b0..Fast-mode plus. The I 2C interface will support Standard-mode, Fast-mode, and Fast-mode Plus, to the
\r
7508 * extent that the pin electronics support these modes. Any changes that need to be made to the pin controls,
\r
7509 * such as changing the drive strength or filtering, must be made by software via the IOCON register associated
\r
7510 * with each I2C pin,
\r
7511 * 0b1..High-speed. In addition to Standard-mode, Fast-mode, and Fast-mode Plus, the I 2C interface will support
\r
7512 * High-speed mode to the extent that the pin electronics support these modes. See Section 25.7.2.2 for more
\r
7515 #define I2C_CFG_HSCAPABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK)
\r
7518 /*! @name STAT - Status register for Master, Slave, and Monitor functions. */
\r
7520 #define I2C_STAT_MSTPENDING_MASK (0x1U)
\r
7521 #define I2C_STAT_MSTPENDING_SHIFT (0U)
\r
7522 /*! MSTPENDING - Master Pending. Indicates that the Master is waiting to continue communication on
\r
7523 * the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what
\r
7524 * type of software service if any the master expects. This flag will cause an interrupt when set
\r
7525 * if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling
\r
7526 * an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle
\r
7527 * state, and no communication is needed, mask this interrupt.
\r
7528 * 0b0..In progress. Communication is in progress and the Master function is busy and cannot currently accept a command.
\r
7529 * 0b1..Pending. The Master function needs software service or is in the idle state. If the master is not in the
\r
7530 * idle state, it is waiting to receive or transmit data or the NACK bit.
\r
7532 #define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK)
\r
7533 #define I2C_STAT_MSTSTATE_MASK (0xEU)
\r
7534 #define I2C_STAT_MSTSTATE_SHIFT (1U)
\r
7535 /*! MSTSTATE - Master State code. The master state code reflects the master state when the
\r
7536 * MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field
\r
7537 * indicates a specific required service for the Master function. All other values are reserved. See
\r
7538 * Table 400 for details of state values and appropriate responses.
\r
7539 * 0b000..Idle. The Master function is available to be used for a new transaction.
\r
7540 * 0b001..Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave.
\r
7541 * 0b010..Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave.
\r
7542 * 0b011..NACK Address. Slave NACKed address.
\r
7543 * 0b100..NACK Data. Slave NACKed transmitted data.
\r
7545 #define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK)
\r
7546 #define I2C_STAT_MSTARBLOSS_MASK (0x10U)
\r
7547 #define I2C_STAT_MSTARBLOSS_SHIFT (4U)
\r
7548 /*! MSTARBLOSS - Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to
\r
7549 * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.
\r
7550 * 0b0..No Arbitration Loss has occurred.
\r
7551 * 0b1..Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master
\r
7552 * function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing,
\r
7553 * or by sending a Start in order to attempt to gain control of the bus when it next becomes idle.
\r
7555 #define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK)
\r
7556 #define I2C_STAT_MSTSTSTPERR_MASK (0x40U)
\r
7557 #define I2C_STAT_MSTSTSTPERR_SHIFT (6U)
\r
7558 /*! MSTSTSTPERR - Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to
\r
7559 * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.
\r
7560 * 0b0..No Start/Stop Error has occurred.
\r
7561 * 0b1..The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is
\r
7562 * not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an
\r
7563 * idle state, no action is required. A request for a Start could be made, or software could attempt to insure
\r
7564 * that the bus has not stalled.
\r
7566 #define I2C_STAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK)
\r
7567 #define I2C_STAT_SLVPENDING_MASK (0x100U)
\r
7568 #define I2C_STAT_SLVPENDING_SHIFT (8U)
\r
7569 /*! SLVPENDING - Slave Pending. Indicates that the Slave function is waiting to continue
\r
7570 * communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if
\r
7571 * enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the
\r
7572 * SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is
\r
7573 * automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time
\r
7574 * when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section
\r
7575 * 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are
\r
7576 * detected automatically. Due to the requirements of the HS I2C specification, slave addresses must
\r
7577 * also be detected automatically, since the address must be acknowledged before the clock can be
\r
7579 * 0b0..In progress. The Slave function does not currently need service.
\r
7580 * 0b1..Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field.
\r
7582 #define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK)
\r
7583 #define I2C_STAT_SLVSTATE_MASK (0x600U)
\r
7584 #define I2C_STAT_SLVSTATE_SHIFT (9U)
\r
7585 /*! SLVSTATE - Slave State code. Each value of this field indicates a specific required service for
\r
7586 * the Slave function. All other values are reserved. See Table 401 for state values and actions.
\r
7587 * note that the occurrence of some states and how they are handled are affected by DMA mode and
\r
7588 * Automatic Operation modes.
\r
7589 * 0b00..Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware.
\r
7590 * 0b01..Slave receive. Received data is available (Slave Receiver mode).
\r
7591 * 0b10..Slave transmit. Data can be transmitted (Slave Transmitter mode).
\r
7593 #define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK)
\r
7594 #define I2C_STAT_SLVNOTSTR_MASK (0x800U)
\r
7595 #define I2C_STAT_SLVNOTSTR_SHIFT (11U)
\r
7596 /*! SLVNOTSTR - Slave Not Stretching. Indicates when the slave function is stretching the I2C clock.
\r
7597 * This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave
\r
7598 * operation. This read-only flag reflects the slave function status in real time.
\r
7599 * 0b0..Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time.
\r
7600 * 0b1..Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or
\r
7601 * Power-down mode could be entered at this time.
\r
7603 #define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK)
\r
7604 #define I2C_STAT_SLVIDX_MASK (0x3000U)
\r
7605 #define I2C_STAT_SLVIDX_SHIFT (12U)
\r
7606 /*! SLVIDX - Slave address match Index. This field is valid when the I2C slave function has been
\r
7607 * selected by receiving an address that matches one of the slave addresses defined by any enabled
\r
7608 * slave address registers, and provides an identification of the address that was matched. It is
\r
7609 * possible that more than one address could be matched, but only one match can be reported here.
\r
7610 * 0b00..Address 0. Slave address 0 was matched.
\r
7611 * 0b01..Address 1. Slave address 1 was matched.
\r
7612 * 0b10..Address 2. Slave address 2 was matched.
\r
7613 * 0b11..Address 3. Slave address 3 was matched.
\r
7615 #define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK)
\r
7616 #define I2C_STAT_SLVSEL_MASK (0x4000U)
\r
7617 #define I2C_STAT_SLVSEL_SHIFT (14U)
\r
7618 /*! SLVSEL - Slave selected flag. SLVSEL is set after an address match when software tells the Slave
\r
7619 * function to acknowledge the address, or when the address has been automatically acknowledged.
\r
7620 * It is cleared when another address cycle presents an address that does not match an enabled
\r
7621 * address on the Slave function, when slave software decides to NACK a matched address, when
\r
7622 * there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of
\r
7623 * Automatic Operation. SLVSEL is not cleared if software NACKs data.
\r
7624 * 0b0..Not selected. The Slave function is not currently selected.
\r
7625 * 0b1..Selected. The Slave function is currently selected.
\r
7627 #define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK)
\r
7628 #define I2C_STAT_SLVDESEL_MASK (0x8000U)
\r
7629 #define I2C_STAT_SLVDESEL_SHIFT (15U)
\r
7630 /*! SLVDESEL - Slave Deselected flag. This flag will cause an interrupt when set if enabled via
\r
7631 * INTENSET. This flag can be cleared by writing a 1 to this bit.
\r
7632 * 0b0..Not deselected. The Slave function has not become deselected. This does not mean that it is currently
\r
7633 * selected. That information can be found in the SLVSEL flag.
\r
7634 * 0b1..Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag
\r
7635 * changing from 1 to 0. See the description of SLVSEL for details on when that event occurs.
\r
7637 #define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK)
\r
7638 #define I2C_STAT_MONRDY_MASK (0x10000U)
\r
7639 #define I2C_STAT_MONRDY_SHIFT (16U)
\r
7640 /*! MONRDY - Monitor Ready. This flag is cleared when the MONRXDAT register is read.
\r
7641 * 0b0..No data. The Monitor function does not currently have data available.
\r
7642 * 0b1..Data waiting. The Monitor function has data waiting to be read.
\r
7644 #define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK)
\r
7645 #define I2C_STAT_MONOV_MASK (0x20000U)
\r
7646 #define I2C_STAT_MONOV_SHIFT (17U)
\r
7647 /*! MONOV - Monitor Overflow flag.
\r
7648 * 0b0..No overrun. Monitor data has not overrun.
\r
7649 * 0b1..Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not
\r
7650 * enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag.
\r
7652 #define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK)
\r
7653 #define I2C_STAT_MONACTIVE_MASK (0x40000U)
\r
7654 #define I2C_STAT_MONACTIVE_SHIFT (18U)
\r
7655 /*! MONACTIVE - Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to
\r
7656 * be active. Active is defined here as when some Master is on the bus: a bus Start has occurred
\r
7657 * more recently than a bus Stop.
\r
7658 * 0b0..Inactive. The Monitor function considers the I2C bus to be inactive.
\r
7659 * 0b1..Active. The Monitor function considers the I2C bus to be active.
\r
7661 #define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK)
\r
7662 #define I2C_STAT_MONIDLE_MASK (0x80000U)
\r
7663 #define I2C_STAT_MONIDLE_SHIFT (19U)
\r
7664 /*! MONIDLE - Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change
\r
7665 * from active to inactive. This can be used by software to decide when to process data
\r
7666 * accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the
\r
7667 * INTENSET register. The flag can be cleared by writing a 1 to this bit.
\r
7668 * 0b0..Not idle. The I2C bus is not idle, or this flag has been cleared by software.
\r
7669 * 0b1..Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software.
\r
7671 #define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK)
\r
7672 #define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U)
\r
7673 #define I2C_STAT_EVENTTIMEOUT_SHIFT (24U)
\r
7674 /*! EVENTTIMEOUT - Event Time-out Interrupt flag. Indicates when the time between events has been
\r
7675 * longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock
\r
7676 * edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus
\r
7678 * 0b0..No time-out. I2C bus events have not caused a time-out.
\r
7679 * 0b1..Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register.
\r
7681 #define I2C_STAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK)
\r
7682 #define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U)
\r
7683 #define I2C_STAT_SCLTIMEOUT_SHIFT (25U)
\r
7684 /*! SCLTIMEOUT - SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the
\r
7685 * time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit.
\r
7686 * 0b0..No time-out. SCL low time has not caused a time-out.
\r
7687 * 0b1..Time-out. SCL low time has caused a time-out.
\r
7689 #define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK)
\r
7692 /*! @name INTENSET - Interrupt Enable Set and read register. */
\r
7694 #define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U)
\r
7695 #define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U)
\r
7696 /*! MSTPENDINGEN - Master Pending interrupt Enable.
\r
7697 * 0b0..Disabled. The MstPending interrupt is disabled.
\r
7698 * 0b1..Enabled. The MstPending interrupt is enabled.
\r
7700 #define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK)
\r
7701 #define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U)
\r
7702 #define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U)
\r
7703 /*! MSTARBLOSSEN - Master Arbitration Loss interrupt Enable.
\r
7704 * 0b0..Disabled. The MstArbLoss interrupt is disabled.
\r
7705 * 0b1..Enabled. The MstArbLoss interrupt is enabled.
\r
7707 #define I2C_INTENSET_MSTARBLOSSEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK)
\r
7708 #define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U)
\r
7709 #define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U)
\r
7710 /*! MSTSTSTPERREN - Master Start/Stop Error interrupt Enable.
\r
7711 * 0b0..Disabled. The MstStStpErr interrupt is disabled.
\r
7712 * 0b1..Enabled. The MstStStpErr interrupt is enabled.
\r
7714 #define I2C_INTENSET_MSTSTSTPERREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK)
\r
7715 #define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U)
\r
7716 #define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U)
\r
7717 /*! SLVPENDINGEN - Slave Pending interrupt Enable.
\r
7718 * 0b0..Disabled. The SlvPending interrupt is disabled.
\r
7719 * 0b1..Enabled. The SlvPending interrupt is enabled.
\r
7721 #define I2C_INTENSET_SLVPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK)
\r
7722 #define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U)
\r
7723 #define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U)
\r
7724 /*! SLVNOTSTREN - Slave Not Stretching interrupt Enable.
\r
7725 * 0b0..Disabled. The SlvNotStr interrupt is disabled.
\r
7726 * 0b1..Enabled. The SlvNotStr interrupt is enabled.
\r
7728 #define I2C_INTENSET_SLVNOTSTREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK)
\r
7729 #define I2C_INTENSET_SLVDESELEN_MASK (0x8000U)
\r
7730 #define I2C_INTENSET_SLVDESELEN_SHIFT (15U)
\r
7731 /*! SLVDESELEN - Slave Deselect interrupt Enable.
\r
7732 * 0b0..Disabled. The SlvDeSel interrupt is disabled.
\r
7733 * 0b1..Enabled. The SlvDeSel interrupt is enabled.
\r
7735 #define I2C_INTENSET_SLVDESELEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK)
\r
7736 #define I2C_INTENSET_MONRDYEN_MASK (0x10000U)
\r
7737 #define I2C_INTENSET_MONRDYEN_SHIFT (16U)
\r
7738 /*! MONRDYEN - Monitor data Ready interrupt Enable.
\r
7739 * 0b0..Disabled. The MonRdy interrupt is disabled.
\r
7740 * 0b1..Enabled. The MonRdy interrupt is enabled.
\r
7742 #define I2C_INTENSET_MONRDYEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK)
\r
7743 #define I2C_INTENSET_MONOVEN_MASK (0x20000U)
\r
7744 #define I2C_INTENSET_MONOVEN_SHIFT (17U)
\r
7745 /*! MONOVEN - Monitor Overrun interrupt Enable.
\r
7746 * 0b0..Disabled. The MonOv interrupt is disabled.
\r
7747 * 0b1..Enabled. The MonOv interrupt is enabled.
\r
7749 #define I2C_INTENSET_MONOVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK)
\r
7750 #define I2C_INTENSET_MONIDLEEN_MASK (0x80000U)
\r
7751 #define I2C_INTENSET_MONIDLEEN_SHIFT (19U)
\r
7752 /*! MONIDLEEN - Monitor Idle interrupt Enable.
\r
7753 * 0b0..Disabled. The MonIdle interrupt is disabled.
\r
7754 * 0b1..Enabled. The MonIdle interrupt is enabled.
\r
7756 #define I2C_INTENSET_MONIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK)
\r
7757 #define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U)
\r
7758 #define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U)
\r
7759 /*! EVENTTIMEOUTEN - Event time-out interrupt Enable.
\r
7760 * 0b0..Disabled. The Event time-out interrupt is disabled.
\r
7761 * 0b1..Enabled. The Event time-out interrupt is enabled.
\r
7763 #define I2C_INTENSET_EVENTTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK)
\r
7764 #define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U)
\r
7765 #define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U)
\r
7766 /*! SCLTIMEOUTEN - SCL time-out interrupt Enable.
\r
7767 * 0b0..Disabled. The SCL time-out interrupt is disabled.
\r
7768 * 0b1..Enabled. The SCL time-out interrupt is enabled.
\r
7770 #define I2C_INTENSET_SCLTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK)
\r
7773 /*! @name INTENCLR - Interrupt Enable Clear register. */
\r
7775 #define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U)
\r
7776 #define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U)
\r
7777 /*! MSTPENDINGCLR - Master Pending interrupt clear. Writing 1 to this bit clears the corresponding
\r
7778 * bit in the INTENSET register if implemented.
\r
7780 #define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK)
\r
7781 #define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U)
\r
7782 #define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U)
\r
7783 /*! MSTARBLOSSCLR - Master Arbitration Loss interrupt clear.
\r
7785 #define I2C_INTENCLR_MSTARBLOSSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK)
\r
7786 #define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U)
\r
7787 #define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U)
\r
7788 /*! MSTSTSTPERRCLR - Master Start/Stop Error interrupt clear.
\r
7790 #define I2C_INTENCLR_MSTSTSTPERRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK)
\r
7791 #define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U)
\r
7792 #define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U)
\r
7793 /*! SLVPENDINGCLR - Slave Pending interrupt clear.
\r
7795 #define I2C_INTENCLR_SLVPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK)
\r
7796 #define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U)
\r
7797 #define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U)
\r
7798 /*! SLVNOTSTRCLR - Slave Not Stretching interrupt clear.
\r
7800 #define I2C_INTENCLR_SLVNOTSTRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK)
\r
7801 #define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U)
\r
7802 #define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U)
\r
7803 /*! SLVDESELCLR - Slave Deselect interrupt clear.
\r
7805 #define I2C_INTENCLR_SLVDESELCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK)
\r
7806 #define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U)
\r
7807 #define I2C_INTENCLR_MONRDYCLR_SHIFT (16U)
\r
7808 /*! MONRDYCLR - Monitor data Ready interrupt clear.
\r
7810 #define I2C_INTENCLR_MONRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK)
\r
7811 #define I2C_INTENCLR_MONOVCLR_MASK (0x20000U)
\r
7812 #define I2C_INTENCLR_MONOVCLR_SHIFT (17U)
\r
7813 /*! MONOVCLR - Monitor Overrun interrupt clear.
\r
7815 #define I2C_INTENCLR_MONOVCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK)
\r
7816 #define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U)
\r
7817 #define I2C_INTENCLR_MONIDLECLR_SHIFT (19U)
\r
7818 /*! MONIDLECLR - Monitor Idle interrupt clear.
\r
7820 #define I2C_INTENCLR_MONIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK)
\r
7821 #define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U)
\r
7822 #define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U)
\r
7823 /*! EVENTTIMEOUTCLR - Event time-out interrupt clear.
\r
7825 #define I2C_INTENCLR_EVENTTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK)
\r
7826 #define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U)
\r
7827 #define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U)
\r
7828 /*! SCLTIMEOUTCLR - SCL time-out interrupt clear.
\r
7830 #define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK)
\r
7833 /*! @name TIMEOUT - Time-out value register. */
\r
7835 #define I2C_TIMEOUT_TOMIN_MASK (0xFU)
\r
7836 #define I2C_TIMEOUT_TOMIN_SHIFT (0U)
\r
7837 /*! TOMIN - Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum
\r
7838 * time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks.
\r
7840 #define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK)
\r
7841 #define I2C_TIMEOUT_TO_MASK (0xFFF0U)
\r
7842 #define I2C_TIMEOUT_TO_SHIFT (4U)
\r
7843 /*! TO - Time-out time value. Specifies the time-out interval value in increments of 16 I 2C
\r
7844 * function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation,
\r
7845 * disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A
\r
7846 * time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after
\r
7847 * 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the
\r
7848 * I2C function clock.
\r
7850 #define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK)
\r
7853 /*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */
\r
7855 #define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU)
\r
7856 #define I2C_CLKDIV_DIVVAL_SHIFT (0U)
\r
7857 /*! DIVVAL - This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that
\r
7858 * need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 =
\r
7859 * FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is
\r
7860 * divided by 65,536 before use.
\r
7862 #define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK)
\r
7865 /*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */
\r
7867 #define I2C_INTSTAT_MSTPENDING_MASK (0x1U)
\r
7868 #define I2C_INTSTAT_MSTPENDING_SHIFT (0U)
\r
7869 /*! MSTPENDING - Master Pending.
\r
7871 #define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK)
\r
7872 #define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U)
\r
7873 #define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U)
\r
7874 /*! MSTARBLOSS - Master Arbitration Loss flag.
\r
7876 #define I2C_INTSTAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK)
\r
7877 #define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U)
\r
7878 #define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U)
\r
7879 /*! MSTSTSTPERR - Master Start/Stop Error flag.
\r
7881 #define I2C_INTSTAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK)
\r
7882 #define I2C_INTSTAT_SLVPENDING_MASK (0x100U)
\r
7883 #define I2C_INTSTAT_SLVPENDING_SHIFT (8U)
\r
7884 /*! SLVPENDING - Slave Pending.
\r
7886 #define I2C_INTSTAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK)
\r
7887 #define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U)
\r
7888 #define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U)
\r
7889 /*! SLVNOTSTR - Slave Not Stretching status.
\r
7891 #define I2C_INTSTAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK)
\r
7892 #define I2C_INTSTAT_SLVDESEL_MASK (0x8000U)
\r
7893 #define I2C_INTSTAT_SLVDESEL_SHIFT (15U)
\r
7894 /*! SLVDESEL - Slave Deselected flag.
\r
7896 #define I2C_INTSTAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK)
\r
7897 #define I2C_INTSTAT_MONRDY_MASK (0x10000U)
\r
7898 #define I2C_INTSTAT_MONRDY_SHIFT (16U)
\r
7899 /*! MONRDY - Monitor Ready.
\r
7901 #define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK)
\r
7902 #define I2C_INTSTAT_MONOV_MASK (0x20000U)
\r
7903 #define I2C_INTSTAT_MONOV_SHIFT (17U)
\r
7904 /*! MONOV - Monitor Overflow flag.
\r
7906 #define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK)
\r
7907 #define I2C_INTSTAT_MONIDLE_MASK (0x80000U)
\r
7908 #define I2C_INTSTAT_MONIDLE_SHIFT (19U)
\r
7909 /*! MONIDLE - Monitor Idle flag.
\r
7911 #define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK)
\r
7912 #define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U)
\r
7913 #define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U)
\r
7914 /*! EVENTTIMEOUT - Event time-out Interrupt flag.
\r
7916 #define I2C_INTSTAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK)
\r
7917 #define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U)
\r
7918 #define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U)
\r
7919 /*! SCLTIMEOUT - SCL time-out Interrupt flag.
\r
7921 #define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK)
\r
7924 /*! @name MSTCTL - Master control register. */
\r
7926 #define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U)
\r
7927 #define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U)
\r
7928 /*! MSTCONTINUE - Master Continue. This bit is write-only.
\r
7930 * 0b1..Continue. Informs the Master function to continue to the next operation. This must done after writing
\r
7931 * transmit data, reading received data, or any other housekeeping related to the next bus operation.
\r
7933 #define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK)
\r
7934 #define I2C_MSTCTL_MSTSTART_MASK (0x2U)
\r
7935 #define I2C_MSTCTL_MSTSTART_SHIFT (1U)
\r
7936 /*! MSTSTART - Master Start control. This bit is write-only.
\r
7938 * 0b1..Start. A Start will be generated on the I2C bus at the next allowed time.
\r
7940 #define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK)
\r
7941 #define I2C_MSTCTL_MSTSTOP_MASK (0x4U)
\r
7942 #define I2C_MSTCTL_MSTSTOP_SHIFT (2U)
\r
7943 /*! MSTSTOP - Master Stop control. This bit is write-only.
\r
7945 * 0b1..Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave
\r
7946 * if the master is receiving data from the slave (Master Receiver mode).
\r
7948 #define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK)
\r
7949 #define I2C_MSTCTL_MSTDMA_MASK (0x8U)
\r
7950 #define I2C_MSTCTL_MSTDMA_SHIFT (3U)
\r
7951 /*! MSTDMA - Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type
\r
7952 * operations such as Start, address, Stop, and address match must always be done with software,
\r
7953 * typically via an interrupt. Address acknowledgement must also be done by software except when
\r
7954 * the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by
\r
7955 * hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA
\r
7956 * must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is
\r
7958 * 0b0..Disable. No DMA requests are generated for master operation.
\r
7959 * 0b1..Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating
\r
7960 * Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically.
\r
7962 #define I2C_MSTCTL_MSTDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK)
\r
7965 /*! @name MSTTIME - Master timing configuration. */
\r
7967 #define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U)
\r
7968 #define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U)
\r
7969 /*! MSTSCLLOW - Master SCL Low time. Specifies the minimum low time that will be asserted by this
\r
7970 * master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This
\r
7971 * corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters
\r
7972 * tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW.
\r
7973 * 0b000..2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider.
\r
7974 * 0b001..3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider.
\r
7975 * 0b010..4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider.
\r
7976 * 0b011..5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider.
\r
7977 * 0b100..6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider.
\r
7978 * 0b101..7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider.
\r
7979 * 0b110..8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider.
\r
7980 * 0b111..9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider.
\r
7982 #define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK)
\r
7983 #define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U)
\r
7984 #define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U)
\r
7985 /*! MSTSCLHIGH - Master SCL High time. Specifies the minimum high time that will be asserted by this
\r
7986 * master on SCL. Other masters in a multi-master system could shorten this time. This
\r
7987 * corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters
\r
7988 * tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH.
\r
7989 * 0b000..2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider.
\r
7990 * 0b001..3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider .
\r
7991 * 0b010..4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider.
\r
7992 * 0b011..5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider.
\r
7993 * 0b100..6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider.
\r
7994 * 0b101..7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider.
\r
7995 * 0b110..8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider.
\r
7996 * 0b111..9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider.
\r
7998 #define I2C_MSTTIME_MSTSCLHIGH(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK)
\r
8001 /*! @name MSTDAT - Combined Master receiver and transmitter data register. */
\r
8003 #define I2C_MSTDAT_DATA_MASK (0xFFU)
\r
8004 #define I2C_MSTDAT_DATA_SHIFT (0U)
\r
8005 /*! DATA - Master function data register. Read: read the most recently received data for the Master
\r
8006 * function. Write: transmit data using the Master function.
\r
8008 #define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK)
\r
8011 /*! @name SLVCTL - Slave control register. */
\r
8013 #define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U)
\r
8014 #define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U)
\r
8015 /*! SLVCONTINUE - Slave Continue.
\r
8017 * 0b1..Continue. Informs the Slave function to continue to the next operation, by clearing the SLVPENDING flag
\r
8018 * in the STAT register. This must be done after writing transmit data, reading received data, or any other
\r
8019 * housekeeping related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE
\r
8020 * should not be set unless SLVPENDING = 1.
\r
8022 #define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK)
\r
8023 #define I2C_SLVCTL_SLVNACK_MASK (0x2U)
\r
8024 #define I2C_SLVCTL_SLVNACK_SHIFT (1U)
\r
8025 /*! SLVNACK - Slave NACK.
\r
8027 * 0b1..NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode).
\r
8029 #define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK)
\r
8030 #define I2C_SLVCTL_SLVDMA_MASK (0x8U)
\r
8031 #define I2C_SLVCTL_SLVDMA_SHIFT (3U)
\r
8032 /*! SLVDMA - Slave DMA enable.
\r
8033 * 0b0..Disabled. No DMA requests are issued for Slave mode operation.
\r
8034 * 0b1..Enabled. DMA requests are issued for I2C slave data transmission and reception.
\r
8036 #define I2C_SLVCTL_SLVDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK)
\r
8037 #define I2C_SLVCTL_AUTOACK_MASK (0x100U)
\r
8038 #define I2C_SLVCTL_AUTOACK_SHIFT (8U)
\r
8039 /*! AUTOACK - Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches
\r
8040 * SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA
\r
8041 * to allow processing of the data without intervention. If this bit is clear and a header
\r
8042 * matches SLVADR0, the behavior is controlled by AUTONACK in the SLVADR0 register: allowing NACK or
\r
8044 * 0b0..Normal, non-automatic operation. If AUTONACK = 0, an SlvPending interrupt is generated when a matching
\r
8045 * address is received. If AUTONACK = 1, received addresses are NACKed (ignored).
\r
8046 * 0b1..A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately,
\r
8047 * allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does
\r
8048 * not match AUTOMATCHREAD, the behavior will depend on the AUTONACK bit in the SLVADR0 register: if AUTONACK
\r
8049 * is set, then it will be Nacked; else if AUTONACK is clear, then a SlvPending interrupt is generated.
\r
8051 #define I2C_SLVCTL_AUTOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK)
\r
8052 #define I2C_SLVCTL_AUTOMATCHREAD_MASK (0x200U)
\r
8053 #define I2C_SLVCTL_AUTOMATCHREAD_SHIFT (9U)
\r
8054 /*! AUTOMATCHREAD - When AUTOACK is set, this bit controls whether it matches a read or write
\r
8055 * request on the next header with an address matching SLVADR0. Since DMA needs to be configured to
\r
8056 * match the transfer direction, the direction needs to be specified. This bit allows a direction to
\r
8057 * be chosen for the next operation.
\r
8058 * 0b0..The expected next operation in Automatic Mode is an I2C write.
\r
8059 * 0b1..The expected next operation in Automatic Mode is an I2C read.
\r
8061 #define I2C_SLVCTL_AUTOMATCHREAD(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK)
\r
8064 /*! @name SLVDAT - Combined Slave receiver and transmitter data register. */
\r
8066 #define I2C_SLVDAT_DATA_MASK (0xFFU)
\r
8067 #define I2C_SLVDAT_DATA_SHIFT (0U)
\r
8068 /*! DATA - Slave function data register. Read: read the most recently received data for the Slave
\r
8069 * function. Write: transmit data using the Slave function.
\r
8071 #define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK)
\r
8074 /*! @name SLVADR - Slave address register. */
\r
8076 #define I2C_SLVADR_SADISABLE_MASK (0x1U)
\r
8077 #define I2C_SLVADR_SADISABLE_SHIFT (0U)
\r
8078 /*! SADISABLE - Slave Address n Disable.
\r
8079 * 0b0..Enabled. Slave Address n is enabled.
\r
8080 * 0b1..Ignored Slave Address n is ignored.
\r
8082 #define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK)
\r
8083 #define I2C_SLVADR_SLVADR_MASK (0xFEU)
\r
8084 #define I2C_SLVADR_SLVADR_SHIFT (1U)
\r
8085 /*! SLVADR - Slave Address. Seven bit slave address that is compared to received addresses if enabled.
\r
8087 #define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK)
\r
8088 #define I2C_SLVADR_AUTONACK_MASK (0x8000U)
\r
8089 #define I2C_SLVADR_AUTONACK_SHIFT (15U)
\r
8090 /*! AUTONACK - Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows
\r
8091 * software to ignore I2C traffic while handling previous I2C data or other operations.
\r
8092 * 0b0..Normal operation, matching I2C addresses are not ignored.
\r
8093 * 0b1..Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches
\r
8094 * SLVADRn, and AUTOMATCHREAD matches the direction.
\r
8096 #define I2C_SLVADR_AUTONACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK)
\r
8099 /* The count of I2C_SLVADR */
\r
8100 #define I2C_SLVADR_COUNT (4U)
\r
8102 /*! @name SLVQUAL0 - Slave Qualification for address 0. */
\r
8104 #define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U)
\r
8105 #define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U)
\r
8106 /*! QUALMODE0 - Qualify mode for slave address 0.
\r
8107 * 0b0..Mask. The SLVQUAL0 field is used as a logical mask for matching address 0.
\r
8108 * 0b1..Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses.
\r
8110 #define I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK)
\r
8111 #define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU)
\r
8112 #define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U)
\r
8113 /*! SLVQUAL0 - Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to
\r
8114 * be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is
\r
8115 * set to 1 will cause an automatic match of the corresponding bit of the received address when it
\r
8116 * is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for
\r
8117 * address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0
\r
8118 * (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]).
\r
8120 #define I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK)
\r
8123 /*! @name MONRXDAT - Monitor receiver data register. */
\r
8125 #define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU)
\r
8126 #define I2C_MONRXDAT_MONRXDAT_SHIFT (0U)
\r
8127 /*! MONRXDAT - Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins.
\r
8129 #define I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK)
\r
8130 #define I2C_MONRXDAT_MONSTART_MASK (0x100U)
\r
8131 #define I2C_MONRXDAT_MONSTART_SHIFT (8U)
\r
8132 /*! MONSTART - Monitor Received Start.
\r
8133 * 0b0..No start detected. The Monitor function has not detected a Start event on the I2C bus.
\r
8134 * 0b1..Start detected. The Monitor function has detected a Start event on the I2C bus.
\r
8136 #define I2C_MONRXDAT_MONSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK)
\r
8137 #define I2C_MONRXDAT_MONRESTART_MASK (0x200U)
\r
8138 #define I2C_MONRXDAT_MONRESTART_SHIFT (9U)
\r
8139 /*! MONRESTART - Monitor Received Repeated Start.
\r
8140 * 0b0..No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus.
\r
8141 * 0b1..Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus.
\r
8143 #define I2C_MONRXDAT_MONRESTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK)
\r
8144 #define I2C_MONRXDAT_MONNACK_MASK (0x400U)
\r
8145 #define I2C_MONRXDAT_MONNACK_SHIFT (10U)
\r
8146 /*! MONNACK - Monitor Received NACK.
\r
8147 * 0b0..Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver.
\r
8148 * 0b1..Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver.
\r
8150 #define I2C_MONRXDAT_MONNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK)
\r
8153 /*! @name ID - Peripheral identification register. */
\r
8155 #define I2C_ID_APERTURE_MASK (0xFFU)
\r
8156 #define I2C_ID_APERTURE_SHIFT (0U)
\r
8157 /*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture.
\r
8159 #define I2C_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_APERTURE_SHIFT)) & I2C_ID_APERTURE_MASK)
\r
8160 #define I2C_ID_MINOR_REV_MASK (0xF00U)
\r
8161 #define I2C_ID_MINOR_REV_SHIFT (8U)
\r
8162 /*! MINOR_REV - Minor revision of module implementation.
\r
8164 #define I2C_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MINOR_REV_SHIFT)) & I2C_ID_MINOR_REV_MASK)
\r
8165 #define I2C_ID_MAJOR_REV_MASK (0xF000U)
\r
8166 #define I2C_ID_MAJOR_REV_SHIFT (12U)
\r
8167 /*! MAJOR_REV - Major revision of module implementation.
\r
8169 #define I2C_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MAJOR_REV_SHIFT)) & I2C_ID_MAJOR_REV_MASK)
\r
8170 #define I2C_ID_ID_MASK (0xFFFF0000U)
\r
8171 #define I2C_ID_ID_SHIFT (16U)
\r
8172 /*! ID - Module identifier for the selected function.
\r
8174 #define I2C_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_ID_SHIFT)) & I2C_ID_ID_MASK)
\r
8180 */ /* end of group I2C_Register_Masks */
\r
8183 /* I2C - Peripheral instance base addresses */
\r
8184 /** Peripheral I2C0 base address */
\r
8185 #define I2C0_BASE (0x40086000u)
\r
8186 /** Peripheral I2C0 base pointer */
\r
8187 #define I2C0 ((I2C_Type *)I2C0_BASE)
\r
8188 /** Peripheral I2C1 base address */
\r
8189 #define I2C1_BASE (0x40087000u)
\r
8190 /** Peripheral I2C1 base pointer */
\r
8191 #define I2C1 ((I2C_Type *)I2C1_BASE)
\r
8192 /** Peripheral I2C2 base address */
\r
8193 #define I2C2_BASE (0x40088000u)
\r
8194 /** Peripheral I2C2 base pointer */
\r
8195 #define I2C2 ((I2C_Type *)I2C2_BASE)
\r
8196 /** Peripheral I2C3 base address */
\r
8197 #define I2C3_BASE (0x40089000u)
\r
8198 /** Peripheral I2C3 base pointer */
\r
8199 #define I2C3 ((I2C_Type *)I2C3_BASE)
\r
8200 /** Peripheral I2C4 base address */
\r
8201 #define I2C4_BASE (0x4008A000u)
\r
8202 /** Peripheral I2C4 base pointer */
\r
8203 #define I2C4 ((I2C_Type *)I2C4_BASE)
\r
8204 /** Peripheral I2C5 base address */
\r
8205 #define I2C5_BASE (0x40096000u)
\r
8206 /** Peripheral I2C5 base pointer */
\r
8207 #define I2C5 ((I2C_Type *)I2C5_BASE)
\r
8208 /** Peripheral I2C6 base address */
\r
8209 #define I2C6_BASE (0x40097000u)
\r
8210 /** Peripheral I2C6 base pointer */
\r
8211 #define I2C6 ((I2C_Type *)I2C6_BASE)
\r
8212 /** Peripheral I2C7 base address */
\r
8213 #define I2C7_BASE (0x40098000u)
\r
8214 /** Peripheral I2C7 base pointer */
\r
8215 #define I2C7 ((I2C_Type *)I2C7_BASE)
\r
8216 /** Peripheral I2C8 base address */
\r
8217 #define I2C8_BASE (0x40099000u)
\r
8218 /** Peripheral I2C8 base pointer */
\r
8219 #define I2C8 ((I2C_Type *)I2C8_BASE)
\r
8220 /** Peripheral I2C9 base address */
\r
8221 #define I2C9_BASE (0x4009A000u)
\r
8222 /** Peripheral I2C9 base pointer */
\r
8223 #define I2C9 ((I2C_Type *)I2C9_BASE)
\r
8224 /** Array initializer of I2C peripheral base addresses */
\r
8225 #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE, I2C8_BASE, I2C9_BASE }
\r
8226 /** Array initializer of I2C peripheral base pointers */
\r
8227 #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7, I2C8, I2C9 }
\r
8228 /** Interrupt vectors for the I2C peripheral type */
\r
8229 #define I2C_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn }
\r
8233 */ /* end of group I2C_Peripheral_Access_Layer */
\r
8236 /* ----------------------------------------------------------------------------
\r
8237 -- I2S Peripheral Access Layer
\r
8238 ---------------------------------------------------------------------------- */
\r
8241 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
\r
8245 /** I2S - Register Layout Typedef */
\r
8247 uint8_t RESERVED_0[3072];
\r
8248 __IO uint32_t CFG1; /**< Configuration register 1 for the primary channel pair., offset: 0xC00 */
\r
8249 __IO uint32_t CFG2; /**< Configuration register 2 for the primary channel pair., offset: 0xC04 */
\r
8250 __IO uint32_t STAT; /**< Status register for the primary channel pair., offset: 0xC08 */
\r
8251 uint8_t RESERVED_1[16];
\r
8252 __IO uint32_t DIV; /**< Clock divider, used by all channel pairs., offset: 0xC1C */
\r
8253 struct { /* offset: 0xC20, array step: 0x20 */
\r
8254 __IO uint32_t PCFG1; /**< Configuration register 1 for channel pair, array offset: 0xC20, array step: 0x20 */
\r
8255 __IO uint32_t PCFG2; /**< Configuration register 2 for channel pair, array offset: 0xC24, array step: 0x20 */
\r
8256 __IO uint32_t PSTAT; /**< Status register for channel pair, array offset: 0xC28, array step: 0x20 */
\r
8257 uint8_t RESERVED_0[20];
\r
8259 uint8_t RESERVED_2[384];
\r
8260 __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */
\r
8261 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */
\r
8262 __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */
\r
8263 uint8_t RESERVED_3[4];
\r
8264 __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */
\r
8265 __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */
\r
8266 __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */
\r
8267 uint8_t RESERVED_4[4];
\r
8268 __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */
\r
8269 __O uint32_t FIFOWR48H; /**< FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE24 */
\r
8270 uint8_t RESERVED_5[8];
\r
8271 __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */
\r
8272 __I uint32_t FIFORD48H; /**< FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE34 */
\r
8273 uint8_t RESERVED_6[8];
\r
8274 __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */
\r
8275 __I uint32_t FIFORD48HNOPOP; /**< FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE44 */
\r
8276 uint8_t RESERVED_7[4020];
\r
8277 __I uint32_t ID; /**< I2S Module identification, offset: 0x1DFC */
\r
8280 /* ----------------------------------------------------------------------------
\r
8281 -- I2S Register Masks
\r
8282 ---------------------------------------------------------------------------- */
\r
8285 * @addtogroup I2S_Register_Masks I2S Register Masks
\r
8289 /*! @name CFG1 - Configuration register 1 for the primary channel pair. */
\r
8291 #define I2S_CFG1_MAINENABLE_MASK (0x1U)
\r
8292 #define I2S_CFG1_MAINENABLE_SHIFT (0U)
\r
8293 /*! MAINENABLE - Main enable for I 2S function in this Flexcomm
\r
8294 * 0b0..All I 2S channel pairs in this Flexcomm are disabled and the internal state machines, counters, and flags
\r
8295 * are reset. No other channel pairs can be enabled.
\r
8296 * 0b1..This I 2S channel pair is enabled. Other channel pairs in this Flexcomm may be enabled in their individual PAIRENABLE bits.
\r
8298 #define I2S_CFG1_MAINENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK)
\r
8299 #define I2S_CFG1_DATAPAUSE_MASK (0x2U)
\r
8300 #define I2S_CFG1_DATAPAUSE_SHIFT (1U)
\r
8301 /*! DATAPAUSE - Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer
\r
8302 * and the FIFO. This could be done in order to change streams, or while restarting after a data
\r
8303 * underflow or overflow. When paused, FIFO operations can be done without corrupting data that is
\r
8304 * in the process of being sent or received. Once a data pause has been requested, the interface
\r
8305 * may need to complete sending data that was in progress before interrupting the flow of data.
\r
8306 * Software must check that the pause is actually in effect before taking action. This is done by
\r
8307 * monitoring the DATAPAUSED flag in the STAT register. When DATAPAUSE is cleared, data transfer
\r
8308 * will resume at the beginning of the next frame.
\r
8309 * 0b0..Normal operation, or resuming normal operation at the next frame if the I2S has already been paused.
\r
8310 * 0b1..A pause in the data flow is being requested. It is in effect when DATAPAUSED in STAT = 1.
\r
8312 #define I2S_CFG1_DATAPAUSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK)
\r
8313 #define I2S_CFG1_PAIRCOUNT_MASK (0xCU)
\r
8314 #define I2S_CFG1_PAIRCOUNT_SHIFT (2U)
\r
8315 /*! PAIRCOUNT - Provides the number of I2S channel pairs in this Flexcomm This is a read-only field
\r
8316 * whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this
\r
8317 * Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 = there are 3 I2S channel pairs
\r
8318 * in this Flexcomm. 11 = there are 4 I2S channel pairs in this Flexcomm.
\r
8319 * 0b00..1 I2S channel pairs in this flexcomm
\r
8320 * 0b01..2 I2S channel pairs in this flexcomm
\r
8321 * 0b10..3 I2S channel pairs in this flexcomm
\r
8322 * 0b11..4 I2S channel pairs in this flexcomm
\r
8324 #define I2S_CFG1_PAIRCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK)
\r
8325 #define I2S_CFG1_MSTSLVCFG_MASK (0x30U)
\r
8326 #define I2S_CFG1_MSTSLVCFG_SHIFT (4U)
\r
8327 /*! MSTSLVCFG - Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm.
\r
8328 * 0b00..Normal slave mode, the default mode. SCK and WS are received from a master and used to transmit or receive data.
\r
8329 * 0b01..WS synchronized master. WS is received from another master and used to synchronize the generation of
\r
8330 * SCK, when divided from the Flexcomm function clock.
\r
8331 * 0b10..Master using an existing SCK. SCK is received and used directly to generate WS, as well as transmitting or receiving data.
\r
8332 * 0b11..Normal master mode. SCK and WS are generated so they can be sent to one or more slave devices.
\r
8334 #define I2S_CFG1_MSTSLVCFG(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK)
\r
8335 #define I2S_CFG1_MODE_MASK (0xC0U)
\r
8336 #define I2S_CFG1_MODE_SHIFT (6U)
\r
8337 /*! MODE - Selects the basic I2S operating mode. Other configurations modify this to obtain all
\r
8338 * supported cases. See Formats and modes for examples.
\r
8339 * 0b00..I2S mode a.k.a. 'classic' mode. WS has a 50% duty cycle, with (for each enabled channel pair) one piece
\r
8340 * of left channel data occurring during the first phase, and one pieces of right channel data occurring
\r
8341 * during the second phase. In this mode, the data region begins one clock after the leading WS edge for the
\r
8342 * frame. For a 50% WS duty cycle, FRAMELEN must define an even number of I2S clocks for the frame. If
\r
8343 * FRAMELEN defines an odd number of clocks per frame, the extra clock will occur on the right.
\r
8344 * 0b01..DSP mode where WS has a 50% duty cycle. See remark for mode 0.
\r
8345 * 0b10..DSP mode where WS has a one clock long pulse at the beginning of each data frame.
\r
8346 * 0b11..DSP mode where WS has a one data slot long pulse at the beginning of each data frame.
\r
8348 #define I2S_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK)
\r
8349 #define I2S_CFG1_RIGHTLOW_MASK (0x100U)
\r
8350 #define I2S_CFG1_RIGHTLOW_SHIFT (8U)
\r
8351 /*! RIGHTLOW - Right channel data is in the Low portion of FIFO data. Essentially, this swaps left
\r
8352 * and right channel data as it is transferred to or from the FIFO. This bit is not used if the
\r
8353 * data width is greater than 24 bits or if PDMDATA = 1. Note that if the ONECHANNEL field (bit 10
\r
8354 * of this register) = 1, the one channel to be used is the nominally the left channel. POSITION
\r
8355 * can still place that data in the frame where right channel data is normally located. if all
\r
8356 * enabled channel pairs have ONECHANNEL = 1, then RIGHTLOW = 1 is not allowed.
\r
8357 * 0b0..The right channel is taken from the high part of the FIFO data. For example, when data is 16 bits, FIFO
\r
8358 * bits 31:16 are used for the right channel.
\r
8359 * 0b1..The right channel is taken from the low part of the FIFO data. For example, when data is 16 bits, FIFO
\r
8360 * bits 15:0 are used for the right channel.
\r
8362 #define I2S_CFG1_RIGHTLOW(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK)
\r
8363 #define I2S_CFG1_LEFTJUST_MASK (0x200U)
\r
8364 #define I2S_CFG1_LEFTJUST_SHIFT (9U)
\r
8365 /*! LEFTJUST - Left Justify data.
\r
8366 * 0b0..Data is transferred between the FIFO and the I2S serializer/deserializer right justified, i.e. starting
\r
8367 * from bit 0 and continuing to the position defined by DATALEN. This would correspond to right justified data
\r
8368 * in the stream on the data bus.
\r
8369 * 0b1..Data is transferred between the FIFO and the I2S serializer/deserializer left justified, i.e. starting
\r
8370 * from the MSB of the FIFO entry and continuing for the number of bits defined by DATALEN. This would
\r
8371 * correspond to left justified data in the stream on the data bus.
\r
8373 #define I2S_CFG1_LEFTJUST(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK)
\r
8374 #define I2S_CFG1_ONECHANNEL_MASK (0x400U)
\r
8375 #define I2S_CFG1_ONECHANNEL_SHIFT (10U)
\r
8376 /*! ONECHANNEL - Single channel mode. Applies to both transmit and receive. This configuration bit
\r
8377 * applies only to the first I2S channel pair. Other channel pairs may select this mode
\r
8378 * independently in their separate CFG1 registers.
\r
8379 * 0b0..I2S data for this channel pair is treated as left and right channels.
\r
8380 * 0b1..I2S data for this channel pair is treated as a single channel, functionally the left channel for this
\r
8381 * pair. In mode 0 only, the right side of the frame begins at POSITION = 0x100. This is because mode 0 makes a
\r
8382 * clear distinction between the left and right sides of the frame. When ONECHANNEL = 1, the single channel
\r
8383 * of data may be placed on the right by setting POSITION to 0x100 + the data position within the right side
\r
8384 * (e.g. 0x108 would place data starting at the 8th clock after the middle of the frame). In other modes, data
\r
8385 * for the single channel of data is placed at the clock defined by POSITION.
\r
8387 #define I2S_CFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK)
\r
8388 #define I2S_CFG1_PDMDATA_MASK (0x800U)
\r
8389 #define I2S_CFG1_PDMDATA_SHIFT (11U)
\r
8390 /*! PDMDATA - PDM Data selection. This bit controls the data source for I2S transmit, and cannot be
\r
8391 * set in Rx mode. This bit only has an effect if the device the Flexcomm resides in includes a
\r
8392 * D-Mic subsystem. For the LPC5411x, this bit applies only to Flexcomm 7.
\r
8393 * 0b0..Normal operation, data is transferred to or from the Flexcomm FIFO.
\r
8394 * 0b1..The data source is the D-Mic subsystem. When PDMDATA = 1, only the primary channel pair can be used in
\r
8395 * this Flexcomm. If ONECHANNEL = 1, only the PDM left data is used. the WS rate must match the Fs (sample
\r
8396 * rate) of the D-Mic decimator. A rate mismatch will at some point cause the I2S to overrun or underrun.
\r
8398 #define I2S_CFG1_PDMDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PDMDATA_SHIFT)) & I2S_CFG1_PDMDATA_MASK)
\r
8399 #define I2S_CFG1_SCK_POL_MASK (0x1000U)
\r
8400 #define I2S_CFG1_SCK_POL_SHIFT (12U)
\r
8401 /*! SCK_POL - SCK polarity.
\r
8402 * 0b0..Data is launched on SCK falling edges and sampled on SCK rising edges (standard for I2S).
\r
8403 * 0b1..Data is launched on SCK rising edges and sampled on SCK falling edges.
\r
8405 #define I2S_CFG1_SCK_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK)
\r
8406 #define I2S_CFG1_WS_POL_MASK (0x2000U)
\r
8407 #define I2S_CFG1_WS_POL_SHIFT (13U)
\r
8408 /*! WS_POL - WS polarity.
\r
8409 * 0b0..Data frames begin at a falling edge of WS (standard for classic I2S).
\r
8410 * 0b1..WS is inverted, resulting in a data frame beginning at a rising edge of WS (standard for most 'non-classic' variations of I2S).
\r
8412 #define I2S_CFG1_WS_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK)
\r
8413 #define I2S_CFG1_DATALEN_MASK (0x1F0000U)
\r
8414 #define I2S_CFG1_DATALEN_SHIFT (16U)
\r
8415 /*! DATALEN - Data Length, minus 1 encoded, defines the number of data bits to be transmitted or
\r
8416 * received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received
\r
8417 * from SDA for the number of bits defined by DATALEN. DATALEN is also used in these ways by the
\r
8418 * I2S: Determines the size of data transfers between the FIFO and the I2S
\r
8419 * serializer/deserializer. See FIFO buffer configurations and usage In mode 1, 2, and 3, determines the location of
\r
8420 * right data following left data in the frame. In mode 3 (where WS has a one data slot long pulse
\r
8421 * at the beginning of each data frame) determines the duration of the WS pulse. Values: 0x00 to
\r
8422 * 0x02 = not supported 0x03 = data is 4 bits in length 0x04 = data is 5 bits in length 0x1F =
\r
8423 * data is 32 bits in length
\r
8425 #define I2S_CFG1_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK)
\r
8428 /*! @name CFG2 - Configuration register 2 for the primary channel pair. */
\r
8430 #define I2S_CFG2_FRAMELEN_MASK (0x1FFU)
\r
8431 #define I2S_CFG2_FRAMELEN_SHIFT (0U)
\r
8432 /*! FRAMELEN - Frame Length, minus 1 encoded, defines the number of clocks and data bits in the
\r
8433 * frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported
\r
8434 * 0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in total length 0x1FF = frame is
\r
8435 * 512 bits in total length if FRAMELEN is an defines an odd length frame (e.g. 33 clocks) in
\r
8436 * mode 0 or 1, the extra clock appears in the right half. When MODE = 3, FRAMELEN must be larger
\r
8437 * than DATALEN in order for the WS pulse to be generated correctly.
\r
8439 #define I2S_CFG2_FRAMELEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK)
\r
8440 #define I2S_CFG2_POSITION_MASK (0x1FF0000U)
\r
8441 #define I2S_CFG2_POSITION_SHIFT (16U)
\r
8442 /*! POSITION - Data Position. Defines the location within the frame of the data for this channel
\r
8443 * pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0, POSITION
\r
8444 * defines the location of data in both the left phase and right phase, starting one clock after
\r
8445 * the WS edge. In other modes, POSITION defines the location of data within the entire frame.
\r
8446 * ONECHANNEL = 1 while MODE = 0 is a special case, see the description of ONECHANNEL. The
\r
8447 * combination of DATALEN and the POSITION fields of all channel pairs must be made such that the channels
\r
8448 * do not overlap within the frame. 0x000 = data begins at bit position 0 (the first bit
\r
8449 * position) within the frame or WS phase. 0x001 = data begins at bit position 1 within the frame or WS
\r
8450 * phase. 0x002 = data begins at bit position 2 within the frame or WS phase.
\r
8452 #define I2S_CFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK)
\r
8455 /*! @name STAT - Status register for the primary channel pair. */
\r
8457 #define I2S_STAT_BUSY_MASK (0x1U)
\r
8458 #define I2S_STAT_BUSY_SHIFT (0U)
\r
8459 /*! BUSY - Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair.
\r
8460 * 0b0..The transmitter/receiver for channel pair is currently idle.
\r
8461 * 0b1..The transmitter/receiver for channel pair is currently processing data.
\r
8463 #define I2S_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK)
\r
8464 #define I2S_STAT_SLVFRMERR_MASK (0x2U)
\r
8465 #define I2S_STAT_SLVFRMERR_SHIFT (1U)
\r
8466 /*! SLVFRMERR - Slave Frame Error flag. This applies when at least one channel pair is operating as
\r
8467 * a slave. An error indicates that the incoming WS signal did not transition as expected due to
\r
8468 * a mismatch between FRAMELEN and the actual incoming I2S stream.
\r
8469 * 0b0..No error has been recorded.
\r
8470 * 0b1..An error has been recorded for some channel pair that is operating in slave mode. ERROR is cleared by writing a 1 to this bit position.
\r
8472 #define I2S_STAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK)
\r
8473 #define I2S_STAT_LR_MASK (0x4U)
\r
8474 #define I2S_STAT_LR_SHIFT (2U)
\r
8475 /*! LR - Left/Right indication. This flag is considered to be a debugging aid and is not expected to
\r
8476 * be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data
\r
8477 * being processed for the currently busy channel pair.
\r
8478 * 0b0..Left channel.
\r
8479 * 0b1..Right channel.
\r
8481 #define I2S_STAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK)
\r
8482 #define I2S_STAT_DATAPAUSED_MASK (0x8U)
\r
8483 #define I2S_STAT_DATAPAUSED_SHIFT (3U)
\r
8484 /*! DATAPAUSED - Data Paused status flag. Applies to all I2S channels
\r
8485 * 0b0..Data is not currently paused. A data pause may have been requested but is not yet in force, waiting for
\r
8486 * an allowed pause point. Refer to the description of the DATAPAUSE control bit in the CFG1 register.
\r
8487 * 0b1..A data pause has been requested and is now in force.
\r
8489 #define I2S_STAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK)
\r
8492 /*! @name DIV - Clock divider, used by all channel pairs. */
\r
8494 #define I2S_DIV_DIV_MASK (0xFFFU)
\r
8495 #define I2S_DIV_DIV_SHIFT (0U)
\r
8496 /*! DIV - This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The
\r
8497 * Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2.
\r
8498 * 0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The Flexcomm function clock is
\r
8499 * divided by 4,096.
\r
8501 #define I2S_DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK)
\r
8504 /*! @name SECCHANNEL_PCFG1 - Configuration register 1 for channel pair */
\r
8506 #define I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK (0x1U)
\r
8507 #define I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT (0U)
\r
8508 /*! PAIRENABLE - Enable for this channel pair..
\r
8510 #define I2S_SECCHANNEL_PCFG1_PAIRENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT)) & I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK)
\r
8511 #define I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK (0x400U)
\r
8512 #define I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT (10U)
\r
8513 /*! ONECHANNEL - Single channel mode.
\r
8515 #define I2S_SECCHANNEL_PCFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT)) & I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK)
\r
8518 /* The count of I2S_SECCHANNEL_PCFG1 */
\r
8519 #define I2S_SECCHANNEL_PCFG1_COUNT (3U)
\r
8521 /*! @name SECCHANNEL_PCFG2 - Configuration register 2 for channel pair */
\r
8523 #define I2S_SECCHANNEL_PCFG2_POSITION_MASK (0x1FF0000U)
\r
8524 #define I2S_SECCHANNEL_PCFG2_POSITION_SHIFT (16U)
\r
8525 /*! POSITION - Data Position.
\r
8527 #define I2S_SECCHANNEL_PCFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG2_POSITION_SHIFT)) & I2S_SECCHANNEL_PCFG2_POSITION_MASK)
\r
8530 /* The count of I2S_SECCHANNEL_PCFG2 */
\r
8531 #define I2S_SECCHANNEL_PCFG2_COUNT (3U)
\r
8533 /*! @name SECCHANNEL_PSTAT - Status register for channel pair */
\r
8535 #define I2S_SECCHANNEL_PSTAT_BUSY_MASK (0x1U)
\r
8536 #define I2S_SECCHANNEL_PSTAT_BUSY_SHIFT (0U)
\r
8537 /*! BUSY - Busy status for this channel pair.
\r
8539 #define I2S_SECCHANNEL_PSTAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_BUSY_SHIFT)) & I2S_SECCHANNEL_PSTAT_BUSY_MASK)
\r
8540 #define I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK (0x2U)
\r
8541 #define I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT (1U)
\r
8542 /*! SLVFRMERR - Save Frame Error flag.
\r
8544 #define I2S_SECCHANNEL_PSTAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT)) & I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK)
\r
8545 #define I2S_SECCHANNEL_PSTAT_LR_MASK (0x4U)
\r
8546 #define I2S_SECCHANNEL_PSTAT_LR_SHIFT (2U)
\r
8547 /*! LR - Left/Right indication.
\r
8549 #define I2S_SECCHANNEL_PSTAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_LR_SHIFT)) & I2S_SECCHANNEL_PSTAT_LR_MASK)
\r
8550 #define I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK (0x8U)
\r
8551 #define I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT (3U)
\r
8552 /*! DATAPAUSED - Data Paused status flag.
\r
8554 #define I2S_SECCHANNEL_PSTAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT)) & I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK)
\r
8557 /* The count of I2S_SECCHANNEL_PSTAT */
\r
8558 #define I2S_SECCHANNEL_PSTAT_COUNT (3U)
\r
8560 /*! @name FIFOCFG - FIFO configuration and enable register. */
\r
8562 #define I2S_FIFOCFG_ENABLETX_MASK (0x1U)
\r
8563 #define I2S_FIFOCFG_ENABLETX_SHIFT (0U)
\r
8564 /*! ENABLETX - Enable the transmit FIFO.
\r
8565 * 0b0..The transmit FIFO is not enabled.
\r
8566 * 0b1..The transmit FIFO is enabled.
\r
8568 #define I2S_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK)
\r
8569 #define I2S_FIFOCFG_ENABLERX_MASK (0x2U)
\r
8570 #define I2S_FIFOCFG_ENABLERX_SHIFT (1U)
\r
8571 /*! ENABLERX - Enable the receive FIFO.
\r
8572 * 0b0..The receive FIFO is not enabled.
\r
8573 * 0b1..The receive FIFO is enabled.
\r
8575 #define I2S_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK)
\r
8576 #define I2S_FIFOCFG_TXI2SE0_MASK (0x4U)
\r
8577 #define I2S_FIFOCFG_TXI2SE0_SHIFT (2U)
\r
8578 /*! TXI2SE0 - Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX
\r
8579 * FIFO becomes empty. This value is sent repeatedly until the I2S is paused, the error is
\r
8580 * cleared, new data is provided, and the I2S is un-paused.
\r
8581 * 0b0..If the TX FIFO becomes empty, the last value is sent. This setting may be used when the data length is 24
\r
8582 * bits or less, or when MONO = 1 for this channel pair.
\r
8583 * 0b1..If the TX FIFO becomes empty, 0 is sent. Use if the data length is greater than 24 bits or if zero fill is preferred.
\r
8585 #define I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK)
\r
8586 #define I2S_FIFOCFG_PACK48_MASK (0x8U)
\r
8587 #define I2S_FIFOCFG_PACK48_SHIFT (3U)
\r
8588 /*! PACK48 - Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA.
\r
8589 * 0b0..48-bit I2S FIFO entries are handled as all 24-bit values.
\r
8590 * 0b1..48-bit I2S FIFO entries are handled as alternating 32-bit and 16-bit values.
\r
8592 #define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK)
\r
8593 #define I2S_FIFOCFG_SIZE_MASK (0x30U)
\r
8594 #define I2S_FIFOCFG_SIZE_SHIFT (4U)
\r
8595 /*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16
\r
8596 * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART.
\r
8598 #define I2S_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK)
\r
8599 #define I2S_FIFOCFG_DMATX_MASK (0x1000U)
\r
8600 #define I2S_FIFOCFG_DMATX_SHIFT (12U)
\r
8601 /*! DMATX - DMA configuration for transmit.
\r
8602 * 0b0..DMA is not used for the transmit function.
\r
8603 * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled.
\r
8605 #define I2S_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK)
\r
8606 #define I2S_FIFOCFG_DMARX_MASK (0x2000U)
\r
8607 #define I2S_FIFOCFG_DMARX_SHIFT (13U)
\r
8608 /*! DMARX - DMA configuration for receive.
\r
8609 * 0b0..DMA is not used for the receive function.
\r
8610 * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled.
\r
8612 #define I2S_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK)
\r
8613 #define I2S_FIFOCFG_WAKETX_MASK (0x4000U)
\r
8614 #define I2S_FIFOCFG_WAKETX_SHIFT (14U)
\r
8615 /*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power
\r
8616 * modes (up to power-down, as long as the peripheral function works in that power mode) without
\r
8617 * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The
\r
8618 * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware
\r
8619 * Wake-up control register.
\r
8620 * 0b0..Only enabled interrupts will wake up the device form reduced power modes.
\r
8621 * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in
\r
8622 * FIFOTRIG, even when the TXLVL interrupt is not enabled.
\r
8624 #define I2S_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK)
\r
8625 #define I2S_FIFOCFG_WAKERX_MASK (0x8000U)
\r
8626 #define I2S_FIFOCFG_WAKERX_SHIFT (15U)
\r
8627 /*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power
\r
8628 * modes (up to power-down, as long as the peripheral function works in that power mode) without
\r
8629 * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The
\r
8630 * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware
\r
8631 * Wake-up control register.
\r
8632 * 0b0..Only enabled interrupts will wake up the device form reduced power modes.
\r
8633 * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in
\r
8634 * FIFOTRIG, even when the RXLVL interrupt is not enabled.
\r
8636 #define I2S_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK)
\r
8637 #define I2S_FIFOCFG_EMPTYTX_MASK (0x10000U)
\r
8638 #define I2S_FIFOCFG_EMPTYTX_SHIFT (16U)
\r
8639 /*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied.
\r
8641 #define I2S_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK)
\r
8642 #define I2S_FIFOCFG_EMPTYRX_MASK (0x20000U)
\r
8643 #define I2S_FIFOCFG_EMPTYRX_SHIFT (17U)
\r
8644 /*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied.
\r
8646 #define I2S_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK)
\r
8649 /*! @name FIFOSTAT - FIFO status register. */
\r
8651 #define I2S_FIFOSTAT_TXERR_MASK (0x1U)
\r
8652 #define I2S_FIFOSTAT_TXERR_SHIFT (0U)
\r
8653 /*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow
\r
8654 * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is
\r
8655 * needed. Cleared by writing a 1 to this bit.
\r
8657 #define I2S_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK)
\r
8658 #define I2S_FIFOSTAT_RXERR_MASK (0x2U)
\r
8659 #define I2S_FIFOSTAT_RXERR_SHIFT (1U)
\r
8660 /*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA
\r
8661 * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit.
\r
8663 #define I2S_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK)
\r
8664 #define I2S_FIFOSTAT_PERINT_MASK (0x8U)
\r
8665 #define I2S_FIFOSTAT_PERINT_SHIFT (3U)
\r
8666 /*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted
\r
8667 * an interrupt. The details can be found by reading the peripheral's STAT register.
\r
8669 #define I2S_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK)
\r
8670 #define I2S_FIFOSTAT_TXEMPTY_MASK (0x10U)
\r
8671 #define I2S_FIFOSTAT_TXEMPTY_SHIFT (4U)
\r
8672 /*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data.
\r
8674 #define I2S_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK)
\r
8675 #define I2S_FIFOSTAT_TXNOTFULL_MASK (0x20U)
\r
8676 #define I2S_FIFOSTAT_TXNOTFULL_SHIFT (5U)
\r
8677 /*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be
\r
8678 * written. When 0, the transmit FIFO is full and another write would cause it to overflow.
\r
8680 #define I2S_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK)
\r
8681 #define I2S_FIFOSTAT_RXNOTEMPTY_MASK (0x40U)
\r
8682 #define I2S_FIFOSTAT_RXNOTEMPTY_SHIFT (6U)
\r
8683 /*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty.
\r
8685 #define I2S_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK)
\r
8686 #define I2S_FIFOSTAT_RXFULL_MASK (0x80U)
\r
8687 #define I2S_FIFOSTAT_RXFULL_SHIFT (7U)
\r
8688 /*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to
\r
8689 * prevent the peripheral from causing an overflow.
\r
8691 #define I2S_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK)
\r
8692 #define I2S_FIFOSTAT_TXLVL_MASK (0x1F00U)
\r
8693 #define I2S_FIFOSTAT_TXLVL_SHIFT (8U)
\r
8694 /*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY
\r
8695 * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at
\r
8696 * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be
\r
8699 #define I2S_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK)
\r
8700 #define I2S_FIFOSTAT_RXLVL_MASK (0x1F0000U)
\r
8701 #define I2S_FIFOSTAT_RXLVL_SHIFT (16U)
\r
8702 /*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and
\r
8703 * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the
\r
8704 * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be
\r
8707 #define I2S_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK)
\r
8710 /*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */
\r
8712 #define I2S_FIFOTRIG_TXLVLENA_MASK (0x1U)
\r
8713 #define I2S_FIFOTRIG_TXLVLENA_SHIFT (0U)
\r
8714 /*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled
\r
8715 * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set.
\r
8716 * 0b0..Transmit FIFO level does not generate a FIFO level trigger.
\r
8717 * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register.
\r
8719 #define I2S_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK)
\r
8720 #define I2S_FIFOTRIG_RXLVLENA_MASK (0x2U)
\r
8721 #define I2S_FIFOTRIG_RXLVLENA_SHIFT (1U)
\r
8722 /*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled
\r
8723 * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set.
\r
8724 * 0b0..Receive FIFO level does not generate a FIFO level trigger.
\r
8725 * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register.
\r
8727 #define I2S_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK)
\r
8728 #define I2S_FIFOTRIG_TXLVL_MASK (0xF00U)
\r
8729 #define I2S_FIFOTRIG_TXLVL_SHIFT (8U)
\r
8730 /*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled
\r
8731 * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to
\r
8732 * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO
\r
8733 * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX
\r
8734 * FIFO level decreases to 15 entries (is no longer full).
\r
8736 #define I2S_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK)
\r
8737 #define I2S_FIFOTRIG_RXLVL_MASK (0xF0000U)
\r
8738 #define I2S_FIFOTRIG_RXLVL_SHIFT (16U)
\r
8739 /*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data
\r
8740 * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level
\r
8741 * can wake up the device just enough to perform DMA, then return to the reduced power mode. See
\r
8742 * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no
\r
8743 * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX
\r
8744 * FIFO has received 16 entries (has become full).
\r
8746 #define I2S_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK)
\r
8749 /*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */
\r
8751 #define I2S_FIFOINTENSET_TXERR_MASK (0x1U)
\r
8752 #define I2S_FIFOINTENSET_TXERR_SHIFT (0U)
\r
8753 /*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register.
\r
8754 * 0b0..No interrupt will be generated for a transmit error.
\r
8755 * 0b1..An interrupt will be generated when a transmit error occurs.
\r
8757 #define I2S_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK)
\r
8758 #define I2S_FIFOINTENSET_RXERR_MASK (0x2U)
\r
8759 #define I2S_FIFOINTENSET_RXERR_SHIFT (1U)
\r
8760 /*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register.
\r
8761 * 0b0..No interrupt will be generated for a receive error.
\r
8762 * 0b1..An interrupt will be generated when a receive error occurs.
\r
8764 #define I2S_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK)
\r
8765 #define I2S_FIFOINTENSET_TXLVL_MASK (0x4U)
\r
8766 #define I2S_FIFOINTENSET_TXLVL_SHIFT (2U)
\r
8767 /*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level
\r
8768 * specified by the TXLVL field in the FIFOTRIG register.
\r
8769 * 0b0..No interrupt will be generated based on the TX FIFO level.
\r
8770 * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases
\r
8771 * to the level specified by TXLVL in the FIFOTRIG register.
\r
8773 #define I2S_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK)
\r
8774 #define I2S_FIFOINTENSET_RXLVL_MASK (0x8U)
\r
8775 #define I2S_FIFOINTENSET_RXLVL_SHIFT (3U)
\r
8776 /*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level
\r
8777 * specified by the TXLVL field in the FIFOTRIG register.
\r
8778 * 0b0..No interrupt will be generated based on the RX FIFO level.
\r
8779 * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level
\r
8780 * increases to the level specified by RXLVL in the FIFOTRIG register.
\r
8782 #define I2S_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK)
\r
8785 /*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */
\r
8787 #define I2S_FIFOINTENCLR_TXERR_MASK (0x1U)
\r
8788 #define I2S_FIFOINTENCLR_TXERR_SHIFT (0U)
\r
8789 /*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register.
\r
8791 #define I2S_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK)
\r
8792 #define I2S_FIFOINTENCLR_RXERR_MASK (0x2U)
\r
8793 #define I2S_FIFOINTENCLR_RXERR_SHIFT (1U)
\r
8794 /*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register.
\r
8796 #define I2S_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK)
\r
8797 #define I2S_FIFOINTENCLR_TXLVL_MASK (0x4U)
\r
8798 #define I2S_FIFOINTENCLR_TXLVL_SHIFT (2U)
\r
8799 /*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register.
\r
8801 #define I2S_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK)
\r
8802 #define I2S_FIFOINTENCLR_RXLVL_MASK (0x8U)
\r
8803 #define I2S_FIFOINTENCLR_RXLVL_SHIFT (3U)
\r
8804 /*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register.
\r
8806 #define I2S_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK)
\r
8809 /*! @name FIFOINTSTAT - FIFO interrupt status register. */
\r
8811 #define I2S_FIFOINTSTAT_TXERR_MASK (0x1U)
\r
8812 #define I2S_FIFOINTSTAT_TXERR_SHIFT (0U)
\r
8813 /*! TXERR - TX FIFO error.
\r
8815 #define I2S_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK)
\r
8816 #define I2S_FIFOINTSTAT_RXERR_MASK (0x2U)
\r
8817 #define I2S_FIFOINTSTAT_RXERR_SHIFT (1U)
\r
8818 /*! RXERR - RX FIFO error.
\r
8820 #define I2S_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK)
\r
8821 #define I2S_FIFOINTSTAT_TXLVL_MASK (0x4U)
\r
8822 #define I2S_FIFOINTSTAT_TXLVL_SHIFT (2U)
\r
8823 /*! TXLVL - Transmit FIFO level interrupt.
\r
8825 #define I2S_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK)
\r
8826 #define I2S_FIFOINTSTAT_RXLVL_MASK (0x8U)
\r
8827 #define I2S_FIFOINTSTAT_RXLVL_SHIFT (3U)
\r
8828 /*! RXLVL - Receive FIFO level interrupt.
\r
8830 #define I2S_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK)
\r
8831 #define I2S_FIFOINTSTAT_PERINT_MASK (0x10U)
\r
8832 #define I2S_FIFOINTSTAT_PERINT_SHIFT (4U)
\r
8833 /*! PERINT - Peripheral interrupt.
\r
8835 #define I2S_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK)
\r
8838 /*! @name FIFOWR - FIFO write data. */
\r
8840 #define I2S_FIFOWR_TXDATA_MASK (0xFFFFFFFFU)
\r
8841 #define I2S_FIFOWR_TXDATA_SHIFT (0U)
\r
8842 /*! TXDATA - Transmit data to the FIFO. The number of bits used depends on configuration details.
\r
8844 #define I2S_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK)
\r
8847 /*! @name FIFOWR48H - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */
\r
8849 #define I2S_FIFOWR48H_TXDATA_MASK (0xFFFFFFU)
\r
8850 #define I2S_FIFOWR48H_TXDATA_SHIFT (0U)
\r
8851 /*! TXDATA - Transmit data to the FIFO. Whether this register is used and the number of bits used depends on configuration details.
\r
8853 #define I2S_FIFOWR48H_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK)
\r
8856 /*! @name FIFORD - FIFO read data. */
\r
8858 #define I2S_FIFORD_RXDATA_MASK (0xFFFFFFFFU)
\r
8859 #define I2S_FIFORD_RXDATA_SHIFT (0U)
\r
8860 /*! RXDATA - Received data from the FIFO. The number of bits used depends on configuration details.
\r
8862 #define I2S_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK)
\r
8865 /*! @name FIFORD48H - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */
\r
8867 #define I2S_FIFORD48H_RXDATA_MASK (0xFFFFFFU)
\r
8868 #define I2S_FIFORD48H_RXDATA_SHIFT (0U)
\r
8869 /*! RXDATA - Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details.
\r
8871 #define I2S_FIFORD48H_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK)
\r
8874 /*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */
\r
8876 #define I2S_FIFORDNOPOP_RXDATA_MASK (0xFFFFFFFFU)
\r
8877 #define I2S_FIFORDNOPOP_RXDATA_SHIFT (0U)
\r
8878 /*! RXDATA - Received data from the FIFO.
\r
8880 #define I2S_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK)
\r
8883 /*! @name FIFORD48HNOPOP - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */
\r
8885 #define I2S_FIFORD48HNOPOP_RXDATA_MASK (0xFFFFFFU)
\r
8886 #define I2S_FIFORD48HNOPOP_RXDATA_SHIFT (0U)
\r
8887 /*! RXDATA - Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details.
\r
8889 #define I2S_FIFORD48HNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK)
\r
8892 /*! @name ID - I2S Module identification */
\r
8894 #define I2S_ID_Aperture_MASK (0xFFU)
\r
8895 #define I2S_ID_Aperture_SHIFT (0U)
\r
8896 /*! Aperture - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture.
\r
8898 #define I2S_ID_Aperture(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Aperture_SHIFT)) & I2S_ID_Aperture_MASK)
\r
8899 #define I2S_ID_Minor_Rev_MASK (0xF00U)
\r
8900 #define I2S_ID_Minor_Rev_SHIFT (8U)
\r
8901 /*! Minor_Rev - Minor revision of module implementation, starting at 0.
\r
8903 #define I2S_ID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Minor_Rev_SHIFT)) & I2S_ID_Minor_Rev_MASK)
\r
8904 #define I2S_ID_Major_Rev_MASK (0xF000U)
\r
8905 #define I2S_ID_Major_Rev_SHIFT (12U)
\r
8906 /*! Major_Rev - Major revision of module implementation, starting at 0.
\r
8908 #define I2S_ID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Major_Rev_SHIFT)) & I2S_ID_Major_Rev_MASK)
\r
8909 #define I2S_ID_ID_MASK (0xFFFF0000U)
\r
8910 #define I2S_ID_ID_SHIFT (16U)
\r
8911 /*! ID - Unique module identifier for this IP block.
\r
8913 #define I2S_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_ID_SHIFT)) & I2S_ID_ID_MASK)
\r
8919 */ /* end of group I2S_Register_Masks */
\r
8922 /* I2S - Peripheral instance base addresses */
\r
8923 /** Peripheral I2S0 base address */
\r
8924 #define I2S0_BASE (0x40097000u)
\r
8925 /** Peripheral I2S0 base pointer */
\r
8926 #define I2S0 ((I2S_Type *)I2S0_BASE)
\r
8927 /** Peripheral I2S1 base address */
\r
8928 #define I2S1_BASE (0x40098000u)
\r
8929 /** Peripheral I2S1 base pointer */
\r
8930 #define I2S1 ((I2S_Type *)I2S1_BASE)
\r
8931 /** Array initializer of I2S peripheral base addresses */
\r
8932 #define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE }
\r
8933 /** Array initializer of I2S peripheral base pointers */
\r
8934 #define I2S_BASE_PTRS { I2S0, I2S1 }
\r
8935 /** Interrupt vectors for the I2S peripheral type */
\r
8936 #define I2S_IRQS { FLEXCOMM6_IRQn, FLEXCOMM7_IRQn }
\r
8940 */ /* end of group I2S_Peripheral_Access_Layer */
\r
8943 /* ----------------------------------------------------------------------------
\r
8944 -- INPUTMUX Peripheral Access Layer
\r
8945 ---------------------------------------------------------------------------- */
\r
8948 * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer
\r
8952 /** INPUTMUX - Register Layout Typedef */
\r
8954 __IO uint32_t SCT0_INMUX[7]; /**< Trigger select register for DMA channel, array offset: 0x0, array step: 0x4 */
\r
8955 uint8_t RESERVED_0[164];
\r
8956 __IO uint32_t PINTSEL[8]; /**< Pin interrupt select register, array offset: 0xC0, array step: 0x4 */
\r
8957 __IO uint32_t DMA_ITRIG_INMUX[32]; /**< Trigger select register for DMA channel, array offset: 0xE0, array step: 0x4 */
\r
8958 __IO uint32_t DMA_OTRIG_INMUX[4]; /**< DMA output trigger selection to become DMA trigger, array offset: 0x160, array step: 0x4 */
\r
8959 uint8_t RESERVED_1[16];
\r
8960 __IO uint32_t FREQMEAS_REF; /**< Selection for frequency measurement reference clock, offset: 0x180 */
\r
8961 __IO uint32_t FREQMEAS_TARGET; /**< Selection for frequency measurement target clock, offset: 0x184 */
\r
8964 /* ----------------------------------------------------------------------------
\r
8965 -- INPUTMUX Register Masks
\r
8966 ---------------------------------------------------------------------------- */
\r
8969 * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks
\r
8973 /*! @name SCT0_INMUX - Trigger select register for DMA channel */
\r
8975 #define INPUTMUX_SCT0_INMUX_INP_N_MASK (0x1FU)
\r
8976 #define INPUTMUX_SCT0_INMUX_INP_N_SHIFT (0U)
\r
8977 /*! INP_N - Input number to SCT0 inputs 0 to 6..
\r
8979 #define INPUTMUX_SCT0_INMUX_INP_N(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SCT0_INMUX_INP_N_SHIFT)) & INPUTMUX_SCT0_INMUX_INP_N_MASK)
\r
8982 /* The count of INPUTMUX_SCT0_INMUX */
\r
8983 #define INPUTMUX_SCT0_INMUX_COUNT (7U)
\r
8985 /*! @name PINTSEL - Pin interrupt select register */
\r
8987 #define INPUTMUX_PINTSEL_INTPIN_MASK (0xFFU)
\r
8988 #define INPUTMUX_PINTSEL_INTPIN_SHIFT (0U)
\r
8989 /*! INTPIN - Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO1_31 correspond to numbers 0 to 63).
\r
8991 #define INPUTMUX_PINTSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK)
\r
8994 /* The count of INPUTMUX_PINTSEL */
\r
8995 #define INPUTMUX_PINTSEL_COUNT (8U)
\r
8997 /*! @name DMA_ITRIG_INMUX - Trigger select register for DMA channel */
\r
8999 #define INPUTMUX_DMA_ITRIG_INMUX_INP_MASK (0x1FU)
\r
9000 #define INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT (0U)
\r
9001 /*! INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 31). 0 = ADC0 Sequence A
\r
9002 * interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 =
\r
9003 * Timer CTIMER0 Match 0 5 = Timer CTIMER0 Match 1 6 = Timer CTIMER1 Match 0 7 = Timer CTIMER2 Match
\r
9004 * 0 8 = Timer CTIMER2 Match 1 9 = Timer CTIMER3 Match 0 10 = Timer CTIMER4 Match 0 11 = Timer
\r
9005 * CTIMER4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin
\r
9006 * interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2
\r
9007 * 19 = DMA output trigger mux 3
\r
9009 #define INPUTMUX_DMA_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_ITRIG_INMUX_INP_MASK)
\r
9012 /* The count of INPUTMUX_DMA_ITRIG_INMUX */
\r
9013 #define INPUTMUX_DMA_ITRIG_INMUX_COUNT (32U)
\r
9015 /*! @name DMA_OTRIG_INMUX - DMA output trigger selection to become DMA trigger */
\r
9017 #define INPUTMUX_DMA_OTRIG_INMUX_INP_MASK (0x1FU)
\r
9018 #define INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT (0U)
\r
9019 /*! INP - DMA trigger output number (decimal value) for DMA channel n (n = 0 to 19).
\r
9021 #define INPUTMUX_DMA_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_OTRIG_INMUX_INP_MASK)
\r
9024 /* The count of INPUTMUX_DMA_OTRIG_INMUX */
\r
9025 #define INPUTMUX_DMA_OTRIG_INMUX_COUNT (4U)
\r
9027 /*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */
\r
9029 #define INPUTMUX_FREQMEAS_REF_CLKIN_MASK (0x1FU)
\r
9030 #define INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT (0U)
\r
9031 /*! CLKIN - Clock source number (decimal value) for frequency measure function target clock: 0 =
\r
9032 * CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock
\r
9033 * (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4
\r
9035 #define INPUTMUX_FREQMEAS_REF_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK)
\r
9038 /*! @name FREQMEAS_TARGET - Selection for frequency measurement target clock */
\r
9040 #define INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK (0x1FU)
\r
9041 #define INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT (0U)
\r
9042 /*! CLKIN - Clock source number (decimal value) for frequency measure function target clock: 0 =
\r
9043 * CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock
\r
9044 * (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4
\r
9046 #define INPUTMUX_FREQMEAS_TARGET_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK)
\r
9052 */ /* end of group INPUTMUX_Register_Masks */
\r
9055 /* INPUTMUX - Peripheral instance base addresses */
\r
9056 /** Peripheral INPUTMUX base address */
\r
9057 #define INPUTMUX_BASE (0x40005000u)
\r
9058 /** Peripheral INPUTMUX base pointer */
\r
9059 #define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE)
\r
9060 /** Array initializer of INPUTMUX peripheral base addresses */
\r
9061 #define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE }
\r
9062 /** Array initializer of INPUTMUX peripheral base pointers */
\r
9063 #define INPUTMUX_BASE_PTRS { INPUTMUX }
\r
9067 */ /* end of group INPUTMUX_Peripheral_Access_Layer */
\r
9070 /* ----------------------------------------------------------------------------
\r
9071 -- IOCON Peripheral Access Layer
\r
9072 ---------------------------------------------------------------------------- */
\r
9075 * @addtogroup IOCON_Peripheral_Access_Layer IOCON Peripheral Access Layer
\r
9079 /** IOCON - Register Layout Typedef */
\r
9081 __IO uint32_t PIO[6][32]; /**< Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 5 pins PIO5_31, array offset: 0x0, array step: index*0x80, index2*0x4 */
\r
9084 /* ----------------------------------------------------------------------------
\r
9085 -- IOCON Register Masks
\r
9086 ---------------------------------------------------------------------------- */
\r
9089 * @addtogroup IOCON_Register_Masks IOCON Register Masks
\r
9093 /*! @name PIO - Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 5 pins PIO5_31 */
\r
9095 #define IOCON_PIO_FUNC_MASK (0xFU)
\r
9096 #define IOCON_PIO_FUNC_SHIFT (0U)
\r
9097 /*! FUNC - Selects pin function.
\r
9098 * 0b0000..Alternative connection 0.
\r
9099 * 0b0001..Alternative connection 1.
\r
9100 * 0b0010..Alternative connection 2.
\r
9101 * 0b0011..Alternative connection 3.
\r
9102 * 0b0100..Alternative connection 4.
\r
9103 * 0b0101..Alternative connection 5.
\r
9104 * 0b0110..Alternative connection 6.
\r
9105 * 0b0111..Alternative connection 7.
\r
9106 * 0b1000..Alternative connection 8.
\r
9107 * 0b1001..Alternative connection 9.
\r
9108 * 0b1010..Alternative connection 10.
\r
9110 #define IOCON_PIO_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK)
\r
9111 #define IOCON_PIO_MODE_MASK (0x30U)
\r
9112 #define IOCON_PIO_MODE_SHIFT (4U)
\r
9113 /*! MODE - Selects function mode (on-chip pull-up/pull-down resistor control).
\r
9114 * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled).
\r
9115 * 0b01..Pull-down. Pull-down resistor enabled.
\r
9116 * 0b10..Pull-up. Pull-up resistor enabled.
\r
9117 * 0b11..Repeater. Repeater mode.
\r
9119 #define IOCON_PIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK)
\r
9120 #define IOCON_PIO_ANAMODE_MASK (0x40U)
\r
9121 #define IOCON_PIO_ANAMODE_SHIFT (6U)
\r
9122 /*! ANAMODE - Enables or disables analog mode.
\r
9123 * 0b0..Enable analog Mode.
\r
9124 * 0b1..Disable analog Mode.
\r
9126 #define IOCON_PIO_ANAMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ANAMODE_SHIFT)) & IOCON_PIO_ANAMODE_MASK)
\r
9127 #define IOCON_PIO_I2CSLEW_MASK (0x40U)
\r
9128 #define IOCON_PIO_I2CSLEW_SHIFT (6U)
\r
9129 /*! I2CSLEW - Controls slew rate of I2C pad.
\r
9133 #define IOCON_PIO_I2CSLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CSLEW_SHIFT)) & IOCON_PIO_I2CSLEW_MASK)
\r
9134 #define IOCON_PIO_INVERT_MASK (0x80U)
\r
9135 #define IOCON_PIO_INVERT_SHIFT (7U)
\r
9136 /*! INVERT - Input polarity.
\r
9137 * 0b0..Disabled. Input function is not inverted.
\r
9138 * 0b1..Enabled. Input is function inverted.
\r
9140 #define IOCON_PIO_INVERT(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INVERT_SHIFT)) & IOCON_PIO_INVERT_MASK)
\r
9141 #define IOCON_PIO_DIGIMODE_MASK (0x100U)
\r
9142 #define IOCON_PIO_DIGIMODE_SHIFT (8U)
\r
9143 /*! DIGIMODE - Select Analog/Digital mode.
\r
9144 * 0b0..Analog mode.
\r
9145 * 0b1..Digital mode.
\r
9147 #define IOCON_PIO_DIGIMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DIGIMODE_SHIFT)) & IOCON_PIO_DIGIMODE_MASK)
\r
9148 #define IOCON_PIO_FILTEROFF_MASK (0x200U)
\r
9149 #define IOCON_PIO_FILTEROFF_SHIFT (9U)
\r
9150 /*! FILTEROFF - Controls input glitch filter.
\r
9151 * 0b0..Filter enabled. Noise pulses below approximately 10 ns are filtered out.
\r
9152 * 0b1..Filter disabled. No input filtering is done.
\r
9154 #define IOCON_PIO_FILTEROFF(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FILTEROFF_SHIFT)) & IOCON_PIO_FILTEROFF_MASK)
\r
9155 #define IOCON_PIO_I2CDRIVE_MASK (0x400U)
\r
9156 #define IOCON_PIO_I2CDRIVE_SHIFT (10U)
\r
9157 /*! I2CDRIVE - Controls the current sink capability of the pin.
\r
9158 * 0b0..Low drive. Output drive sink is 4 mA. This is sufficient for standard and fast mode I2C.
\r
9159 * 0b1..High drive. Output drive sink is 20 mA. This is needed for Fast Mode Plus I 2C. Refer to the appropriate
\r
9160 * specific device data sheet for details.
\r
9162 #define IOCON_PIO_I2CDRIVE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CDRIVE_SHIFT)) & IOCON_PIO_I2CDRIVE_MASK)
\r
9163 #define IOCON_PIO_SLEW_MASK (0x400U)
\r
9164 #define IOCON_PIO_SLEW_SHIFT (10U)
\r
9165 /*! SLEW - Driver slew rate.
\r
9166 * 0b0..Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.
\r
9167 * 0b1..Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.
\r
9169 #define IOCON_PIO_SLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW_SHIFT)) & IOCON_PIO_SLEW_MASK)
\r
9170 #define IOCON_PIO_I2CFILTEROFF_MASK (0x800U)
\r
9171 #define IOCON_PIO_I2CFILTEROFF_SHIFT (11U)
\r
9172 /*! I2CFILTEROFF - Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation.
\r
9173 * 0b0..Enabled. I2C 50 ns glitch filter enabled.
\r
9174 * 0b1..Disabled. I2C 50 ns glitch filter disabled.
\r
9176 #define IOCON_PIO_I2CFILTEROFF(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CFILTEROFF_SHIFT)) & IOCON_PIO_I2CFILTEROFF_MASK)
\r
9177 #define IOCON_PIO_OD_MASK (0x800U)
\r
9178 #define IOCON_PIO_OD_SHIFT (11U)
\r
9179 /*! OD - Controls open-drain mode.
\r
9180 * 0b0..Normal. Normal push-pull output
\r
9181 * 0b1..Open-drain. Simulated open-drain output (high drive disabled).
\r
9183 #define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK)
\r
9186 /* The count of IOCON_PIO */
\r
9187 #define IOCON_PIO_COUNT (6U)
\r
9189 /* The count of IOCON_PIO */
\r
9190 #define IOCON_PIO_COUNT2 (32U)
\r
9195 */ /* end of group IOCON_Register_Masks */
\r
9198 /* IOCON - Peripheral instance base addresses */
\r
9199 /** Peripheral IOCON base address */
\r
9200 #define IOCON_BASE (0x40001000u)
\r
9201 /** Peripheral IOCON base pointer */
\r
9202 #define IOCON ((IOCON_Type *)IOCON_BASE)
\r
9203 /** Array initializer of IOCON peripheral base addresses */
\r
9204 #define IOCON_BASE_ADDRS { IOCON_BASE }
\r
9205 /** Array initializer of IOCON peripheral base pointers */
\r
9206 #define IOCON_BASE_PTRS { IOCON }
\r
9210 */ /* end of group IOCON_Peripheral_Access_Layer */
\r
9213 /* ----------------------------------------------------------------------------
\r
9214 -- LCD Peripheral Access Layer
\r
9215 ---------------------------------------------------------------------------- */
\r
9218 * @addtogroup LCD_Peripheral_Access_Layer LCD Peripheral Access Layer
\r
9222 /** LCD - Register Layout Typedef */
\r
9224 __IO uint32_t TIMH; /**< Horizontal Timing Control register, offset: 0x0 */
\r
9225 __IO uint32_t TIMV; /**< Vertical Timing Control register, offset: 0x4 */
\r
9226 __IO uint32_t POL; /**< Clock and Signal Polarity Control register, offset: 0x8 */
\r
9227 __IO uint32_t LE; /**< Line End Control register, offset: 0xC */
\r
9228 __IO uint32_t UPBASE; /**< Upper Panel Frame Base Address register, offset: 0x10 */
\r
9229 __IO uint32_t LPBASE; /**< Lower Panel Frame Base Address register, offset: 0x14 */
\r
9230 __IO uint32_t CTRL; /**< LCD Control register, offset: 0x18 */
\r
9231 __IO uint32_t INTMSK; /**< Interrupt Mask register, offset: 0x1C */
\r
9232 __I uint32_t INTRAW; /**< Raw Interrupt Status register, offset: 0x20 */
\r
9233 __I uint32_t INTSTAT; /**< Masked Interrupt Status register, offset: 0x24 */
\r
9234 __O uint32_t INTCLR; /**< Interrupt Clear register, offset: 0x28 */
\r
9235 __I uint32_t UPCURR; /**< Upper Panel Current Address Value register, offset: 0x2C */
\r
9236 __I uint32_t LPCURR; /**< Lower Panel Current Address Value register, offset: 0x30 */
\r
9237 uint8_t RESERVED_0[460];
\r
9238 __IO uint32_t PAL[128]; /**< 256x16-bit Color Palette registers, array offset: 0x200, array step: 0x4 */
\r
9239 uint8_t RESERVED_1[1024];
\r
9240 __IO uint32_t CRSR_IMG[256]; /**< Cursor Image registers, array offset: 0x800, array step: 0x4 */
\r
9241 __IO uint32_t CRSR_CTRL; /**< Cursor Control register, offset: 0xC00 */
\r
9242 __IO uint32_t CRSR_CFG; /**< Cursor Configuration register, offset: 0xC04 */
\r
9243 __IO uint32_t CRSR_PAL0; /**< Cursor Palette register 0, offset: 0xC08 */
\r
9244 __IO uint32_t CRSR_PAL1; /**< Cursor Palette register 1, offset: 0xC0C */
\r
9245 __IO uint32_t CRSR_XY; /**< Cursor XY Position register, offset: 0xC10 */
\r
9246 __IO uint32_t CRSR_CLIP; /**< Cursor Clip Position register, offset: 0xC14 */
\r
9247 uint8_t RESERVED_2[8];
\r
9248 __IO uint32_t CRSR_INTMSK; /**< Cursor Interrupt Mask register, offset: 0xC20 */
\r
9249 __O uint32_t CRSR_INTCLR; /**< Cursor Interrupt Clear register, offset: 0xC24 */
\r
9250 __I uint32_t CRSR_INTRAW; /**< Cursor Raw Interrupt Status register, offset: 0xC28 */
\r
9251 __I uint32_t CRSR_INTSTAT; /**< Cursor Masked Interrupt Status register, offset: 0xC2C */
\r
9254 /* ----------------------------------------------------------------------------
\r
9255 -- LCD Register Masks
\r
9256 ---------------------------------------------------------------------------- */
\r
9259 * @addtogroup LCD_Register_Masks LCD Register Masks
\r
9263 /*! @name TIMH - Horizontal Timing Control register */
\r
9265 #define LCD_TIMH_PPL_MASK (0xFCU)
\r
9266 #define LCD_TIMH_PPL_SHIFT (2U)
\r
9267 /*! PPL - Pixels-per-line.
\r
9269 #define LCD_TIMH_PPL(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMH_PPL_SHIFT)) & LCD_TIMH_PPL_MASK)
\r
9270 #define LCD_TIMH_HSW_MASK (0xFF00U)
\r
9271 #define LCD_TIMH_HSW_SHIFT (8U)
\r
9272 /*! HSW - Horizontal synchronization pulse width.
\r
9274 #define LCD_TIMH_HSW(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMH_HSW_SHIFT)) & LCD_TIMH_HSW_MASK)
\r
9275 #define LCD_TIMH_HFP_MASK (0xFF0000U)
\r
9276 #define LCD_TIMH_HFP_SHIFT (16U)
\r
9277 /*! HFP - Horizontal front porch.
\r
9279 #define LCD_TIMH_HFP(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMH_HFP_SHIFT)) & LCD_TIMH_HFP_MASK)
\r
9280 #define LCD_TIMH_HBP_MASK (0xFF000000U)
\r
9281 #define LCD_TIMH_HBP_SHIFT (24U)
\r
9282 /*! HBP - Horizontal back porch.
\r
9284 #define LCD_TIMH_HBP(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMH_HBP_SHIFT)) & LCD_TIMH_HBP_MASK)
\r
9287 /*! @name TIMV - Vertical Timing Control register */
\r
9289 #define LCD_TIMV_LPP_MASK (0x3FFU)
\r
9290 #define LCD_TIMV_LPP_SHIFT (0U)
\r
9291 /*! LPP - Lines per panel.
\r
9293 #define LCD_TIMV_LPP(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMV_LPP_SHIFT)) & LCD_TIMV_LPP_MASK)
\r
9294 #define LCD_TIMV_VSW_MASK (0xFC00U)
\r
9295 #define LCD_TIMV_VSW_SHIFT (10U)
\r
9296 /*! VSW - Vertical synchronization pulse width.
\r
9298 #define LCD_TIMV_VSW(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMV_VSW_SHIFT)) & LCD_TIMV_VSW_MASK)
\r
9299 #define LCD_TIMV_VFP_MASK (0xFF0000U)
\r
9300 #define LCD_TIMV_VFP_SHIFT (16U)
\r
9301 /*! VFP - Vertical front porch.
\r
9303 #define LCD_TIMV_VFP(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMV_VFP_SHIFT)) & LCD_TIMV_VFP_MASK)
\r
9304 #define LCD_TIMV_VBP_MASK (0xFF000000U)
\r
9305 #define LCD_TIMV_VBP_SHIFT (24U)
\r
9306 /*! VBP - Vertical back porch.
\r
9308 #define LCD_TIMV_VBP(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMV_VBP_SHIFT)) & LCD_TIMV_VBP_MASK)
\r
9311 /*! @name POL - Clock and Signal Polarity Control register */
\r
9313 #define LCD_POL_PCD_LO_MASK (0x1FU)
\r
9314 #define LCD_POL_PCD_LO_SHIFT (0U)
\r
9315 /*! PCD_LO - Lower five bits of panel clock divisor.
\r
9317 #define LCD_POL_PCD_LO(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_PCD_LO_SHIFT)) & LCD_POL_PCD_LO_MASK)
\r
9318 #define LCD_POL_ACB_MASK (0x7C0U)
\r
9319 #define LCD_POL_ACB_SHIFT (6U)
\r
9320 /*! ACB - AC bias pin frequency.
\r
9322 #define LCD_POL_ACB(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_ACB_SHIFT)) & LCD_POL_ACB_MASK)
\r
9323 #define LCD_POL_IVS_MASK (0x800U)
\r
9324 #define LCD_POL_IVS_SHIFT (11U)
\r
9325 /*! IVS - Invert vertical synchronization.
\r
9327 #define LCD_POL_IVS(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_IVS_SHIFT)) & LCD_POL_IVS_MASK)
\r
9328 #define LCD_POL_IHS_MASK (0x1000U)
\r
9329 #define LCD_POL_IHS_SHIFT (12U)
\r
9330 /*! IHS - Invert horizontal synchronization.
\r
9332 #define LCD_POL_IHS(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_IHS_SHIFT)) & LCD_POL_IHS_MASK)
\r
9333 #define LCD_POL_IPC_MASK (0x2000U)
\r
9334 #define LCD_POL_IPC_SHIFT (13U)
\r
9335 /*! IPC - Invert panel clock.
\r
9337 #define LCD_POL_IPC(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_IPC_SHIFT)) & LCD_POL_IPC_MASK)
\r
9338 #define LCD_POL_IOE_MASK (0x4000U)
\r
9339 #define LCD_POL_IOE_SHIFT (14U)
\r
9340 /*! IOE - Invert output enable.
\r
9342 #define LCD_POL_IOE(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_IOE_SHIFT)) & LCD_POL_IOE_MASK)
\r
9343 #define LCD_POL_CPL_MASK (0x3FF0000U)
\r
9344 #define LCD_POL_CPL_SHIFT (16U)
\r
9345 /*! CPL - Clocks per line.
\r
9347 #define LCD_POL_CPL(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_CPL_SHIFT)) & LCD_POL_CPL_MASK)
\r
9348 #define LCD_POL_BCD_MASK (0x4000000U)
\r
9349 #define LCD_POL_BCD_SHIFT (26U)
\r
9350 /*! BCD - Bypass panel clock divider.
\r
9352 #define LCD_POL_BCD(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_BCD_SHIFT)) & LCD_POL_BCD_MASK)
\r
9353 #define LCD_POL_PCD_HI_MASK (0xF8000000U)
\r
9354 #define LCD_POL_PCD_HI_SHIFT (27U)
\r
9355 /*! PCD_HI - Upper five bits of panel clock divisor.
\r
9357 #define LCD_POL_PCD_HI(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_PCD_HI_SHIFT)) & LCD_POL_PCD_HI_MASK)
\r
9360 /*! @name LE - Line End Control register */
\r
9362 #define LCD_LE_LED_MASK (0x7FU)
\r
9363 #define LCD_LE_LED_SHIFT (0U)
\r
9364 /*! LED - Line-end delay.
\r
9366 #define LCD_LE_LED(x) (((uint32_t)(((uint32_t)(x)) << LCD_LE_LED_SHIFT)) & LCD_LE_LED_MASK)
\r
9367 #define LCD_LE_LEE_MASK (0x10000U)
\r
9368 #define LCD_LE_LEE_SHIFT (16U)
\r
9369 /*! LEE - LCD Line end enable.
\r
9371 #define LCD_LE_LEE(x) (((uint32_t)(((uint32_t)(x)) << LCD_LE_LEE_SHIFT)) & LCD_LE_LEE_MASK)
\r
9374 /*! @name UPBASE - Upper Panel Frame Base Address register */
\r
9376 #define LCD_UPBASE_LCDUPBASE_MASK (0xFFFFFFF8U)
\r
9377 #define LCD_UPBASE_LCDUPBASE_SHIFT (3U)
\r
9378 /*! LCDUPBASE - LCD upper panel base address.
\r
9380 #define LCD_UPBASE_LCDUPBASE(x) (((uint32_t)(((uint32_t)(x)) << LCD_UPBASE_LCDUPBASE_SHIFT)) & LCD_UPBASE_LCDUPBASE_MASK)
\r
9383 /*! @name LPBASE - Lower Panel Frame Base Address register */
\r
9385 #define LCD_LPBASE_LCDLPBASE_MASK (0xFFFFFFF8U)
\r
9386 #define LCD_LPBASE_LCDLPBASE_SHIFT (3U)
\r
9387 /*! LCDLPBASE - LCD lower panel base address.
\r
9389 #define LCD_LPBASE_LCDLPBASE(x) (((uint32_t)(((uint32_t)(x)) << LCD_LPBASE_LCDLPBASE_SHIFT)) & LCD_LPBASE_LCDLPBASE_MASK)
\r
9392 /*! @name CTRL - LCD Control register */
\r
9394 #define LCD_CTRL_LCDEN_MASK (0x1U)
\r
9395 #define LCD_CTRL_LCDEN_SHIFT (0U)
\r
9396 /*! LCDEN - LCD enable control bit.
\r
9398 #define LCD_CTRL_LCDEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDEN_SHIFT)) & LCD_CTRL_LCDEN_MASK)
\r
9399 #define LCD_CTRL_LCDBPP_MASK (0xEU)
\r
9400 #define LCD_CTRL_LCDBPP_SHIFT (1U)
\r
9401 /*! LCDBPP - LCD bits per pixel.
\r
9403 #define LCD_CTRL_LCDBPP(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDBPP_SHIFT)) & LCD_CTRL_LCDBPP_MASK)
\r
9404 #define LCD_CTRL_LCDBW_MASK (0x10U)
\r
9405 #define LCD_CTRL_LCDBW_SHIFT (4U)
\r
9406 /*! LCDBW - STN LCD monochrome/color selection.
\r
9408 #define LCD_CTRL_LCDBW(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDBW_SHIFT)) & LCD_CTRL_LCDBW_MASK)
\r
9409 #define LCD_CTRL_LCDTFT_MASK (0x20U)
\r
9410 #define LCD_CTRL_LCDTFT_SHIFT (5U)
\r
9411 /*! LCDTFT - LCD panel TFT type selection.
\r
9413 #define LCD_CTRL_LCDTFT(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDTFT_SHIFT)) & LCD_CTRL_LCDTFT_MASK)
\r
9414 #define LCD_CTRL_LCDMONO8_MASK (0x40U)
\r
9415 #define LCD_CTRL_LCDMONO8_SHIFT (6U)
\r
9416 /*! LCDMONO8 - Monochrome LCD interface width.
\r
9418 #define LCD_CTRL_LCDMONO8(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDMONO8_SHIFT)) & LCD_CTRL_LCDMONO8_MASK)
\r
9419 #define LCD_CTRL_LCDDUAL_MASK (0x80U)
\r
9420 #define LCD_CTRL_LCDDUAL_SHIFT (7U)
\r
9421 /*! LCDDUAL - Single or Dual LCD panel selection.
\r
9423 #define LCD_CTRL_LCDDUAL(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDDUAL_SHIFT)) & LCD_CTRL_LCDDUAL_MASK)
\r
9424 #define LCD_CTRL_BGR_MASK (0x100U)
\r
9425 #define LCD_CTRL_BGR_SHIFT (8U)
\r
9426 /*! BGR - Color format selection.
\r
9428 #define LCD_CTRL_BGR(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_BGR_SHIFT)) & LCD_CTRL_BGR_MASK)
\r
9429 #define LCD_CTRL_BEBO_MASK (0x200U)
\r
9430 #define LCD_CTRL_BEBO_SHIFT (9U)
\r
9431 /*! BEBO - Big-endian Byte Order.
\r
9433 #define LCD_CTRL_BEBO(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_BEBO_SHIFT)) & LCD_CTRL_BEBO_MASK)
\r
9434 #define LCD_CTRL_BEPO_MASK (0x400U)
\r
9435 #define LCD_CTRL_BEPO_SHIFT (10U)
\r
9436 /*! BEPO - Big-Endian Pixel Ordering.
\r
9438 #define LCD_CTRL_BEPO(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_BEPO_SHIFT)) & LCD_CTRL_BEPO_MASK)
\r
9439 #define LCD_CTRL_LCDPWR_MASK (0x800U)
\r
9440 #define LCD_CTRL_LCDPWR_SHIFT (11U)
\r
9441 /*! LCDPWR - LCD power enable.
\r
9443 #define LCD_CTRL_LCDPWR(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDPWR_SHIFT)) & LCD_CTRL_LCDPWR_MASK)
\r
9444 #define LCD_CTRL_LCDVCOMP_MASK (0x3000U)
\r
9445 #define LCD_CTRL_LCDVCOMP_SHIFT (12U)
\r
9446 /*! LCDVCOMP - LCD Vertical Compare Interrupt.
\r
9448 #define LCD_CTRL_LCDVCOMP(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDVCOMP_SHIFT)) & LCD_CTRL_LCDVCOMP_MASK)
\r
9449 #define LCD_CTRL_WATERMARK_MASK (0x10000U)
\r
9450 #define LCD_CTRL_WATERMARK_SHIFT (16U)
\r
9451 /*! WATERMARK - LCD DMA FIFO watermark level.
\r
9453 #define LCD_CTRL_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_WATERMARK_SHIFT)) & LCD_CTRL_WATERMARK_MASK)
\r
9456 /*! @name INTMSK - Interrupt Mask register */
\r
9458 #define LCD_INTMSK_FUFIM_MASK (0x2U)
\r
9459 #define LCD_INTMSK_FUFIM_SHIFT (1U)
\r
9460 /*! FUFIM - FIFO underflow interrupt enable.
\r
9462 #define LCD_INTMSK_FUFIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTMSK_FUFIM_SHIFT)) & LCD_INTMSK_FUFIM_MASK)
\r
9463 #define LCD_INTMSK_LNBUIM_MASK (0x4U)
\r
9464 #define LCD_INTMSK_LNBUIM_SHIFT (2U)
\r
9465 /*! LNBUIM - LCD next base address update interrupt enable.
\r
9467 #define LCD_INTMSK_LNBUIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTMSK_LNBUIM_SHIFT)) & LCD_INTMSK_LNBUIM_MASK)
\r
9468 #define LCD_INTMSK_VCOMPIM_MASK (0x8U)
\r
9469 #define LCD_INTMSK_VCOMPIM_SHIFT (3U)
\r
9470 /*! VCOMPIM - Vertical compare interrupt enable.
\r
9472 #define LCD_INTMSK_VCOMPIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTMSK_VCOMPIM_SHIFT)) & LCD_INTMSK_VCOMPIM_MASK)
\r
9473 #define LCD_INTMSK_BERIM_MASK (0x10U)
\r
9474 #define LCD_INTMSK_BERIM_SHIFT (4U)
\r
9475 /*! BERIM - AHB master error interrupt enable.
\r
9477 #define LCD_INTMSK_BERIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTMSK_BERIM_SHIFT)) & LCD_INTMSK_BERIM_MASK)
\r
9480 /*! @name INTRAW - Raw Interrupt Status register */
\r
9482 #define LCD_INTRAW_FUFRIS_MASK (0x2U)
\r
9483 #define LCD_INTRAW_FUFRIS_SHIFT (1U)
\r
9484 /*! FUFRIS - FIFO underflow raw interrupt status.
\r
9486 #define LCD_INTRAW_FUFRIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTRAW_FUFRIS_SHIFT)) & LCD_INTRAW_FUFRIS_MASK)
\r
9487 #define LCD_INTRAW_LNBURIS_MASK (0x4U)
\r
9488 #define LCD_INTRAW_LNBURIS_SHIFT (2U)
\r
9489 /*! LNBURIS - LCD next address base update raw interrupt status.
\r
9491 #define LCD_INTRAW_LNBURIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTRAW_LNBURIS_SHIFT)) & LCD_INTRAW_LNBURIS_MASK)
\r
9492 #define LCD_INTRAW_VCOMPRIS_MASK (0x8U)
\r
9493 #define LCD_INTRAW_VCOMPRIS_SHIFT (3U)
\r
9494 /*! VCOMPRIS - Vertical compare raw interrupt status.
\r
9496 #define LCD_INTRAW_VCOMPRIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTRAW_VCOMPRIS_SHIFT)) & LCD_INTRAW_VCOMPRIS_MASK)
\r
9497 #define LCD_INTRAW_BERRAW_MASK (0x10U)
\r
9498 #define LCD_INTRAW_BERRAW_SHIFT (4U)
\r
9499 /*! BERRAW - AHB master bus error raw interrupt status.
\r
9501 #define LCD_INTRAW_BERRAW(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTRAW_BERRAW_SHIFT)) & LCD_INTRAW_BERRAW_MASK)
\r
9504 /*! @name INTSTAT - Masked Interrupt Status register */
\r
9506 #define LCD_INTSTAT_FUFMIS_MASK (0x2U)
\r
9507 #define LCD_INTSTAT_FUFMIS_SHIFT (1U)
\r
9508 /*! FUFMIS - FIFO underflow masked interrupt status.
\r
9510 #define LCD_INTSTAT_FUFMIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTSTAT_FUFMIS_SHIFT)) & LCD_INTSTAT_FUFMIS_MASK)
\r
9511 #define LCD_INTSTAT_LNBUMIS_MASK (0x4U)
\r
9512 #define LCD_INTSTAT_LNBUMIS_SHIFT (2U)
\r
9513 /*! LNBUMIS - LCD next address base update masked interrupt status.
\r
9515 #define LCD_INTSTAT_LNBUMIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTSTAT_LNBUMIS_SHIFT)) & LCD_INTSTAT_LNBUMIS_MASK)
\r
9516 #define LCD_INTSTAT_VCOMPMIS_MASK (0x8U)
\r
9517 #define LCD_INTSTAT_VCOMPMIS_SHIFT (3U)
\r
9518 /*! VCOMPMIS - Vertical compare masked interrupt status.
\r
9520 #define LCD_INTSTAT_VCOMPMIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTSTAT_VCOMPMIS_SHIFT)) & LCD_INTSTAT_VCOMPMIS_MASK)
\r
9521 #define LCD_INTSTAT_BERMIS_MASK (0x10U)
\r
9522 #define LCD_INTSTAT_BERMIS_SHIFT (4U)
\r
9523 /*! BERMIS - AHB master bus error masked interrupt status.
\r
9525 #define LCD_INTSTAT_BERMIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTSTAT_BERMIS_SHIFT)) & LCD_INTSTAT_BERMIS_MASK)
\r
9528 /*! @name INTCLR - Interrupt Clear register */
\r
9530 #define LCD_INTCLR_FUFIC_MASK (0x2U)
\r
9531 #define LCD_INTCLR_FUFIC_SHIFT (1U)
\r
9532 /*! FUFIC - FIFO underflow interrupt clear.
\r
9534 #define LCD_INTCLR_FUFIC(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTCLR_FUFIC_SHIFT)) & LCD_INTCLR_FUFIC_MASK)
\r
9535 #define LCD_INTCLR_LNBUIC_MASK (0x4U)
\r
9536 #define LCD_INTCLR_LNBUIC_SHIFT (2U)
\r
9537 /*! LNBUIC - LCD next address base update interrupt clear.
\r
9539 #define LCD_INTCLR_LNBUIC(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTCLR_LNBUIC_SHIFT)) & LCD_INTCLR_LNBUIC_MASK)
\r
9540 #define LCD_INTCLR_VCOMPIC_MASK (0x8U)
\r
9541 #define LCD_INTCLR_VCOMPIC_SHIFT (3U)
\r
9542 /*! VCOMPIC - Vertical compare interrupt clear.
\r
9544 #define LCD_INTCLR_VCOMPIC(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTCLR_VCOMPIC_SHIFT)) & LCD_INTCLR_VCOMPIC_MASK)
\r
9545 #define LCD_INTCLR_BERIC_MASK (0x10U)
\r
9546 #define LCD_INTCLR_BERIC_SHIFT (4U)
\r
9547 /*! BERIC - AHB master error interrupt clear.
\r
9549 #define LCD_INTCLR_BERIC(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTCLR_BERIC_SHIFT)) & LCD_INTCLR_BERIC_MASK)
\r
9552 /*! @name UPCURR - Upper Panel Current Address Value register */
\r
9554 #define LCD_UPCURR_LCDUPCURR_MASK (0xFFFFFFFFU)
\r
9555 #define LCD_UPCURR_LCDUPCURR_SHIFT (0U)
\r
9556 /*! LCDUPCURR - LCD Upper Panel Current Address.
\r
9558 #define LCD_UPCURR_LCDUPCURR(x) (((uint32_t)(((uint32_t)(x)) << LCD_UPCURR_LCDUPCURR_SHIFT)) & LCD_UPCURR_LCDUPCURR_MASK)
\r
9561 /*! @name LPCURR - Lower Panel Current Address Value register */
\r
9563 #define LCD_LPCURR_LCDLPCURR_MASK (0xFFFFFFFFU)
\r
9564 #define LCD_LPCURR_LCDLPCURR_SHIFT (0U)
\r
9565 /*! LCDLPCURR - LCD Lower Panel Current Address.
\r
9567 #define LCD_LPCURR_LCDLPCURR(x) (((uint32_t)(((uint32_t)(x)) << LCD_LPCURR_LCDLPCURR_SHIFT)) & LCD_LPCURR_LCDLPCURR_MASK)
\r
9570 /*! @name PAL - 256x16-bit Color Palette registers */
\r
9572 #define LCD_PAL_R04_0_MASK (0x1FU)
\r
9573 #define LCD_PAL_R04_0_SHIFT (0U)
\r
9574 /*! R04_0 - Red palette data.
\r
9576 #define LCD_PAL_R04_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_R04_0_SHIFT)) & LCD_PAL_R04_0_MASK)
\r
9577 #define LCD_PAL_G04_0_MASK (0x3E0U)
\r
9578 #define LCD_PAL_G04_0_SHIFT (5U)
\r
9579 /*! G04_0 - Green palette data.
\r
9581 #define LCD_PAL_G04_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_G04_0_SHIFT)) & LCD_PAL_G04_0_MASK)
\r
9582 #define LCD_PAL_B04_0_MASK (0x7C00U)
\r
9583 #define LCD_PAL_B04_0_SHIFT (10U)
\r
9584 /*! B04_0 - Blue palette data.
\r
9586 #define LCD_PAL_B04_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_B04_0_SHIFT)) & LCD_PAL_B04_0_MASK)
\r
9587 #define LCD_PAL_I0_MASK (0x8000U)
\r
9588 #define LCD_PAL_I0_SHIFT (15U)
\r
9589 /*! I0 - Intensity / unused bit.
\r
9591 #define LCD_PAL_I0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_I0_SHIFT)) & LCD_PAL_I0_MASK)
\r
9592 #define LCD_PAL_R14_0_MASK (0x1F0000U)
\r
9593 #define LCD_PAL_R14_0_SHIFT (16U)
\r
9594 /*! R14_0 - Red palette data.
\r
9596 #define LCD_PAL_R14_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_R14_0_SHIFT)) & LCD_PAL_R14_0_MASK)
\r
9597 #define LCD_PAL_G14_0_MASK (0x3E00000U)
\r
9598 #define LCD_PAL_G14_0_SHIFT (21U)
\r
9599 /*! G14_0 - Green palette data.
\r
9601 #define LCD_PAL_G14_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_G14_0_SHIFT)) & LCD_PAL_G14_0_MASK)
\r
9602 #define LCD_PAL_B14_0_MASK (0x7C000000U)
\r
9603 #define LCD_PAL_B14_0_SHIFT (26U)
\r
9604 /*! B14_0 - Blue palette data.
\r
9606 #define LCD_PAL_B14_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_B14_0_SHIFT)) & LCD_PAL_B14_0_MASK)
\r
9607 #define LCD_PAL_I1_MASK (0x80000000U)
\r
9608 #define LCD_PAL_I1_SHIFT (31U)
\r
9609 /*! I1 - Intensity / unused bit.
\r
9611 #define LCD_PAL_I1(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_I1_SHIFT)) & LCD_PAL_I1_MASK)
\r
9614 /* The count of LCD_PAL */
\r
9615 #define LCD_PAL_COUNT (128U)
\r
9617 /*! @name CRSR_IMG - Cursor Image registers */
\r
9619 #define LCD_CRSR_IMG_CRSR_IMG_MASK (0xFFFFFFFFU)
\r
9620 #define LCD_CRSR_IMG_CRSR_IMG_SHIFT (0U)
\r
9621 /*! CRSR_IMG - Cursor Image data.
\r
9623 #define LCD_CRSR_IMG_CRSR_IMG(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_IMG_CRSR_IMG_SHIFT)) & LCD_CRSR_IMG_CRSR_IMG_MASK)
\r
9626 /* The count of LCD_CRSR_IMG */
\r
9627 #define LCD_CRSR_IMG_COUNT (256U)
\r
9629 /*! @name CRSR_CTRL - Cursor Control register */
\r
9631 #define LCD_CRSR_CTRL_CRSRON_MASK (0x1U)
\r
9632 #define LCD_CRSR_CTRL_CRSRON_SHIFT (0U)
\r
9633 /*! CRSRON - Cursor enable.
\r
9635 #define LCD_CRSR_CTRL_CRSRON(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CTRL_CRSRON_SHIFT)) & LCD_CRSR_CTRL_CRSRON_MASK)
\r
9636 #define LCD_CRSR_CTRL_CRSRNUM1_0_MASK (0x30U)
\r
9637 #define LCD_CRSR_CTRL_CRSRNUM1_0_SHIFT (4U)
\r
9638 /*! CRSRNUM1_0 - Cursor image number.
\r
9640 #define LCD_CRSR_CTRL_CRSRNUM1_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CTRL_CRSRNUM1_0_SHIFT)) & LCD_CRSR_CTRL_CRSRNUM1_0_MASK)
\r
9643 /*! @name CRSR_CFG - Cursor Configuration register */
\r
9645 #define LCD_CRSR_CFG_CRSRSIZE_MASK (0x1U)
\r
9646 #define LCD_CRSR_CFG_CRSRSIZE_SHIFT (0U)
\r
9647 /*! CRSRSIZE - Cursor size selection.
\r
9649 #define LCD_CRSR_CFG_CRSRSIZE(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CFG_CRSRSIZE_SHIFT)) & LCD_CRSR_CFG_CRSRSIZE_MASK)
\r
9650 #define LCD_CRSR_CFG_FRAMESYNC_MASK (0x2U)
\r
9651 #define LCD_CRSR_CFG_FRAMESYNC_SHIFT (1U)
\r
9652 /*! FRAMESYNC - Cursor frame synchronization type.
\r
9654 #define LCD_CRSR_CFG_FRAMESYNC(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CFG_FRAMESYNC_SHIFT)) & LCD_CRSR_CFG_FRAMESYNC_MASK)
\r
9657 /*! @name CRSR_PAL0 - Cursor Palette register 0 */
\r
9659 #define LCD_CRSR_PAL0_RED_MASK (0xFFU)
\r
9660 #define LCD_CRSR_PAL0_RED_SHIFT (0U)
\r
9661 /*! RED - Red color component.
\r
9663 #define LCD_CRSR_PAL0_RED(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL0_RED_SHIFT)) & LCD_CRSR_PAL0_RED_MASK)
\r
9664 #define LCD_CRSR_PAL0_GREEN_MASK (0xFF00U)
\r
9665 #define LCD_CRSR_PAL0_GREEN_SHIFT (8U)
\r
9666 /*! GREEN - Green color component.
\r
9668 #define LCD_CRSR_PAL0_GREEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL0_GREEN_SHIFT)) & LCD_CRSR_PAL0_GREEN_MASK)
\r
9669 #define LCD_CRSR_PAL0_BLUE_MASK (0xFF0000U)
\r
9670 #define LCD_CRSR_PAL0_BLUE_SHIFT (16U)
\r
9671 /*! BLUE - Blue color component.
\r
9673 #define LCD_CRSR_PAL0_BLUE(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL0_BLUE_SHIFT)) & LCD_CRSR_PAL0_BLUE_MASK)
\r
9676 /*! @name CRSR_PAL1 - Cursor Palette register 1 */
\r
9678 #define LCD_CRSR_PAL1_RED_MASK (0xFFU)
\r
9679 #define LCD_CRSR_PAL1_RED_SHIFT (0U)
\r
9680 /*! RED - Red color component.
\r
9682 #define LCD_CRSR_PAL1_RED(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL1_RED_SHIFT)) & LCD_CRSR_PAL1_RED_MASK)
\r
9683 #define LCD_CRSR_PAL1_GREEN_MASK (0xFF00U)
\r
9684 #define LCD_CRSR_PAL1_GREEN_SHIFT (8U)
\r
9685 /*! GREEN - Green color component.
\r
9687 #define LCD_CRSR_PAL1_GREEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL1_GREEN_SHIFT)) & LCD_CRSR_PAL1_GREEN_MASK)
\r
9688 #define LCD_CRSR_PAL1_BLUE_MASK (0xFF0000U)
\r
9689 #define LCD_CRSR_PAL1_BLUE_SHIFT (16U)
\r
9690 /*! BLUE - Blue color component.
\r
9692 #define LCD_CRSR_PAL1_BLUE(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL1_BLUE_SHIFT)) & LCD_CRSR_PAL1_BLUE_MASK)
\r
9695 /*! @name CRSR_XY - Cursor XY Position register */
\r
9697 #define LCD_CRSR_XY_CRSRX_MASK (0x3FFU)
\r
9698 #define LCD_CRSR_XY_CRSRX_SHIFT (0U)
\r
9699 /*! CRSRX - X ordinate of the cursor origin measured in pixels.
\r
9701 #define LCD_CRSR_XY_CRSRX(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_XY_CRSRX_SHIFT)) & LCD_CRSR_XY_CRSRX_MASK)
\r
9702 #define LCD_CRSR_XY_CRSRY_MASK (0x3FF0000U)
\r
9703 #define LCD_CRSR_XY_CRSRY_SHIFT (16U)
\r
9704 /*! CRSRY - Y ordinate of the cursor origin measured in pixels.
\r
9706 #define LCD_CRSR_XY_CRSRY(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_XY_CRSRY_SHIFT)) & LCD_CRSR_XY_CRSRY_MASK)
\r
9709 /*! @name CRSR_CLIP - Cursor Clip Position register */
\r
9711 #define LCD_CRSR_CLIP_CRSRCLIPX_MASK (0x3FU)
\r
9712 #define LCD_CRSR_CLIP_CRSRCLIPX_SHIFT (0U)
\r
9713 /*! CRSRCLIPX - Cursor clip position for X direction.
\r
9715 #define LCD_CRSR_CLIP_CRSRCLIPX(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CLIP_CRSRCLIPX_SHIFT)) & LCD_CRSR_CLIP_CRSRCLIPX_MASK)
\r
9716 #define LCD_CRSR_CLIP_CRSRCLIPY_MASK (0x3F00U)
\r
9717 #define LCD_CRSR_CLIP_CRSRCLIPY_SHIFT (8U)
\r
9718 /*! CRSRCLIPY - Cursor clip position for Y direction.
\r
9720 #define LCD_CRSR_CLIP_CRSRCLIPY(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CLIP_CRSRCLIPY_SHIFT)) & LCD_CRSR_CLIP_CRSRCLIPY_MASK)
\r
9723 /*! @name CRSR_INTMSK - Cursor Interrupt Mask register */
\r
9725 #define LCD_CRSR_INTMSK_CRSRIM_MASK (0x1U)
\r
9726 #define LCD_CRSR_INTMSK_CRSRIM_SHIFT (0U)
\r
9727 /*! CRSRIM - Cursor interrupt mask.
\r
9729 #define LCD_CRSR_INTMSK_CRSRIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_INTMSK_CRSRIM_SHIFT)) & LCD_CRSR_INTMSK_CRSRIM_MASK)
\r
9732 /*! @name CRSR_INTCLR - Cursor Interrupt Clear register */
\r
9734 #define LCD_CRSR_INTCLR_CRSRIC_MASK (0x1U)
\r
9735 #define LCD_CRSR_INTCLR_CRSRIC_SHIFT (0U)
\r
9736 /*! CRSRIC - Cursor interrupt clear.
\r
9738 #define LCD_CRSR_INTCLR_CRSRIC(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_INTCLR_CRSRIC_SHIFT)) & LCD_CRSR_INTCLR_CRSRIC_MASK)
\r
9741 /*! @name CRSR_INTRAW - Cursor Raw Interrupt Status register */
\r
9743 #define LCD_CRSR_INTRAW_CRSRRIS_MASK (0x1U)
\r
9744 #define LCD_CRSR_INTRAW_CRSRRIS_SHIFT (0U)
\r
9745 /*! CRSRRIS - Cursor raw interrupt status.
\r
9747 #define LCD_CRSR_INTRAW_CRSRRIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_INTRAW_CRSRRIS_SHIFT)) & LCD_CRSR_INTRAW_CRSRRIS_MASK)
\r
9750 /*! @name CRSR_INTSTAT - Cursor Masked Interrupt Status register */
\r
9752 #define LCD_CRSR_INTSTAT_CRSRMIS_MASK (0x1U)
\r
9753 #define LCD_CRSR_INTSTAT_CRSRMIS_SHIFT (0U)
\r
9754 /*! CRSRMIS - Cursor masked interrupt status.
\r
9756 #define LCD_CRSR_INTSTAT_CRSRMIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_INTSTAT_CRSRMIS_SHIFT)) & LCD_CRSR_INTSTAT_CRSRMIS_MASK)
\r
9762 */ /* end of group LCD_Register_Masks */
\r
9765 /* LCD - Peripheral instance base addresses */
\r
9766 /** Peripheral LCD base address */
\r
9767 #define LCD_BASE (0x40083000u)
\r
9768 /** Peripheral LCD base pointer */
\r
9769 #define LCD ((LCD_Type *)LCD_BASE)
\r
9770 /** Array initializer of LCD peripheral base addresses */
\r
9771 #define LCD_BASE_ADDRS { LCD_BASE }
\r
9772 /** Array initializer of LCD peripheral base pointers */
\r
9773 #define LCD_BASE_PTRS { LCD }
\r
9774 /** Interrupt vectors for the LCD peripheral type */
\r
9775 #define LCD_IRQS { LCD_IRQn }
\r
9779 */ /* end of group LCD_Peripheral_Access_Layer */
\r
9782 /* ----------------------------------------------------------------------------
\r
9783 -- MRT Peripheral Access Layer
\r
9784 ---------------------------------------------------------------------------- */
\r
9787 * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer
\r
9791 /** MRT - Register Layout Typedef */
\r
9793 struct { /* offset: 0x0, array step: 0x10 */
\r
9794 __IO uint32_t INTVAL; /**< MRT Time interval value register. This value is loaded into the TIMER register., array offset: 0x0, array step: 0x10 */
\r
9795 __I uint32_t TIMER; /**< MRT Timer register. This register reads the value of the down-counter., array offset: 0x4, array step: 0x10 */
\r
9796 __IO uint32_t CTRL; /**< MRT Control register. This register controls the MRT modes., array offset: 0x8, array step: 0x10 */
\r
9797 __IO uint32_t STAT; /**< MRT Status register., array offset: 0xC, array step: 0x10 */
\r
9799 uint8_t RESERVED_0[176];
\r
9800 __IO uint32_t MODCFG; /**< Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature., offset: 0xF0 */
\r
9801 __I uint32_t IDLE_CH; /**< Idle channel register. This register returns the number of the first idle channel., offset: 0xF4 */
\r
9802 __IO uint32_t IRQ_FLAG; /**< Global interrupt flag register, offset: 0xF8 */
\r
9805 /* ----------------------------------------------------------------------------
\r
9806 -- MRT Register Masks
\r
9807 ---------------------------------------------------------------------------- */
\r
9810 * @addtogroup MRT_Register_Masks MRT Register Masks
\r
9814 /*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */
\r
9816 #define MRT_CHANNEL_INTVAL_IVALUE_MASK (0xFFFFFFU)
\r
9817 #define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U)
\r
9818 /*! IVALUE - Time interval load value. This value is loaded into the TIMERn register and the MRT
\r
9819 * channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to
\r
9820 * this bit field starts the timer immediately. If the timer is running, writing a zero to this
\r
9821 * bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer
\r
9822 * stops at the end of the time interval.
\r
9824 #define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK)
\r
9825 #define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U)
\r
9826 #define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U)
\r
9827 /*! LOAD - Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register.
\r
9828 * This bit is write-only. Reading this bit always returns 0.
\r
9829 * 0b0..No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the
\r
9830 * time interval if the repeat mode is selected.
\r
9831 * 0b1..Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running.
\r
9833 #define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK)
\r
9836 /* The count of MRT_CHANNEL_INTVAL */
\r
9837 #define MRT_CHANNEL_INTVAL_COUNT (4U)
\r
9839 /*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */
\r
9841 #define MRT_CHANNEL_TIMER_VALUE_MASK (0xFFFFFFU)
\r
9842 #define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U)
\r
9843 /*! VALUE - Holds the current timer value of the down-counter. The initial value of the TIMERn
\r
9844 * register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval
\r
9845 * or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn
\r
9846 * register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields
\r
9847 * returns -1 (0x00FF FFFF).
\r
9849 #define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK)
\r
9852 /* The count of MRT_CHANNEL_TIMER */
\r
9853 #define MRT_CHANNEL_TIMER_COUNT (4U)
\r
9855 /*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */
\r
9857 #define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U)
\r
9858 #define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U)
\r
9859 /*! INTEN - Enable the TIMERn interrupt.
\r
9860 * 0b0..Disabled. TIMERn interrupt is disabled.
\r
9861 * 0b1..Enabled. TIMERn interrupt is enabled.
\r
9863 #define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK)
\r
9864 #define MRT_CHANNEL_CTRL_MODE_MASK (0x6U)
\r
9865 #define MRT_CHANNEL_CTRL_MODE_SHIFT (1U)
\r
9866 /*! MODE - Selects timer mode.
\r
9867 * 0b00..Repeat interrupt mode.
\r
9868 * 0b01..One-shot interrupt mode.
\r
9869 * 0b10..One-shot stall mode.
\r
9872 #define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK)
\r
9875 /* The count of MRT_CHANNEL_CTRL */
\r
9876 #define MRT_CHANNEL_CTRL_COUNT (4U)
\r
9878 /*! @name CHANNEL_STAT - MRT Status register. */
\r
9880 #define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U)
\r
9881 #define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U)
\r
9882 /*! INTFLAG - Monitors the interrupt flag.
\r
9883 * 0b0..No pending interrupt. Writing a zero is equivalent to no operation.
\r
9884 * 0b1..Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If
\r
9885 * the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt
\r
9886 * are raised. Writing a 1 to this bit clears the interrupt request.
\r
9888 #define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK)
\r
9889 #define MRT_CHANNEL_STAT_RUN_MASK (0x2U)
\r
9890 #define MRT_CHANNEL_STAT_RUN_SHIFT (1U)
\r
9891 /*! RUN - Indicates the state of TIMERn. This bit is read-only.
\r
9892 * 0b0..Idle state. TIMERn is stopped.
\r
9893 * 0b1..Running. TIMERn is running.
\r
9895 #define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK)
\r
9896 #define MRT_CHANNEL_STAT_INUSE_MASK (0x4U)
\r
9897 #define MRT_CHANNEL_STAT_INUSE_SHIFT (2U)
\r
9898 /*! INUSE - Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG
\r
9899 * register, and affects the use of IDLE_CH. See Idle channel register for details of the two operating
\r
9901 * 0b0..This channel is not in use.
\r
9902 * 0b1..This channel is in use.
\r
9904 #define MRT_CHANNEL_STAT_INUSE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK)
\r
9907 /* The count of MRT_CHANNEL_STAT */
\r
9908 #define MRT_CHANNEL_STAT_COUNT (4U)
\r
9910 /*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. */
\r
9912 #define MRT_MODCFG_NOC_MASK (0xFU)
\r
9913 #define MRT_MODCFG_NOC_SHIFT (0U)
\r
9914 /*! NOC - Identifies the number of channels in this MRT.(4 channels on this device.)
\r
9916 #define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK)
\r
9917 #define MRT_MODCFG_NOB_MASK (0x1F0U)
\r
9918 #define MRT_MODCFG_NOB_SHIFT (4U)
\r
9919 /*! NOB - Identifies the number of timer bits in this MRT. (24 bits wide on this device.)
\r
9921 #define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK)
\r
9922 #define MRT_MODCFG_MULTITASK_MASK (0x80000000U)
\r
9923 #define MRT_MODCFG_MULTITASK_SHIFT (31U)
\r
9924 /*! MULTITASK - Selects the operating mode for the INUSE flags and the IDLE_CH register.
\r
9925 * 0b0..Hardware status mode. In this mode, the INUSE(n) flags for all channels are reset.
\r
9926 * 0b1..Multi-task mode.
\r
9928 #define MRT_MODCFG_MULTITASK(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK)
\r
9931 /*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */
\r
9933 #define MRT_IDLE_CH_CHAN_MASK (0xF0U)
\r
9934 #define MRT_IDLE_CH_CHAN_SHIFT (4U)
\r
9935 /*! CHAN - Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is
\r
9936 * positioned such that it can be used as an offset from the MRT base address in order to access
\r
9937 * the registers for the allocated channel. If all timer channels are running, CHAN = 0xF. See
\r
9938 * text above for more details.
\r
9940 #define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK)
\r
9943 /*! @name IRQ_FLAG - Global interrupt flag register */
\r
9945 #define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U)
\r
9946 #define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U)
\r
9947 /*! GFLAG0 - Monitors the interrupt flag of TIMER0.
\r
9948 * 0b0..No pending interrupt. Writing a zero is equivalent to no operation.
\r
9949 * 0b1..Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If
\r
9950 * the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global
\r
9951 * interrupt are raised. Writing a 1 to this bit clears the interrupt request.
\r
9953 #define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK)
\r
9954 #define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U)
\r
9955 #define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U)
\r
9956 /*! GFLAG1 - Monitors the interrupt flag of TIMER1. See description of channel 0.
\r
9958 #define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK)
\r
9959 #define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U)
\r
9960 #define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U)
\r
9961 /*! GFLAG2 - Monitors the interrupt flag of TIMER2. See description of channel 0.
\r
9963 #define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK)
\r
9964 #define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U)
\r
9965 #define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U)
\r
9966 /*! GFLAG3 - Monitors the interrupt flag of TIMER3. See description of channel 0.
\r
9968 #define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK)
\r
9974 */ /* end of group MRT_Register_Masks */
\r
9977 /* MRT - Peripheral instance base addresses */
\r
9978 /** Peripheral MRT0 base address */
\r
9979 #define MRT0_BASE (0x4000D000u)
\r
9980 /** Peripheral MRT0 base pointer */
\r
9981 #define MRT0 ((MRT_Type *)MRT0_BASE)
\r
9982 /** Array initializer of MRT peripheral base addresses */
\r
9983 #define MRT_BASE_ADDRS { MRT0_BASE }
\r
9984 /** Array initializer of MRT peripheral base pointers */
\r
9985 #define MRT_BASE_PTRS { MRT0 }
\r
9986 /** Interrupt vectors for the MRT peripheral type */
\r
9987 #define MRT_IRQS { MRT0_IRQn }
\r
9991 */ /* end of group MRT_Peripheral_Access_Layer */
\r
9994 /* ----------------------------------------------------------------------------
\r
9995 -- OTPC Peripheral Access Layer
\r
9996 ---------------------------------------------------------------------------- */
\r
9999 * @addtogroup OTPC_Peripheral_Access_Layer OTPC Peripheral Access Layer
\r
10003 /** OTPC - Register Layout Typedef */
\r
10005 uint8_t RESERVED_0[16];
\r
10006 __I uint32_t AESKEY[8]; /**< Register for reading the AES key., array offset: 0x10, array step: 0x4 */
\r
10007 __I uint32_t ECRP; /**< ECRP options., offset: 0x30 */
\r
10008 uint8_t RESERVED_1[4];
\r
10009 __I uint32_t USER0; /**< User application specific options., offset: 0x38 */
\r
10010 __I uint32_t USER1; /**< User application specific options., offset: 0x3C */
\r
10013 /* ----------------------------------------------------------------------------
\r
10014 -- OTPC Register Masks
\r
10015 ---------------------------------------------------------------------------- */
\r
10018 * @addtogroup OTPC_Register_Masks OTPC Register Masks
\r
10022 /*! @name AESKEY - Register for reading the AES key. */
\r
10024 #define OTPC_AESKEY_KEY_MASK (0xFFFFFFFFU)
\r
10025 #define OTPC_AESKEY_KEY_SHIFT (0U)
\r
10026 /*! KEY - AES key.
\r
10028 #define OTPC_AESKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << OTPC_AESKEY_KEY_SHIFT)) & OTPC_AESKEY_KEY_MASK)
\r
10031 /* The count of OTPC_AESKEY */
\r
10032 #define OTPC_AESKEY_COUNT (8U)
\r
10034 /*! @name ECRP - ECRP options. */
\r
10036 #define OTPC_ECRP_CRP_MASS_ERASE_DISABLE_MASK (0x10U)
\r
10037 #define OTPC_ECRP_CRP_MASS_ERASE_DISABLE_SHIFT (4U)
\r
10038 /*! CRP_MASS_ERASE_DISABLE - Disable or enable CRP mass erase.
\r
10040 #define OTPC_ECRP_CRP_MASS_ERASE_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_MASS_ERASE_DISABLE_SHIFT)) & OTPC_ECRP_CRP_MASS_ERASE_DISABLE_MASK)
\r
10041 #define OTPC_ECRP_IAP_PROTECTION_ENABLE_MASK (0x20U)
\r
10042 #define OTPC_ECRP_IAP_PROTECTION_ENABLE_SHIFT (5U)
\r
10043 /*! IAP_PROTECTION_ENABLE - This bit controls the ability to enable checking for ECRP in IAP functions.
\r
10045 #define OTPC_ECRP_IAP_PROTECTION_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_IAP_PROTECTION_ENABLE_SHIFT)) & OTPC_ECRP_IAP_PROTECTION_ENABLE_MASK)
\r
10046 #define OTPC_ECRP_CRP_ISP_DISABLE_PIN_MASK (0x40U)
\r
10047 #define OTPC_ECRP_CRP_ISP_DISABLE_PIN_SHIFT (6U)
\r
10048 /*! CRP_ISP_DISABLE_PIN - This bit controls the ability to enter ISP mode using the ISP pin.
\r
10050 #define OTPC_ECRP_CRP_ISP_DISABLE_PIN(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_ISP_DISABLE_PIN_SHIFT)) & OTPC_ECRP_CRP_ISP_DISABLE_PIN_MASK)
\r
10051 #define OTPC_ECRP_CRP_ISP_DISABLE_IAP_MASK (0x80U)
\r
10052 #define OTPC_ECRP_CRP_ISP_DISABLE_IAP_SHIFT (7U)
\r
10053 /*! CRP_ISP_DISABLE_IAP - This bit controls the ability to re-invoke ISP using IAP routines.
\r
10055 #define OTPC_ECRP_CRP_ISP_DISABLE_IAP(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_ISP_DISABLE_IAP_SHIFT)) & OTPC_ECRP_CRP_ISP_DISABLE_IAP_MASK)
\r
10056 #define OTPC_ECRP_CRP_ALLOW_ZERO_MASK (0x200U)
\r
10057 #define OTPC_ECRP_CRP_ALLOW_ZERO_SHIFT (9U)
\r
10058 /*! CRP_ALLOW_ZERO - This bit controls how 0 is treated when read as a ECRP value..
\r
10060 #define OTPC_ECRP_CRP_ALLOW_ZERO(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_ALLOW_ZERO_SHIFT)) & OTPC_ECRP_CRP_ALLOW_ZERO_MASK)
\r
10061 #define OTPC_ECRP_JTAG_DISABLE_MASK (0x80000000U)
\r
10062 #define OTPC_ECRP_JTAG_DISABLE_SHIFT (31U)
\r
10063 /*! JTAG_DISABLE - 0 => Enable SWD/JTAG; 1 => Disable SWD/JTAG..
\r
10065 #define OTPC_ECRP_JTAG_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_JTAG_DISABLE_SHIFT)) & OTPC_ECRP_JTAG_DISABLE_MASK)
\r
10068 /*! @name USER0 - User application specific options. */
\r
10070 #define OTPC_USER0_USER0_MASK (0xFFFFFFFFU)
\r
10071 #define OTPC_USER0_USER0_SHIFT (0U)
\r
10072 /*! USER0 - User application specific option.
\r
10074 #define OTPC_USER0_USER0(x) (((uint32_t)(((uint32_t)(x)) << OTPC_USER0_USER0_SHIFT)) & OTPC_USER0_USER0_MASK)
\r
10077 /*! @name USER1 - User application specific options. */
\r
10079 #define OTPC_USER1_USER1_MASK (0xFFFFFFFFU)
\r
10080 #define OTPC_USER1_USER1_SHIFT (0U)
\r
10081 /*! USER1 - User application specific option.
\r
10083 #define OTPC_USER1_USER1(x) (((uint32_t)(((uint32_t)(x)) << OTPC_USER1_USER1_SHIFT)) & OTPC_USER1_USER1_MASK)
\r
10089 */ /* end of group OTPC_Register_Masks */
\r
10092 /* OTPC - Peripheral instance base addresses */
\r
10093 /** Peripheral OTPC base address */
\r
10094 #define OTPC_BASE (0x40015000u)
\r
10095 /** Peripheral OTPC base pointer */
\r
10096 #define OTPC ((OTPC_Type *)OTPC_BASE)
\r
10097 /** Array initializer of OTPC peripheral base addresses */
\r
10098 #define OTPC_BASE_ADDRS { OTPC_BASE }
\r
10099 /** Array initializer of OTPC peripheral base pointers */
\r
10100 #define OTPC_BASE_PTRS { OTPC }
\r
10104 */ /* end of group OTPC_Peripheral_Access_Layer */
\r
10107 /* ----------------------------------------------------------------------------
\r
10108 -- PINT Peripheral Access Layer
\r
10109 ---------------------------------------------------------------------------- */
\r
10112 * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer
\r
10116 /** PINT - Register Layout Typedef */
\r
10118 __IO uint32_t ISEL; /**< Pin Interrupt Mode register, offset: 0x0 */
\r
10119 __IO uint32_t IENR; /**< Pin interrupt level or rising edge interrupt enable register, offset: 0x4 */
\r
10120 __O uint32_t SIENR; /**< Pin interrupt level or rising edge interrupt set register, offset: 0x8 */
\r
10121 __O uint32_t CIENR; /**< Pin interrupt level (rising edge interrupt) clear register, offset: 0xC */
\r
10122 __IO uint32_t IENF; /**< Pin interrupt active level or falling edge interrupt enable register, offset: 0x10 */
\r
10123 __O uint32_t SIENF; /**< Pin interrupt active level or falling edge interrupt set register, offset: 0x14 */
\r
10124 __O uint32_t CIENF; /**< Pin interrupt active level or falling edge interrupt clear register, offset: 0x18 */
\r
10125 __IO uint32_t RISE; /**< Pin interrupt rising edge register, offset: 0x1C */
\r
10126 __IO uint32_t FALL; /**< Pin interrupt falling edge register, offset: 0x20 */
\r
10127 __IO uint32_t IST; /**< Pin interrupt status register, offset: 0x24 */
\r
10128 __IO uint32_t PMCTRL; /**< Pattern match interrupt control register, offset: 0x28 */
\r
10129 __IO uint32_t PMSRC; /**< Pattern match interrupt bit-slice source register, offset: 0x2C */
\r
10130 __IO uint32_t PMCFG; /**< Pattern match interrupt bit slice configuration register, offset: 0x30 */
\r
10133 /* ----------------------------------------------------------------------------
\r
10134 -- PINT Register Masks
\r
10135 ---------------------------------------------------------------------------- */
\r
10138 * @addtogroup PINT_Register_Masks PINT Register Masks
\r
10142 /*! @name ISEL - Pin Interrupt Mode register */
\r
10144 #define PINT_ISEL_PMODE_MASK (0xFFU)
\r
10145 #define PINT_ISEL_PMODE_SHIFT (0U)
\r
10146 /*! PMODE - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt
\r
10147 * selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive
\r
10149 #define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK)
\r
10152 /*! @name IENR - Pin interrupt level or rising edge interrupt enable register */
\r
10154 #define PINT_IENR_ENRL_MASK (0xFFU)
\r
10155 #define PINT_IENR_ENRL_SHIFT (0U)
\r
10156 /*! ENRL - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the
\r
10157 * pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable
\r
10158 * rising edge or level interrupt.
\r
10160 #define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK)
\r
10163 /*! @name SIENR - Pin interrupt level or rising edge interrupt set register */
\r
10165 #define PINT_SIENR_SETENRL_MASK (0xFFU)
\r
10166 #define PINT_SIENR_SETENRL_SHIFT (0U)
\r
10167 /*! SETENRL - Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n
\r
10168 * sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt.
\r
10170 #define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK)
\r
10173 /*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */
\r
10175 #define PINT_CIENR_CENRL_MASK (0xFFU)
\r
10176 #define PINT_CIENR_CENRL_SHIFT (0U)
\r
10177 /*! CENRL - Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit
\r
10178 * n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level
\r
10181 #define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK)
\r
10184 /*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */
\r
10186 #define PINT_IENF_ENAF_MASK (0xFFU)
\r
10187 #define PINT_IENF_ENAF_SHIFT (0U)
\r
10188 /*! ENAF - Enables the falling edge or configures the active level interrupt for each pin interrupt.
\r
10189 * Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt
\r
10190 * or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active
\r
10191 * interrupt level HIGH.
\r
10193 #define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK)
\r
10196 /*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */
\r
10198 #define PINT_SIENF_SETENAF_MASK (0xFFU)
\r
10199 #define PINT_SIENF_SETENAF_SHIFT (0U)
\r
10200 /*! SETENAF - Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n
\r
10201 * sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable
\r
10202 * falling edge interrupt.
\r
10204 #define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK)
\r
10207 /*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */
\r
10209 #define PINT_CIENF_CENAF_MASK (0xFFU)
\r
10210 #define PINT_CIENF_CENAF_SHIFT (0U)
\r
10211 /*! CENAF - Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n
\r
10212 * clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or
\r
10213 * falling edge interrupt disabled.
\r
10215 #define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK)
\r
10218 /*! @name RISE - Pin interrupt rising edge register */
\r
10220 #define PINT_RISE_RDET_MASK (0xFFU)
\r
10221 #define PINT_RISE_RDET_SHIFT (0U)
\r
10222 /*! RDET - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read
\r
10223 * 0: No rising edge has been detected on this pin since Reset or the last time a one was written
\r
10224 * to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the
\r
10225 * last time a one was written to this bit. Write 1: clear rising edge detection for this pin.
\r
10227 #define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK)
\r
10230 /*! @name FALL - Pin interrupt falling edge register */
\r
10232 #define PINT_FALL_FDET_MASK (0xFFU)
\r
10233 #define PINT_FALL_FDET_SHIFT (0U)
\r
10234 /*! FDET - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read
\r
10235 * 0: No falling edge has been detected on this pin since Reset or the last time a one was
\r
10236 * written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or
\r
10237 * the last time a one was written to this bit. Write 1: clear falling edge detection for this
\r
10240 #define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK)
\r
10243 /*! @name IST - Pin interrupt status register */
\r
10245 #define PINT_IST_PSTAT_MASK (0xFFU)
\r
10246 #define PINT_IST_PSTAT_SHIFT (0U)
\r
10247 /*! PSTAT - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts
\r
10248 * the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for
\r
10249 * this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this
\r
10250 * interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin.
\r
10251 * Write 1 (level-sensitive): switch the active level for this pin (in the IENF register).
\r
10253 #define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK)
\r
10256 /*! @name PMCTRL - Pattern match interrupt control register */
\r
10258 #define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U)
\r
10259 #define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U)
\r
10260 /*! SEL_PMATCH - Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function.
\r
10261 * 0b0..Pin interrupt. Interrupts are driven in response to the standard pin interrupt function.
\r
10262 * 0b1..Pattern match. Interrupts are driven in response to pattern matches.
\r
10264 #define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK)
\r
10265 #define PINT_PMCTRL_ENA_RXEV_MASK (0x2U)
\r
10266 #define PINT_PMCTRL_ENA_RXEV_SHIFT (1U)
\r
10267 /*! ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true.
\r
10268 * 0b0..Disabled. RXEV output to the CPU is disabled.
\r
10269 * 0b1..Enabled. RXEV output to the CPU is enabled.
\r
10271 #define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK)
\r
10272 #define PINT_PMCTRL_PMAT_MASK (0xFF000000U)
\r
10273 #define PINT_PMCTRL_PMAT_SHIFT (24U)
\r
10274 /*! PMAT - This field displays the current state of pattern matches. A 1 in any bit of this field
\r
10275 * indicates that the corresponding product term is matched by the current state of the appropriate
\r
10278 #define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK)
\r
10281 /*! @name PMSRC - Pattern match interrupt bit-slice source register */
\r
10283 #define PINT_PMSRC_SRC0_MASK (0x700U)
\r
10284 #define PINT_PMSRC_SRC0_SHIFT (8U)
\r
10285 /*! SRC0 - Selects the input source for bit slice 0
\r
10286 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0.
\r
10287 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 0.
\r
10288 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 0.
\r
10289 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 0.
\r
10290 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 0.
\r
10291 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 0.
\r
10292 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 0.
\r
10293 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0.
\r
10295 #define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK)
\r
10296 #define PINT_PMSRC_SRC1_MASK (0x3800U)
\r
10297 #define PINT_PMSRC_SRC1_SHIFT (11U)
\r
10298 /*! SRC1 - Selects the input source for bit slice 1
\r
10299 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1.
\r
10300 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 1.
\r
10301 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 1.
\r
10302 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 1.
\r
10303 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 1.
\r
10304 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 1.
\r
10305 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 1.
\r
10306 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1.
\r
10308 #define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK)
\r
10309 #define PINT_PMSRC_SRC2_MASK (0x1C000U)
\r
10310 #define PINT_PMSRC_SRC2_SHIFT (14U)
\r
10311 /*! SRC2 - Selects the input source for bit slice 2
\r
10312 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2.
\r
10313 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 2.
\r
10314 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 2.
\r
10315 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 2.
\r
10316 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 2.
\r
10317 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 2.
\r
10318 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 2.
\r
10319 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2.
\r
10321 #define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK)
\r
10322 #define PINT_PMSRC_SRC3_MASK (0xE0000U)
\r
10323 #define PINT_PMSRC_SRC3_SHIFT (17U)
\r
10324 /*! SRC3 - Selects the input source for bit slice 3
\r
10325 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 3.
\r
10326 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 3.
\r
10327 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 3.
\r
10328 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 3.
\r
10329 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 3.
\r
10330 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 3.
\r
10331 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 3.
\r
10332 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3.
\r
10334 #define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK)
\r
10335 #define PINT_PMSRC_SRC4_MASK (0x700000U)
\r
10336 #define PINT_PMSRC_SRC4_SHIFT (20U)
\r
10337 /*! SRC4 - Selects the input source for bit slice 4
\r
10338 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4.
\r
10339 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 4.
\r
10340 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 4.
\r
10341 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 4.
\r
10342 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 4.
\r
10343 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 4.
\r
10344 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 4.
\r
10345 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4.
\r
10347 #define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK)
\r
10348 #define PINT_PMSRC_SRC5_MASK (0x3800000U)
\r
10349 #define PINT_PMSRC_SRC5_SHIFT (23U)
\r
10350 /*! SRC5 - Selects the input source for bit slice 5
\r
10351 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5.
\r
10352 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5.
\r
10353 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 5.
\r
10354 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 5.
\r
10355 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 5.
\r
10356 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 5.
\r
10357 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 5.
\r
10358 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5.
\r
10360 #define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK)
\r
10361 #define PINT_PMSRC_SRC6_MASK (0x1C000000U)
\r
10362 #define PINT_PMSRC_SRC6_SHIFT (26U)
\r
10363 /*! SRC6 - Selects the input source for bit slice 6
\r
10364 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6.
\r
10365 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 6.
\r
10366 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 6.
\r
10367 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 6.
\r
10368 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 6.
\r
10369 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 6.
\r
10370 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 6.
\r
10371 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6.
\r
10373 #define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK)
\r
10374 #define PINT_PMSRC_SRC7_MASK (0xE0000000U)
\r
10375 #define PINT_PMSRC_SRC7_SHIFT (29U)
\r
10376 /*! SRC7 - Selects the input source for bit slice 7
\r
10377 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 7.
\r
10378 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 7.
\r
10379 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 7.
\r
10380 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 7.
\r
10381 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 7.
\r
10382 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 7.
\r
10383 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 7.
\r
10384 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 7.
\r
10386 #define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK)
\r
10389 /*! @name PMCFG - Pattern match interrupt bit slice configuration register */
\r
10391 #define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U)
\r
10392 #define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U)
\r
10393 /*! PROD_ENDPTS0 - Determines whether slice 0 is an endpoint.
\r
10394 * 0b0..No effect. Slice 0 is not an endpoint.
\r
10395 * 0b1..endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true.
\r
10397 #define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK)
\r
10398 #define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U)
\r
10399 #define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U)
\r
10400 /*! PROD_ENDPTS1 - Determines whether slice 1 is an endpoint.
\r
10401 * 0b0..No effect. Slice 1 is not an endpoint.
\r
10402 * 0b1..endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true.
\r
10404 #define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK)
\r
10405 #define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U)
\r
10406 #define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U)
\r
10407 /*! PROD_ENDPTS2 - Determines whether slice 2 is an endpoint.
\r
10408 * 0b0..No effect. Slice 2 is not an endpoint.
\r
10409 * 0b1..endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true.
\r
10411 #define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK)
\r
10412 #define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U)
\r
10413 #define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U)
\r
10414 /*! PROD_ENDPTS3 - Determines whether slice 3 is an endpoint.
\r
10415 * 0b0..No effect. Slice 3 is not an endpoint.
\r
10416 * 0b1..endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true.
\r
10418 #define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK)
\r
10419 #define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U)
\r
10420 #define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U)
\r
10421 /*! PROD_ENDPTS4 - Determines whether slice 4 is an endpoint.
\r
10422 * 0b0..No effect. Slice 4 is not an endpoint.
\r
10423 * 0b1..endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true.
\r
10425 #define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK)
\r
10426 #define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U)
\r
10427 #define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U)
\r
10428 /*! PROD_ENDPTS5 - Determines whether slice 5 is an endpoint.
\r
10429 * 0b0..No effect. Slice 5 is not an endpoint.
\r
10430 * 0b1..endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true.
\r
10432 #define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK)
\r
10433 #define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U)
\r
10434 #define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U)
\r
10435 /*! PROD_ENDPTS6 - Determines whether slice 6 is an endpoint.
\r
10436 * 0b0..No effect. Slice 6 is not an endpoint.
\r
10437 * 0b1..endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true.
\r
10439 #define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK)
\r
10440 #define PINT_PMCFG_CFG0_MASK (0x700U)
\r
10441 #define PINT_PMCFG_CFG0_SHIFT (8U)
\r
10442 /*! CFG0 - Specifies the match contribution condition for bit slice 0.
\r
10443 * 0b000..Constant HIGH. This bit slice always contributes to a product term match.
\r
10444 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
\r
10445 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
\r
10446 * PMSRC registers are written to.
\r
10447 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
\r
10448 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
\r
10449 * PMSRC registers are written to.
\r
10450 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
\r
10451 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
\r
10452 * cleared when the PMCFG or the PMSRC registers are written to.
\r
10453 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
\r
10454 * 0b101..Low level. Match occurs when there is a low level on the specified input.
\r
10455 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
\r
10456 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
\r
10457 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
\r
10458 * is cleared after one clock cycle.
\r
10460 #define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK)
\r
10461 #define PINT_PMCFG_CFG1_MASK (0x3800U)
\r
10462 #define PINT_PMCFG_CFG1_SHIFT (11U)
\r
10463 /*! CFG1 - Specifies the match contribution condition for bit slice 1.
\r
10464 * 0b000..Constant HIGH. This bit slice always contributes to a product term match.
\r
10465 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
\r
10466 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
\r
10467 * PMSRC registers are written to.
\r
10468 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
\r
10469 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
\r
10470 * PMSRC registers are written to.
\r
10471 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
\r
10472 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
\r
10473 * cleared when the PMCFG or the PMSRC registers are written to.
\r
10474 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
\r
10475 * 0b101..Low level. Match occurs when there is a low level on the specified input.
\r
10476 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
\r
10477 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
\r
10478 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
\r
10479 * is cleared after one clock cycle.
\r
10481 #define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK)
\r
10482 #define PINT_PMCFG_CFG2_MASK (0x1C000U)
\r
10483 #define PINT_PMCFG_CFG2_SHIFT (14U)
\r
10484 /*! CFG2 - Specifies the match contribution condition for bit slice 2.
\r
10485 * 0b000..Constant HIGH. This bit slice always contributes to a product term match.
\r
10486 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
\r
10487 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
\r
10488 * PMSRC registers are written to.
\r
10489 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
\r
10490 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
\r
10491 * PMSRC registers are written to.
\r
10492 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
\r
10493 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
\r
10494 * cleared when the PMCFG or the PMSRC registers are written to.
\r
10495 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
\r
10496 * 0b101..Low level. Match occurs when there is a low level on the specified input.
\r
10497 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
\r
10498 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
\r
10499 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
\r
10500 * is cleared after one clock cycle.
\r
10502 #define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK)
\r
10503 #define PINT_PMCFG_CFG3_MASK (0xE0000U)
\r
10504 #define PINT_PMCFG_CFG3_SHIFT (17U)
\r
10505 /*! CFG3 - Specifies the match contribution condition for bit slice 3.
\r
10506 * 0b000..Constant HIGH. This bit slice always contributes to a product term match.
\r
10507 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
\r
10508 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
\r
10509 * PMSRC registers are written to.
\r
10510 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
\r
10511 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
\r
10512 * PMSRC registers are written to.
\r
10513 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
\r
10514 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
\r
10515 * cleared when the PMCFG or the PMSRC registers are written to.
\r
10516 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
\r
10517 * 0b101..Low level. Match occurs when there is a low level on the specified input.
\r
10518 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
\r
10519 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
\r
10520 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
\r
10521 * is cleared after one clock cycle.
\r
10523 #define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK)
\r
10524 #define PINT_PMCFG_CFG4_MASK (0x700000U)
\r
10525 #define PINT_PMCFG_CFG4_SHIFT (20U)
\r
10526 /*! CFG4 - Specifies the match contribution condition for bit slice 4.
\r
10527 * 0b000..Constant HIGH. This bit slice always contributes to a product term match.
\r
10528 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
\r
10529 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
\r
10530 * PMSRC registers are written to.
\r
10531 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
\r
10532 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
\r
10533 * PMSRC registers are written to.
\r
10534 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
\r
10535 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
\r
10536 * cleared when the PMCFG or the PMSRC registers are written to.
\r
10537 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
\r
10538 * 0b101..Low level. Match occurs when there is a low level on the specified input.
\r
10539 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
\r
10540 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
\r
10541 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
\r
10542 * is cleared after one clock cycle.
\r
10544 #define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK)
\r
10545 #define PINT_PMCFG_CFG5_MASK (0x3800000U)
\r
10546 #define PINT_PMCFG_CFG5_SHIFT (23U)
\r
10547 /*! CFG5 - Specifies the match contribution condition for bit slice 5.
\r
10548 * 0b000..Constant HIGH. This bit slice always contributes to a product term match.
\r
10549 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
\r
10550 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
\r
10551 * PMSRC registers are written to.
\r
10552 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
\r
10553 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
\r
10554 * PMSRC registers are written to.
\r
10555 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
\r
10556 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
\r
10557 * cleared when the PMCFG or the PMSRC registers are written to.
\r
10558 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
\r
10559 * 0b101..Low level. Match occurs when there is a low level on the specified input.
\r
10560 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
\r
10561 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
\r
10562 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
\r
10563 * is cleared after one clock cycle.
\r
10565 #define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK)
\r
10566 #define PINT_PMCFG_CFG6_MASK (0x1C000000U)
\r
10567 #define PINT_PMCFG_CFG6_SHIFT (26U)
\r
10568 /*! CFG6 - Specifies the match contribution condition for bit slice 6.
\r
10569 * 0b000..Constant HIGH. This bit slice always contributes to a product term match.
\r
10570 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
\r
10571 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
\r
10572 * PMSRC registers are written to.
\r
10573 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
\r
10574 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
\r
10575 * PMSRC registers are written to.
\r
10576 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
\r
10577 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
\r
10578 * cleared when the PMCFG or the PMSRC registers are written to.
\r
10579 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
\r
10580 * 0b101..Low level. Match occurs when there is a low level on the specified input.
\r
10581 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
\r
10582 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
\r
10583 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
\r
10584 * is cleared after one clock cycle.
\r
10586 #define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK)
\r
10587 #define PINT_PMCFG_CFG7_MASK (0xE0000000U)
\r
10588 #define PINT_PMCFG_CFG7_SHIFT (29U)
\r
10589 /*! CFG7 - Specifies the match contribution condition for bit slice 7.
\r
10590 * 0b000..Constant HIGH. This bit slice always contributes to a product term match.
\r
10591 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
\r
10592 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
\r
10593 * PMSRC registers are written to.
\r
10594 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
\r
10595 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the
\r
10596 * PMSRC registers are written to.
\r
10597 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
\r
10598 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
\r
10599 * cleared when the PMCFG or the PMSRC registers are written to.
\r
10600 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
\r
10601 * 0b101..Low level. Match occurs when there is a low level on the specified input.
\r
10602 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
\r
10603 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
\r
10604 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
\r
10605 * is cleared after one clock cycle.
\r
10607 #define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK)
\r
10613 */ /* end of group PINT_Register_Masks */
\r
10616 /* PINT - Peripheral instance base addresses */
\r
10617 /** Peripheral PINT base address */
\r
10618 #define PINT_BASE (0x40004000u)
\r
10619 /** Peripheral PINT base pointer */
\r
10620 #define PINT ((PINT_Type *)PINT_BASE)
\r
10621 /** Array initializer of PINT peripheral base addresses */
\r
10622 #define PINT_BASE_ADDRS { PINT_BASE }
\r
10623 /** Array initializer of PINT peripheral base pointers */
\r
10624 #define PINT_BASE_PTRS { PINT }
\r
10625 /** Interrupt vectors for the PINT peripheral type */
\r
10626 #define PINT_IRQS { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn }
\r
10630 */ /* end of group PINT_Peripheral_Access_Layer */
\r
10633 /* ----------------------------------------------------------------------------
\r
10634 -- RIT Peripheral Access Layer
\r
10635 ---------------------------------------------------------------------------- */
\r
10638 * @addtogroup RIT_Peripheral_Access_Layer RIT Peripheral Access Layer
\r
10642 /** RIT - Register Layout Typedef */
\r
10644 __IO uint32_t COMPVAL; /**< Compare value LSB register, offset: 0x0 */
\r
10645 __IO uint32_t MASK; /**< Mask LSB register, offset: 0x4 */
\r
10646 __IO uint32_t CTRL; /**< Control register, offset: 0x8 */
\r
10647 __IO uint32_t COUNTER; /**< Counter LSB register, offset: 0xC */
\r
10648 __IO uint32_t COMPVAL_H; /**< Compare value MSB register, offset: 0x10 */
\r
10649 __IO uint32_t MASK_H; /**< Mask MSB register, offset: 0x14 */
\r
10650 uint8_t RESERVED_0[4];
\r
10651 __IO uint32_t COUNTER_H; /**< Counter MSB register, offset: 0x1C */
\r
10654 /* ----------------------------------------------------------------------------
\r
10655 -- RIT Register Masks
\r
10656 ---------------------------------------------------------------------------- */
\r
10659 * @addtogroup RIT_Register_Masks RIT Register Masks
\r
10663 /*! @name COMPVAL - Compare value LSB register */
\r
10665 #define RIT_COMPVAL_RICOMP_MASK (0xFFFFFFFFU)
\r
10666 #define RIT_COMPVAL_RICOMP_SHIFT (0U)
\r
10669 #define RIT_COMPVAL_RICOMP(x) (((uint32_t)(((uint32_t)(x)) << RIT_COMPVAL_RICOMP_SHIFT)) & RIT_COMPVAL_RICOMP_MASK)
\r
10672 /*! @name MASK - Mask LSB register */
\r
10674 #define RIT_MASK_RIMASK_MASK (0xFFFFFFFFU)
\r
10675 #define RIT_MASK_RIMASK_SHIFT (0U)
\r
10676 /*! RIMASK - Mask register.
\r
10678 #define RIT_MASK_RIMASK(x) (((uint32_t)(((uint32_t)(x)) << RIT_MASK_RIMASK_SHIFT)) & RIT_MASK_RIMASK_MASK)
\r
10681 /*! @name CTRL - Control register */
\r
10683 #define RIT_CTRL_RITINT_MASK (0x1U)
\r
10684 #define RIT_CTRL_RITINT_SHIFT (0U)
\r
10685 /*! RITINT - Interrupt flag.
\r
10687 #define RIT_CTRL_RITINT(x) (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITINT_SHIFT)) & RIT_CTRL_RITINT_MASK)
\r
10688 #define RIT_CTRL_RITENCLR_MASK (0x2U)
\r
10689 #define RIT_CTRL_RITENCLR_SHIFT (1U)
\r
10690 /*! RITENCLR - Timer enable clear.
\r
10692 #define RIT_CTRL_RITENCLR(x) (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITENCLR_SHIFT)) & RIT_CTRL_RITENCLR_MASK)
\r
10693 #define RIT_CTRL_RITENBR_MASK (0x4U)
\r
10694 #define RIT_CTRL_RITENBR_SHIFT (2U)
\r
10695 /*! RITENBR - Timer enable for debug.
\r
10697 #define RIT_CTRL_RITENBR(x) (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITENBR_SHIFT)) & RIT_CTRL_RITENBR_MASK)
\r
10698 #define RIT_CTRL_RITEN_MASK (0x8U)
\r
10699 #define RIT_CTRL_RITEN_SHIFT (3U)
\r
10700 /*! RITEN - Timer enable.
\r
10702 #define RIT_CTRL_RITEN(x) (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITEN_SHIFT)) & RIT_CTRL_RITEN_MASK)
\r
10705 /*! @name COUNTER - Counter LSB register */
\r
10707 #define RIT_COUNTER_RICOUNTER_MASK (0xFFFFFFFFU)
\r
10708 #define RIT_COUNTER_RICOUNTER_SHIFT (0U)
\r
10709 /*! RICOUNTER - 32 LSBs of the up counter.
\r
10711 #define RIT_COUNTER_RICOUNTER(x) (((uint32_t)(((uint32_t)(x)) << RIT_COUNTER_RICOUNTER_SHIFT)) & RIT_COUNTER_RICOUNTER_MASK)
\r
10714 /*! @name COMPVAL_H - Compare value MSB register */
\r
10716 #define RIT_COMPVAL_H_RICOMP_MASK (0xFFFFU)
\r
10717 #define RIT_COMPVAL_H_RICOMP_SHIFT (0U)
\r
10718 /*! RICOMP - Compare value MSB register.
\r
10720 #define RIT_COMPVAL_H_RICOMP(x) (((uint32_t)(((uint32_t)(x)) << RIT_COMPVAL_H_RICOMP_SHIFT)) & RIT_COMPVAL_H_RICOMP_MASK)
\r
10723 /*! @name MASK_H - Mask MSB register */
\r
10725 #define RIT_MASK_H_RIMASK_MASK (0xFFFFU)
\r
10726 #define RIT_MASK_H_RIMASK_SHIFT (0U)
\r
10727 /*! RIMASK - Mask register.
\r
10729 #define RIT_MASK_H_RIMASK(x) (((uint32_t)(((uint32_t)(x)) << RIT_MASK_H_RIMASK_SHIFT)) & RIT_MASK_H_RIMASK_MASK)
\r
10732 /*! @name COUNTER_H - Counter MSB register */
\r
10734 #define RIT_COUNTER_H_RICOUNTER_MASK (0xFFFFU)
\r
10735 #define RIT_COUNTER_H_RICOUNTER_SHIFT (0U)
\r
10736 /*! RICOUNTER - 16 LSBs of the up counter.
\r
10738 #define RIT_COUNTER_H_RICOUNTER(x) (((uint32_t)(((uint32_t)(x)) << RIT_COUNTER_H_RICOUNTER_SHIFT)) & RIT_COUNTER_H_RICOUNTER_MASK)
\r
10744 */ /* end of group RIT_Register_Masks */
\r
10747 /* RIT - Peripheral instance base addresses */
\r
10748 /** Peripheral RIT base address */
\r
10749 #define RIT_BASE (0x4002D000u)
\r
10750 /** Peripheral RIT base pointer */
\r
10751 #define RIT ((RIT_Type *)RIT_BASE)
\r
10752 /** Array initializer of RIT peripheral base addresses */
\r
10753 #define RIT_BASE_ADDRS { RIT_BASE }
\r
10754 /** Array initializer of RIT peripheral base pointers */
\r
10755 #define RIT_BASE_PTRS { RIT }
\r
10756 /** Interrupt vectors for the RIT peripheral type */
\r
10757 #define RIT_IRQS { RIT_IRQn }
\r
10761 */ /* end of group RIT_Peripheral_Access_Layer */
\r
10764 /* ----------------------------------------------------------------------------
\r
10765 -- RTC Peripheral Access Layer
\r
10766 ---------------------------------------------------------------------------- */
\r
10769 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
\r
10773 /** RTC - Register Layout Typedef */
\r
10775 __IO uint32_t CTRL; /**< RTC control register, offset: 0x0 */
\r
10776 __IO uint32_t MATCH; /**< RTC match register, offset: 0x4 */
\r
10777 __IO uint32_t COUNT; /**< RTC counter register, offset: 0x8 */
\r
10778 __IO uint32_t WAKE; /**< High-resolution/wake-up timer control register, offset: 0xC */
\r
10779 uint8_t RESERVED_0[48];
\r
10780 __IO uint32_t GPREG[8]; /**< General Purpose register, array offset: 0x40, array step: 0x4 */
\r
10783 /* ----------------------------------------------------------------------------
\r
10784 -- RTC Register Masks
\r
10785 ---------------------------------------------------------------------------- */
\r
10788 * @addtogroup RTC_Register_Masks RTC Register Masks
\r
10792 /*! @name CTRL - RTC control register */
\r
10794 #define RTC_CTRL_SWRESET_MASK (0x1U)
\r
10795 #define RTC_CTRL_SWRESET_SHIFT (0U)
\r
10796 /*! SWRESET - Software reset control
\r
10797 * 0b0..Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any operation of the RTC.
\r
10798 * 0b1..In reset. The RTC is held in reset. All register bits within the RTC will be forced to their reset value
\r
10799 * except the OFD bit. This bit must be cleared before writing to any register in the RTC - including writes
\r
10800 * to set any of the other bits within this register. Do not attempt to write to any bits of this register at
\r
10801 * the same time that the reset bit is being cleared.
\r
10803 #define RTC_CTRL_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SWRESET_SHIFT)) & RTC_CTRL_SWRESET_MASK)
\r
10804 #define RTC_CTRL_ALARM1HZ_MASK (0x4U)
\r
10805 #define RTC_CTRL_ALARM1HZ_SHIFT (2U)
\r
10806 /*! ALARM1HZ - RTC 1 Hz timer alarm flag status.
\r
10807 * 0b0..No match. No match has occurred on the 1 Hz RTC timer. Writing a 0 has no effect.
\r
10808 * 0b1..Match. A match condition has occurred on the 1 Hz RTC timer. This flag generates an RTC alarm interrupt
\r
10809 * request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit.
\r
10811 #define RTC_CTRL_ALARM1HZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARM1HZ_SHIFT)) & RTC_CTRL_ALARM1HZ_MASK)
\r
10812 #define RTC_CTRL_WAKE1KHZ_MASK (0x8U)
\r
10813 #define RTC_CTRL_WAKE1KHZ_SHIFT (3U)
\r
10814 /*! WAKE1KHZ - RTC 1 kHz timer wake-up flag status.
\r
10815 * 0b0..Run. The RTC 1 kHz timer is running. Writing a 0 has no effect.
\r
10816 * 0b1..Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up
\r
10817 * interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit.
\r
10819 #define RTC_CTRL_WAKE1KHZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKE1KHZ_SHIFT)) & RTC_CTRL_WAKE1KHZ_MASK)
\r
10820 #define RTC_CTRL_ALARMDPD_EN_MASK (0x10U)
\r
10821 #define RTC_CTRL_ALARMDPD_EN_SHIFT (4U)
\r
10822 /*! ALARMDPD_EN - RTC 1 Hz timer alarm enable for Deep power-down.
\r
10823 * 0b0..Disable. A match on the 1 Hz RTC timer will not bring the part out of Deep power-down mode.
\r
10824 * 0b1..Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode.
\r
10826 #define RTC_CTRL_ALARMDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARMDPD_EN_SHIFT)) & RTC_CTRL_ALARMDPD_EN_MASK)
\r
10827 #define RTC_CTRL_WAKEDPD_EN_MASK (0x20U)
\r
10828 #define RTC_CTRL_WAKEDPD_EN_SHIFT (5U)
\r
10829 /*! WAKEDPD_EN - RTC 1 kHz timer wake-up enable for Deep power-down.
\r
10830 * 0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode.
\r
10831 * 0b1..Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mode.
\r
10833 #define RTC_CTRL_WAKEDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKEDPD_EN_SHIFT)) & RTC_CTRL_WAKEDPD_EN_MASK)
\r
10834 #define RTC_CTRL_RTC1KHZ_EN_MASK (0x40U)
\r
10835 #define RTC_CTRL_RTC1KHZ_EN_SHIFT (6U)
\r
10836 /*! RTC1KHZ_EN - RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz
\r
10837 * timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0).
\r
10838 * 0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode.
\r
10839 * 0b1..Enable. The 1 kHz RTC timer is enabled.
\r
10841 #define RTC_CTRL_RTC1KHZ_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC1KHZ_EN_SHIFT)) & RTC_CTRL_RTC1KHZ_EN_MASK)
\r
10842 #define RTC_CTRL_RTC_EN_MASK (0x80U)
\r
10843 #define RTC_CTRL_RTC_EN_SHIFT (7U)
\r
10844 /*! RTC_EN - RTC enable.
\r
10845 * 0b0..Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. This bit should
\r
10846 * be 0 when writing to load a value in the RTC counter register.
\r
10847 * 0b1..Enable. The 1 Hz RTC clock is running and RTC operation is enabled. This bit must be set to initiate
\r
10848 * operation of the RTC. The first clock to the RTC counter occurs 1 s after this bit is set. To also enable the
\r
10849 * high-resolution, 1 kHz clock, set bit 6 in this register.
\r
10851 #define RTC_CTRL_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_EN_SHIFT)) & RTC_CTRL_RTC_EN_MASK)
\r
10852 #define RTC_CTRL_RTC_OSC_PD_MASK (0x100U)
\r
10853 #define RTC_CTRL_RTC_OSC_PD_SHIFT (8U)
\r
10854 /*! RTC_OSC_PD - RTC oscillator power-down control.
\r
10855 * 0b0..See RTC_OSC_BYPASS
\r
10856 * 0b1..RTC oscillator is powered-down.
\r
10858 #define RTC_CTRL_RTC_OSC_PD(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_PD_SHIFT)) & RTC_CTRL_RTC_OSC_PD_MASK)
\r
10861 /*! @name MATCH - RTC match register */
\r
10863 #define RTC_MATCH_MATVAL_MASK (0xFFFFFFFFU)
\r
10864 #define RTC_MATCH_MATVAL_SHIFT (0U)
\r
10865 /*! MATVAL - Contains the match value against which the 1 Hz RTC timer will be compared to set the
\r
10866 * alarm flag RTC_ALARM and generate an alarm interrupt/wake-up if enabled.
\r
10868 #define RTC_MATCH_MATVAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MATCH_MATVAL_SHIFT)) & RTC_MATCH_MATVAL_MASK)
\r
10871 /*! @name COUNT - RTC counter register */
\r
10873 #define RTC_COUNT_VAL_MASK (0xFFFFFFFFU)
\r
10874 #define RTC_COUNT_VAL_SHIFT (0U)
\r
10875 /*! VAL - A read reflects the current value of the main, 1 Hz RTC timer. A write loads a new initial
\r
10876 * value into the timer. The RTC counter will count up continuously at a 1 Hz rate once the RTC
\r
10877 * Software Reset is removed (by clearing bit 0 of the CTRL register). Only write to this
\r
10878 * register when the RTC_EN bit in the RTC CTRL Register is 0. The counter increments one second after
\r
10879 * the RTC_EN bit is set.
\r
10881 #define RTC_COUNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_COUNT_VAL_SHIFT)) & RTC_COUNT_VAL_MASK)
\r
10884 /*! @name WAKE - High-resolution/wake-up timer control register */
\r
10886 #define RTC_WAKE_VAL_MASK (0xFFFFU)
\r
10887 #define RTC_WAKE_VAL_SHIFT (0U)
\r
10888 /*! VAL - A read reflects the current value of the high-resolution/wake-up timer. A write pre-loads
\r
10889 * a start count value into the wake-up timer and initializes a count-down sequence. Do not write
\r
10890 * to this register while counting is in progress.
\r
10892 #define RTC_WAKE_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_VAL_SHIFT)) & RTC_WAKE_VAL_MASK)
\r
10895 /*! @name GPREG - General Purpose register */
\r
10897 #define RTC_GPREG_GPDATA_MASK (0xFFFFFFFFU)
\r
10898 #define RTC_GPREG_GPDATA_SHIFT (0U)
\r
10899 /*! GPDATA - Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied.
\r
10901 #define RTC_GPREG_GPDATA(x) (((uint32_t)(((uint32_t)(x)) << RTC_GPREG_GPDATA_SHIFT)) & RTC_GPREG_GPDATA_MASK)
\r
10904 /* The count of RTC_GPREG */
\r
10905 #define RTC_GPREG_COUNT (8U)
\r
10910 */ /* end of group RTC_Register_Masks */
\r
10913 /* RTC - Peripheral instance base addresses */
\r
10914 /** Peripheral RTC base address */
\r
10915 #define RTC_BASE (0x4002C000u)
\r
10916 /** Peripheral RTC base pointer */
\r
10917 #define RTC ((RTC_Type *)RTC_BASE)
\r
10918 /** Array initializer of RTC peripheral base addresses */
\r
10919 #define RTC_BASE_ADDRS { RTC_BASE }
\r
10920 /** Array initializer of RTC peripheral base pointers */
\r
10921 #define RTC_BASE_PTRS { RTC }
\r
10922 /** Interrupt vectors for the RTC peripheral type */
\r
10923 #define RTC_IRQS { RTC_IRQn }
\r
10927 */ /* end of group RTC_Peripheral_Access_Layer */
\r
10930 /* ----------------------------------------------------------------------------
\r
10931 -- SCT Peripheral Access Layer
\r
10932 ---------------------------------------------------------------------------- */
\r
10935 * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer
\r
10939 /** SCT - Register Layout Typedef */
\r
10941 __IO uint32_t CONFIG; /**< SCT configuration register, offset: 0x0 */
\r
10942 __IO uint32_t CTRL; /**< SCT control register, offset: 0x4 */
\r
10943 __IO uint32_t LIMIT; /**< SCT limit event select register, offset: 0x8 */
\r
10944 __IO uint32_t HALT; /**< SCT halt event select register, offset: 0xC */
\r
10945 __IO uint32_t STOP; /**< SCT stop event select register, offset: 0x10 */
\r
10946 __IO uint32_t START; /**< SCT start event select register, offset: 0x14 */
\r
10947 uint8_t RESERVED_0[40];
\r
10948 __IO uint32_t COUNT; /**< SCT counter register, offset: 0x40 */
\r
10949 __IO uint32_t STATE; /**< SCT state register, offset: 0x44 */
\r
10950 __I uint32_t INPUT; /**< SCT input register, offset: 0x48 */
\r
10951 __IO uint32_t REGMODE; /**< SCT match/capture mode register, offset: 0x4C */
\r
10952 __IO uint32_t OUTPUT; /**< SCT output register, offset: 0x50 */
\r
10953 __IO uint32_t OUTPUTDIRCTRL; /**< SCT output counter direction control register, offset: 0x54 */
\r
10954 __IO uint32_t RES; /**< SCT conflict resolution register, offset: 0x58 */
\r
10955 __IO uint32_t DMAREQ0; /**< SCT DMA request 0 register, offset: 0x5C */
\r
10956 __IO uint32_t DMAREQ1; /**< SCT DMA request 1 register, offset: 0x60 */
\r
10957 uint8_t RESERVED_1[140];
\r
10958 __IO uint32_t EVEN; /**< SCT event interrupt enable register, offset: 0xF0 */
\r
10959 __IO uint32_t EVFLAG; /**< SCT event flag register, offset: 0xF4 */
\r
10960 __IO uint32_t CONEN; /**< SCT conflict interrupt enable register, offset: 0xF8 */
\r
10961 __IO uint32_t CONFLAG; /**< SCT conflict flag register, offset: 0xFC */
\r
10962 union { /* offset: 0x100 */
\r
10963 __IO uint32_t CAP[16]; /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */
\r
10964 __IO uint32_t MATCH[16]; /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */
\r
10966 uint8_t RESERVED_2[192];
\r
10967 union { /* offset: 0x200 */
\r
10968 __IO uint32_t CAPCTRL[16]; /**< SCT capture control register, array offset: 0x200, array step: 0x4 */
\r
10969 __IO uint32_t MATCHREL[16]; /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */
\r
10971 uint8_t RESERVED_3[192];
\r
10972 struct { /* offset: 0x300, array step: 0x8 */
\r
10973 __IO uint32_t STATE; /**< SCT event state register 0, array offset: 0x300, array step: 0x8 */
\r
10974 __IO uint32_t CTRL; /**< SCT event control register 0, array offset: 0x304, array step: 0x8 */
\r
10976 uint8_t RESERVED_4[384];
\r
10977 struct { /* offset: 0x500, array step: 0x8 */
\r
10978 __IO uint32_t SET; /**< SCT output 0 set register, array offset: 0x500, array step: 0x8 */
\r
10979 __IO uint32_t CLR; /**< SCT output 0 clear register, array offset: 0x504, array step: 0x8 */
\r
10983 /* ----------------------------------------------------------------------------
\r
10984 -- SCT Register Masks
\r
10985 ---------------------------------------------------------------------------- */
\r
10988 * @addtogroup SCT_Register_Masks SCT Register Masks
\r
10992 /*! @name CONFIG - SCT configuration register */
\r
10994 #define SCT_CONFIG_UNIFY_MASK (0x1U)
\r
10995 #define SCT_CONFIG_UNIFY_SHIFT (0U)
\r
10996 /*! UNIFY - SCT operation
\r
10997 * 0b0..The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H.
\r
10998 * 0b1..The SCT operates as a unified 32-bit counter.
\r
11000 #define SCT_CONFIG_UNIFY(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK)
\r
11001 #define SCT_CONFIG_CLKMODE_MASK (0x6U)
\r
11002 #define SCT_CONFIG_CLKMODE_SHIFT (1U)
\r
11003 /*! CLKMODE - SCT clock mode
\r
11004 * 0b00..System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers.
\r
11005 * 0b01..Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are
\r
11006 * only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The
\r
11007 * minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the
\r
11008 * high-performance, sampled-clock mode.
\r
11009 * 0b10..SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the
\r
11010 * counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the
\r
11011 * clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode.
\r
11012 * 0b11..Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL
\r
11013 * field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system
\r
11014 * clock. The input clock rate must be at least half the system clock rate and can be the same or faster than
\r
11015 * the system clock.
\r
11017 #define SCT_CONFIG_CLKMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK)
\r
11018 #define SCT_CONFIG_CKSEL_MASK (0x78U)
\r
11019 #define SCT_CONFIG_CKSEL_SHIFT (3U)
\r
11020 /*! CKSEL - SCT clock select. The specific functionality of the designated input/edge is dependent
\r
11021 * on the CLKMODE bit selection in this register.
\r
11022 * 0b0000..Rising edges on input 0.
\r
11023 * 0b0001..Falling edges on input 0.
\r
11024 * 0b0010..Rising edges on input 1.
\r
11025 * 0b0011..Falling edges on input 1.
\r
11026 * 0b0100..Rising edges on input 2.
\r
11027 * 0b0101..Falling edges on input 2.
\r
11028 * 0b0110..Rising edges on input 3.
\r
11029 * 0b0111..Falling edges on input 3.
\r
11030 * 0b1000..Rising edges on input 4.
\r
11031 * 0b1001..Falling edges on input 4.
\r
11032 * 0b1010..Rising edges on input 5.
\r
11033 * 0b1011..Falling edges on input 5.
\r
11034 * 0b1100..Rising edges on input 6.
\r
11035 * 0b1101..Falling edges on input 6.
\r
11036 * 0b1110..Rising edges on input 7.
\r
11037 * 0b1111..Falling edges on input 7.
\r
11039 #define SCT_CONFIG_CKSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK)
\r
11040 #define SCT_CONFIG_NORELOAD_L_MASK (0x80U)
\r
11041 #define SCT_CONFIG_NORELOAD_L_SHIFT (7U)
\r
11042 /*! NORELOAD_L - A 1 in this bit prevents the lower match registers from being reloaded from their
\r
11043 * respective reload registers. Setting this bit eliminates the need to write to the reload
\r
11044 * registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any
\r
11045 * time. This bit applies to both the higher and lower registers when the UNIFY bit is set.
\r
11047 #define SCT_CONFIG_NORELOAD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_L_SHIFT)) & SCT_CONFIG_NORELOAD_L_MASK)
\r
11048 #define SCT_CONFIG_NORELOAD_H_MASK (0x100U)
\r
11049 #define SCT_CONFIG_NORELOAD_H_SHIFT (8U)
\r
11050 /*! NORELOAD_H - A 1 in this bit prevents the higher match registers from being reloaded from their
\r
11051 * respective reload registers. Setting this bit eliminates the need to write to the reload
\r
11052 * registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at
\r
11053 * any time. This bit is not used when the UNIFY bit is set.
\r
11055 #define SCT_CONFIG_NORELOAD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK)
\r
11056 #define SCT_CONFIG_INSYNC_MASK (0x1FE00U)
\r
11057 #define SCT_CONFIG_INSYNC_SHIFT (9U)
\r
11058 /*! INSYNC - Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all
\r
11059 * other bits are reserved. A 1 in one of these bits subjects the corresponding input to
\r
11060 * synchronization to the SCT clock, before it is used to create an event. If an input is known to
\r
11061 * already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note:
\r
11062 * The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input
\r
11063 * clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation.
\r
11064 * It does not apply to the clock input specified in the CKSEL field.
\r
11066 #define SCT_CONFIG_INSYNC(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK)
\r
11067 #define SCT_CONFIG_AUTOLIMIT_L_MASK (0x20000U)
\r
11068 #define SCT_CONFIG_AUTOLIMIT_L_SHIFT (17U)
\r
11069 /*! AUTOLIMIT_L - A one in this bit causes a match on match register 0 to be treated as a de-facto
\r
11070 * LIMIT condition without the need to define an associated event. As with any LIMIT event, this
\r
11071 * automatic limit causes the counter to be cleared to zero in unidirectional mode or to change
\r
11072 * the direction of count in bi-directional mode. Software can write to set or clear this bit at
\r
11073 * any time. This bit applies to both the higher and lower registers when the UNIFY bit is set.
\r
11075 #define SCT_CONFIG_AUTOLIMIT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK)
\r
11076 #define SCT_CONFIG_AUTOLIMIT_H_MASK (0x40000U)
\r
11077 #define SCT_CONFIG_AUTOLIMIT_H_SHIFT (18U)
\r
11078 /*! AUTOLIMIT_H - A one in this bit will cause a match on match register 0 to be treated as a
\r
11079 * de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event,
\r
11080 * this automatic limit causes the counter to be cleared to zero in unidirectional mode or to
\r
11081 * change the direction of count in bi-directional mode. Software can write to set or clear this bit
\r
11082 * at any time. This bit is not used when the UNIFY bit is set.
\r
11084 #define SCT_CONFIG_AUTOLIMIT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK)
\r
11087 /*! @name CTRL - SCT control register */
\r
11089 #define SCT_CTRL_DOWN_L_MASK (0x1U)
\r
11090 #define SCT_CTRL_DOWN_L_SHIFT (0U)
\r
11091 /*! DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit
\r
11092 * when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit
\r
11093 * when the counter is counting down and a limit condition occurs or when the counter reaches 0.
\r
11095 #define SCT_CTRL_DOWN_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK)
\r
11096 #define SCT_CTRL_STOP_L_MASK (0x2U)
\r
11097 #define SCT_CTRL_STOP_L_SHIFT (1U)
\r
11098 /*! STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events
\r
11099 * related to the counter can occur. If a designated start event occurs, this bit is cleared and
\r
11100 * counting resumes.
\r
11102 #define SCT_CTRL_STOP_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK)
\r
11103 #define SCT_CTRL_HALT_L_MASK (0x4U)
\r
11104 #define SCT_CTRL_HALT_L_SHIFT (2U)
\r
11105 /*! HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A
\r
11106 * reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to
\r
11107 * remove the halt condition while keeping the SCT in the stop condition (not running) with a
\r
11108 * single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set,
\r
11109 * only software can clear this bit to restore counter operation. This bit is set on reset.
\r
11111 #define SCT_CTRL_HALT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK)
\r
11112 #define SCT_CTRL_CLRCTR_L_MASK (0x8U)
\r
11113 #define SCT_CTRL_CLRCTR_L_SHIFT (3U)
\r
11114 /*! CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0.
\r
11116 #define SCT_CTRL_CLRCTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK)
\r
11117 #define SCT_CTRL_BIDIR_L_MASK (0x10U)
\r
11118 #define SCT_CTRL_BIDIR_L_SHIFT (4U)
\r
11119 /*! BIDIR_L - L or unified counter direction select
\r
11120 * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero.
\r
11121 * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0.
\r
11123 #define SCT_CTRL_BIDIR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK)
\r
11124 #define SCT_CTRL_PRE_L_MASK (0x1FE0U)
\r
11125 #define SCT_CTRL_PRE_L_SHIFT (5U)
\r
11126 /*! PRE_L - Specifies the factor by which the SCT clock is prescaled to produce the L or unified
\r
11127 * counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1.
\r
11128 * Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.
\r
11130 #define SCT_CTRL_PRE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK)
\r
11131 #define SCT_CTRL_DOWN_H_MASK (0x10000U)
\r
11132 #define SCT_CTRL_DOWN_H_SHIFT (16U)
\r
11133 /*! DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the
\r
11134 * counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit
\r
11135 * when the counter is counting down and a limit condition occurs or when the counter reaches 0.
\r
11137 #define SCT_CTRL_DOWN_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK)
\r
11138 #define SCT_CTRL_STOP_H_MASK (0x20000U)
\r
11139 #define SCT_CTRL_STOP_H_SHIFT (17U)
\r
11140 /*! STOP_H - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to
\r
11141 * the counter can occur. If such an event matches the mask in the Start register, this bit is
\r
11142 * cleared and counting resumes.
\r
11144 #define SCT_CTRL_STOP_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK)
\r
11145 #define SCT_CTRL_HALT_H_MASK (0x40000U)
\r
11146 #define SCT_CTRL_HALT_H_SHIFT (18U)
\r
11147 /*! HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets
\r
11148 * this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the
\r
11149 * halt condition while keeping the SCT in the stop condition (not running) with a single write to
\r
11150 * this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit
\r
11151 * can only be cleared by software to restore counter operation. This bit is set on reset.
\r
11153 #define SCT_CTRL_HALT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK)
\r
11154 #define SCT_CTRL_CLRCTR_H_MASK (0x80000U)
\r
11155 #define SCT_CTRL_CLRCTR_H_SHIFT (19U)
\r
11156 /*! CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0.
\r
11158 #define SCT_CTRL_CLRCTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK)
\r
11159 #define SCT_CTRL_BIDIR_H_MASK (0x100000U)
\r
11160 #define SCT_CTRL_BIDIR_H_SHIFT (20U)
\r
11161 /*! BIDIR_H - Direction select
\r
11162 * 0b0..The H counter counts up to its limit condition, then is cleared to zero.
\r
11163 * 0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0.
\r
11165 #define SCT_CTRL_BIDIR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK)
\r
11166 #define SCT_CTRL_PRE_H_MASK (0x1FE00000U)
\r
11167 #define SCT_CTRL_PRE_H_SHIFT (21U)
\r
11168 /*! PRE_H - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock.
\r
11169 * The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the
\r
11170 * counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.
\r
11172 #define SCT_CTRL_PRE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK)
\r
11175 /*! @name LIMIT - SCT limit event select register */
\r
11177 #define SCT_LIMIT_LIMMSK_L_MASK (0xFFFFU)
\r
11178 #define SCT_LIMIT_LIMMSK_L_SHIFT (0U)
\r
11179 /*! LIMMSK_L - If bit n is one, event n is used as a counter limit for the L or unified counter
\r
11180 * (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
\r
11182 #define SCT_LIMIT_LIMMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK)
\r
11183 #define SCT_LIMIT_LIMMSK_H_MASK (0xFFFF0000U)
\r
11184 #define SCT_LIMIT_LIMMSK_H_SHIFT (16U)
\r
11185 /*! LIMMSK_H - If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit
\r
11186 * 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT.
\r
11188 #define SCT_LIMIT_LIMMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK)
\r
11191 /*! @name HALT - SCT halt event select register */
\r
11193 #define SCT_HALT_HALTMSK_L_MASK (0xFFFFU)
\r
11194 #define SCT_HALT_HALTMSK_L_SHIFT (0U)
\r
11195 /*! HALTMSK_L - If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0,
\r
11196 * event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
\r
11198 #define SCT_HALT_HALTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK)
\r
11199 #define SCT_HALT_HALTMSK_H_MASK (0xFFFF0000U)
\r
11200 #define SCT_HALT_HALTMSK_H_SHIFT (16U)
\r
11201 /*! HALTMSK_H - If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16,
\r
11202 * event 1 = bit 17, etc.). The number of bits = number of events in this SCT.
\r
11204 #define SCT_HALT_HALTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK)
\r
11207 /*! @name STOP - SCT stop event select register */
\r
11209 #define SCT_STOP_STOPMSK_L_MASK (0xFFFFU)
\r
11210 #define SCT_STOP_STOPMSK_L_SHIFT (0U)
\r
11211 /*! STOPMSK_L - If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0,
\r
11212 * event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
\r
11214 #define SCT_STOP_STOPMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK)
\r
11215 #define SCT_STOP_STOPMSK_H_MASK (0xFFFF0000U)
\r
11216 #define SCT_STOP_STOPMSK_H_SHIFT (16U)
\r
11217 /*! STOPMSK_H - If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16,
\r
11218 * event 1 = bit 17, etc.). The number of bits = number of events in this SCT.
\r
11220 #define SCT_STOP_STOPMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK)
\r
11223 /*! @name START - SCT start event select register */
\r
11225 #define SCT_START_STARTMSK_L_MASK (0xFFFFU)
\r
11226 #define SCT_START_STARTMSK_L_SHIFT (0U)
\r
11227 /*! STARTMSK_L - If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit
\r
11228 * 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
\r
11230 #define SCT_START_STARTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK)
\r
11231 #define SCT_START_STARTMSK_H_MASK (0xFFFF0000U)
\r
11232 #define SCT_START_STARTMSK_H_SHIFT (16U)
\r
11233 /*! STARTMSK_H - If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit
\r
11234 * 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT.
\r
11236 #define SCT_START_STARTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK)
\r
11239 /*! @name COUNT - SCT counter register */
\r
11241 #define SCT_COUNT_CTR_L_MASK (0xFFFFU)
\r
11242 #define SCT_COUNT_CTR_L_SHIFT (0U)
\r
11243 /*! CTR_L - When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write
\r
11244 * the lower 16 bits of the 32-bit unified counter.
\r
11246 #define SCT_COUNT_CTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK)
\r
11247 #define SCT_COUNT_CTR_H_MASK (0xFFFF0000U)
\r
11248 #define SCT_COUNT_CTR_H_SHIFT (16U)
\r
11249 /*! CTR_H - When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write
\r
11250 * the upper 16 bits of the 32-bit unified counter.
\r
11252 #define SCT_COUNT_CTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK)
\r
11255 /*! @name STATE - SCT state register */
\r
11257 #define SCT_STATE_STATE_L_MASK (0x1FU)
\r
11258 #define SCT_STATE_STATE_L_SHIFT (0U)
\r
11259 /*! STATE_L - State variable.
\r
11261 #define SCT_STATE_STATE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK)
\r
11262 #define SCT_STATE_STATE_H_MASK (0x1F0000U)
\r
11263 #define SCT_STATE_STATE_H_SHIFT (16U)
\r
11264 /*! STATE_H - State variable.
\r
11266 #define SCT_STATE_STATE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK)
\r
11269 /*! @name INPUT - SCT input register */
\r
11271 #define SCT_INPUT_AIN0_MASK (0x1U)
\r
11272 #define SCT_INPUT_AIN0_SHIFT (0U)
\r
11273 /*! AIN0 - Input 0 state. Input 0 state on the last SCT clock edge.
\r
11275 #define SCT_INPUT_AIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK)
\r
11276 #define SCT_INPUT_AIN1_MASK (0x2U)
\r
11277 #define SCT_INPUT_AIN1_SHIFT (1U)
\r
11278 /*! AIN1 - Input 1 state. Input 1 state on the last SCT clock edge.
\r
11280 #define SCT_INPUT_AIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK)
\r
11281 #define SCT_INPUT_AIN2_MASK (0x4U)
\r
11282 #define SCT_INPUT_AIN2_SHIFT (2U)
\r
11283 /*! AIN2 - Input 2 state. Input 2 state on the last SCT clock edge.
\r
11285 #define SCT_INPUT_AIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK)
\r
11286 #define SCT_INPUT_AIN3_MASK (0x8U)
\r
11287 #define SCT_INPUT_AIN3_SHIFT (3U)
\r
11288 /*! AIN3 - Input 3 state. Input 3 state on the last SCT clock edge.
\r
11290 #define SCT_INPUT_AIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK)
\r
11291 #define SCT_INPUT_AIN4_MASK (0x10U)
\r
11292 #define SCT_INPUT_AIN4_SHIFT (4U)
\r
11293 /*! AIN4 - Input 4 state. Input 4 state on the last SCT clock edge.
\r
11295 #define SCT_INPUT_AIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK)
\r
11296 #define SCT_INPUT_AIN5_MASK (0x20U)
\r
11297 #define SCT_INPUT_AIN5_SHIFT (5U)
\r
11298 /*! AIN5 - Input 5 state. Input 5 state on the last SCT clock edge.
\r
11300 #define SCT_INPUT_AIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK)
\r
11301 #define SCT_INPUT_AIN6_MASK (0x40U)
\r
11302 #define SCT_INPUT_AIN6_SHIFT (6U)
\r
11303 /*! AIN6 - Input 6 state. Input 6 state on the last SCT clock edge.
\r
11305 #define SCT_INPUT_AIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK)
\r
11306 #define SCT_INPUT_AIN7_MASK (0x80U)
\r
11307 #define SCT_INPUT_AIN7_SHIFT (7U)
\r
11308 /*! AIN7 - Input 7 state. Input 7 state on the last SCT clock edge.
\r
11310 #define SCT_INPUT_AIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK)
\r
11311 #define SCT_INPUT_AIN8_MASK (0x100U)
\r
11312 #define SCT_INPUT_AIN8_SHIFT (8U)
\r
11313 /*! AIN8 - Input 8 state. Input 8 state on the last SCT clock edge.
\r
11315 #define SCT_INPUT_AIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK)
\r
11316 #define SCT_INPUT_AIN9_MASK (0x200U)
\r
11317 #define SCT_INPUT_AIN9_SHIFT (9U)
\r
11318 /*! AIN9 - Input 9 state. Input 9 state on the last SCT clock edge.
\r
11320 #define SCT_INPUT_AIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK)
\r
11321 #define SCT_INPUT_AIN10_MASK (0x400U)
\r
11322 #define SCT_INPUT_AIN10_SHIFT (10U)
\r
11323 /*! AIN10 - Input 10 state. Input 10 state on the last SCT clock edge.
\r
11325 #define SCT_INPUT_AIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK)
\r
11326 #define SCT_INPUT_AIN11_MASK (0x800U)
\r
11327 #define SCT_INPUT_AIN11_SHIFT (11U)
\r
11328 /*! AIN11 - Input 11 state. Input 11 state on the last SCT clock edge.
\r
11330 #define SCT_INPUT_AIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK)
\r
11331 #define SCT_INPUT_AIN12_MASK (0x1000U)
\r
11332 #define SCT_INPUT_AIN12_SHIFT (12U)
\r
11333 /*! AIN12 - Input 12 state. Input 12 state on the last SCT clock edge.
\r
11335 #define SCT_INPUT_AIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK)
\r
11336 #define SCT_INPUT_AIN13_MASK (0x2000U)
\r
11337 #define SCT_INPUT_AIN13_SHIFT (13U)
\r
11338 /*! AIN13 - Input 13 state. Input 13 state on the last SCT clock edge.
\r
11340 #define SCT_INPUT_AIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK)
\r
11341 #define SCT_INPUT_AIN14_MASK (0x4000U)
\r
11342 #define SCT_INPUT_AIN14_SHIFT (14U)
\r
11343 /*! AIN14 - Input 14 state. Input 14 state on the last SCT clock edge.
\r
11345 #define SCT_INPUT_AIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK)
\r
11346 #define SCT_INPUT_AIN15_MASK (0x8000U)
\r
11347 #define SCT_INPUT_AIN15_SHIFT (15U)
\r
11348 /*! AIN15 - Input 15 state. Input 15 state on the last SCT clock edge.
\r
11350 #define SCT_INPUT_AIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK)
\r
11351 #define SCT_INPUT_SIN0_MASK (0x10000U)
\r
11352 #define SCT_INPUT_SIN0_SHIFT (16U)
\r
11353 /*! SIN0 - Input 0 state. Input 0 state following the synchronization specified by INSYNC.
\r
11355 #define SCT_INPUT_SIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK)
\r
11356 #define SCT_INPUT_SIN1_MASK (0x20000U)
\r
11357 #define SCT_INPUT_SIN1_SHIFT (17U)
\r
11358 /*! SIN1 - Input 1 state. Input 1 state following the synchronization specified by INSYNC.
\r
11360 #define SCT_INPUT_SIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK)
\r
11361 #define SCT_INPUT_SIN2_MASK (0x40000U)
\r
11362 #define SCT_INPUT_SIN2_SHIFT (18U)
\r
11363 /*! SIN2 - Input 2 state. Input 2 state following the synchronization specified by INSYNC.
\r
11365 #define SCT_INPUT_SIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK)
\r
11366 #define SCT_INPUT_SIN3_MASK (0x80000U)
\r
11367 #define SCT_INPUT_SIN3_SHIFT (19U)
\r
11368 /*! SIN3 - Input 3 state. Input 3 state following the synchronization specified by INSYNC.
\r
11370 #define SCT_INPUT_SIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK)
\r
11371 #define SCT_INPUT_SIN4_MASK (0x100000U)
\r
11372 #define SCT_INPUT_SIN4_SHIFT (20U)
\r
11373 /*! SIN4 - Input 4 state. Input 4 state following the synchronization specified by INSYNC.
\r
11375 #define SCT_INPUT_SIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK)
\r
11376 #define SCT_INPUT_SIN5_MASK (0x200000U)
\r
11377 #define SCT_INPUT_SIN5_SHIFT (21U)
\r
11378 /*! SIN5 - Input 5 state. Input 5 state following the synchronization specified by INSYNC.
\r
11380 #define SCT_INPUT_SIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK)
\r
11381 #define SCT_INPUT_SIN6_MASK (0x400000U)
\r
11382 #define SCT_INPUT_SIN6_SHIFT (22U)
\r
11383 /*! SIN6 - Input 6 state. Input 6 state following the synchronization specified by INSYNC.
\r
11385 #define SCT_INPUT_SIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK)
\r
11386 #define SCT_INPUT_SIN7_MASK (0x800000U)
\r
11387 #define SCT_INPUT_SIN7_SHIFT (23U)
\r
11388 /*! SIN7 - Input 7 state. Input 7 state following the synchronization specified by INSYNC.
\r
11390 #define SCT_INPUT_SIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK)
\r
11391 #define SCT_INPUT_SIN8_MASK (0x1000000U)
\r
11392 #define SCT_INPUT_SIN8_SHIFT (24U)
\r
11393 /*! SIN8 - Input 8 state. Input 8 state following the synchronization specified by INSYNC.
\r
11395 #define SCT_INPUT_SIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK)
\r
11396 #define SCT_INPUT_SIN9_MASK (0x2000000U)
\r
11397 #define SCT_INPUT_SIN9_SHIFT (25U)
\r
11398 /*! SIN9 - Input 9 state. Input 9 state following the synchronization specified by INSYNC.
\r
11400 #define SCT_INPUT_SIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK)
\r
11401 #define SCT_INPUT_SIN10_MASK (0x4000000U)
\r
11402 #define SCT_INPUT_SIN10_SHIFT (26U)
\r
11403 /*! SIN10 - Input 10 state. Input 10 state following the synchronization specified by INSYNC.
\r
11405 #define SCT_INPUT_SIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK)
\r
11406 #define SCT_INPUT_SIN11_MASK (0x8000000U)
\r
11407 #define SCT_INPUT_SIN11_SHIFT (27U)
\r
11408 /*! SIN11 - Input 11 state. Input 11 state following the synchronization specified by INSYNC.
\r
11410 #define SCT_INPUT_SIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK)
\r
11411 #define SCT_INPUT_SIN12_MASK (0x10000000U)
\r
11412 #define SCT_INPUT_SIN12_SHIFT (28U)
\r
11413 /*! SIN12 - Input 12 state. Input 12 state following the synchronization specified by INSYNC.
\r
11415 #define SCT_INPUT_SIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK)
\r
11416 #define SCT_INPUT_SIN13_MASK (0x20000000U)
\r
11417 #define SCT_INPUT_SIN13_SHIFT (29U)
\r
11418 /*! SIN13 - Input 13 state. Input 13 state following the synchronization specified by INSYNC.
\r
11420 #define SCT_INPUT_SIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK)
\r
11421 #define SCT_INPUT_SIN14_MASK (0x40000000U)
\r
11422 #define SCT_INPUT_SIN14_SHIFT (30U)
\r
11423 /*! SIN14 - Input 14 state. Input 14 state following the synchronization specified by INSYNC.
\r
11425 #define SCT_INPUT_SIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK)
\r
11426 #define SCT_INPUT_SIN15_MASK (0x80000000U)
\r
11427 #define SCT_INPUT_SIN15_SHIFT (31U)
\r
11428 /*! SIN15 - Input 15 state. Input 15 state following the synchronization specified by INSYNC.
\r
11430 #define SCT_INPUT_SIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK)
\r
11433 /*! @name REGMODE - SCT match/capture mode register */
\r
11435 #define SCT_REGMODE_REGMOD_L_MASK (0xFFFFU)
\r
11436 #define SCT_REGMODE_REGMOD_L_SHIFT (0U)
\r
11437 /*! REGMOD_L - Each bit controls one match/capture register (register 0 = bit 0, register 1 = bit 1,
\r
11438 * etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as
\r
11439 * match register. 1 = register operates as capture register.
\r
11441 #define SCT_REGMODE_REGMOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK)
\r
11442 #define SCT_REGMODE_REGMOD_H_MASK (0xFFFF0000U)
\r
11443 #define SCT_REGMODE_REGMOD_H_SHIFT (16U)
\r
11444 /*! REGMOD_H - Each bit controls one match/capture register (register 0 = bit 16, register 1 = bit
\r
11445 * 17, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as
\r
11446 * match registers. 1 = register operates as capture registers.
\r
11448 #define SCT_REGMODE_REGMOD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK)
\r
11451 /*! @name OUTPUT - SCT output register */
\r
11453 #define SCT_OUTPUT_OUT_MASK (0xFFFFU)
\r
11454 #define SCT_OUTPUT_OUT_SHIFT (0U)
\r
11455 /*! OUT - Writing a 1 to bit n forces the corresponding output HIGH. Writing a 0 forces the
\r
11456 * corresponding output LOW (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of
\r
11457 * outputs in this SCT.
\r
11459 #define SCT_OUTPUT_OUT(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK)
\r
11462 /*! @name OUTPUTDIRCTRL - SCT output counter direction control register */
\r
11464 #define SCT_OUTPUTDIRCTRL_SETCLR0_MASK (0x3U)
\r
11465 #define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT (0U)
\r
11466 /*! SETCLR0 - Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value.
\r
11467 * 0b00..Set and clear do not depend on the direction of any counter.
\r
11468 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
\r
11469 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
\r
11471 #define SCT_OUTPUTDIRCTRL_SETCLR0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK)
\r
11472 #define SCT_OUTPUTDIRCTRL_SETCLR1_MASK (0xCU)
\r
11473 #define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT (2U)
\r
11474 /*! SETCLR1 - Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value.
\r
11475 * 0b00..Set and clear do not depend on the direction of any counter.
\r
11476 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
\r
11477 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
\r
11479 #define SCT_OUTPUTDIRCTRL_SETCLR1(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK)
\r
11480 #define SCT_OUTPUTDIRCTRL_SETCLR2_MASK (0x30U)
\r
11481 #define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT (4U)
\r
11482 /*! SETCLR2 - Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value.
\r
11483 * 0b00..Set and clear do not depend on the direction of any counter.
\r
11484 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
\r
11485 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
\r
11487 #define SCT_OUTPUTDIRCTRL_SETCLR2(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK)
\r
11488 #define SCT_OUTPUTDIRCTRL_SETCLR3_MASK (0xC0U)
\r
11489 #define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT (6U)
\r
11490 /*! SETCLR3 - Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value.
\r
11491 * 0b00..Set and clear do not depend on the direction of any counter.
\r
11492 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
\r
11493 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
\r
11495 #define SCT_OUTPUTDIRCTRL_SETCLR3(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK)
\r
11496 #define SCT_OUTPUTDIRCTRL_SETCLR4_MASK (0x300U)
\r
11497 #define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT (8U)
\r
11498 /*! SETCLR4 - Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value.
\r
11499 * 0b00..Set and clear do not depend on the direction of any counter.
\r
11500 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
\r
11501 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
\r
11503 #define SCT_OUTPUTDIRCTRL_SETCLR4(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK)
\r
11504 #define SCT_OUTPUTDIRCTRL_SETCLR5_MASK (0xC00U)
\r
11505 #define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT (10U)
\r
11506 /*! SETCLR5 - Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value.
\r
11507 * 0b00..Set and clear do not depend on the direction of any counter.
\r
11508 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
\r
11509 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
\r
11511 #define SCT_OUTPUTDIRCTRL_SETCLR5(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK)
\r
11512 #define SCT_OUTPUTDIRCTRL_SETCLR6_MASK (0x3000U)
\r
11513 #define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT (12U)
\r
11514 /*! SETCLR6 - Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value.
\r
11515 * 0b00..Set and clear do not depend on the direction of any counter.
\r
11516 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
\r
11517 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
\r
11519 #define SCT_OUTPUTDIRCTRL_SETCLR6(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK)
\r
11520 #define SCT_OUTPUTDIRCTRL_SETCLR7_MASK (0xC000U)
\r
11521 #define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT (14U)
\r
11522 /*! SETCLR7 - Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value.
\r
11523 * 0b00..Set and clear do not depend on the direction of any counter.
\r
11524 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
\r
11525 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
\r
11527 #define SCT_OUTPUTDIRCTRL_SETCLR7(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK)
\r
11528 #define SCT_OUTPUTDIRCTRL_SETCLR8_MASK (0x30000U)
\r
11529 #define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT (16U)
\r
11530 /*! SETCLR8 - Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value.
\r
11531 * 0b00..Set and clear do not depend on the direction of any counter.
\r
11532 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
\r
11533 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
\r
11535 #define SCT_OUTPUTDIRCTRL_SETCLR8(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK)
\r
11536 #define SCT_OUTPUTDIRCTRL_SETCLR9_MASK (0xC0000U)
\r
11537 #define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT (18U)
\r
11538 /*! SETCLR9 - Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value.
\r
11539 * 0b00..Set and clear do not depend on the direction of any counter.
\r
11540 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
\r
11541 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
\r
11543 #define SCT_OUTPUTDIRCTRL_SETCLR9(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK)
\r
11544 #define SCT_OUTPUTDIRCTRL_SETCLR10_MASK (0x300000U)
\r
11545 #define SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT (20U)
\r
11546 /*! SETCLR10 - Set/clear operation on output 10. Value 0x3 is reserved. Do not program this value.
\r
11547 * 0b00..Set and clear do not depend on the direction of any counter.
\r
11548 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
\r
11549 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
\r
11551 #define SCT_OUTPUTDIRCTRL_SETCLR10(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR10_MASK)
\r
11552 #define SCT_OUTPUTDIRCTRL_SETCLR11_MASK (0xC00000U)
\r
11553 #define SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT (22U)
\r
11554 /*! SETCLR11 - Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value.
\r
11555 * 0b00..Set and clear do not depend on the direction of any counter.
\r
11556 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
\r
11557 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
\r
11559 #define SCT_OUTPUTDIRCTRL_SETCLR11(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR11_MASK)
\r
11560 #define SCT_OUTPUTDIRCTRL_SETCLR12_MASK (0x3000000U)
\r
11561 #define SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT (24U)
\r
11562 /*! SETCLR12 - Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value.
\r
11563 * 0b00..Set and clear do not depend on the direction of any counter.
\r
11564 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
\r
11565 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
\r
11567 #define SCT_OUTPUTDIRCTRL_SETCLR12(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR12_MASK)
\r
11568 #define SCT_OUTPUTDIRCTRL_SETCLR13_MASK (0xC000000U)
\r
11569 #define SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT (26U)
\r
11570 /*! SETCLR13 - Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value.
\r
11571 * 0b00..Set and clear do not depend on the direction of any counter.
\r
11572 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
\r
11573 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
\r
11575 #define SCT_OUTPUTDIRCTRL_SETCLR13(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR13_MASK)
\r
11576 #define SCT_OUTPUTDIRCTRL_SETCLR14_MASK (0x30000000U)
\r
11577 #define SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT (28U)
\r
11578 /*! SETCLR14 - Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value.
\r
11579 * 0b00..Set and clear do not depend on the direction of any counter.
\r
11580 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
\r
11581 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
\r
11583 #define SCT_OUTPUTDIRCTRL_SETCLR14(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR14_MASK)
\r
11584 #define SCT_OUTPUTDIRCTRL_SETCLR15_MASK (0xC0000000U)
\r
11585 #define SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT (30U)
\r
11586 /*! SETCLR15 - Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value.
\r
11587 * 0b00..Set and clear do not depend on the direction of any counter.
\r
11588 * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
\r
11589 * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
\r
11591 #define SCT_OUTPUTDIRCTRL_SETCLR15(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR15_MASK)
\r
11594 /*! @name RES - SCT conflict resolution register */
\r
11596 #define SCT_RES_O0RES_MASK (0x3U)
\r
11597 #define SCT_RES_O0RES_SHIFT (0U)
\r
11598 /*! O0RES - Effect of simultaneous set and clear on output 0.
\r
11599 * 0b00..No change.
\r
11600 * 0b01..Set output (or clear based on the SETCLR0 field in the OUTPUTDIRCTRL register).
\r
11601 * 0b10..Clear output (or set based on the SETCLR0 field).
\r
11602 * 0b11..Toggle output.
\r
11604 #define SCT_RES_O0RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK)
\r
11605 #define SCT_RES_O1RES_MASK (0xCU)
\r
11606 #define SCT_RES_O1RES_SHIFT (2U)
\r
11607 /*! O1RES - Effect of simultaneous set and clear on output 1.
\r
11608 * 0b00..No change.
\r
11609 * 0b01..Set output (or clear based on the SETCLR1 field in the OUTPUTDIRCTRL register).
\r
11610 * 0b10..Clear output (or set based on the SETCLR1 field).
\r
11611 * 0b11..Toggle output.
\r
11613 #define SCT_RES_O1RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK)
\r
11614 #define SCT_RES_O2RES_MASK (0x30U)
\r
11615 #define SCT_RES_O2RES_SHIFT (4U)
\r
11616 /*! O2RES - Effect of simultaneous set and clear on output 2.
\r
11617 * 0b00..No change.
\r
11618 * 0b01..Set output (or clear based on the SETCLR2 field in the OUTPUTDIRCTRL register).
\r
11619 * 0b10..Clear output n (or set based on the SETCLR2 field).
\r
11620 * 0b11..Toggle output.
\r
11622 #define SCT_RES_O2RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK)
\r
11623 #define SCT_RES_O3RES_MASK (0xC0U)
\r
11624 #define SCT_RES_O3RES_SHIFT (6U)
\r
11625 /*! O3RES - Effect of simultaneous set and clear on output 3.
\r
11626 * 0b00..No change.
\r
11627 * 0b01..Set output (or clear based on the SETCLR3 field in the OUTPUTDIRCTRL register).
\r
11628 * 0b10..Clear output (or set based on the SETCLR3 field).
\r
11629 * 0b11..Toggle output.
\r
11631 #define SCT_RES_O3RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK)
\r
11632 #define SCT_RES_O4RES_MASK (0x300U)
\r
11633 #define SCT_RES_O4RES_SHIFT (8U)
\r
11634 /*! O4RES - Effect of simultaneous set and clear on output 4.
\r
11635 * 0b00..No change.
\r
11636 * 0b01..Set output (or clear based on the SETCLR4 field in the OUTPUTDIRCTRL register).
\r
11637 * 0b10..Clear output (or set based on the SETCLR4 field).
\r
11638 * 0b11..Toggle output.
\r
11640 #define SCT_RES_O4RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK)
\r
11641 #define SCT_RES_O5RES_MASK (0xC00U)
\r
11642 #define SCT_RES_O5RES_SHIFT (10U)
\r
11643 /*! O5RES - Effect of simultaneous set and clear on output 5.
\r
11644 * 0b00..No change.
\r
11645 * 0b01..Set output (or clear based on the SETCLR5 field in the OUTPUTDIRCTRL register).
\r
11646 * 0b10..Clear output (or set based on the SETCLR5 field).
\r
11647 * 0b11..Toggle output.
\r
11649 #define SCT_RES_O5RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK)
\r
11650 #define SCT_RES_O6RES_MASK (0x3000U)
\r
11651 #define SCT_RES_O6RES_SHIFT (12U)
\r
11652 /*! O6RES - Effect of simultaneous set and clear on output 6.
\r
11653 * 0b00..No change.
\r
11654 * 0b01..Set output (or clear based on the SETCLR6 field in the OUTPUTDIRCTRL register).
\r
11655 * 0b10..Clear output (or set based on the SETCLR6 field).
\r
11656 * 0b11..Toggle output.
\r
11658 #define SCT_RES_O6RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK)
\r
11659 #define SCT_RES_O7RES_MASK (0xC000U)
\r
11660 #define SCT_RES_O7RES_SHIFT (14U)
\r
11661 /*! O7RES - Effect of simultaneous set and clear on output 7.
\r
11662 * 0b00..No change.
\r
11663 * 0b01..Set output (or clear based on the SETCLR7 field in the OUTPUTDIRCTRL register).
\r
11664 * 0b10..Clear output n (or set based on the SETCLR7 field).
\r
11665 * 0b11..Toggle output.
\r
11667 #define SCT_RES_O7RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK)
\r
11668 #define SCT_RES_O8RES_MASK (0x30000U)
\r
11669 #define SCT_RES_O8RES_SHIFT (16U)
\r
11670 /*! O8RES - Effect of simultaneous set and clear on output 8.
\r
11671 * 0b00..No change.
\r
11672 * 0b01..Set output (or clear based on the SETCLR8 field in the OUTPUTDIRCTRL register).
\r
11673 * 0b10..Clear output (or set based on the SETCLR8 field).
\r
11674 * 0b11..Toggle output.
\r
11676 #define SCT_RES_O8RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK)
\r
11677 #define SCT_RES_O9RES_MASK (0xC0000U)
\r
11678 #define SCT_RES_O9RES_SHIFT (18U)
\r
11679 /*! O9RES - Effect of simultaneous set and clear on output 9.
\r
11680 * 0b00..No change.
\r
11681 * 0b01..Set output (or clear based on the SETCLR9 field in the OUTPUTDIRCTRL register).
\r
11682 * 0b10..Clear output (or set based on the SETCLR9 field).
\r
11683 * 0b11..Toggle output.
\r
11685 #define SCT_RES_O9RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK)
\r
11686 #define SCT_RES_O10RES_MASK (0x300000U)
\r
11687 #define SCT_RES_O10RES_SHIFT (20U)
\r
11688 /*! O10RES - Effect of simultaneous set and clear on output 10.
\r
11689 * 0b00..No change.
\r
11690 * 0b01..Set output (or clear based on the SETCLR10 field in the OUTPUTDIRCTRL register).
\r
11691 * 0b10..Clear output (or set based on the SETCLR10 field).
\r
11692 * 0b11..Toggle output.
\r
11694 #define SCT_RES_O10RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O10RES_SHIFT)) & SCT_RES_O10RES_MASK)
\r
11695 #define SCT_RES_O11RES_MASK (0xC00000U)
\r
11696 #define SCT_RES_O11RES_SHIFT (22U)
\r
11697 /*! O11RES - Effect of simultaneous set and clear on output 11.
\r
11698 * 0b00..No change.
\r
11699 * 0b01..Set output (or clear based on the SETCLR11 field in the OUTPUTDIRCTRL register).
\r
11700 * 0b10..Clear output (or set based on the SETCLR11 field).
\r
11701 * 0b11..Toggle output.
\r
11703 #define SCT_RES_O11RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O11RES_SHIFT)) & SCT_RES_O11RES_MASK)
\r
11704 #define SCT_RES_O12RES_MASK (0x3000000U)
\r
11705 #define SCT_RES_O12RES_SHIFT (24U)
\r
11706 /*! O12RES - Effect of simultaneous set and clear on output 12.
\r
11707 * 0b00..No change.
\r
11708 * 0b01..Set output (or clear based on the SETCLR12 field in the OUTPUTDIRCTRL register).
\r
11709 * 0b10..Clear output (or set based on the SETCLR12 field).
\r
11710 * 0b11..Toggle output.
\r
11712 #define SCT_RES_O12RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O12RES_SHIFT)) & SCT_RES_O12RES_MASK)
\r
11713 #define SCT_RES_O13RES_MASK (0xC000000U)
\r
11714 #define SCT_RES_O13RES_SHIFT (26U)
\r
11715 /*! O13RES - Effect of simultaneous set and clear on output 13.
\r
11716 * 0b00..No change.
\r
11717 * 0b01..Set output (or clear based on the SETCLR13 field in the OUTPUTDIRCTRL register).
\r
11718 * 0b10..Clear output (or set based on the SETCLR13 field).
\r
11719 * 0b11..Toggle output.
\r
11721 #define SCT_RES_O13RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O13RES_SHIFT)) & SCT_RES_O13RES_MASK)
\r
11722 #define SCT_RES_O14RES_MASK (0x30000000U)
\r
11723 #define SCT_RES_O14RES_SHIFT (28U)
\r
11724 /*! O14RES - Effect of simultaneous set and clear on output 14.
\r
11725 * 0b00..No change.
\r
11726 * 0b01..Set output (or clear based on the SETCLR14 field in the OUTPUTDIRCTRL register).
\r
11727 * 0b10..Clear output (or set based on the SETCLR14 field).
\r
11728 * 0b11..Toggle output.
\r
11730 #define SCT_RES_O14RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O14RES_SHIFT)) & SCT_RES_O14RES_MASK)
\r
11731 #define SCT_RES_O15RES_MASK (0xC0000000U)
\r
11732 #define SCT_RES_O15RES_SHIFT (30U)
\r
11733 /*! O15RES - Effect of simultaneous set and clear on output 15.
\r
11734 * 0b00..No change.
\r
11735 * 0b01..Set output (or clear based on the SETCLR15 field in the OUTPUTDIRCTRL register).
\r
11736 * 0b10..Clear output (or set based on the SETCLR15 field).
\r
11737 * 0b11..Toggle output.
\r
11739 #define SCT_RES_O15RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O15RES_SHIFT)) & SCT_RES_O15RES_MASK)
\r
11742 /*! @name DMAREQ0 - SCT DMA request 0 register */
\r
11744 #define SCT_DMAREQ0_DEV_0_MASK (0xFFFFU)
\r
11745 #define SCT_DMAREQ0_DEV_0_SHIFT (0U)
\r
11746 /*! DEV_0 - If bit n is one, event n triggers DMA request 0 (event 0 = bit 0, event 1 = bit 1,
\r
11747 * etc.). The number of bits = number of events in this SCT.
\r
11749 #define SCT_DMAREQ0_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_0_SHIFT)) & SCT_DMAREQ0_DEV_0_MASK)
\r
11750 #define SCT_DMAREQ0_DRL0_MASK (0x40000000U)
\r
11751 #define SCT_DMAREQ0_DRL0_SHIFT (30U)
\r
11752 /*! DRL0 - A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers.
\r
11754 #define SCT_DMAREQ0_DRL0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRL0_SHIFT)) & SCT_DMAREQ0_DRL0_MASK)
\r
11755 #define SCT_DMAREQ0_DRQ0_MASK (0x80000000U)
\r
11756 #define SCT_DMAREQ0_DRQ0_SHIFT (31U)
\r
11757 /*! DRQ0 - This read-only bit indicates the state of DMA Request 0. Note that if the related DMA
\r
11758 * channel is enabled and properly set up, it is unlikely that software will see this flag, it will
\r
11759 * be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA
\r
11762 #define SCT_DMAREQ0_DRQ0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRQ0_SHIFT)) & SCT_DMAREQ0_DRQ0_MASK)
\r
11765 /*! @name DMAREQ1 - SCT DMA request 1 register */
\r
11767 #define SCT_DMAREQ1_DEV_1_MASK (0xFFFFU)
\r
11768 #define SCT_DMAREQ1_DEV_1_SHIFT (0U)
\r
11769 /*! DEV_1 - If bit n is one, event n triggers DMA request 1 (event 0 = bit 0, event 1 = bit 1,
\r
11770 * etc.). The number of bits = number of events in this SCT.
\r
11772 #define SCT_DMAREQ1_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_1_SHIFT)) & SCT_DMAREQ1_DEV_1_MASK)
\r
11773 #define SCT_DMAREQ1_DRL1_MASK (0x40000000U)
\r
11774 #define SCT_DMAREQ1_DRL1_SHIFT (30U)
\r
11775 /*! DRL1 - A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers.
\r
11777 #define SCT_DMAREQ1_DRL1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRL1_SHIFT)) & SCT_DMAREQ1_DRL1_MASK)
\r
11778 #define SCT_DMAREQ1_DRQ1_MASK (0x80000000U)
\r
11779 #define SCT_DMAREQ1_DRQ1_SHIFT (31U)
\r
11780 /*! DRQ1 - This read-only bit indicates the state of DMA Request 1. Note that if the related DMA
\r
11781 * channel is enabled and properly set up, it is unlikely that software will see this flag, it will
\r
11782 * be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA
\r
11785 #define SCT_DMAREQ1_DRQ1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRQ1_SHIFT)) & SCT_DMAREQ1_DRQ1_MASK)
\r
11788 /*! @name EVEN - SCT event interrupt enable register */
\r
11790 #define SCT_EVEN_IEN_MASK (0xFFFFU)
\r
11791 #define SCT_EVEN_IEN_SHIFT (0U)
\r
11792 /*! IEN - The SCT requests an interrupt when bit n of this register and the event flag register are
\r
11793 * both one (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in
\r
11796 #define SCT_EVEN_IEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK)
\r
11799 /*! @name EVFLAG - SCT event flag register */
\r
11801 #define SCT_EVFLAG_FLAG_MASK (0xFFFFU)
\r
11802 #define SCT_EVFLAG_FLAG_SHIFT (0U)
\r
11803 /*! FLAG - Bit n is one if event n has occurred since reset or a 1 was last written to this bit
\r
11804 * (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
\r
11806 #define SCT_EVFLAG_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK)
\r
11809 /*! @name CONEN - SCT conflict interrupt enable register */
\r
11811 #define SCT_CONEN_NCEN_MASK (0xFFFFU)
\r
11812 #define SCT_CONEN_NCEN_SHIFT (0U)
\r
11813 /*! NCEN - The SCT requests an interrupt when bit n of this register and the SCT conflict flag
\r
11814 * register are both one (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of
\r
11815 * outputs in this SCT.
\r
11817 #define SCT_CONEN_NCEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK)
\r
11820 /*! @name CONFLAG - SCT conflict flag register */
\r
11822 #define SCT_CONFLAG_NCFLAG_MASK (0xFFFFU)
\r
11823 #define SCT_CONFLAG_NCFLAG_SHIFT (0U)
\r
11824 /*! NCFLAG - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was
\r
11825 * last written to this bit (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits =
\r
11826 * number of outputs in this SCT.
\r
11828 #define SCT_CONFLAG_NCFLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK)
\r
11829 #define SCT_CONFLAG_BUSERRL_MASK (0x40000000U)
\r
11830 #define SCT_CONFLAG_BUSERRL_SHIFT (30U)
\r
11831 /*! BUSERRL - The most recent bus error from this SCT involved writing CTR L/Unified, STATE
\r
11832 * L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write
\r
11833 * to certain L and H registers can be half successful and half unsuccessful.
\r
11835 #define SCT_CONFLAG_BUSERRL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK)
\r
11836 #define SCT_CONFLAG_BUSERRH_MASK (0x80000000U)
\r
11837 #define SCT_CONFLAG_BUSERRH_SHIFT (31U)
\r
11838 /*! BUSERRH - The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or
\r
11839 * the Output register when the H counter was not halted.
\r
11841 #define SCT_CONFLAG_BUSERRH(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK)
\r
11844 /*! @name CAP - SCT capture register of capture channel */
\r
11846 #define SCT_CAP_CAPn_L_MASK (0xFFFFU)
\r
11847 #define SCT_CAP_CAPn_L_SHIFT (0U)
\r
11848 /*! CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured.
\r
11849 * When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last
\r
11852 #define SCT_CAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_L_SHIFT)) & SCT_CAP_CAPn_L_MASK)
\r
11853 #define SCT_CAP_CAPn_H_MASK (0xFFFF0000U)
\r
11854 #define SCT_CAP_CAPn_H_SHIFT (16U)
\r
11855 /*! CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured.
\r
11856 * When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last
\r
11859 #define SCT_CAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_H_SHIFT)) & SCT_CAP_CAPn_H_MASK)
\r
11862 /* The count of SCT_CAP */
\r
11863 #define SCT_CAP_COUNT (16U)
\r
11865 /*! @name MATCH - SCT match value register of match channels */
\r
11867 #define SCT_MATCH_MATCHn_L_MASK (0xFFFFU)
\r
11868 #define SCT_MATCH_MATCHn_L_SHIFT (0U)
\r
11869 /*! MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When
\r
11870 * UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified
\r
11873 #define SCT_MATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_L_SHIFT)) & SCT_MATCH_MATCHn_L_MASK)
\r
11874 #define SCT_MATCH_MATCHn_H_MASK (0xFFFF0000U)
\r
11875 #define SCT_MATCH_MATCHn_H_SHIFT (16U)
\r
11876 /*! MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When
\r
11877 * UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified
\r
11880 #define SCT_MATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_H_SHIFT)) & SCT_MATCH_MATCHn_H_MASK)
\r
11883 /* The count of SCT_MATCH */
\r
11884 #define SCT_MATCH_COUNT (16U)
\r
11886 /*! @name CAPCTRL - SCT capture control register */
\r
11888 #define SCT_CAPCTRL_CAPCONn_L_MASK (0xFFFFU)
\r
11889 #define SCT_CAPCTRL_CAPCONn_L_SHIFT (0U)
\r
11890 /*! CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1)
\r
11891 * register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of
\r
11892 * match/captures in this SCT.
\r
11894 #define SCT_CAPCTRL_CAPCONn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_L_SHIFT)) & SCT_CAPCTRL_CAPCONn_L_MASK)
\r
11895 #define SCT_CAPCTRL_CAPCONn_H_MASK (0xFFFF0000U)
\r
11896 #define SCT_CAPCTRL_CAPCONn_H_SHIFT (16U)
\r
11897 /*! CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event
\r
11898 * 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.
\r
11900 #define SCT_CAPCTRL_CAPCONn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_H_SHIFT)) & SCT_CAPCTRL_CAPCONn_H_MASK)
\r
11903 /* The count of SCT_CAPCTRL */
\r
11904 #define SCT_CAPCTRL_COUNT (16U)
\r
11906 /*! @name MATCHREL - SCT match reload value register */
\r
11908 #define SCT_MATCHREL_RELOADn_L_MASK (0xFFFFU)
\r
11909 #define SCT_MATCHREL_RELOADn_L_SHIFT (0U)
\r
11910 /*! RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register.
\r
11911 * When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn
\r
11914 #define SCT_MATCHREL_RELOADn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_L_SHIFT)) & SCT_MATCHREL_RELOADn_L_MASK)
\r
11915 #define SCT_MATCHREL_RELOADn_H_MASK (0xFFFF0000U)
\r
11916 #define SCT_MATCHREL_RELOADn_H_SHIFT (16U)
\r
11917 /*! RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When
\r
11918 * UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn
\r
11921 #define SCT_MATCHREL_RELOADn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_H_SHIFT)) & SCT_MATCHREL_RELOADn_H_MASK)
\r
11924 /* The count of SCT_MATCHREL */
\r
11925 #define SCT_MATCHREL_COUNT (16U)
\r
11927 /*! @name EV_STATE - SCT event state register 0 */
\r
11929 #define SCT_EV_STATE_STATEMSKn_MASK (0xFFFFU)
\r
11930 #define SCT_EV_STATE_STATEMSKn_SHIFT (0U)
\r
11931 /*! STATEMSKn - If bit m is one, event n happens in state m of the counter selected by the HEVENT
\r
11932 * bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of
\r
11933 * bits = number of states in this SCT.
\r
11935 #define SCT_EV_STATE_STATEMSKn(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_STATE_STATEMSKn_SHIFT)) & SCT_EV_STATE_STATEMSKn_MASK)
\r
11938 /* The count of SCT_EV_STATE */
\r
11939 #define SCT_EV_STATE_COUNT (16U)
\r
11941 /*! @name EV_CTRL - SCT event control register 0 */
\r
11943 #define SCT_EV_CTRL_MATCHSEL_MASK (0xFU)
\r
11944 #define SCT_EV_CTRL_MATCHSEL_SHIFT (0U)
\r
11945 /*! MATCHSEL - Selects the Match register associated with this event (if any). A match can occur
\r
11946 * only when the counter selected by the HEVENT bit is running.
\r
11948 #define SCT_EV_CTRL_MATCHSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHSEL_SHIFT)) & SCT_EV_CTRL_MATCHSEL_MASK)
\r
11949 #define SCT_EV_CTRL_HEVENT_MASK (0x10U)
\r
11950 #define SCT_EV_CTRL_HEVENT_SHIFT (4U)
\r
11951 /*! HEVENT - Select L/H counter. Do not set this bit if UNIFY = 1.
\r
11952 * 0b0..Selects the L state and the L match register selected by MATCHSEL.
\r
11953 * 0b1..Selects the H state and the H match register selected by MATCHSEL.
\r
11955 #define SCT_EV_CTRL_HEVENT(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_HEVENT_SHIFT)) & SCT_EV_CTRL_HEVENT_MASK)
\r
11956 #define SCT_EV_CTRL_OUTSEL_MASK (0x20U)
\r
11957 #define SCT_EV_CTRL_OUTSEL_SHIFT (5U)
\r
11958 /*! OUTSEL - Input/output select
\r
11959 * 0b0..Selects the inputs selected by IOSEL.
\r
11960 * 0b1..Selects the outputs selected by IOSEL.
\r
11962 #define SCT_EV_CTRL_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_OUTSEL_SHIFT)) & SCT_EV_CTRL_OUTSEL_MASK)
\r
11963 #define SCT_EV_CTRL_IOSEL_MASK (0x3C0U)
\r
11964 #define SCT_EV_CTRL_IOSEL_SHIFT (6U)
\r
11965 /*! IOSEL - Selects the input or output signal number associated with this event (if any). Do not
\r
11966 * select an input in this register if CKMODE is 1x. In this case the clock input is an implicit
\r
11967 * ingredient of every event.
\r
11969 #define SCT_EV_CTRL_IOSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOSEL_SHIFT)) & SCT_EV_CTRL_IOSEL_MASK)
\r
11970 #define SCT_EV_CTRL_IOCOND_MASK (0xC00U)
\r
11971 #define SCT_EV_CTRL_IOCOND_SHIFT (10U)
\r
11972 /*! IOCOND - Selects the I/O condition for event n. (The detection of edges on outputs lag the
\r
11973 * conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state
\r
11974 * detection, an input must have a minimum pulse width of at least one SCT clock period .
\r
11980 #define SCT_EV_CTRL_IOCOND(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOCOND_SHIFT)) & SCT_EV_CTRL_IOCOND_MASK)
\r
11981 #define SCT_EV_CTRL_COMBMODE_MASK (0x3000U)
\r
11982 #define SCT_EV_CTRL_COMBMODE_SHIFT (12U)
\r
11983 /*! COMBMODE - Selects how the specified match and I/O condition are used and combined.
\r
11984 * 0b00..OR. The event occurs when either the specified match or I/O condition occurs.
\r
11985 * 0b01..MATCH. Uses the specified match only.
\r
11986 * 0b10..IO. Uses the specified I/O condition only.
\r
11987 * 0b11..AND. The event occurs when the specified match and I/O condition occur simultaneously.
\r
11989 #define SCT_EV_CTRL_COMBMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_COMBMODE_SHIFT)) & SCT_EV_CTRL_COMBMODE_MASK)
\r
11990 #define SCT_EV_CTRL_STATELD_MASK (0x4000U)
\r
11991 #define SCT_EV_CTRL_STATELD_SHIFT (14U)
\r
11992 /*! STATELD - This bit controls how the STATEV value modifies the state selected by HEVENT when this
\r
11993 * event is the highest-numbered event occurring for that state.
\r
11994 * 0b0..STATEV value is added into STATE (the carry-out is ignored).
\r
11995 * 0b1..STATEV value is loaded into STATE.
\r
11997 #define SCT_EV_CTRL_STATELD(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATELD_SHIFT)) & SCT_EV_CTRL_STATELD_MASK)
\r
11998 #define SCT_EV_CTRL_STATEV_MASK (0xF8000U)
\r
11999 #define SCT_EV_CTRL_STATEV_SHIFT (15U)
\r
12000 /*! STATEV - This value is loaded into or added to the state selected by HEVENT, depending on
\r
12001 * STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and
\r
12002 * STATEV are both zero, there is no change to the STATE value.
\r
12004 #define SCT_EV_CTRL_STATEV(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATEV_SHIFT)) & SCT_EV_CTRL_STATEV_MASK)
\r
12005 #define SCT_EV_CTRL_MATCHMEM_MASK (0x100000U)
\r
12006 #define SCT_EV_CTRL_MATCHMEM_SHIFT (20U)
\r
12007 /*! MATCHMEM - If this bit is one and the COMBMODE field specifies a match component to the
\r
12008 * triggering of this event, then a match is considered to be active whenever the counter value is
\r
12009 * GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR
\r
12010 * EQUAL TO the match value when counting down. If this bit is zero, a match is only be active
\r
12011 * during the cycle when the counter is equal to the match value.
\r
12013 #define SCT_EV_CTRL_MATCHMEM(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHMEM_SHIFT)) & SCT_EV_CTRL_MATCHMEM_MASK)
\r
12014 #define SCT_EV_CTRL_DIRECTION_MASK (0x600000U)
\r
12015 #define SCT_EV_CTRL_DIRECTION_SHIFT (21U)
\r
12016 /*! DIRECTION - Direction qualifier for event generation. This field only applies when the counters
\r
12017 * are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
\r
12018 * 0b00..Direction independent. This event is triggered regardless of the count direction.
\r
12019 * 0b01..Counting up. This event is triggered only during up-counting when BIDIR = 1.
\r
12020 * 0b10..Counting down. This event is triggered only during down-counting when BIDIR = 1.
\r
12022 #define SCT_EV_CTRL_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_DIRECTION_SHIFT)) & SCT_EV_CTRL_DIRECTION_MASK)
\r
12025 /* The count of SCT_EV_CTRL */
\r
12026 #define SCT_EV_CTRL_COUNT (16U)
\r
12028 /*! @name OUT_SET - SCT output 0 set register */
\r
12030 #define SCT_OUT_SET_SET_MASK (0xFFFFU)
\r
12031 #define SCT_OUT_SET_SET_SHIFT (0U)
\r
12032 /*! SET - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output
\r
12033 * 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the
\r
12034 * counter is used in bi-directional mode, it is possible to reverse the action specified by the
\r
12035 * output set and clear registers when counting down, See the OUTPUTCTRL register.
\r
12037 #define SCT_OUT_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK)
\r
12040 /* The count of SCT_OUT_SET */
\r
12041 #define SCT_OUT_SET_COUNT (10U)
\r
12043 /*! @name OUT_CLR - SCT output 0 clear register */
\r
12045 #define SCT_OUT_CLR_CLR_MASK (0xFFFFU)
\r
12046 #define SCT_OUT_CLR_CLR_SHIFT (0U)
\r
12047 /*! CLR - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0
\r
12048 * = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the
\r
12049 * counter is used in bi-directional mode, it is possible to reverse the action specified by the
\r
12050 * output set and clear registers when counting down, See the OUTPUTCTRL register.
\r
12052 #define SCT_OUT_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK)
\r
12055 /* The count of SCT_OUT_CLR */
\r
12056 #define SCT_OUT_CLR_COUNT (10U)
\r
12061 */ /* end of group SCT_Register_Masks */
\r
12064 /* SCT - Peripheral instance base addresses */
\r
12065 /** Peripheral SCT0 base address */
\r
12066 #define SCT0_BASE (0x40085000u)
\r
12067 /** Peripheral SCT0 base pointer */
\r
12068 #define SCT0 ((SCT_Type *)SCT0_BASE)
\r
12069 /** Array initializer of SCT peripheral base addresses */
\r
12070 #define SCT_BASE_ADDRS { SCT0_BASE }
\r
12071 /** Array initializer of SCT peripheral base pointers */
\r
12072 #define SCT_BASE_PTRS { SCT0 }
\r
12073 /** Interrupt vectors for the SCT peripheral type */
\r
12074 #define SCT_IRQS { SCT0_IRQn }
\r
12078 */ /* end of group SCT_Peripheral_Access_Layer */
\r
12081 /* ----------------------------------------------------------------------------
\r
12082 -- SDIF Peripheral Access Layer
\r
12083 ---------------------------------------------------------------------------- */
\r
12086 * @addtogroup SDIF_Peripheral_Access_Layer SDIF Peripheral Access Layer
\r
12090 /** SDIF - Register Layout Typedef */
\r
12092 __IO uint32_t CTRL; /**< Control register, offset: 0x0 */
\r
12093 __IO uint32_t PWREN; /**< Power Enable register, offset: 0x4 */
\r
12094 __IO uint32_t CLKDIV; /**< Clock Divider register, offset: 0x8 */
\r
12095 uint8_t RESERVED_0[4];
\r
12096 __IO uint32_t CLKENA; /**< Clock Enable register, offset: 0x10 */
\r
12097 __IO uint32_t TMOUT; /**< Time-out register, offset: 0x14 */
\r
12098 __IO uint32_t CTYPE; /**< Card Type register, offset: 0x18 */
\r
12099 __IO uint32_t BLKSIZ; /**< Block Size register, offset: 0x1C */
\r
12100 __IO uint32_t BYTCNT; /**< Byte Count register, offset: 0x20 */
\r
12101 __IO uint32_t INTMASK; /**< Interrupt Mask register, offset: 0x24 */
\r
12102 __IO uint32_t CMDARG; /**< Command Argument register, offset: 0x28 */
\r
12103 __IO uint32_t CMD; /**< Command register, offset: 0x2C */
\r
12104 __I uint32_t RESP[4]; /**< Response register, array offset: 0x30, array step: 0x4 */
\r
12105 __I uint32_t MINTSTS; /**< Masked Interrupt Status register, offset: 0x40 */
\r
12106 __IO uint32_t RINTSTS; /**< Raw Interrupt Status register, offset: 0x44 */
\r
12107 __I uint32_t STATUS; /**< Status register, offset: 0x48 */
\r
12108 __IO uint32_t FIFOTH; /**< FIFO Threshold Watermark register, offset: 0x4C */
\r
12109 __I uint32_t CDETECT; /**< Card Detect register, offset: 0x50 */
\r
12110 __I uint32_t WRTPRT; /**< Write Protect register, offset: 0x54 */
\r
12111 uint8_t RESERVED_1[4];
\r
12112 __I uint32_t TCBCNT; /**< Transferred CIU Card Byte Count register, offset: 0x5C */
\r
12113 __I uint32_t TBBCNT; /**< Transferred Host to BIU-FIFO Byte Count register, offset: 0x60 */
\r
12114 __IO uint32_t DEBNCE; /**< Debounce Count register, offset: 0x64 */
\r
12115 uint8_t RESERVED_2[16];
\r
12116 __IO uint32_t RST_N; /**< Hardware Reset, offset: 0x78 */
\r
12117 uint8_t RESERVED_3[4];
\r
12118 __IO uint32_t BMOD; /**< Bus Mode register, offset: 0x80 */
\r
12119 __O uint32_t PLDMND; /**< Poll Demand register, offset: 0x84 */
\r
12120 __IO uint32_t DBADDR; /**< Descriptor List Base Address register, offset: 0x88 */
\r
12121 __IO uint32_t IDSTS; /**< Internal DMAC Status register, offset: 0x8C */
\r
12122 __IO uint32_t IDINTEN; /**< Internal DMAC Interrupt Enable register, offset: 0x90 */
\r
12123 __I uint32_t DSCADDR; /**< Current Host Descriptor Address register, offset: 0x94 */
\r
12124 __I uint32_t BUFADDR; /**< Current Buffer Descriptor Address register, offset: 0x98 */
\r
12125 uint8_t RESERVED_4[100];
\r
12126 __IO uint32_t CARDTHRCTL; /**< Card Threshold Control, offset: 0x100 */
\r
12127 __IO uint32_t BACKENDPWR; /**< Power control, offset: 0x104 */
\r
12128 uint8_t RESERVED_5[248];
\r
12129 __IO uint32_t FIFO[64]; /**< SDIF FIFO, array offset: 0x200, array step: 0x4 */
\r
12132 /* ----------------------------------------------------------------------------
\r
12133 -- SDIF Register Masks
\r
12134 ---------------------------------------------------------------------------- */
\r
12137 * @addtogroup SDIF_Register_Masks SDIF Register Masks
\r
12141 /*! @name CTRL - Control register */
\r
12143 #define SDIF_CTRL_CONTROLLER_RESET_MASK (0x1U)
\r
12144 #define SDIF_CTRL_CONTROLLER_RESET_SHIFT (0U)
\r
12145 /*! CONTROLLER_RESET - Controller reset.
\r
12147 #define SDIF_CTRL_CONTROLLER_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CONTROLLER_RESET_SHIFT)) & SDIF_CTRL_CONTROLLER_RESET_MASK)
\r
12148 #define SDIF_CTRL_FIFO_RESET_MASK (0x2U)
\r
12149 #define SDIF_CTRL_FIFO_RESET_SHIFT (1U)
\r
12150 /*! FIFO_RESET - Fifo reset.
\r
12152 #define SDIF_CTRL_FIFO_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_FIFO_RESET_SHIFT)) & SDIF_CTRL_FIFO_RESET_MASK)
\r
12153 #define SDIF_CTRL_DMA_RESET_MASK (0x4U)
\r
12154 #define SDIF_CTRL_DMA_RESET_SHIFT (2U)
\r
12155 /*! DMA_RESET - DMA reset.
\r
12157 #define SDIF_CTRL_DMA_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK)
\r
12158 #define SDIF_CTRL_INT_ENABLE_MASK (0x10U)
\r
12159 #define SDIF_CTRL_INT_ENABLE_SHIFT (4U)
\r
12160 /*! INT_ENABLE - Global interrupt enable/disable bit.
\r
12162 #define SDIF_CTRL_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_INT_ENABLE_SHIFT)) & SDIF_CTRL_INT_ENABLE_MASK)
\r
12163 #define SDIF_CTRL_READ_WAIT_MASK (0x40U)
\r
12164 #define SDIF_CTRL_READ_WAIT_SHIFT (6U)
\r
12165 /*! READ_WAIT - Read/wait.
\r
12167 #define SDIF_CTRL_READ_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_READ_WAIT_SHIFT)) & SDIF_CTRL_READ_WAIT_MASK)
\r
12168 #define SDIF_CTRL_SEND_IRQ_RESPONSE_MASK (0x80U)
\r
12169 #define SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT (7U)
\r
12170 /*! SEND_IRQ_RESPONSE - Send irq response.
\r
12172 #define SDIF_CTRL_SEND_IRQ_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT)) & SDIF_CTRL_SEND_IRQ_RESPONSE_MASK)
\r
12173 #define SDIF_CTRL_ABORT_READ_DATA_MASK (0x100U)
\r
12174 #define SDIF_CTRL_ABORT_READ_DATA_SHIFT (8U)
\r
12175 /*! ABORT_READ_DATA - Abort read data.
\r
12177 #define SDIF_CTRL_ABORT_READ_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_ABORT_READ_DATA_SHIFT)) & SDIF_CTRL_ABORT_READ_DATA_MASK)
\r
12178 #define SDIF_CTRL_SEND_CCSD_MASK (0x200U)
\r
12179 #define SDIF_CTRL_SEND_CCSD_SHIFT (9U)
\r
12180 /*! SEND_CCSD - Send ccsd.
\r
12182 #define SDIF_CTRL_SEND_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_CCSD_SHIFT)) & SDIF_CTRL_SEND_CCSD_MASK)
\r
12183 #define SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK (0x400U)
\r
12184 #define SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT (10U)
\r
12185 /*! SEND_AUTO_STOP_CCSD - Send auto stop ccsd.
\r
12187 #define SDIF_CTRL_SEND_AUTO_STOP_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT)) & SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK)
\r
12188 #define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK (0x800U)
\r
12189 #define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT (11U)
\r
12190 /*! CEATA_DEVICE_INTERRUPT_STATUS - CEATA device interrupt status.
\r
12192 #define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT)) & SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK)
\r
12193 #define SDIF_CTRL_CARD_VOLTAGE_A0_MASK (0x10000U)
\r
12194 #define SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT (16U)
\r
12195 /*! CARD_VOLTAGE_A0 - Controls the state of the SD_VOLT0 pin.
\r
12197 #define SDIF_CTRL_CARD_VOLTAGE_A0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A0_MASK)
\r
12198 #define SDIF_CTRL_CARD_VOLTAGE_A1_MASK (0x20000U)
\r
12199 #define SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT (17U)
\r
12200 /*! CARD_VOLTAGE_A1 - Controls the state of the SD_VOLT1 pin.
\r
12202 #define SDIF_CTRL_CARD_VOLTAGE_A1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A1_MASK)
\r
12203 #define SDIF_CTRL_CARD_VOLTAGE_A2_MASK (0x40000U)
\r
12204 #define SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT (18U)
\r
12205 /*! CARD_VOLTAGE_A2 - Controls the state of the SD_VOLT2 pin.
\r
12207 #define SDIF_CTRL_CARD_VOLTAGE_A2(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A2_MASK)
\r
12208 #define SDIF_CTRL_USE_INTERNAL_DMAC_MASK (0x2000000U)
\r
12209 #define SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT (25U)
\r
12210 /*! USE_INTERNAL_DMAC - SD/MMC DMA use.
\r
12212 #define SDIF_CTRL_USE_INTERNAL_DMAC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT)) & SDIF_CTRL_USE_INTERNAL_DMAC_MASK)
\r
12215 /*! @name PWREN - Power Enable register */
\r
12217 #define SDIF_PWREN_POWER_ENABLE_MASK (0x1U)
\r
12218 #define SDIF_PWREN_POWER_ENABLE_SHIFT (0U)
\r
12219 /*! POWER_ENABLE - Power on/off switch for card; once power is turned on, software should wait for
\r
12220 * regulator/switch ramp-up time before trying to initialize card.
\r
12222 #define SDIF_PWREN_POWER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE_SHIFT)) & SDIF_PWREN_POWER_ENABLE_MASK)
\r
12225 /*! @name CLKDIV - Clock Divider register */
\r
12227 #define SDIF_CLKDIV_CLK_DIVIDER0_MASK (0xFFU)
\r
12228 #define SDIF_CLKDIV_CLK_DIVIDER0_SHIFT (0U)
\r
12229 /*! CLK_DIVIDER0 - Clock divider-0 value.
\r
12231 #define SDIF_CLKDIV_CLK_DIVIDER0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKDIV_CLK_DIVIDER0_SHIFT)) & SDIF_CLKDIV_CLK_DIVIDER0_MASK)
\r
12234 /*! @name CLKENA - Clock Enable register */
\r
12236 #define SDIF_CLKENA_CCLK_ENABLE_MASK (0x1U)
\r
12237 #define SDIF_CLKENA_CCLK_ENABLE_SHIFT (0U)
\r
12238 /*! CCLK_ENABLE - Clock-enable control for SD card clock.
\r
12240 #define SDIF_CLKENA_CCLK_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK_ENABLE_MASK)
\r
12241 #define SDIF_CLKENA_CCLK_LOW_POWER_MASK (0x10000U)
\r
12242 #define SDIF_CLKENA_CCLK_LOW_POWER_SHIFT (16U)
\r
12243 /*! CCLK_LOW_POWER - Low-power control for SD card clock.
\r
12245 #define SDIF_CLKENA_CCLK_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK_LOW_POWER_MASK)
\r
12248 /*! @name TMOUT - Time-out register */
\r
12250 #define SDIF_TMOUT_RESPONSE_TIMEOUT_MASK (0xFFU)
\r
12251 #define SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT (0U)
\r
12252 /*! RESPONSE_TIMEOUT - Response time-out value.
\r
12254 #define SDIF_TMOUT_RESPONSE_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT)) & SDIF_TMOUT_RESPONSE_TIMEOUT_MASK)
\r
12255 #define SDIF_TMOUT_DATA_TIMEOUT_MASK (0xFFFFFF00U)
\r
12256 #define SDIF_TMOUT_DATA_TIMEOUT_SHIFT (8U)
\r
12257 /*! DATA_TIMEOUT - Value for card Data Read time-out; same value also used for Data Starvation by Host time-out.
\r
12259 #define SDIF_TMOUT_DATA_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_DATA_TIMEOUT_SHIFT)) & SDIF_TMOUT_DATA_TIMEOUT_MASK)
\r
12262 /*! @name CTYPE - Card Type register */
\r
12264 #define SDIF_CTYPE_CARD_WIDTH0_MASK (0x1U)
\r
12265 #define SDIF_CTYPE_CARD_WIDTH0_SHIFT (0U)
\r
12266 /*! CARD_WIDTH0 - Indicates if card is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit
\r
12267 * modes only work when 8-bit mode in CARD_WIDTH1 is not enabled (bit 16 in this register is set to
\r
12270 #define SDIF_CTYPE_CARD_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD_WIDTH0_MASK)
\r
12271 #define SDIF_CTYPE_CARD_WIDTH1_MASK (0x10000U)
\r
12272 #define SDIF_CTYPE_CARD_WIDTH1_SHIFT (16U)
\r
12273 /*! CARD_WIDTH1 - Indicates if card is 8-bit: 0 - Non 8-bit mode 1 - 8-bit mode.
\r
12275 #define SDIF_CTYPE_CARD_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD_WIDTH1_MASK)
\r
12278 /*! @name BLKSIZ - Block Size register */
\r
12280 #define SDIF_BLKSIZ_BLOCK_SIZE_MASK (0xFFFFU)
\r
12281 #define SDIF_BLKSIZ_BLOCK_SIZE_SHIFT (0U)
\r
12282 /*! BLOCK_SIZE - Block size.
\r
12284 #define SDIF_BLKSIZ_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BLKSIZ_BLOCK_SIZE_SHIFT)) & SDIF_BLKSIZ_BLOCK_SIZE_MASK)
\r
12287 /*! @name BYTCNT - Byte Count register */
\r
12289 #define SDIF_BYTCNT_BYTE_COUNT_MASK (0xFFFFFFFFU)
\r
12290 #define SDIF_BYTCNT_BYTE_COUNT_SHIFT (0U)
\r
12291 /*! BYTE_COUNT - Number of bytes to be transferred; should be integer multiple of Block Size for block transfers.
\r
12293 #define SDIF_BYTCNT_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BYTCNT_BYTE_COUNT_SHIFT)) & SDIF_BYTCNT_BYTE_COUNT_MASK)
\r
12296 /*! @name INTMASK - Interrupt Mask register */
\r
12298 #define SDIF_INTMASK_CDET_MASK (0x1U)
\r
12299 #define SDIF_INTMASK_CDET_SHIFT (0U)
\r
12300 /*! CDET - Card detect.
\r
12302 #define SDIF_INTMASK_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDET_SHIFT)) & SDIF_INTMASK_CDET_MASK)
\r
12303 #define SDIF_INTMASK_RE_MASK (0x2U)
\r
12304 #define SDIF_INTMASK_RE_SHIFT (1U)
\r
12305 /*! RE - Response error.
\r
12307 #define SDIF_INTMASK_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RE_SHIFT)) & SDIF_INTMASK_RE_MASK)
\r
12308 #define SDIF_INTMASK_CDONE_MASK (0x4U)
\r
12309 #define SDIF_INTMASK_CDONE_SHIFT (2U)
\r
12310 /*! CDONE - Command done.
\r
12312 #define SDIF_INTMASK_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDONE_SHIFT)) & SDIF_INTMASK_CDONE_MASK)
\r
12313 #define SDIF_INTMASK_DTO_MASK (0x8U)
\r
12314 #define SDIF_INTMASK_DTO_SHIFT (3U)
\r
12315 /*! DTO - Data transfer over.
\r
12317 #define SDIF_INTMASK_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DTO_SHIFT)) & SDIF_INTMASK_DTO_MASK)
\r
12318 #define SDIF_INTMASK_TXDR_MASK (0x10U)
\r
12319 #define SDIF_INTMASK_TXDR_SHIFT (4U)
\r
12320 /*! TXDR - Transmit FIFO data request.
\r
12322 #define SDIF_INTMASK_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_TXDR_SHIFT)) & SDIF_INTMASK_TXDR_MASK)
\r
12323 #define SDIF_INTMASK_RXDR_MASK (0x20U)
\r
12324 #define SDIF_INTMASK_RXDR_SHIFT (5U)
\r
12325 /*! RXDR - Receive FIFO data request.
\r
12327 #define SDIF_INTMASK_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RXDR_SHIFT)) & SDIF_INTMASK_RXDR_MASK)
\r
12328 #define SDIF_INTMASK_RCRC_MASK (0x40U)
\r
12329 #define SDIF_INTMASK_RCRC_SHIFT (6U)
\r
12330 /*! RCRC - Response CRC error.
\r
12332 #define SDIF_INTMASK_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RCRC_SHIFT)) & SDIF_INTMASK_RCRC_MASK)
\r
12333 #define SDIF_INTMASK_DCRC_MASK (0x80U)
\r
12334 #define SDIF_INTMASK_DCRC_SHIFT (7U)
\r
12335 /*! DCRC - Data CRC error.
\r
12337 #define SDIF_INTMASK_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DCRC_SHIFT)) & SDIF_INTMASK_DCRC_MASK)
\r
12338 #define SDIF_INTMASK_RTO_MASK (0x100U)
\r
12339 #define SDIF_INTMASK_RTO_SHIFT (8U)
\r
12340 /*! RTO - Response time-out.
\r
12342 #define SDIF_INTMASK_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RTO_SHIFT)) & SDIF_INTMASK_RTO_MASK)
\r
12343 #define SDIF_INTMASK_DRTO_MASK (0x200U)
\r
12344 #define SDIF_INTMASK_DRTO_SHIFT (9U)
\r
12345 /*! DRTO - Data read time-out.
\r
12347 #define SDIF_INTMASK_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DRTO_SHIFT)) & SDIF_INTMASK_DRTO_MASK)
\r
12348 #define SDIF_INTMASK_HTO_MASK (0x400U)
\r
12349 #define SDIF_INTMASK_HTO_SHIFT (10U)
\r
12350 /*! HTO - Data starvation-by-host time-out (HTO).
\r
12352 #define SDIF_INTMASK_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HTO_SHIFT)) & SDIF_INTMASK_HTO_MASK)
\r
12353 #define SDIF_INTMASK_FRUN_MASK (0x800U)
\r
12354 #define SDIF_INTMASK_FRUN_SHIFT (11U)
\r
12355 /*! FRUN - FIFO underrun/overrun error.
\r
12357 #define SDIF_INTMASK_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_FRUN_SHIFT)) & SDIF_INTMASK_FRUN_MASK)
\r
12358 #define SDIF_INTMASK_HLE_MASK (0x1000U)
\r
12359 #define SDIF_INTMASK_HLE_SHIFT (12U)
\r
12360 /*! HLE - Hardware locked write error.
\r
12362 #define SDIF_INTMASK_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HLE_SHIFT)) & SDIF_INTMASK_HLE_MASK)
\r
12363 #define SDIF_INTMASK_SBE_MASK (0x2000U)
\r
12364 #define SDIF_INTMASK_SBE_SHIFT (13U)
\r
12365 /*! SBE - Start-bit error.
\r
12367 #define SDIF_INTMASK_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SBE_SHIFT)) & SDIF_INTMASK_SBE_MASK)
\r
12368 #define SDIF_INTMASK_ACD_MASK (0x4000U)
\r
12369 #define SDIF_INTMASK_ACD_SHIFT (14U)
\r
12370 /*! ACD - Auto command done.
\r
12372 #define SDIF_INTMASK_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_ACD_SHIFT)) & SDIF_INTMASK_ACD_MASK)
\r
12373 #define SDIF_INTMASK_EBE_MASK (0x8000U)
\r
12374 #define SDIF_INTMASK_EBE_SHIFT (15U)
\r
12375 /*! EBE - End-bit error (read)/Write no CRC.
\r
12377 #define SDIF_INTMASK_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_EBE_SHIFT)) & SDIF_INTMASK_EBE_MASK)
\r
12378 #define SDIF_INTMASK_SDIO_INT_MASK_MASK (0x10000U)
\r
12379 #define SDIF_INTMASK_SDIO_INT_MASK_SHIFT (16U)
\r
12380 /*! SDIO_INT_MASK - Mask SDIO interrupt.
\r
12382 #define SDIF_INTMASK_SDIO_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SDIO_INT_MASK_SHIFT)) & SDIF_INTMASK_SDIO_INT_MASK_MASK)
\r
12385 /*! @name CMDARG - Command Argument register */
\r
12387 #define SDIF_CMDARG_CMD_ARG_MASK (0xFFFFFFFFU)
\r
12388 #define SDIF_CMDARG_CMD_ARG_SHIFT (0U)
\r
12389 /*! CMD_ARG - Value indicates command argument to be passed to card.
\r
12391 #define SDIF_CMDARG_CMD_ARG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMDARG_CMD_ARG_SHIFT)) & SDIF_CMDARG_CMD_ARG_MASK)
\r
12394 /*! @name CMD - Command register */
\r
12396 #define SDIF_CMD_CMD_INDEX_MASK (0x3FU)
\r
12397 #define SDIF_CMD_CMD_INDEX_SHIFT (0U)
\r
12398 /*! CMD_INDEX - Command index.
\r
12400 #define SDIF_CMD_CMD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CMD_INDEX_SHIFT)) & SDIF_CMD_CMD_INDEX_MASK)
\r
12401 #define SDIF_CMD_RESPONSE_EXPECT_MASK (0x40U)
\r
12402 #define SDIF_CMD_RESPONSE_EXPECT_SHIFT (6U)
\r
12403 /*! RESPONSE_EXPECT - Response expect.
\r
12405 #define SDIF_CMD_RESPONSE_EXPECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_EXPECT_SHIFT)) & SDIF_CMD_RESPONSE_EXPECT_MASK)
\r
12406 #define SDIF_CMD_RESPONSE_LENGTH_MASK (0x80U)
\r
12407 #define SDIF_CMD_RESPONSE_LENGTH_SHIFT (7U)
\r
12408 /*! RESPONSE_LENGTH - Response length.
\r
12410 #define SDIF_CMD_RESPONSE_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_LENGTH_SHIFT)) & SDIF_CMD_RESPONSE_LENGTH_MASK)
\r
12411 #define SDIF_CMD_CHECK_RESPONSE_CRC_MASK (0x100U)
\r
12412 #define SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT (8U)
\r
12413 /*! CHECK_RESPONSE_CRC - Check response CRC.
\r
12415 #define SDIF_CMD_CHECK_RESPONSE_CRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT)) & SDIF_CMD_CHECK_RESPONSE_CRC_MASK)
\r
12416 #define SDIF_CMD_DATA_EXPECTED_MASK (0x200U)
\r
12417 #define SDIF_CMD_DATA_EXPECTED_SHIFT (9U)
\r
12418 /*! DATA_EXPECTED - Data expected.
\r
12420 #define SDIF_CMD_DATA_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DATA_EXPECTED_SHIFT)) & SDIF_CMD_DATA_EXPECTED_MASK)
\r
12421 #define SDIF_CMD_READ_WRITE_MASK (0x400U)
\r
12422 #define SDIF_CMD_READ_WRITE_SHIFT (10U)
\r
12423 /*! READ_WRITE - read/write.
\r
12425 #define SDIF_CMD_READ_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_WRITE_SHIFT)) & SDIF_CMD_READ_WRITE_MASK)
\r
12426 #define SDIF_CMD_TRANSFER_MODE_MASK (0x800U)
\r
12427 #define SDIF_CMD_TRANSFER_MODE_SHIFT (11U)
\r
12428 /*! TRANSFER_MODE - Transfer mode.
\r
12430 #define SDIF_CMD_TRANSFER_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_TRANSFER_MODE_SHIFT)) & SDIF_CMD_TRANSFER_MODE_MASK)
\r
12431 #define SDIF_CMD_SEND_AUTO_STOP_MASK (0x1000U)
\r
12432 #define SDIF_CMD_SEND_AUTO_STOP_SHIFT (12U)
\r
12433 /*! SEND_AUTO_STOP - Send auto stop.
\r
12435 #define SDIF_CMD_SEND_AUTO_STOP(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_AUTO_STOP_SHIFT)) & SDIF_CMD_SEND_AUTO_STOP_MASK)
\r
12436 #define SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK (0x2000U)
\r
12437 #define SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT (13U)
\r
12438 /*! WAIT_PRVDATA_COMPLETE - Wait prvdata complete.
\r
12440 #define SDIF_CMD_WAIT_PRVDATA_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT)) & SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK)
\r
12441 #define SDIF_CMD_STOP_ABORT_CMD_MASK (0x4000U)
\r
12442 #define SDIF_CMD_STOP_ABORT_CMD_SHIFT (14U)
\r
12443 /*! STOP_ABORT_CMD - Stop abort command.
\r
12445 #define SDIF_CMD_STOP_ABORT_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_STOP_ABORT_CMD_SHIFT)) & SDIF_CMD_STOP_ABORT_CMD_MASK)
\r
12446 #define SDIF_CMD_SEND_INITIALIZATION_MASK (0x8000U)
\r
12447 #define SDIF_CMD_SEND_INITIALIZATION_SHIFT (15U)
\r
12448 /*! SEND_INITIALIZATION - Send initialization.
\r
12450 #define SDIF_CMD_SEND_INITIALIZATION(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_INITIALIZATION_SHIFT)) & SDIF_CMD_SEND_INITIALIZATION_MASK)
\r
12451 #define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK (0x200000U)
\r
12452 #define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT (21U)
\r
12453 /*! UPDATE_CLOCK_REGISTERS_ONLY - Update clock registers only.
\r
12455 #define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT)) & SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK)
\r
12456 #define SDIF_CMD_READ_CEATA_DEVICE_MASK (0x400000U)
\r
12457 #define SDIF_CMD_READ_CEATA_DEVICE_SHIFT (22U)
\r
12458 /*! READ_CEATA_DEVICE - Read ceata device.
\r
12460 #define SDIF_CMD_READ_CEATA_DEVICE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_CEATA_DEVICE_SHIFT)) & SDIF_CMD_READ_CEATA_DEVICE_MASK)
\r
12461 #define SDIF_CMD_CCS_EXPECTED_MASK (0x800000U)
\r
12462 #define SDIF_CMD_CCS_EXPECTED_SHIFT (23U)
\r
12463 /*! CCS_EXPECTED - CCS expected.
\r
12465 #define SDIF_CMD_CCS_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CCS_EXPECTED_SHIFT)) & SDIF_CMD_CCS_EXPECTED_MASK)
\r
12466 #define SDIF_CMD_ENABLE_BOOT_MASK (0x1000000U)
\r
12467 #define SDIF_CMD_ENABLE_BOOT_SHIFT (24U)
\r
12468 /*! ENABLE_BOOT - Enable Boot - this bit should be set only for mandatory boot mode.
\r
12470 #define SDIF_CMD_ENABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_ENABLE_BOOT_SHIFT)) & SDIF_CMD_ENABLE_BOOT_MASK)
\r
12471 #define SDIF_CMD_EXPECT_BOOT_ACK_MASK (0x2000000U)
\r
12472 #define SDIF_CMD_EXPECT_BOOT_ACK_SHIFT (25U)
\r
12473 /*! EXPECT_BOOT_ACK - Expect Boot Acknowledge.
\r
12475 #define SDIF_CMD_EXPECT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_EXPECT_BOOT_ACK_SHIFT)) & SDIF_CMD_EXPECT_BOOT_ACK_MASK)
\r
12476 #define SDIF_CMD_DISABLE_BOOT_MASK (0x4000000U)
\r
12477 #define SDIF_CMD_DISABLE_BOOT_SHIFT (26U)
\r
12478 /*! DISABLE_BOOT - Disable Boot.
\r
12480 #define SDIF_CMD_DISABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DISABLE_BOOT_SHIFT)) & SDIF_CMD_DISABLE_BOOT_MASK)
\r
12481 #define SDIF_CMD_BOOT_MODE_MASK (0x8000000U)
\r
12482 #define SDIF_CMD_BOOT_MODE_SHIFT (27U)
\r
12483 /*! BOOT_MODE - Boot Mode.
\r
12485 #define SDIF_CMD_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_BOOT_MODE_SHIFT)) & SDIF_CMD_BOOT_MODE_MASK)
\r
12486 #define SDIF_CMD_VOLT_SWITCH_MASK (0x10000000U)
\r
12487 #define SDIF_CMD_VOLT_SWITCH_SHIFT (28U)
\r
12488 /*! VOLT_SWITCH - Voltage switch bit.
\r
12490 #define SDIF_CMD_VOLT_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_VOLT_SWITCH_SHIFT)) & SDIF_CMD_VOLT_SWITCH_MASK)
\r
12491 #define SDIF_CMD_USE_HOLD_REG_MASK (0x20000000U)
\r
12492 #define SDIF_CMD_USE_HOLD_REG_SHIFT (29U)
\r
12493 /*! USE_HOLD_REG - Use Hold Register.
\r
12495 #define SDIF_CMD_USE_HOLD_REG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_USE_HOLD_REG_SHIFT)) & SDIF_CMD_USE_HOLD_REG_MASK)
\r
12496 #define SDIF_CMD_START_CMD_MASK (0x80000000U)
\r
12497 #define SDIF_CMD_START_CMD_SHIFT (31U)
\r
12498 /*! START_CMD - Start command.
\r
12500 #define SDIF_CMD_START_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_START_CMD_SHIFT)) & SDIF_CMD_START_CMD_MASK)
\r
12503 /*! @name RESP - Response register */
\r
12505 #define SDIF_RESP_RESPONSE_MASK (0xFFFFFFFFU)
\r
12506 #define SDIF_RESP_RESPONSE_SHIFT (0U)
\r
12507 /*! RESPONSE - Bits of response.
\r
12509 #define SDIF_RESP_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RESP_RESPONSE_SHIFT)) & SDIF_RESP_RESPONSE_MASK)
\r
12512 /* The count of SDIF_RESP */
\r
12513 #define SDIF_RESP_COUNT (4U)
\r
12515 /*! @name MINTSTS - Masked Interrupt Status register */
\r
12517 #define SDIF_MINTSTS_CDET_MASK (0x1U)
\r
12518 #define SDIF_MINTSTS_CDET_SHIFT (0U)
\r
12519 /*! CDET - Card detect.
\r
12521 #define SDIF_MINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDET_SHIFT)) & SDIF_MINTSTS_CDET_MASK)
\r
12522 #define SDIF_MINTSTS_RE_MASK (0x2U)
\r
12523 #define SDIF_MINTSTS_RE_SHIFT (1U)
\r
12524 /*! RE - Response error.
\r
12526 #define SDIF_MINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RE_SHIFT)) & SDIF_MINTSTS_RE_MASK)
\r
12527 #define SDIF_MINTSTS_CDONE_MASK (0x4U)
\r
12528 #define SDIF_MINTSTS_CDONE_SHIFT (2U)
\r
12529 /*! CDONE - Command done.
\r
12531 #define SDIF_MINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDONE_SHIFT)) & SDIF_MINTSTS_CDONE_MASK)
\r
12532 #define SDIF_MINTSTS_DTO_MASK (0x8U)
\r
12533 #define SDIF_MINTSTS_DTO_SHIFT (3U)
\r
12534 /*! DTO - Data transfer over.
\r
12536 #define SDIF_MINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DTO_SHIFT)) & SDIF_MINTSTS_DTO_MASK)
\r
12537 #define SDIF_MINTSTS_TXDR_MASK (0x10U)
\r
12538 #define SDIF_MINTSTS_TXDR_SHIFT (4U)
\r
12539 /*! TXDR - Transmit FIFO data request.
\r
12541 #define SDIF_MINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_TXDR_SHIFT)) & SDIF_MINTSTS_TXDR_MASK)
\r
12542 #define SDIF_MINTSTS_RXDR_MASK (0x20U)
\r
12543 #define SDIF_MINTSTS_RXDR_SHIFT (5U)
\r
12544 /*! RXDR - Receive FIFO data request.
\r
12546 #define SDIF_MINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RXDR_SHIFT)) & SDIF_MINTSTS_RXDR_MASK)
\r
12547 #define SDIF_MINTSTS_RCRC_MASK (0x40U)
\r
12548 #define SDIF_MINTSTS_RCRC_SHIFT (6U)
\r
12549 /*! RCRC - Response CRC error.
\r
12551 #define SDIF_MINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RCRC_SHIFT)) & SDIF_MINTSTS_RCRC_MASK)
\r
12552 #define SDIF_MINTSTS_DCRC_MASK (0x80U)
\r
12553 #define SDIF_MINTSTS_DCRC_SHIFT (7U)
\r
12554 /*! DCRC - Data CRC error.
\r
12556 #define SDIF_MINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DCRC_SHIFT)) & SDIF_MINTSTS_DCRC_MASK)
\r
12557 #define SDIF_MINTSTS_RTO_MASK (0x100U)
\r
12558 #define SDIF_MINTSTS_RTO_SHIFT (8U)
\r
12559 /*! RTO - Response time-out.
\r
12561 #define SDIF_MINTSTS_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RTO_SHIFT)) & SDIF_MINTSTS_RTO_MASK)
\r
12562 #define SDIF_MINTSTS_DRTO_MASK (0x200U)
\r
12563 #define SDIF_MINTSTS_DRTO_SHIFT (9U)
\r
12564 /*! DRTO - Data read time-out.
\r
12566 #define SDIF_MINTSTS_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DRTO_SHIFT)) & SDIF_MINTSTS_DRTO_MASK)
\r
12567 #define SDIF_MINTSTS_HTO_MASK (0x400U)
\r
12568 #define SDIF_MINTSTS_HTO_SHIFT (10U)
\r
12569 /*! HTO - Data starvation-by-host time-out (HTO).
\r
12571 #define SDIF_MINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HTO_SHIFT)) & SDIF_MINTSTS_HTO_MASK)
\r
12572 #define SDIF_MINTSTS_FRUN_MASK (0x800U)
\r
12573 #define SDIF_MINTSTS_FRUN_SHIFT (11U)
\r
12574 /*! FRUN - FIFO underrun/overrun error.
\r
12576 #define SDIF_MINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_FRUN_SHIFT)) & SDIF_MINTSTS_FRUN_MASK)
\r
12577 #define SDIF_MINTSTS_HLE_MASK (0x1000U)
\r
12578 #define SDIF_MINTSTS_HLE_SHIFT (12U)
\r
12579 /*! HLE - Hardware locked write error.
\r
12581 #define SDIF_MINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HLE_SHIFT)) & SDIF_MINTSTS_HLE_MASK)
\r
12582 #define SDIF_MINTSTS_SBE_MASK (0x2000U)
\r
12583 #define SDIF_MINTSTS_SBE_SHIFT (13U)
\r
12584 /*! SBE - Start-bit error.
\r
12586 #define SDIF_MINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SBE_SHIFT)) & SDIF_MINTSTS_SBE_MASK)
\r
12587 #define SDIF_MINTSTS_ACD_MASK (0x4000U)
\r
12588 #define SDIF_MINTSTS_ACD_SHIFT (14U)
\r
12589 /*! ACD - Auto command done.
\r
12591 #define SDIF_MINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_ACD_SHIFT)) & SDIF_MINTSTS_ACD_MASK)
\r
12592 #define SDIF_MINTSTS_EBE_MASK (0x8000U)
\r
12593 #define SDIF_MINTSTS_EBE_SHIFT (15U)
\r
12594 /*! EBE - End-bit error (read)/write no CRC.
\r
12596 #define SDIF_MINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_EBE_SHIFT)) & SDIF_MINTSTS_EBE_MASK)
\r
12597 #define SDIF_MINTSTS_SDIO_INTERRUPT_MASK (0x10000U)
\r
12598 #define SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT (16U)
\r
12599 /*! SDIO_INTERRUPT - Interrupt from SDIO card.
\r
12601 #define SDIF_MINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_MINTSTS_SDIO_INTERRUPT_MASK)
\r
12604 /*! @name RINTSTS - Raw Interrupt Status register */
\r
12606 #define SDIF_RINTSTS_CDET_MASK (0x1U)
\r
12607 #define SDIF_RINTSTS_CDET_SHIFT (0U)
\r
12608 /*! CDET - Card detect.
\r
12610 #define SDIF_RINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDET_SHIFT)) & SDIF_RINTSTS_CDET_MASK)
\r
12611 #define SDIF_RINTSTS_RE_MASK (0x2U)
\r
12612 #define SDIF_RINTSTS_RE_SHIFT (1U)
\r
12613 /*! RE - Response error.
\r
12615 #define SDIF_RINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RE_SHIFT)) & SDIF_RINTSTS_RE_MASK)
\r
12616 #define SDIF_RINTSTS_CDONE_MASK (0x4U)
\r
12617 #define SDIF_RINTSTS_CDONE_SHIFT (2U)
\r
12618 /*! CDONE - Command done.
\r
12620 #define SDIF_RINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDONE_SHIFT)) & SDIF_RINTSTS_CDONE_MASK)
\r
12621 #define SDIF_RINTSTS_DTO_MASK (0x8U)
\r
12622 #define SDIF_RINTSTS_DTO_SHIFT (3U)
\r
12623 /*! DTO - Data transfer over.
\r
12625 #define SDIF_RINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DTO_SHIFT)) & SDIF_RINTSTS_DTO_MASK)
\r
12626 #define SDIF_RINTSTS_TXDR_MASK (0x10U)
\r
12627 #define SDIF_RINTSTS_TXDR_SHIFT (4U)
\r
12628 /*! TXDR - Transmit FIFO data request.
\r
12630 #define SDIF_RINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_TXDR_SHIFT)) & SDIF_RINTSTS_TXDR_MASK)
\r
12631 #define SDIF_RINTSTS_RXDR_MASK (0x20U)
\r
12632 #define SDIF_RINTSTS_RXDR_SHIFT (5U)
\r
12633 /*! RXDR - Receive FIFO data request.
\r
12635 #define SDIF_RINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RXDR_SHIFT)) & SDIF_RINTSTS_RXDR_MASK)
\r
12636 #define SDIF_RINTSTS_RCRC_MASK (0x40U)
\r
12637 #define SDIF_RINTSTS_RCRC_SHIFT (6U)
\r
12638 /*! RCRC - Response CRC error.
\r
12640 #define SDIF_RINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RCRC_SHIFT)) & SDIF_RINTSTS_RCRC_MASK)
\r
12641 #define SDIF_RINTSTS_DCRC_MASK (0x80U)
\r
12642 #define SDIF_RINTSTS_DCRC_SHIFT (7U)
\r
12643 /*! DCRC - Data CRC error.
\r
12645 #define SDIF_RINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DCRC_SHIFT)) & SDIF_RINTSTS_DCRC_MASK)
\r
12646 #define SDIF_RINTSTS_RTO_BAR_MASK (0x100U)
\r
12647 #define SDIF_RINTSTS_RTO_BAR_SHIFT (8U)
\r
12648 /*! RTO_BAR - Response time-out (RTO)/Boot Ack Received (BAR).
\r
12650 #define SDIF_RINTSTS_RTO_BAR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RTO_BAR_SHIFT)) & SDIF_RINTSTS_RTO_BAR_MASK)
\r
12651 #define SDIF_RINTSTS_DRTO_BDS_MASK (0x200U)
\r
12652 #define SDIF_RINTSTS_DRTO_BDS_SHIFT (9U)
\r
12653 /*! DRTO_BDS - Data read time-out (DRTO)/Boot Data Start (BDS).
\r
12655 #define SDIF_RINTSTS_DRTO_BDS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DRTO_BDS_SHIFT)) & SDIF_RINTSTS_DRTO_BDS_MASK)
\r
12656 #define SDIF_RINTSTS_HTO_MASK (0x400U)
\r
12657 #define SDIF_RINTSTS_HTO_SHIFT (10U)
\r
12658 /*! HTO - Data starvation-by-host time-out (HTO).
\r
12660 #define SDIF_RINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HTO_SHIFT)) & SDIF_RINTSTS_HTO_MASK)
\r
12661 #define SDIF_RINTSTS_FRUN_MASK (0x800U)
\r
12662 #define SDIF_RINTSTS_FRUN_SHIFT (11U)
\r
12663 /*! FRUN - FIFO underrun/overrun error.
\r
12665 #define SDIF_RINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_FRUN_SHIFT)) & SDIF_RINTSTS_FRUN_MASK)
\r
12666 #define SDIF_RINTSTS_HLE_MASK (0x1000U)
\r
12667 #define SDIF_RINTSTS_HLE_SHIFT (12U)
\r
12668 /*! HLE - Hardware locked write error.
\r
12670 #define SDIF_RINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HLE_SHIFT)) & SDIF_RINTSTS_HLE_MASK)
\r
12671 #define SDIF_RINTSTS_SBE_MASK (0x2000U)
\r
12672 #define SDIF_RINTSTS_SBE_SHIFT (13U)
\r
12673 /*! SBE - Start-bit error.
\r
12675 #define SDIF_RINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SBE_SHIFT)) & SDIF_RINTSTS_SBE_MASK)
\r
12676 #define SDIF_RINTSTS_ACD_MASK (0x4000U)
\r
12677 #define SDIF_RINTSTS_ACD_SHIFT (14U)
\r
12678 /*! ACD - Auto command done.
\r
12680 #define SDIF_RINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_ACD_SHIFT)) & SDIF_RINTSTS_ACD_MASK)
\r
12681 #define SDIF_RINTSTS_EBE_MASK (0x8000U)
\r
12682 #define SDIF_RINTSTS_EBE_SHIFT (15U)
\r
12683 /*! EBE - End-bit error (read)/write no CRC.
\r
12685 #define SDIF_RINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_EBE_SHIFT)) & SDIF_RINTSTS_EBE_MASK)
\r
12686 #define SDIF_RINTSTS_SDIO_INTERRUPT_MASK (0x10000U)
\r
12687 #define SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT (16U)
\r
12688 /*! SDIO_INTERRUPT - Interrupt from SDIO card.
\r
12690 #define SDIF_RINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_RINTSTS_SDIO_INTERRUPT_MASK)
\r
12693 /*! @name STATUS - Status register */
\r
12695 #define SDIF_STATUS_FIFO_RX_WATERMARK_MASK (0x1U)
\r
12696 #define SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT (0U)
\r
12697 /*! FIFO_RX_WATERMARK - FIFO reached Receive watermark level; not qualified with data transfer.
\r
12699 #define SDIF_STATUS_FIFO_RX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_RX_WATERMARK_MASK)
\r
12700 #define SDIF_STATUS_FIFO_TX_WATERMARK_MASK (0x2U)
\r
12701 #define SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT (1U)
\r
12702 /*! FIFO_TX_WATERMARK - FIFO reached Transmit watermark level; not qualified with data transfer.
\r
12704 #define SDIF_STATUS_FIFO_TX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_TX_WATERMARK_MASK)
\r
12705 #define SDIF_STATUS_FIFO_EMPTY_MASK (0x4U)
\r
12706 #define SDIF_STATUS_FIFO_EMPTY_SHIFT (2U)
\r
12707 /*! FIFO_EMPTY - FIFO is empty status.
\r
12709 #define SDIF_STATUS_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_EMPTY_SHIFT)) & SDIF_STATUS_FIFO_EMPTY_MASK)
\r
12710 #define SDIF_STATUS_FIFO_FULL_MASK (0x8U)
\r
12711 #define SDIF_STATUS_FIFO_FULL_SHIFT (3U)
\r
12712 /*! FIFO_FULL - FIFO is full status.
\r
12714 #define SDIF_STATUS_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_FULL_SHIFT)) & SDIF_STATUS_FIFO_FULL_MASK)
\r
12715 #define SDIF_STATUS_CMDFSMSTATES_MASK (0xF0U)
\r
12716 #define SDIF_STATUS_CMDFSMSTATES_SHIFT (4U)
\r
12717 /*! CMDFSMSTATES - Command FSM states: 0 - Idle 1 - Send init sequence 2 - Tx cmd start bit 3 - Tx
\r
12718 * cmd tx bit 4 - Tx cmd index + arg 5 - Tx cmd crc7 6 - Tx cmd end bit 7 - Rx resp start bit 8 -
\r
12719 * Rx resp IRQ response 9 - Rx resp tx bit 10 - Rx resp cmd idx 11 - Rx resp data 12 - Rx resp
\r
12720 * crc7 13 - Rx resp end bit 14 - Cmd path wait NCC 15 - Wait; CMD-to-response turnaround NOTE: The
\r
12721 * command FSM state is represented using 19 bits.
\r
12723 #define SDIF_STATUS_CMDFSMSTATES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_CMDFSMSTATES_SHIFT)) & SDIF_STATUS_CMDFSMSTATES_MASK)
\r
12724 #define SDIF_STATUS_DATA_3_STATUS_MASK (0x100U)
\r
12725 #define SDIF_STATUS_DATA_3_STATUS_SHIFT (8U)
\r
12726 /*! DATA_3_STATUS - Raw selected card_data[3]; checks whether card is present 0 - card not present 1 - card present.
\r
12728 #define SDIF_STATUS_DATA_3_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_3_STATUS_SHIFT)) & SDIF_STATUS_DATA_3_STATUS_MASK)
\r
12729 #define SDIF_STATUS_DATA_BUSY_MASK (0x200U)
\r
12730 #define SDIF_STATUS_DATA_BUSY_SHIFT (9U)
\r
12731 /*! DATA_BUSY - Inverted version of raw selected card_data[0] 0 - card data not busy 1 - card data busy.
\r
12733 #define SDIF_STATUS_DATA_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_BUSY_SHIFT)) & SDIF_STATUS_DATA_BUSY_MASK)
\r
12734 #define SDIF_STATUS_DATA_STATE_MC_BUSY_MASK (0x400U)
\r
12735 #define SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT (10U)
\r
12736 /*! DATA_STATE_MC_BUSY - Data transmit or receive state-machine is busy.
\r
12738 #define SDIF_STATUS_DATA_STATE_MC_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT)) & SDIF_STATUS_DATA_STATE_MC_BUSY_MASK)
\r
12739 #define SDIF_STATUS_RESPONSE_INDEX_MASK (0x1F800U)
\r
12740 #define SDIF_STATUS_RESPONSE_INDEX_SHIFT (11U)
\r
12741 /*! RESPONSE_INDEX - Index of previous response, including any auto-stop sent by core.
\r
12743 #define SDIF_STATUS_RESPONSE_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK)
\r
12744 #define SDIF_STATUS_FIFO_COUNT_MASK (0x3FFE0000U)
\r
12745 #define SDIF_STATUS_FIFO_COUNT_SHIFT (17U)
\r
12746 /*! FIFO_COUNT - FIFO count - Number of filled locations in FIFO.
\r
12748 #define SDIF_STATUS_FIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_COUNT_SHIFT)) & SDIF_STATUS_FIFO_COUNT_MASK)
\r
12749 #define SDIF_STATUS_DMA_ACK_MASK (0x40000000U)
\r
12750 #define SDIF_STATUS_DMA_ACK_SHIFT (30U)
\r
12751 /*! DMA_ACK - DMA acknowledge signal state.
\r
12753 #define SDIF_STATUS_DMA_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_ACK_SHIFT)) & SDIF_STATUS_DMA_ACK_MASK)
\r
12754 #define SDIF_STATUS_DMA_REQ_MASK (0x80000000U)
\r
12755 #define SDIF_STATUS_DMA_REQ_SHIFT (31U)
\r
12756 /*! DMA_REQ - DMA request signal state.
\r
12758 #define SDIF_STATUS_DMA_REQ(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_REQ_SHIFT)) & SDIF_STATUS_DMA_REQ_MASK)
\r
12761 /*! @name FIFOTH - FIFO Threshold Watermark register */
\r
12763 #define SDIF_FIFOTH_TX_WMARK_MASK (0xFFFU)
\r
12764 #define SDIF_FIFOTH_TX_WMARK_SHIFT (0U)
\r
12765 /*! TX_WMARK - FIFO threshold watermark level when transmitting data to card.
\r
12767 #define SDIF_FIFOTH_TX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_TX_WMARK_SHIFT)) & SDIF_FIFOTH_TX_WMARK_MASK)
\r
12768 #define SDIF_FIFOTH_RX_WMARK_MASK (0xFFF0000U)
\r
12769 #define SDIF_FIFOTH_RX_WMARK_SHIFT (16U)
\r
12770 /*! RX_WMARK - FIFO threshold watermark level when receiving data to card.
\r
12772 #define SDIF_FIFOTH_RX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_RX_WMARK_SHIFT)) & SDIF_FIFOTH_RX_WMARK_MASK)
\r
12773 #define SDIF_FIFOTH_DMA_MTS_MASK (0x70000000U)
\r
12774 #define SDIF_FIFOTH_DMA_MTS_SHIFT (28U)
\r
12775 /*! DMA_MTS - Burst size of multiple transaction; should be programmed same as DW-DMA controller
\r
12776 * multiple-transaction-size SRC/DEST_MSIZE.
\r
12778 #define SDIF_FIFOTH_DMA_MTS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_DMA_MTS_SHIFT)) & SDIF_FIFOTH_DMA_MTS_MASK)
\r
12781 /*! @name CDETECT - Card Detect register */
\r
12783 #define SDIF_CDETECT_CARD_DETECT_MASK (0x1U)
\r
12784 #define SDIF_CDETECT_CARD_DETECT_SHIFT (0U)
\r
12785 /*! CARD_DETECT - Card detect.
\r
12787 #define SDIF_CDETECT_CARD_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD_DETECT_SHIFT)) & SDIF_CDETECT_CARD_DETECT_MASK)
\r
12790 /*! @name WRTPRT - Write Protect register */
\r
12792 #define SDIF_WRTPRT_WRITE_PROTECT_MASK (0x1U)
\r
12793 #define SDIF_WRTPRT_WRITE_PROTECT_SHIFT (0U)
\r
12794 /*! WRITE_PROTECT - Write protect.
\r
12796 #define SDIF_WRTPRT_WRITE_PROTECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_WRTPRT_WRITE_PROTECT_SHIFT)) & SDIF_WRTPRT_WRITE_PROTECT_MASK)
\r
12799 /*! @name TCBCNT - Transferred CIU Card Byte Count register */
\r
12801 #define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK (0xFFFFFFFFU)
\r
12802 #define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT (0U)
\r
12803 /*! TRANS_CARD_BYTE_COUNT - Number of bytes transferred by CIU unit to card.
\r
12805 #define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT)) & SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK)
\r
12808 /*! @name TBBCNT - Transferred Host to BIU-FIFO Byte Count register */
\r
12810 #define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK (0xFFFFFFFFU)
\r
12811 #define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT (0U)
\r
12812 /*! TRANS_FIFO_BYTE_COUNT - Number of bytes transferred between Host/DMA memory and BIU FIFO.
\r
12814 #define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT)) & SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK)
\r
12817 /*! @name DEBNCE - Debounce Count register */
\r
12819 #define SDIF_DEBNCE_DEBOUNCE_COUNT_MASK (0xFFFFFFU)
\r
12820 #define SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT (0U)
\r
12821 /*! DEBOUNCE_COUNT - Number of host clocks (SD_CLK) used by debounce filter logic for card detect; typical debounce time is 5-25 ms.
\r
12823 #define SDIF_DEBNCE_DEBOUNCE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT)) & SDIF_DEBNCE_DEBOUNCE_COUNT_MASK)
\r
12826 /*! @name RST_N - Hardware Reset */
\r
12828 #define SDIF_RST_N_CARD_RESET_MASK (0x1U)
\r
12829 #define SDIF_RST_N_CARD_RESET_SHIFT (0U)
\r
12830 /*! CARD_RESET - Hardware reset.
\r
12832 #define SDIF_RST_N_CARD_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RST_N_CARD_RESET_SHIFT)) & SDIF_RST_N_CARD_RESET_MASK)
\r
12835 /*! @name BMOD - Bus Mode register */
\r
12837 #define SDIF_BMOD_SWR_MASK (0x1U)
\r
12838 #define SDIF_BMOD_SWR_SHIFT (0U)
\r
12839 /*! SWR - Software Reset.
\r
12841 #define SDIF_BMOD_SWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_SWR_SHIFT)) & SDIF_BMOD_SWR_MASK)
\r
12842 #define SDIF_BMOD_FB_MASK (0x2U)
\r
12843 #define SDIF_BMOD_FB_SHIFT (1U)
\r
12844 /*! FB - Fixed Burst.
\r
12846 #define SDIF_BMOD_FB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_FB_SHIFT)) & SDIF_BMOD_FB_MASK)
\r
12847 #define SDIF_BMOD_DSL_MASK (0x7CU)
\r
12848 #define SDIF_BMOD_DSL_SHIFT (2U)
\r
12849 /*! DSL - Descriptor Skip Length.
\r
12851 #define SDIF_BMOD_DSL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DSL_SHIFT)) & SDIF_BMOD_DSL_MASK)
\r
12852 #define SDIF_BMOD_DE_MASK (0x80U)
\r
12853 #define SDIF_BMOD_DE_SHIFT (7U)
\r
12854 /*! DE - SD/MMC DMA Enable.
\r
12856 #define SDIF_BMOD_DE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DE_SHIFT)) & SDIF_BMOD_DE_MASK)
\r
12857 #define SDIF_BMOD_PBL_MASK (0x700U)
\r
12858 #define SDIF_BMOD_PBL_SHIFT (8U)
\r
12859 /*! PBL - Programmable Burst Length.
\r
12861 #define SDIF_BMOD_PBL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_PBL_SHIFT)) & SDIF_BMOD_PBL_MASK)
\r
12864 /*! @name PLDMND - Poll Demand register */
\r
12866 #define SDIF_PLDMND_PD_MASK (0xFFFFFFFFU)
\r
12867 #define SDIF_PLDMND_PD_SHIFT (0U)
\r
12868 /*! PD - Poll Demand.
\r
12870 #define SDIF_PLDMND_PD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PLDMND_PD_SHIFT)) & SDIF_PLDMND_PD_MASK)
\r
12873 /*! @name DBADDR - Descriptor List Base Address register */
\r
12875 #define SDIF_DBADDR_SDL_MASK (0xFFFFFFFFU)
\r
12876 #define SDIF_DBADDR_SDL_SHIFT (0U)
\r
12877 /*! SDL - Start of Descriptor List.
\r
12879 #define SDIF_DBADDR_SDL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DBADDR_SDL_SHIFT)) & SDIF_DBADDR_SDL_MASK)
\r
12882 /*! @name IDSTS - Internal DMAC Status register */
\r
12884 #define SDIF_IDSTS_TI_MASK (0x1U)
\r
12885 #define SDIF_IDSTS_TI_SHIFT (0U)
\r
12886 /*! TI - Transmit Interrupt.
\r
12888 #define SDIF_IDSTS_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_TI_SHIFT)) & SDIF_IDSTS_TI_MASK)
\r
12889 #define SDIF_IDSTS_RI_MASK (0x2U)
\r
12890 #define SDIF_IDSTS_RI_SHIFT (1U)
\r
12891 /*! RI - Receive Interrupt.
\r
12893 #define SDIF_IDSTS_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_RI_SHIFT)) & SDIF_IDSTS_RI_MASK)
\r
12894 #define SDIF_IDSTS_FBE_MASK (0x4U)
\r
12895 #define SDIF_IDSTS_FBE_SHIFT (2U)
\r
12896 /*! FBE - Fatal Bus Error Interrupt.
\r
12898 #define SDIF_IDSTS_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FBE_SHIFT)) & SDIF_IDSTS_FBE_MASK)
\r
12899 #define SDIF_IDSTS_DU_MASK (0x10U)
\r
12900 #define SDIF_IDSTS_DU_SHIFT (4U)
\r
12901 /*! DU - Descriptor Unavailable Interrupt.
\r
12903 #define SDIF_IDSTS_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_DU_SHIFT)) & SDIF_IDSTS_DU_MASK)
\r
12904 #define SDIF_IDSTS_CES_MASK (0x20U)
\r
12905 #define SDIF_IDSTS_CES_SHIFT (5U)
\r
12906 /*! CES - Card Error Summary.
\r
12908 #define SDIF_IDSTS_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_CES_SHIFT)) & SDIF_IDSTS_CES_MASK)
\r
12909 #define SDIF_IDSTS_NIS_MASK (0x100U)
\r
12910 #define SDIF_IDSTS_NIS_SHIFT (8U)
\r
12911 /*! NIS - Normal Interrupt Summary.
\r
12913 #define SDIF_IDSTS_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_NIS_SHIFT)) & SDIF_IDSTS_NIS_MASK)
\r
12914 #define SDIF_IDSTS_AIS_MASK (0x200U)
\r
12915 #define SDIF_IDSTS_AIS_SHIFT (9U)
\r
12916 /*! AIS - Abnormal Interrupt Summary.
\r
12918 #define SDIF_IDSTS_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_AIS_SHIFT)) & SDIF_IDSTS_AIS_MASK)
\r
12919 #define SDIF_IDSTS_EB_MASK (0x1C00U)
\r
12920 #define SDIF_IDSTS_EB_SHIFT (10U)
\r
12921 /*! EB - Error Bits.
\r
12923 #define SDIF_IDSTS_EB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_EB_SHIFT)) & SDIF_IDSTS_EB_MASK)
\r
12924 #define SDIF_IDSTS_FSM_MASK (0x1E000U)
\r
12925 #define SDIF_IDSTS_FSM_SHIFT (13U)
\r
12926 /*! FSM - DMAC state machine present state.
\r
12928 #define SDIF_IDSTS_FSM(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FSM_SHIFT)) & SDIF_IDSTS_FSM_MASK)
\r
12931 /*! @name IDINTEN - Internal DMAC Interrupt Enable register */
\r
12933 #define SDIF_IDINTEN_TI_MASK (0x1U)
\r
12934 #define SDIF_IDINTEN_TI_SHIFT (0U)
\r
12935 /*! TI - Transmit Interrupt Enable.
\r
12937 #define SDIF_IDINTEN_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_TI_SHIFT)) & SDIF_IDINTEN_TI_MASK)
\r
12938 #define SDIF_IDINTEN_RI_MASK (0x2U)
\r
12939 #define SDIF_IDINTEN_RI_SHIFT (1U)
\r
12940 /*! RI - Receive Interrupt Enable.
\r
12942 #define SDIF_IDINTEN_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_RI_SHIFT)) & SDIF_IDINTEN_RI_MASK)
\r
12943 #define SDIF_IDINTEN_FBE_MASK (0x4U)
\r
12944 #define SDIF_IDINTEN_FBE_SHIFT (2U)
\r
12945 /*! FBE - Fatal Bus Error Enable.
\r
12947 #define SDIF_IDINTEN_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_FBE_SHIFT)) & SDIF_IDINTEN_FBE_MASK)
\r
12948 #define SDIF_IDINTEN_DU_MASK (0x10U)
\r
12949 #define SDIF_IDINTEN_DU_SHIFT (4U)
\r
12950 /*! DU - Descriptor Unavailable Interrupt.
\r
12952 #define SDIF_IDINTEN_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_DU_SHIFT)) & SDIF_IDINTEN_DU_MASK)
\r
12953 #define SDIF_IDINTEN_CES_MASK (0x20U)
\r
12954 #define SDIF_IDINTEN_CES_SHIFT (5U)
\r
12955 /*! CES - Card Error summary Interrupt Enable.
\r
12957 #define SDIF_IDINTEN_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_CES_SHIFT)) & SDIF_IDINTEN_CES_MASK)
\r
12958 #define SDIF_IDINTEN_NIS_MASK (0x100U)
\r
12959 #define SDIF_IDINTEN_NIS_SHIFT (8U)
\r
12960 /*! NIS - Normal Interrupt Summary Enable.
\r
12962 #define SDIF_IDINTEN_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_NIS_SHIFT)) & SDIF_IDINTEN_NIS_MASK)
\r
12963 #define SDIF_IDINTEN_AIS_MASK (0x200U)
\r
12964 #define SDIF_IDINTEN_AIS_SHIFT (9U)
\r
12965 /*! AIS - Abnormal Interrupt Summary Enable.
\r
12967 #define SDIF_IDINTEN_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_AIS_SHIFT)) & SDIF_IDINTEN_AIS_MASK)
\r
12970 /*! @name DSCADDR - Current Host Descriptor Address register */
\r
12972 #define SDIF_DSCADDR_HDA_MASK (0xFFFFFFFFU)
\r
12973 #define SDIF_DSCADDR_HDA_SHIFT (0U)
\r
12974 /*! HDA - Host Descriptor Address Pointer.
\r
12976 #define SDIF_DSCADDR_HDA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DSCADDR_HDA_SHIFT)) & SDIF_DSCADDR_HDA_MASK)
\r
12979 /*! @name BUFADDR - Current Buffer Descriptor Address register */
\r
12981 #define SDIF_BUFADDR_HBA_MASK (0xFFFFFFFFU)
\r
12982 #define SDIF_BUFADDR_HBA_SHIFT (0U)
\r
12983 /*! HBA - Host Buffer Address Pointer.
\r
12985 #define SDIF_BUFADDR_HBA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BUFADDR_HBA_SHIFT)) & SDIF_BUFADDR_HBA_MASK)
\r
12988 /*! @name CARDTHRCTL - Card Threshold Control */
\r
12990 #define SDIF_CARDTHRCTL_CARDRDTHREN_MASK (0x1U)
\r
12991 #define SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT (0U)
\r
12992 /*! CARDRDTHREN - Card Read Threshold Enable.
\r
12994 #define SDIF_CARDTHRCTL_CARDRDTHREN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT)) & SDIF_CARDTHRCTL_CARDRDTHREN_MASK)
\r
12995 #define SDIF_CARDTHRCTL_BSYCLRINTEN_MASK (0x2U)
\r
12996 #define SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT (1U)
\r
12997 /*! BSYCLRINTEN - Busy Clear Interrupt Enable.
\r
12999 #define SDIF_CARDTHRCTL_BSYCLRINTEN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT)) & SDIF_CARDTHRCTL_BSYCLRINTEN_MASK)
\r
13000 #define SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK (0xFF0000U)
\r
13001 #define SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT (16U)
\r
13002 /*! CARDTHRESHOLD - Card Threshold size.
\r
13004 #define SDIF_CARDTHRCTL_CARDTHRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT)) & SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK)
\r
13007 /*! @name BACKENDPWR - Power control */
\r
13009 #define SDIF_BACKENDPWR_BACKENDPWR_MASK (0x1U)
\r
13010 #define SDIF_BACKENDPWR_BACKENDPWR_SHIFT (0U)
\r
13011 /*! BACKENDPWR - Back-end Power control for card application.
\r
13013 #define SDIF_BACKENDPWR_BACKENDPWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BACKENDPWR_BACKENDPWR_SHIFT)) & SDIF_BACKENDPWR_BACKENDPWR_MASK)
\r
13016 /*! @name FIFO - SDIF FIFO */
\r
13018 #define SDIF_FIFO_DATA_MASK (0xFFFFFFFFU)
\r
13019 #define SDIF_FIFO_DATA_SHIFT (0U)
\r
13020 /*! DATA - SDIF FIFO.
\r
13022 #define SDIF_FIFO_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFO_DATA_SHIFT)) & SDIF_FIFO_DATA_MASK)
\r
13025 /* The count of SDIF_FIFO */
\r
13026 #define SDIF_FIFO_COUNT (64U)
\r
13031 */ /* end of group SDIF_Register_Masks */
\r
13034 /* SDIF - Peripheral instance base addresses */
\r
13035 /** Peripheral SDIF base address */
\r
13036 #define SDIF_BASE (0x4009B000u)
\r
13037 /** Peripheral SDIF base pointer */
\r
13038 #define SDIF ((SDIF_Type *)SDIF_BASE)
\r
13039 /** Array initializer of SDIF peripheral base addresses */
\r
13040 #define SDIF_BASE_ADDRS { SDIF_BASE }
\r
13041 /** Array initializer of SDIF peripheral base pointers */
\r
13042 #define SDIF_BASE_PTRS { SDIF }
\r
13043 /** Interrupt vectors for the SDIF peripheral type */
\r
13044 #define SDIF_IRQS { SDIO_IRQn }
\r
13048 */ /* end of group SDIF_Peripheral_Access_Layer */
\r
13051 /* ----------------------------------------------------------------------------
\r
13052 -- SHA Peripheral Access Layer
\r
13053 ---------------------------------------------------------------------------- */
\r
13056 * @addtogroup SHA_Peripheral_Access_Layer SHA Peripheral Access Layer
\r
13060 /** SHA - Register Layout Typedef */
\r
13062 __IO uint32_t CTRL; /**< Control register, offset: 0x0 */
\r
13063 __IO uint32_t STATUS; /**< Status register, offset: 0x4 */
\r
13064 __IO uint32_t INTENSET; /**< Interrupt Enable register, offset: 0x8 */
\r
13065 __O uint32_t INTENCLR; /**< Interrupt Clear register, offset: 0xC */
\r
13066 __IO uint32_t MEMCTRL; /**< Memory Control register, offset: 0x10 */
\r
13067 __IO uint32_t MEMADDR; /**< Memory Address register, offset: 0x14 */
\r
13068 uint8_t RESERVED_0[8];
\r
13069 __O uint32_t INDATA; /**< Input Data register, offset: 0x20 */
\r
13070 __O uint32_t ALIAS[7]; /**< Alias register, array offset: 0x24, array step: 0x4 */
\r
13071 __I uint32_t DIGEST[8]; /**< Digest register, array offset: 0x40, array step: 0x4 */
\r
13074 /* ----------------------------------------------------------------------------
\r
13075 -- SHA Register Masks
\r
13076 ---------------------------------------------------------------------------- */
\r
13079 * @addtogroup SHA_Register_Masks SHA Register Masks
\r
13083 /*! @name CTRL - Control register */
\r
13085 #define SHA_CTRL_MODE_MASK (0x3U)
\r
13086 #define SHA_CTRL_MODE_SHIFT (0U)
\r
13087 /*! MODE - This field is used to select the operational mode of SHA block.
\r
13089 #define SHA_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << SHA_CTRL_MODE_SHIFT)) & SHA_CTRL_MODE_MASK)
\r
13090 #define SHA_CTRL_NEW_MASK (0x10U)
\r
13091 #define SHA_CTRL_NEW_SHIFT (4U)
\r
13092 /*! NEW - When this bit is set, a new hash operation is started.
\r
13094 #define SHA_CTRL_NEW(x) (((uint32_t)(((uint32_t)(x)) << SHA_CTRL_NEW_SHIFT)) & SHA_CTRL_NEW_MASK)
\r
13095 #define SHA_CTRL_DMA_MASK (0x100U)
\r
13096 #define SHA_CTRL_DMA_SHIFT (8U)
\r
13097 /*! DMA - When this bit is set, the DMA is used to fill INDATA.
\r
13099 #define SHA_CTRL_DMA(x) (((uint32_t)(((uint32_t)(x)) << SHA_CTRL_DMA_SHIFT)) & SHA_CTRL_DMA_MASK)
\r
13102 /*! @name STATUS - Status register */
\r
13104 #define SHA_STATUS_WAITING_MASK (0x1U)
\r
13105 #define SHA_STATUS_WAITING_SHIFT (0U)
\r
13106 /*! WAITING - This field indicates if the block is waiting for more data to process.
\r
13108 #define SHA_STATUS_WAITING(x) (((uint32_t)(((uint32_t)(x)) << SHA_STATUS_WAITING_SHIFT)) & SHA_STATUS_WAITING_MASK)
\r
13109 #define SHA_STATUS_DIGEST_MASK (0x2U)
\r
13110 #define SHA_STATUS_DIGEST_SHIFT (1U)
\r
13111 /*! DIGEST - This field indicates if a DIGEST is ready and waiting and there is no active next block that has already started.
\r
13113 #define SHA_STATUS_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << SHA_STATUS_DIGEST_SHIFT)) & SHA_STATUS_DIGEST_MASK)
\r
13114 #define SHA_STATUS_ERROR_MASK (0x4U)
\r
13115 #define SHA_STATUS_ERROR_SHIFT (2U)
\r
13116 /*! ERROR - This field indicates if an error has occurred.
\r
13118 #define SHA_STATUS_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SHA_STATUS_ERROR_SHIFT)) & SHA_STATUS_ERROR_MASK)
\r
13121 /*! @name INTENSET - Interrupt Enable register */
\r
13123 #define SHA_INTENSET_WAITING_MASK (0x1U)
\r
13124 #define SHA_INTENSET_WAITING_SHIFT (0U)
\r
13125 /*! WAITING - This field indicates if interrupt should be enabled when waiting for input data.
\r
13127 #define SHA_INTENSET_WAITING(x) (((uint32_t)(((uint32_t)(x)) << SHA_INTENSET_WAITING_SHIFT)) & SHA_INTENSET_WAITING_MASK)
\r
13128 #define SHA_INTENSET_DIGEST_MASK (0x2U)
\r
13129 #define SHA_INTENSET_DIGEST_SHIFT (1U)
\r
13130 /*! DIGEST - This field indicates if interrupt is generated when Digest is ready (completed a Hash or completed a full sequence).
\r
13132 #define SHA_INTENSET_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << SHA_INTENSET_DIGEST_SHIFT)) & SHA_INTENSET_DIGEST_MASK)
\r
13133 #define SHA_INTENSET_ERROR_MASK (0x4U)
\r
13134 #define SHA_INTENSET_ERROR_SHIFT (2U)
\r
13135 /*! ERROR - This field indicates if interrupt is generated on an ERROR (as defined in STAT register).
\r
13137 #define SHA_INTENSET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SHA_INTENSET_ERROR_SHIFT)) & SHA_INTENSET_ERROR_MASK)
\r
13140 /*! @name INTENCLR - Interrupt Clear register */
\r
13142 #define SHA_INTENCLR_WAITING_MASK (0x1U)
\r
13143 #define SHA_INTENCLR_WAITING_SHIFT (0U)
\r
13144 /*! WAITING - Writing a 1 clears the interrupt enabled by the INTENSET register.
\r
13146 #define SHA_INTENCLR_WAITING(x) (((uint32_t)(((uint32_t)(x)) << SHA_INTENCLR_WAITING_SHIFT)) & SHA_INTENCLR_WAITING_MASK)
\r
13147 #define SHA_INTENCLR_DIGEST_MASK (0x2U)
\r
13148 #define SHA_INTENCLR_DIGEST_SHIFT (1U)
\r
13149 /*! DIGEST - Writing a 1 clears the interrupt enabled by the INTENSET register.
\r
13151 #define SHA_INTENCLR_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << SHA_INTENCLR_DIGEST_SHIFT)) & SHA_INTENCLR_DIGEST_MASK)
\r
13152 #define SHA_INTENCLR_ERROR_MASK (0x4U)
\r
13153 #define SHA_INTENCLR_ERROR_SHIFT (2U)
\r
13154 /*! ERROR - Writing a 1 clears the interrupt enabled by the INTENSET register.
\r
13156 #define SHA_INTENCLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SHA_INTENCLR_ERROR_SHIFT)) & SHA_INTENCLR_ERROR_MASK)
\r
13159 /*! @name MEMCTRL - Memory Control register */
\r
13161 #define SHA_MEMCTRL_MASTER_MASK (0x1U)
\r
13162 #define SHA_MEMCTRL_MASTER_SHIFT (0U)
\r
13163 /*! MASTER - This field is used to enable SHA block as AHB bus master.
\r
13165 #define SHA_MEMCTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SHA_MEMCTRL_MASTER_SHIFT)) & SHA_MEMCTRL_MASTER_MASK)
\r
13166 #define SHA_MEMCTRL_COUNT_MASK (0x7FF0000U)
\r
13167 #define SHA_MEMCTRL_COUNT_SHIFT (16U)
\r
13168 /*! COUNT - This field indicates the number of 512-bit blocks to copy starting at MEMADDR.
\r
13170 #define SHA_MEMCTRL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SHA_MEMCTRL_COUNT_SHIFT)) & SHA_MEMCTRL_COUNT_MASK)
\r
13173 /*! @name MEMADDR - Memory Address register */
\r
13175 #define SHA_MEMADDR_BASEADDR_MASK (0xFFFFFFFFU)
\r
13176 #define SHA_MEMADDR_BASEADDR_SHIFT (0U)
\r
13177 /*! BASEADDR - This field indicates the base address in Internal Flash, SRAM0, SRAMX, or SPIFI to start copying from.
\r
13179 #define SHA_MEMADDR_BASEADDR(x) (((uint32_t)(((uint32_t)(x)) << SHA_MEMADDR_BASEADDR_SHIFT)) & SHA_MEMADDR_BASEADDR_MASK)
\r
13182 /*! @name INDATA - Input Data register */
\r
13184 #define SHA_INDATA_DATA_MASK (0xFFFFFFFFU)
\r
13185 #define SHA_INDATA_DATA_SHIFT (0U)
\r
13186 /*! DATA - In this field the next word is written in little-endian format.
\r
13188 #define SHA_INDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << SHA_INDATA_DATA_SHIFT)) & SHA_INDATA_DATA_MASK)
\r
13191 /*! @name ALIAS - Alias register */
\r
13193 #define SHA_ALIAS_DATA_MASK (0xFFFFFFFFU)
\r
13194 #define SHA_ALIAS_DATA_SHIFT (0U)
\r
13195 /*! DATA - In this field the next word is written in little-endian format.
\r
13197 #define SHA_ALIAS_DATA(x) (((uint32_t)(((uint32_t)(x)) << SHA_ALIAS_DATA_SHIFT)) & SHA_ALIAS_DATA_MASK)
\r
13200 /* The count of SHA_ALIAS */
\r
13201 #define SHA_ALIAS_COUNT (7U)
\r
13203 /*! @name DIGEST - Digest register */
\r
13205 #define SHA_DIGEST_DIGEST_MASK (0xFFFFFFFFU)
\r
13206 #define SHA_DIGEST_DIGEST_SHIFT (0U)
\r
13207 /*! DIGEST - This field contains one word of the Digest.
\r
13209 #define SHA_DIGEST_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << SHA_DIGEST_DIGEST_SHIFT)) & SHA_DIGEST_DIGEST_MASK)
\r
13212 /* The count of SHA_DIGEST */
\r
13213 #define SHA_DIGEST_COUNT (8U)
\r
13218 */ /* end of group SHA_Register_Masks */
\r
13221 /* SHA - Peripheral instance base addresses */
\r
13222 /** Peripheral SHA0 base address */
\r
13223 #define SHA0_BASE (0x400A4000u)
\r
13224 /** Peripheral SHA0 base pointer */
\r
13225 #define SHA0 ((SHA_Type *)SHA0_BASE)
\r
13226 /** Array initializer of SHA peripheral base addresses */
\r
13227 #define SHA_BASE_ADDRS { SHA0_BASE }
\r
13228 /** Array initializer of SHA peripheral base pointers */
\r
13229 #define SHA_BASE_PTRS { SHA0 }
\r
13233 */ /* end of group SHA_Peripheral_Access_Layer */
\r
13236 /* ----------------------------------------------------------------------------
\r
13237 -- SMARTCARD Peripheral Access Layer
\r
13238 ---------------------------------------------------------------------------- */
\r
13241 * @addtogroup SMARTCARD_Peripheral_Access_Layer SMARTCARD Peripheral Access Layer
\r
13245 /** SMARTCARD - Register Layout Typedef */
\r
13247 union { /* offset: 0x0 */
\r
13248 __IO uint32_t DLL; /**< Divisor Latch LSB, offset: 0x0 */
\r
13249 __I uint32_t RBR; /**< Receiver Buffer Register, offset: 0x0 */
\r
13250 __O uint32_t THR; /**< Transmit Holding Register, offset: 0x0 */
\r
13252 union { /* offset: 0x4 */
\r
13253 __IO uint32_t DLM; /**< Divisor Latch MSB, offset: 0x4 */
\r
13254 __IO uint32_t IER; /**< Interrupt Enable Register, offset: 0x4 */
\r
13256 union { /* offset: 0x8 */
\r
13257 __O uint32_t FCR; /**< FIFO Control Register, offset: 0x8 */
\r
13258 __I uint32_t IIR; /**< Interrupt ID Register, offset: 0x8 */
\r
13260 __IO uint32_t LCR; /**< Line Control Register, offset: 0xC */
\r
13261 uint8_t RESERVED_0[4];
\r
13262 __I uint32_t LSR; /**< Line Status Register, offset: 0x14 */
\r
13263 uint8_t RESERVED_1[4];
\r
13264 __IO uint32_t SCR; /**< Scratch Pad Register, offset: 0x1C */
\r
13265 uint8_t RESERVED_2[12];
\r
13266 __IO uint32_t OSR; /**< Oversampling register, offset: 0x2C */
\r
13267 uint8_t RESERVED_3[24];
\r
13268 __IO uint32_t SCICTRL; /**< Smart Card Interface control register, offset: 0x48 */
\r
13269 } SMARTCARD_Type;
\r
13271 /* ----------------------------------------------------------------------------
\r
13272 -- SMARTCARD Register Masks
\r
13273 ---------------------------------------------------------------------------- */
\r
13276 * @addtogroup SMARTCARD_Register_Masks SMARTCARD Register Masks
\r
13280 /*! @name DLL - Divisor Latch LSB */
\r
13282 #define SMARTCARD_DLL_DLLSB_MASK (0xFFU)
\r
13283 #define SMARTCARD_DLL_DLLSB_SHIFT (0U)
\r
13284 /*! DLLSB - The SCIn Divisor Latch LSB Register, along with the SCInDLM register, determines the baud rate of the SCIn.
\r
13286 #define SMARTCARD_DLL_DLLSB(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_DLL_DLLSB_SHIFT)) & SMARTCARD_DLL_DLLSB_MASK)
\r
13289 /*! @name RBR - Receiver Buffer Register */
\r
13291 #define SMARTCARD_RBR_RBR_MASK (0xFFU)
\r
13292 #define SMARTCARD_RBR_RBR_SHIFT (0U)
\r
13293 /*! RBR - The SCIn Receiver Buffer Register contains the oldest received byte in the SCIn Rx FIFO.
\r
13295 #define SMARTCARD_RBR_RBR(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_RBR_RBR_SHIFT)) & SMARTCARD_RBR_RBR_MASK)
\r
13298 /*! @name THR - Transmit Holding Register */
\r
13300 #define SMARTCARD_THR_THR_MASK (0xFFU)
\r
13301 #define SMARTCARD_THR_THR_SHIFT (0U)
\r
13302 /*! THR - Writing to the SCIn Transmit Holding Register causes the data to be stored in the SCIn transmit FIFO.
\r
13304 #define SMARTCARD_THR_THR(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_THR_THR_SHIFT)) & SMARTCARD_THR_THR_MASK)
\r
13307 /*! @name DLM - Divisor Latch MSB */
\r
13309 #define SMARTCARD_DLM_DLMSB_MASK (0xFFU)
\r
13310 #define SMARTCARD_DLM_DLMSB_SHIFT (0U)
\r
13311 /*! DLMSB - The SCIn Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the SCIn.
\r
13313 #define SMARTCARD_DLM_DLMSB(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_DLM_DLMSB_SHIFT)) & SMARTCARD_DLM_DLMSB_MASK)
\r
13316 /*! @name IER - Interrupt Enable Register */
\r
13318 #define SMARTCARD_IER_RBRIE_MASK (0x1U)
\r
13319 #define SMARTCARD_IER_RBRIE_SHIFT (0U)
\r
13320 /*! RBRIE - RBR Interrupt Enable.
\r
13322 #define SMARTCARD_IER_RBRIE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IER_RBRIE_SHIFT)) & SMARTCARD_IER_RBRIE_MASK)
\r
13323 #define SMARTCARD_IER_THREIE_MASK (0x2U)
\r
13324 #define SMARTCARD_IER_THREIE_SHIFT (1U)
\r
13325 /*! THREIE - THRE Interrupt Enable.
\r
13327 #define SMARTCARD_IER_THREIE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IER_THREIE_SHIFT)) & SMARTCARD_IER_THREIE_MASK)
\r
13328 #define SMARTCARD_IER_RXIE_MASK (0x4U)
\r
13329 #define SMARTCARD_IER_RXIE_SHIFT (2U)
\r
13330 /*! RXIE - RX Line Status Interrupt Enable.
\r
13332 #define SMARTCARD_IER_RXIE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IER_RXIE_SHIFT)) & SMARTCARD_IER_RXIE_MASK)
\r
13335 /*! @name FCR - FIFO Control Register */
\r
13337 #define SMARTCARD_FCR_FIFOEN_MASK (0x1U)
\r
13338 #define SMARTCARD_FCR_FIFOEN_SHIFT (0U)
\r
13339 /*! FIFOEN - FIFO Enable.
\r
13341 #define SMARTCARD_FCR_FIFOEN(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_FIFOEN_SHIFT)) & SMARTCARD_FCR_FIFOEN_MASK)
\r
13342 #define SMARTCARD_FCR_RXFIFORES_MASK (0x2U)
\r
13343 #define SMARTCARD_FCR_RXFIFORES_SHIFT (1U)
\r
13344 /*! RXFIFORES - RX FIFO Reset.
\r
13346 #define SMARTCARD_FCR_RXFIFORES(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_RXFIFORES_SHIFT)) & SMARTCARD_FCR_RXFIFORES_MASK)
\r
13347 #define SMARTCARD_FCR_TXFIFORES_MASK (0x4U)
\r
13348 #define SMARTCARD_FCR_TXFIFORES_SHIFT (2U)
\r
13349 /*! TXFIFORES - TX FIFO Reset.
\r
13351 #define SMARTCARD_FCR_TXFIFORES(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_TXFIFORES_SHIFT)) & SMARTCARD_FCR_TXFIFORES_MASK)
\r
13352 #define SMARTCARD_FCR_DMAMODE_MASK (0x8U)
\r
13353 #define SMARTCARD_FCR_DMAMODE_SHIFT (3U)
\r
13354 /*! DMAMODE - DMA Mode Select.
\r
13356 #define SMARTCARD_FCR_DMAMODE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_DMAMODE_SHIFT)) & SMARTCARD_FCR_DMAMODE_MASK)
\r
13357 #define SMARTCARD_FCR_RXTRIGLVL_MASK (0xC0U)
\r
13358 #define SMARTCARD_FCR_RXTRIGLVL_SHIFT (6U)
\r
13359 /*! RXTRIGLVL - RX Trigger Level.
\r
13361 #define SMARTCARD_FCR_RXTRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_RXTRIGLVL_SHIFT)) & SMARTCARD_FCR_RXTRIGLVL_MASK)
\r
13364 /*! @name IIR - Interrupt ID Register */
\r
13366 #define SMARTCARD_IIR_INTSTATUS_MASK (0x1U)
\r
13367 #define SMARTCARD_IIR_INTSTATUS_SHIFT (0U)
\r
13368 /*! INTSTATUS - Interrupt status.
\r
13370 #define SMARTCARD_IIR_INTSTATUS(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IIR_INTSTATUS_SHIFT)) & SMARTCARD_IIR_INTSTATUS_MASK)
\r
13371 #define SMARTCARD_IIR_INTID_MASK (0xEU)
\r
13372 #define SMARTCARD_IIR_INTID_SHIFT (1U)
\r
13373 /*! INTID - Interrupt identification.
\r
13375 #define SMARTCARD_IIR_INTID(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IIR_INTID_SHIFT)) & SMARTCARD_IIR_INTID_MASK)
\r
13376 #define SMARTCARD_IIR_FIFOENABLE_MASK (0xC0U)
\r
13377 #define SMARTCARD_IIR_FIFOENABLE_SHIFT (6U)
\r
13378 /*! FIFOENABLE - Copies of SCInFCR[0].
\r
13380 #define SMARTCARD_IIR_FIFOENABLE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IIR_FIFOENABLE_SHIFT)) & SMARTCARD_IIR_FIFOENABLE_MASK)
\r
13383 /*! @name LCR - Line Control Register */
\r
13385 #define SMARTCARD_LCR_WLS_MASK (0x3U)
\r
13386 #define SMARTCARD_LCR_WLS_SHIFT (0U)
\r
13387 /*! WLS - Word Length Select.
\r
13389 #define SMARTCARD_LCR_WLS(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_WLS_SHIFT)) & SMARTCARD_LCR_WLS_MASK)
\r
13390 #define SMARTCARD_LCR_SBS_MASK (0x4U)
\r
13391 #define SMARTCARD_LCR_SBS_SHIFT (2U)
\r
13392 /*! SBS - Stop Bit Select.
\r
13394 #define SMARTCARD_LCR_SBS(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_SBS_SHIFT)) & SMARTCARD_LCR_SBS_MASK)
\r
13395 #define SMARTCARD_LCR_PE_MASK (0x8U)
\r
13396 #define SMARTCARD_LCR_PE_SHIFT (3U)
\r
13397 /*! PE - Parity Enable.
\r
13399 #define SMARTCARD_LCR_PE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_PE_SHIFT)) & SMARTCARD_LCR_PE_MASK)
\r
13400 #define SMARTCARD_LCR_PS_MASK (0x30U)
\r
13401 #define SMARTCARD_LCR_PS_SHIFT (4U)
\r
13402 /*! PS - Parity Select.
\r
13404 #define SMARTCARD_LCR_PS(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_PS_SHIFT)) & SMARTCARD_LCR_PS_MASK)
\r
13405 #define SMARTCARD_LCR_DLAB_MASK (0x80U)
\r
13406 #define SMARTCARD_LCR_DLAB_SHIFT (7U)
\r
13407 /*! DLAB - Divisor Latch Access Bit.
\r
13409 #define SMARTCARD_LCR_DLAB(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_DLAB_SHIFT)) & SMARTCARD_LCR_DLAB_MASK)
\r
13412 /*! @name LSR - Line Status Register */
\r
13414 #define SMARTCARD_LSR_RDR_MASK (0x1U)
\r
13415 #define SMARTCARD_LSR_RDR_SHIFT (0U)
\r
13416 /*! RDR - Receiver Data Ready.
\r
13418 #define SMARTCARD_LSR_RDR(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_RDR_SHIFT)) & SMARTCARD_LSR_RDR_MASK)
\r
13419 #define SMARTCARD_LSR_OE_MASK (0x2U)
\r
13420 #define SMARTCARD_LSR_OE_SHIFT (1U)
\r
13421 /*! OE - Overrun Error.
\r
13423 #define SMARTCARD_LSR_OE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_OE_SHIFT)) & SMARTCARD_LSR_OE_MASK)
\r
13424 #define SMARTCARD_LSR_PE_MASK (0x4U)
\r
13425 #define SMARTCARD_LSR_PE_SHIFT (2U)
\r
13426 /*! PE - Parity Error.
\r
13428 #define SMARTCARD_LSR_PE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_PE_SHIFT)) & SMARTCARD_LSR_PE_MASK)
\r
13429 #define SMARTCARD_LSR_FE_MASK (0x8U)
\r
13430 #define SMARTCARD_LSR_FE_SHIFT (3U)
\r
13431 /*! FE - Framing Error.
\r
13433 #define SMARTCARD_LSR_FE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_FE_SHIFT)) & SMARTCARD_LSR_FE_MASK)
\r
13434 #define SMARTCARD_LSR_THRE_MASK (0x20U)
\r
13435 #define SMARTCARD_LSR_THRE_SHIFT (5U)
\r
13436 /*! THRE - Transmitter Holding Register Empty.
\r
13438 #define SMARTCARD_LSR_THRE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_THRE_SHIFT)) & SMARTCARD_LSR_THRE_MASK)
\r
13439 #define SMARTCARD_LSR_TEMT_MASK (0x40U)
\r
13440 #define SMARTCARD_LSR_TEMT_SHIFT (6U)
\r
13441 /*! TEMT - Transmitter Empty.
\r
13443 #define SMARTCARD_LSR_TEMT(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_TEMT_SHIFT)) & SMARTCARD_LSR_TEMT_MASK)
\r
13444 #define SMARTCARD_LSR_RXFE_MASK (0x80U)
\r
13445 #define SMARTCARD_LSR_RXFE_SHIFT (7U)
\r
13446 /*! RXFE - Error in RX FIFO.
\r
13448 #define SMARTCARD_LSR_RXFE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_RXFE_SHIFT)) & SMARTCARD_LSR_RXFE_MASK)
\r
13451 /*! @name SCR - Scratch Pad Register */
\r
13453 #define SMARTCARD_SCR_PAD_MASK (0xFFU)
\r
13454 #define SMARTCARD_SCR_PAD_SHIFT (0U)
\r
13455 /*! PAD - A readable, writable byte.
\r
13457 #define SMARTCARD_SCR_PAD(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCR_PAD_SHIFT)) & SMARTCARD_SCR_PAD_MASK)
\r
13460 /*! @name OSR - Oversampling register */
\r
13462 #define SMARTCARD_OSR_OSFRAC_MASK (0xEU)
\r
13463 #define SMARTCARD_OSR_OSFRAC_SHIFT (1U)
\r
13464 /*! OSFRAC - Fractional part of the oversampling ratio, in units of 1/8th of an input clock period.
\r
13466 #define SMARTCARD_OSR_OSFRAC(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_OSR_OSFRAC_SHIFT)) & SMARTCARD_OSR_OSFRAC_MASK)
\r
13467 #define SMARTCARD_OSR_OSINT_MASK (0xF0U)
\r
13468 #define SMARTCARD_OSR_OSINT_SHIFT (4U)
\r
13469 /*! OSINT - Integer part of the oversampling ratio, minus 1.
\r
13471 #define SMARTCARD_OSR_OSINT(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_OSR_OSINT_SHIFT)) & SMARTCARD_OSR_OSINT_MASK)
\r
13472 #define SMARTCARD_OSR_FDINT_MASK (0x7F00U)
\r
13473 #define SMARTCARD_OSR_FDINT_SHIFT (8U)
\r
13474 /*! FDINT - These bits act as a more-significant extension of the OSint field, allowing an
\r
13475 * oversampling ratio up to 2048 as required by ISO7816-3.
\r
13477 #define SMARTCARD_OSR_FDINT(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_OSR_FDINT_SHIFT)) & SMARTCARD_OSR_FDINT_MASK)
\r
13480 /*! @name SCICTRL - Smart Card Interface control register */
\r
13482 #define SMARTCARD_SCICTRL_SCIEN_MASK (0x1U)
\r
13483 #define SMARTCARD_SCICTRL_SCIEN_SHIFT (0U)
\r
13484 /*! SCIEN - Smart Card Interface Enable.
\r
13486 #define SMARTCARD_SCICTRL_SCIEN(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_SCIEN_SHIFT)) & SMARTCARD_SCICTRL_SCIEN_MASK)
\r
13487 #define SMARTCARD_SCICTRL_NACKDIS_MASK (0x2U)
\r
13488 #define SMARTCARD_SCICTRL_NACKDIS_SHIFT (1U)
\r
13489 /*! NACKDIS - NACK response disable.
\r
13491 #define SMARTCARD_SCICTRL_NACKDIS(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_NACKDIS_SHIFT)) & SMARTCARD_SCICTRL_NACKDIS_MASK)
\r
13492 #define SMARTCARD_SCICTRL_PROTSEL_MASK (0x4U)
\r
13493 #define SMARTCARD_SCICTRL_PROTSEL_SHIFT (2U)
\r
13494 /*! PROTSEL - Protocol selection as defined in the ISO7816-3 standard.
\r
13496 #define SMARTCARD_SCICTRL_PROTSEL(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_PROTSEL_SHIFT)) & SMARTCARD_SCICTRL_PROTSEL_MASK)
\r
13497 #define SMARTCARD_SCICTRL_TXRETRY_MASK (0xE0U)
\r
13498 #define SMARTCARD_SCICTRL_TXRETRY_SHIFT (5U)
\r
13499 /*! TXRETRY - Maximum number of retransmissions in case of a negative acknowledge (protocol T=0).
\r
13501 #define SMARTCARD_SCICTRL_TXRETRY(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_TXRETRY_SHIFT)) & SMARTCARD_SCICTRL_TXRETRY_MASK)
\r
13502 #define SMARTCARD_SCICTRL_GUARDTIME_MASK (0xFF00U)
\r
13503 #define SMARTCARD_SCICTRL_GUARDTIME_SHIFT (8U)
\r
13504 /*! GUARDTIME - Extra guard time.
\r
13506 #define SMARTCARD_SCICTRL_GUARDTIME(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_GUARDTIME_SHIFT)) & SMARTCARD_SCICTRL_GUARDTIME_MASK)
\r
13512 */ /* end of group SMARTCARD_Register_Masks */
\r
13515 /* SMARTCARD - Peripheral instance base addresses */
\r
13516 /** Peripheral SMARTCARD0 base address */
\r
13517 #define SMARTCARD0_BASE (0x40036000u)
\r
13518 /** Peripheral SMARTCARD0 base pointer */
\r
13519 #define SMARTCARD0 ((SMARTCARD_Type *)SMARTCARD0_BASE)
\r
13520 /** Peripheral SMARTCARD1 base address */
\r
13521 #define SMARTCARD1_BASE (0x40037000u)
\r
13522 /** Peripheral SMARTCARD1 base pointer */
\r
13523 #define SMARTCARD1 ((SMARTCARD_Type *)SMARTCARD1_BASE)
\r
13524 /** Array initializer of SMARTCARD peripheral base addresses */
\r
13525 #define SMARTCARD_BASE_ADDRS { SMARTCARD0_BASE, SMARTCARD1_BASE }
\r
13526 /** Array initializer of SMARTCARD peripheral base pointers */
\r
13527 #define SMARTCARD_BASE_PTRS { SMARTCARD0, SMARTCARD1 }
\r
13528 /** Interrupt vectors for the SMARTCARD peripheral type */
\r
13529 #define SMARTCARD_IRQS { SMARTCARD0_IRQn, SMARTCARD1_IRQn }
\r
13533 */ /* end of group SMARTCARD_Peripheral_Access_Layer */
\r
13536 /* ----------------------------------------------------------------------------
\r
13537 -- SPI Peripheral Access Layer
\r
13538 ---------------------------------------------------------------------------- */
\r
13541 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
\r
13545 /** SPI - Register Layout Typedef */
\r
13547 uint8_t RESERVED_0[1024];
\r
13548 __IO uint32_t CFG; /**< SPI Configuration register, offset: 0x400 */
\r
13549 __IO uint32_t DLY; /**< SPI Delay register, offset: 0x404 */
\r
13550 __IO uint32_t STAT; /**< SPI Status. Some status flags can be cleared by writing a 1 to that bit position., offset: 0x408 */
\r
13551 __IO uint32_t INTENSET; /**< SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0x40C */
\r
13552 __O uint32_t INTENCLR; /**< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared., offset: 0x410 */
\r
13553 uint8_t RESERVED_1[16];
\r
13554 __IO uint32_t DIV; /**< SPI clock Divider, offset: 0x424 */
\r
13555 __I uint32_t INTSTAT; /**< SPI Interrupt Status, offset: 0x428 */
\r
13556 uint8_t RESERVED_2[2516];
\r
13557 __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */
\r
13558 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */
\r
13559 __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */
\r
13560 uint8_t RESERVED_3[4];
\r
13561 __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */
\r
13562 __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */
\r
13563 __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */
\r
13564 uint8_t RESERVED_4[4];
\r
13565 __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */
\r
13566 uint8_t RESERVED_5[12];
\r
13567 __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */
\r
13568 uint8_t RESERVED_6[12];
\r
13569 __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */
\r
13570 uint8_t RESERVED_7[440];
\r
13571 __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */
\r
13574 /* ----------------------------------------------------------------------------
\r
13575 -- SPI Register Masks
\r
13576 ---------------------------------------------------------------------------- */
\r
13579 * @addtogroup SPI_Register_Masks SPI Register Masks
\r
13583 /*! @name CFG - SPI Configuration register */
\r
13585 #define SPI_CFG_ENABLE_MASK (0x1U)
\r
13586 #define SPI_CFG_ENABLE_SHIFT (0U)
\r
13587 /*! ENABLE - SPI enable.
\r
13588 * 0b0..Disabled. The SPI is disabled and the internal state machine and counters are reset.
\r
13589 * 0b1..Enabled. The SPI is enabled for operation.
\r
13591 #define SPI_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK)
\r
13592 #define SPI_CFG_MASTER_MASK (0x4U)
\r
13593 #define SPI_CFG_MASTER_SHIFT (2U)
\r
13594 /*! MASTER - Master mode select.
\r
13595 * 0b0..Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output.
\r
13596 * 0b1..Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input.
\r
13598 #define SPI_CFG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK)
\r
13599 #define SPI_CFG_LSBF_MASK (0x8U)
\r
13600 #define SPI_CFG_LSBF_SHIFT (3U)
\r
13601 /*! LSBF - LSB First mode enable.
\r
13602 * 0b0..Standard. Data is transmitted and received in standard MSB first order.
\r
13603 * 0b1..Reverse. Data is transmitted and received in reverse order (LSB first).
\r
13605 #define SPI_CFG_LSBF(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK)
\r
13606 #define SPI_CFG_CPHA_MASK (0x10U)
\r
13607 #define SPI_CFG_CPHA_SHIFT (4U)
\r
13608 /*! CPHA - Clock Phase select.
\r
13609 * 0b0..Change. The SPI captures serial data on the first clock transition of the transfer (when the clock
\r
13610 * changes away from the rest state). Data is changed on the following edge.
\r
13611 * 0b1..Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock
\r
13612 * changes away from the rest state). Data is captured on the following edge.
\r
13614 #define SPI_CFG_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK)
\r
13615 #define SPI_CFG_CPOL_MASK (0x20U)
\r
13616 #define SPI_CFG_CPOL_SHIFT (5U)
\r
13617 /*! CPOL - Clock Polarity select.
\r
13618 * 0b0..Low. The rest state of the clock (between transfers) is low.
\r
13619 * 0b1..High. The rest state of the clock (between transfers) is high.
\r
13621 #define SPI_CFG_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK)
\r
13622 #define SPI_CFG_LOOP_MASK (0x80U)
\r
13623 #define SPI_CFG_LOOP_SHIFT (7U)
\r
13624 /*! LOOP - Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit
\r
13625 * and receive data connected together to allow simple software testing.
\r
13629 #define SPI_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK)
\r
13630 #define SPI_CFG_SPOL0_MASK (0x100U)
\r
13631 #define SPI_CFG_SPOL0_SHIFT (8U)
\r
13632 /*! SPOL0 - SSEL0 Polarity select.
\r
13633 * 0b0..Low. The SSEL0 pin is active low.
\r
13634 * 0b1..High. The SSEL0 pin is active high.
\r
13636 #define SPI_CFG_SPOL0(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK)
\r
13637 #define SPI_CFG_SPOL1_MASK (0x200U)
\r
13638 #define SPI_CFG_SPOL1_SHIFT (9U)
\r
13639 /*! SPOL1 - SSEL1 Polarity select.
\r
13640 * 0b0..Low. The SSEL1 pin is active low.
\r
13641 * 0b1..High. The SSEL1 pin is active high.
\r
13643 #define SPI_CFG_SPOL1(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK)
\r
13644 #define SPI_CFG_SPOL2_MASK (0x400U)
\r
13645 #define SPI_CFG_SPOL2_SHIFT (10U)
\r
13646 /*! SPOL2 - SSEL2 Polarity select.
\r
13647 * 0b0..Low. The SSEL2 pin is active low.
\r
13648 * 0b1..High. The SSEL2 pin is active high.
\r
13650 #define SPI_CFG_SPOL2(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK)
\r
13651 #define SPI_CFG_SPOL3_MASK (0x800U)
\r
13652 #define SPI_CFG_SPOL3_SHIFT (11U)
\r
13653 /*! SPOL3 - SSEL3 Polarity select.
\r
13654 * 0b0..Low. The SSEL3 pin is active low.
\r
13655 * 0b1..High. The SSEL3 pin is active high.
\r
13657 #define SPI_CFG_SPOL3(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK)
\r
13660 /*! @name DLY - SPI Delay register */
\r
13662 #define SPI_DLY_PRE_DELAY_MASK (0xFU)
\r
13663 #define SPI_DLY_PRE_DELAY_SHIFT (0U)
\r
13664 /*! PRE_DELAY - Controls the amount of time between SSEL assertion and the beginning of a data
\r
13665 * transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This
\r
13666 * is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI
\r
13667 * clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are
\r
13670 #define SPI_DLY_PRE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK)
\r
13671 #define SPI_DLY_POST_DELAY_MASK (0xF0U)
\r
13672 #define SPI_DLY_POST_DELAY_SHIFT (4U)
\r
13673 /*! POST_DELAY - Controls the amount of time between the end of a data transfer and SSEL
\r
13674 * deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock
\r
13675 * times are inserted. 0xF = 15 SPI clock times are inserted.
\r
13677 #define SPI_DLY_POST_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK)
\r
13678 #define SPI_DLY_FRAME_DELAY_MASK (0xF00U)
\r
13679 #define SPI_DLY_FRAME_DELAY_SHIFT (8U)
\r
13680 /*! FRAME_DELAY - If the EOF flag is set, controls the minimum amount of time between the current
\r
13681 * frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1
\r
13682 * = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock
\r
13683 * times are inserted.
\r
13685 #define SPI_DLY_FRAME_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK)
\r
13686 #define SPI_DLY_TRANSFER_DELAY_MASK (0xF000U)
\r
13687 #define SPI_DLY_TRANSFER_DELAY_SHIFT (12U)
\r
13688 /*! TRANSFER_DELAY - Controls the minimum amount of time that the SSEL is deasserted between
\r
13689 * transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1
\r
13690 * = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that
\r
13691 * SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16
\r
13692 * SPI clock times.
\r
13694 #define SPI_DLY_TRANSFER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK)
\r
13697 /*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position. */
\r
13699 #define SPI_STAT_SSA_MASK (0x10U)
\r
13700 #define SPI_STAT_SSA_SHIFT (4U)
\r
13701 /*! SSA - Slave Select Assert. This flag is set whenever any slave select transitions from
\r
13702 * deasserted to asserted, in both master and slave modes. This allows determining when the SPI
\r
13703 * transmit/receive functions become busy, and allows waking up the device from reduced power modes when a
\r
13704 * slave mode access begins. This flag is cleared by software.
\r
13706 #define SPI_STAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK)
\r
13707 #define SPI_STAT_SSD_MASK (0x20U)
\r
13708 #define SPI_STAT_SSD_SHIFT (5U)
\r
13709 /*! SSD - Slave Select Deassert. This flag is set whenever any asserted slave selects transition to
\r
13710 * deasserted, in both master and slave modes. This allows determining when the SPI
\r
13711 * transmit/receive functions become idle. This flag is cleared by software.
\r
13713 #define SPI_STAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK)
\r
13714 #define SPI_STAT_STALLED_MASK (0x40U)
\r
13715 #define SPI_STAT_STALLED_SHIFT (6U)
\r
13716 /*! STALLED - Stalled status flag. This indicates whether the SPI is currently in a stall condition.
\r
13718 #define SPI_STAT_STALLED(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK)
\r
13719 #define SPI_STAT_ENDTRANSFER_MASK (0x80U)
\r
13720 #define SPI_STAT_ENDTRANSFER_SHIFT (7U)
\r
13721 /*! ENDTRANSFER - End Transfer control bit. Software can set this bit to force an end to the current
\r
13722 * transfer when the transmitter finishes any activity already in progress, as if the EOT flag
\r
13723 * had been set prior to the last transmission. This capability is included to support cases where
\r
13724 * it is not known when transmit data is written that it will be the end of a transfer. The bit
\r
13725 * is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end
\r
13726 * of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted.
\r
13728 #define SPI_STAT_ENDTRANSFER(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK)
\r
13729 #define SPI_STAT_MSTIDLE_MASK (0x100U)
\r
13730 #define SPI_STAT_MSTIDLE_SHIFT (8U)
\r
13731 /*! MSTIDLE - Master idle status flag. This bit is 1 whenever the SPI master function is fully idle.
\r
13732 * This means that the transmit holding register is empty and the transmitter is not in the
\r
13733 * process of sending data.
\r
13735 #define SPI_STAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK)
\r
13738 /*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */
\r
13740 #define SPI_INTENSET_SSAEN_MASK (0x10U)
\r
13741 #define SPI_INTENSET_SSAEN_SHIFT (4U)
\r
13742 /*! SSAEN - Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted.
\r
13743 * 0b0..Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted.
\r
13744 * 0b1..Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted.
\r
13746 #define SPI_INTENSET_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK)
\r
13747 #define SPI_INTENSET_SSDEN_MASK (0x20U)
\r
13748 #define SPI_INTENSET_SSDEN_SHIFT (5U)
\r
13749 /*! SSDEN - Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted.
\r
13750 * 0b0..Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted.
\r
13751 * 0b1..Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted.
\r
13753 #define SPI_INTENSET_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK)
\r
13754 #define SPI_INTENSET_MSTIDLEEN_MASK (0x100U)
\r
13755 #define SPI_INTENSET_MSTIDLEEN_SHIFT (8U)
\r
13756 /*! MSTIDLEEN - Master idle interrupt enable.
\r
13757 * 0b0..No interrupt will be generated when the SPI master function is idle.
\r
13758 * 0b1..An interrupt will be generated when the SPI master function is fully idle.
\r
13760 #define SPI_INTENSET_MSTIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK)
\r
13763 /*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. */
\r
13765 #define SPI_INTENCLR_SSAEN_MASK (0x10U)
\r
13766 #define SPI_INTENCLR_SSAEN_SHIFT (4U)
\r
13767 /*! SSAEN - Writing 1 clears the corresponding bit in the INTENSET register.
\r
13769 #define SPI_INTENCLR_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK)
\r
13770 #define SPI_INTENCLR_SSDEN_MASK (0x20U)
\r
13771 #define SPI_INTENCLR_SSDEN_SHIFT (5U)
\r
13772 /*! SSDEN - Writing 1 clears the corresponding bit in the INTENSET register.
\r
13774 #define SPI_INTENCLR_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK)
\r
13775 #define SPI_INTENCLR_MSTIDLE_MASK (0x100U)
\r
13776 #define SPI_INTENCLR_MSTIDLE_SHIFT (8U)
\r
13777 /*! MSTIDLE - Writing 1 clears the corresponding bit in the INTENSET register.
\r
13779 #define SPI_INTENCLR_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK)
\r
13782 /*! @name DIV - SPI clock Divider */
\r
13784 #define SPI_DIV_DIVVAL_MASK (0xFFFFU)
\r
13785 #define SPI_DIV_DIVVAL_SHIFT (0U)
\r
13786 /*! DIVVAL - Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the
\r
13787 * SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1,
\r
13788 * the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results
\r
13791 #define SPI_DIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK)
\r
13794 /*! @name INTSTAT - SPI Interrupt Status */
\r
13796 #define SPI_INTSTAT_SSA_MASK (0x10U)
\r
13797 #define SPI_INTSTAT_SSA_SHIFT (4U)
\r
13798 /*! SSA - Slave Select Assert.
\r
13800 #define SPI_INTSTAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK)
\r
13801 #define SPI_INTSTAT_SSD_MASK (0x20U)
\r
13802 #define SPI_INTSTAT_SSD_SHIFT (5U)
\r
13803 /*! SSD - Slave Select Deassert.
\r
13805 #define SPI_INTSTAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK)
\r
13806 #define SPI_INTSTAT_MSTIDLE_MASK (0x100U)
\r
13807 #define SPI_INTSTAT_MSTIDLE_SHIFT (8U)
\r
13808 /*! MSTIDLE - Master Idle status flag.
\r
13810 #define SPI_INTSTAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK)
\r
13813 /*! @name FIFOCFG - FIFO configuration and enable register. */
\r
13815 #define SPI_FIFOCFG_ENABLETX_MASK (0x1U)
\r
13816 #define SPI_FIFOCFG_ENABLETX_SHIFT (0U)
\r
13817 /*! ENABLETX - Enable the transmit FIFO.
\r
13818 * 0b0..The transmit FIFO is not enabled.
\r
13819 * 0b1..The transmit FIFO is enabled.
\r
13821 #define SPI_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK)
\r
13822 #define SPI_FIFOCFG_ENABLERX_MASK (0x2U)
\r
13823 #define SPI_FIFOCFG_ENABLERX_SHIFT (1U)
\r
13824 /*! ENABLERX - Enable the receive FIFO.
\r
13825 * 0b0..The receive FIFO is not enabled.
\r
13826 * 0b1..The receive FIFO is enabled.
\r
13828 #define SPI_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK)
\r
13829 #define SPI_FIFOCFG_SIZE_MASK (0x30U)
\r
13830 #define SPI_FIFOCFG_SIZE_SHIFT (4U)
\r
13831 /*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16
\r
13832 * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART.
\r
13834 #define SPI_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK)
\r
13835 #define SPI_FIFOCFG_DMATX_MASK (0x1000U)
\r
13836 #define SPI_FIFOCFG_DMATX_SHIFT (12U)
\r
13837 /*! DMATX - DMA configuration for transmit.
\r
13838 * 0b0..DMA is not used for the transmit function.
\r
13839 * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled.
\r
13841 #define SPI_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK)
\r
13842 #define SPI_FIFOCFG_DMARX_MASK (0x2000U)
\r
13843 #define SPI_FIFOCFG_DMARX_SHIFT (13U)
\r
13844 /*! DMARX - DMA configuration for receive.
\r
13845 * 0b0..DMA is not used for the receive function.
\r
13846 * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled.
\r
13848 #define SPI_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK)
\r
13849 #define SPI_FIFOCFG_WAKETX_MASK (0x4000U)
\r
13850 #define SPI_FIFOCFG_WAKETX_SHIFT (14U)
\r
13851 /*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power
\r
13852 * modes (up to power-down, as long as the peripheral function works in that power mode) without
\r
13853 * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The
\r
13854 * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware
\r
13855 * Wake-up control register.
\r
13856 * 0b0..Only enabled interrupts will wake up the device form reduced power modes.
\r
13857 * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in
\r
13858 * FIFOTRIG, even when the TXLVL interrupt is not enabled.
\r
13860 #define SPI_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK)
\r
13861 #define SPI_FIFOCFG_WAKERX_MASK (0x8000U)
\r
13862 #define SPI_FIFOCFG_WAKERX_SHIFT (15U)
\r
13863 /*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power
\r
13864 * modes (up to power-down, as long as the peripheral function works in that power mode) without
\r
13865 * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The
\r
13866 * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware
\r
13867 * Wake-up control register.
\r
13868 * 0b0..Only enabled interrupts will wake up the device form reduced power modes.
\r
13869 * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in
\r
13870 * FIFOTRIG, even when the RXLVL interrupt is not enabled.
\r
13872 #define SPI_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK)
\r
13873 #define SPI_FIFOCFG_EMPTYTX_MASK (0x10000U)
\r
13874 #define SPI_FIFOCFG_EMPTYTX_SHIFT (16U)
\r
13875 /*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied.
\r
13877 #define SPI_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK)
\r
13878 #define SPI_FIFOCFG_EMPTYRX_MASK (0x20000U)
\r
13879 #define SPI_FIFOCFG_EMPTYRX_SHIFT (17U)
\r
13880 /*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied.
\r
13882 #define SPI_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK)
\r
13885 /*! @name FIFOSTAT - FIFO status register. */
\r
13887 #define SPI_FIFOSTAT_TXERR_MASK (0x1U)
\r
13888 #define SPI_FIFOSTAT_TXERR_SHIFT (0U)
\r
13889 /*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow
\r
13890 * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is
\r
13891 * needed. Cleared by writing a 1 to this bit.
\r
13893 #define SPI_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK)
\r
13894 #define SPI_FIFOSTAT_RXERR_MASK (0x2U)
\r
13895 #define SPI_FIFOSTAT_RXERR_SHIFT (1U)
\r
13896 /*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA
\r
13897 * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit.
\r
13899 #define SPI_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK)
\r
13900 #define SPI_FIFOSTAT_PERINT_MASK (0x8U)
\r
13901 #define SPI_FIFOSTAT_PERINT_SHIFT (3U)
\r
13902 /*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted
\r
13903 * an interrupt. The details can be found by reading the peripheral's STAT register.
\r
13905 #define SPI_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK)
\r
13906 #define SPI_FIFOSTAT_TXEMPTY_MASK (0x10U)
\r
13907 #define SPI_FIFOSTAT_TXEMPTY_SHIFT (4U)
\r
13908 /*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data.
\r
13910 #define SPI_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK)
\r
13911 #define SPI_FIFOSTAT_TXNOTFULL_MASK (0x20U)
\r
13912 #define SPI_FIFOSTAT_TXNOTFULL_SHIFT (5U)
\r
13913 /*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be
\r
13914 * written. When 0, the transmit FIFO is full and another write would cause it to overflow.
\r
13916 #define SPI_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK)
\r
13917 #define SPI_FIFOSTAT_RXNOTEMPTY_MASK (0x40U)
\r
13918 #define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT (6U)
\r
13919 /*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty.
\r
13921 #define SPI_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK)
\r
13922 #define SPI_FIFOSTAT_RXFULL_MASK (0x80U)
\r
13923 #define SPI_FIFOSTAT_RXFULL_SHIFT (7U)
\r
13924 /*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to
\r
13925 * prevent the peripheral from causing an overflow.
\r
13927 #define SPI_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK)
\r
13928 #define SPI_FIFOSTAT_TXLVL_MASK (0x1F00U)
\r
13929 #define SPI_FIFOSTAT_TXLVL_SHIFT (8U)
\r
13930 /*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY
\r
13931 * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at
\r
13932 * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be
\r
13935 #define SPI_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK)
\r
13936 #define SPI_FIFOSTAT_RXLVL_MASK (0x1F0000U)
\r
13937 #define SPI_FIFOSTAT_RXLVL_SHIFT (16U)
\r
13938 /*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and
\r
13939 * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the
\r
13940 * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be
\r
13943 #define SPI_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK)
\r
13946 /*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */
\r
13948 #define SPI_FIFOTRIG_TXLVLENA_MASK (0x1U)
\r
13949 #define SPI_FIFOTRIG_TXLVLENA_SHIFT (0U)
\r
13950 /*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled
\r
13951 * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set.
\r
13952 * 0b0..Transmit FIFO level does not generate a FIFO level trigger.
\r
13953 * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register.
\r
13955 #define SPI_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK)
\r
13956 #define SPI_FIFOTRIG_RXLVLENA_MASK (0x2U)
\r
13957 #define SPI_FIFOTRIG_RXLVLENA_SHIFT (1U)
\r
13958 /*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled
\r
13959 * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set.
\r
13960 * 0b0..Receive FIFO level does not generate a FIFO level trigger.
\r
13961 * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register.
\r
13963 #define SPI_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK)
\r
13964 #define SPI_FIFOTRIG_TXLVL_MASK (0xF00U)
\r
13965 #define SPI_FIFOTRIG_TXLVL_SHIFT (8U)
\r
13966 /*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled
\r
13967 * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to
\r
13968 * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO
\r
13969 * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX
\r
13970 * FIFO level decreases to 15 entries (is no longer full).
\r
13972 #define SPI_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK)
\r
13973 #define SPI_FIFOTRIG_RXLVL_MASK (0xF0000U)
\r
13974 #define SPI_FIFOTRIG_RXLVL_SHIFT (16U)
\r
13975 /*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data
\r
13976 * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level
\r
13977 * can wake up the device just enough to perform DMA, then return to the reduced power mode. See
\r
13978 * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no
\r
13979 * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX
\r
13980 * FIFO has received 16 entries (has become full).
\r
13982 #define SPI_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK)
\r
13985 /*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */
\r
13987 #define SPI_FIFOINTENSET_TXERR_MASK (0x1U)
\r
13988 #define SPI_FIFOINTENSET_TXERR_SHIFT (0U)
\r
13989 /*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register.
\r
13990 * 0b0..No interrupt will be generated for a transmit error.
\r
13991 * 0b1..An interrupt will be generated when a transmit error occurs.
\r
13993 #define SPI_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK)
\r
13994 #define SPI_FIFOINTENSET_RXERR_MASK (0x2U)
\r
13995 #define SPI_FIFOINTENSET_RXERR_SHIFT (1U)
\r
13996 /*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register.
\r
13997 * 0b0..No interrupt will be generated for a receive error.
\r
13998 * 0b1..An interrupt will be generated when a receive error occurs.
\r
14000 #define SPI_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK)
\r
14001 #define SPI_FIFOINTENSET_TXLVL_MASK (0x4U)
\r
14002 #define SPI_FIFOINTENSET_TXLVL_SHIFT (2U)
\r
14003 /*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level
\r
14004 * specified by the TXLVL field in the FIFOTRIG register.
\r
14005 * 0b0..No interrupt will be generated based on the TX FIFO level.
\r
14006 * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases
\r
14007 * to the level specified by TXLVL in the FIFOTRIG register.
\r
14009 #define SPI_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK)
\r
14010 #define SPI_FIFOINTENSET_RXLVL_MASK (0x8U)
\r
14011 #define SPI_FIFOINTENSET_RXLVL_SHIFT (3U)
\r
14012 /*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level
\r
14013 * specified by the TXLVL field in the FIFOTRIG register.
\r
14014 * 0b0..No interrupt will be generated based on the RX FIFO level.
\r
14015 * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level
\r
14016 * increases to the level specified by RXLVL in the FIFOTRIG register.
\r
14018 #define SPI_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK)
\r
14021 /*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */
\r
14023 #define SPI_FIFOINTENCLR_TXERR_MASK (0x1U)
\r
14024 #define SPI_FIFOINTENCLR_TXERR_SHIFT (0U)
\r
14025 /*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register.
\r
14027 #define SPI_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK)
\r
14028 #define SPI_FIFOINTENCLR_RXERR_MASK (0x2U)
\r
14029 #define SPI_FIFOINTENCLR_RXERR_SHIFT (1U)
\r
14030 /*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register.
\r
14032 #define SPI_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK)
\r
14033 #define SPI_FIFOINTENCLR_TXLVL_MASK (0x4U)
\r
14034 #define SPI_FIFOINTENCLR_TXLVL_SHIFT (2U)
\r
14035 /*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register.
\r
14037 #define SPI_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK)
\r
14038 #define SPI_FIFOINTENCLR_RXLVL_MASK (0x8U)
\r
14039 #define SPI_FIFOINTENCLR_RXLVL_SHIFT (3U)
\r
14040 /*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register.
\r
14042 #define SPI_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK)
\r
14045 /*! @name FIFOINTSTAT - FIFO interrupt status register. */
\r
14047 #define SPI_FIFOINTSTAT_TXERR_MASK (0x1U)
\r
14048 #define SPI_FIFOINTSTAT_TXERR_SHIFT (0U)
\r
14049 /*! TXERR - TX FIFO error.
\r
14051 #define SPI_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK)
\r
14052 #define SPI_FIFOINTSTAT_RXERR_MASK (0x2U)
\r
14053 #define SPI_FIFOINTSTAT_RXERR_SHIFT (1U)
\r
14054 /*! RXERR - RX FIFO error.
\r
14056 #define SPI_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK)
\r
14057 #define SPI_FIFOINTSTAT_TXLVL_MASK (0x4U)
\r
14058 #define SPI_FIFOINTSTAT_TXLVL_SHIFT (2U)
\r
14059 /*! TXLVL - Transmit FIFO level interrupt.
\r
14061 #define SPI_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK)
\r
14062 #define SPI_FIFOINTSTAT_RXLVL_MASK (0x8U)
\r
14063 #define SPI_FIFOINTSTAT_RXLVL_SHIFT (3U)
\r
14064 /*! RXLVL - Receive FIFO level interrupt.
\r
14066 #define SPI_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK)
\r
14067 #define SPI_FIFOINTSTAT_PERINT_MASK (0x10U)
\r
14068 #define SPI_FIFOINTSTAT_PERINT_SHIFT (4U)
\r
14069 /*! PERINT - Peripheral interrupt.
\r
14071 #define SPI_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK)
\r
14074 /*! @name FIFOWR - FIFO write data. */
\r
14076 #define SPI_FIFOWR_TXDATA_MASK (0xFFFFU)
\r
14077 #define SPI_FIFOWR_TXDATA_SHIFT (0U)
\r
14078 /*! TXDATA - Transmit data to the FIFO.
\r
14080 #define SPI_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK)
\r
14081 #define SPI_FIFOWR_TXSSEL0_N_MASK (0x10000U)
\r
14082 #define SPI_FIFOWR_TXSSEL0_N_SHIFT (16U)
\r
14083 /*! TXSSEL0_N - Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default.
\r
14084 * 0b0..SSEL0 asserted.
\r
14085 * 0b1..SSEL0 not asserted.
\r
14087 #define SPI_FIFOWR_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK)
\r
14088 #define SPI_FIFOWR_TXSSEL1_N_MASK (0x20000U)
\r
14089 #define SPI_FIFOWR_TXSSEL1_N_SHIFT (17U)
\r
14090 /*! TXSSEL1_N - Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default.
\r
14091 * 0b0..SSEL1 asserted.
\r
14092 * 0b1..SSEL1 not asserted.
\r
14094 #define SPI_FIFOWR_TXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK)
\r
14095 #define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U)
\r
14096 #define SPI_FIFOWR_TXSSEL2_N_SHIFT (18U)
\r
14097 /*! TXSSEL2_N - Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default.
\r
14098 * 0b0..SSEL2 asserted.
\r
14099 * 0b1..SSEL2 not asserted.
\r
14101 #define SPI_FIFOWR_TXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK)
\r
14102 #define SPI_FIFOWR_TXSSEL3_N_MASK (0x80000U)
\r
14103 #define SPI_FIFOWR_TXSSEL3_N_SHIFT (19U)
\r
14104 /*! TXSSEL3_N - Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default.
\r
14105 * 0b0..SSEL3 asserted.
\r
14106 * 0b1..SSEL3 not asserted.
\r
14108 #define SPI_FIFOWR_TXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK)
\r
14109 #define SPI_FIFOWR_EOT_MASK (0x100000U)
\r
14110 #define SPI_FIFOWR_EOT_SHIFT (20U)
\r
14111 /*! EOT - End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain
\r
14112 * so far at least the time specified by the Transfer_delay value in the DLY register.
\r
14113 * 0b0..SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data.
\r
14114 * 0b1..SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data.
\r
14116 #define SPI_FIFOWR_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK)
\r
14117 #define SPI_FIFOWR_EOF_MASK (0x200000U)
\r
14118 #define SPI_FIFOWR_EOF_SHIFT (21U)
\r
14119 /*! EOF - End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value
\r
14120 * in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay
\r
14121 * value = 0. This control can be used as part of the support for frame lengths greater than 16
\r
14123 * 0b0..Data not EOF. This piece of data transmitted is not treated as the end of a frame.
\r
14124 * 0b1..Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be
\r
14125 * inserted before subsequent data is transmitted.
\r
14127 #define SPI_FIFOWR_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK)
\r
14128 #define SPI_FIFOWR_RXIGNORE_MASK (0x400000U)
\r
14129 #define SPI_FIFOWR_RXIGNORE_SHIFT (22U)
\r
14130 /*! RXIGNORE - Receive Ignore. This allows data to be transmitted using the SPI without the need to
\r
14131 * read unneeded data from the receiver. Setting this bit simplifies the transmit process and can
\r
14132 * be used with the DMA.
\r
14133 * 0b0..Read received data. Received data must be read in order to allow transmission to progress. SPI transmit
\r
14134 * will halt when the receive data FIFO is full. In slave mode, an overrun error will occur if received data
\r
14135 * is not read before new data is received.
\r
14136 * 0b1..Ignore received data. Received data is ignored, allowing transmission without reading unneeded received
\r
14137 * data. No receiver flags are generated.
\r
14139 #define SPI_FIFOWR_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK)
\r
14140 #define SPI_FIFOWR_LEN_MASK (0xF000000U)
\r
14141 #define SPI_FIFOWR_LEN_SHIFT (24U)
\r
14142 /*! LEN - Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths
\r
14143 * greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved.
\r
14144 * 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5 bits in length. 0xF = Data
\r
14145 * transfer is 16 bits in length.
\r
14147 #define SPI_FIFOWR_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK)
\r
14150 /*! @name FIFORD - FIFO read data. */
\r
14152 #define SPI_FIFORD_RXDATA_MASK (0xFFFFU)
\r
14153 #define SPI_FIFORD_RXDATA_SHIFT (0U)
\r
14154 /*! RXDATA - Received data from the FIFO.
\r
14156 #define SPI_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK)
\r
14157 #define SPI_FIFORD_RXSSEL0_N_MASK (0x10000U)
\r
14158 #define SPI_FIFORD_RXSSEL0_N_SHIFT (16U)
\r
14159 /*! RXSSEL0_N - Slave Select for receive. This field allows the state of the SSEL0 pin to be saved
\r
14160 * along with received data. The value will reflect the SSEL0 pin for both master and slave
\r
14161 * operation. A zero indicates that a slave select is active. The actual polarity of each slave select
\r
14162 * pin is configured by the related SPOL bit in CFG.
\r
14164 #define SPI_FIFORD_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK)
\r
14165 #define SPI_FIFORD_RXSSEL1_N_MASK (0x20000U)
\r
14166 #define SPI_FIFORD_RXSSEL1_N_SHIFT (17U)
\r
14167 /*! RXSSEL1_N - Slave Select for receive. This field allows the state of the SSEL1 pin to be saved
\r
14168 * along with received data. The value will reflect the SSEL1 pin for both master and slave
\r
14169 * operation. A zero indicates that a slave select is active. The actual polarity of each slave select
\r
14170 * pin is configured by the related SPOL bit in CFG.
\r
14172 #define SPI_FIFORD_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK)
\r
14173 #define SPI_FIFORD_RXSSEL2_N_MASK (0x40000U)
\r
14174 #define SPI_FIFORD_RXSSEL2_N_SHIFT (18U)
\r
14175 /*! RXSSEL2_N - Slave Select for receive. This field allows the state of the SSEL2 pin to be saved
\r
14176 * along with received data. The value will reflect the SSEL2 pin for both master and slave
\r
14177 * operation. A zero indicates that a slave select is active. The actual polarity of each slave select
\r
14178 * pin is configured by the related SPOL bit in CFG.
\r
14180 #define SPI_FIFORD_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK)
\r
14181 #define SPI_FIFORD_RXSSEL3_N_MASK (0x80000U)
\r
14182 #define SPI_FIFORD_RXSSEL3_N_SHIFT (19U)
\r
14183 /*! RXSSEL3_N - Slave Select for receive. This field allows the state of the SSEL3 pin to be saved
\r
14184 * along with received data. The value will reflect the SSEL3 pin for both master and slave
\r
14185 * operation. A zero indicates that a slave select is active. The actual polarity of each slave select
\r
14186 * pin is configured by the related SPOL bit in CFG.
\r
14188 #define SPI_FIFORD_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK)
\r
14189 #define SPI_FIFORD_SOT_MASK (0x100000U)
\r
14190 #define SPI_FIFORD_SOT_SHIFT (20U)
\r
14191 /*! SOT - Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went
\r
14192 * from deasserted to asserted (i.e., any previous transfer has ended). This information can be
\r
14193 * used to identify the first piece of data in cases where the transfer length is greater than 16
\r
14196 #define SPI_FIFORD_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK)
\r
14199 /*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */
\r
14201 #define SPI_FIFORDNOPOP_RXDATA_MASK (0xFFFFU)
\r
14202 #define SPI_FIFORDNOPOP_RXDATA_SHIFT (0U)
\r
14203 /*! RXDATA - Received data from the FIFO.
\r
14205 #define SPI_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK)
\r
14206 #define SPI_FIFORDNOPOP_RXSSEL0_N_MASK (0x10000U)
\r
14207 #define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT (16U)
\r
14208 /*! RXSSEL0_N - Slave Select for receive.
\r
14210 #define SPI_FIFORDNOPOP_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK)
\r
14211 #define SPI_FIFORDNOPOP_RXSSEL1_N_MASK (0x20000U)
\r
14212 #define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT (17U)
\r
14213 /*! RXSSEL1_N - Slave Select for receive.
\r
14215 #define SPI_FIFORDNOPOP_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK)
\r
14216 #define SPI_FIFORDNOPOP_RXSSEL2_N_MASK (0x40000U)
\r
14217 #define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT (18U)
\r
14218 /*! RXSSEL2_N - Slave Select for receive.
\r
14220 #define SPI_FIFORDNOPOP_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK)
\r
14221 #define SPI_FIFORDNOPOP_RXSSEL3_N_MASK (0x80000U)
\r
14222 #define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT (19U)
\r
14223 /*! RXSSEL3_N - Slave Select for receive.
\r
14225 #define SPI_FIFORDNOPOP_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK)
\r
14226 #define SPI_FIFORDNOPOP_SOT_MASK (0x100000U)
\r
14227 #define SPI_FIFORDNOPOP_SOT_SHIFT (20U)
\r
14228 /*! SOT - Start of transfer flag.
\r
14230 #define SPI_FIFORDNOPOP_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK)
\r
14233 /*! @name ID - Peripheral identification register. */
\r
14235 #define SPI_ID_APERTURE_MASK (0xFFU)
\r
14236 #define SPI_ID_APERTURE_SHIFT (0U)
\r
14237 /*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture.
\r
14239 #define SPI_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_APERTURE_SHIFT)) & SPI_ID_APERTURE_MASK)
\r
14240 #define SPI_ID_MINOR_REV_MASK (0xF00U)
\r
14241 #define SPI_ID_MINOR_REV_SHIFT (8U)
\r
14242 /*! MINOR_REV - Minor revision of module implementation.
\r
14244 #define SPI_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MINOR_REV_SHIFT)) & SPI_ID_MINOR_REV_MASK)
\r
14245 #define SPI_ID_MAJOR_REV_MASK (0xF000U)
\r
14246 #define SPI_ID_MAJOR_REV_SHIFT (12U)
\r
14247 /*! MAJOR_REV - Major revision of module implementation.
\r
14249 #define SPI_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MAJOR_REV_SHIFT)) & SPI_ID_MAJOR_REV_MASK)
\r
14250 #define SPI_ID_ID_MASK (0xFFFF0000U)
\r
14251 #define SPI_ID_ID_SHIFT (16U)
\r
14252 /*! ID - Module identifier for the selected function.
\r
14254 #define SPI_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_ID_SHIFT)) & SPI_ID_ID_MASK)
\r
14260 */ /* end of group SPI_Register_Masks */
\r
14263 /* SPI - Peripheral instance base addresses */
\r
14264 /** Peripheral SPI0 base address */
\r
14265 #define SPI0_BASE (0x40086000u)
\r
14266 /** Peripheral SPI0 base pointer */
\r
14267 #define SPI0 ((SPI_Type *)SPI0_BASE)
\r
14268 /** Peripheral SPI1 base address */
\r
14269 #define SPI1_BASE (0x40087000u)
\r
14270 /** Peripheral SPI1 base pointer */
\r
14271 #define SPI1 ((SPI_Type *)SPI1_BASE)
\r
14272 /** Peripheral SPI2 base address */
\r
14273 #define SPI2_BASE (0x40088000u)
\r
14274 /** Peripheral SPI2 base pointer */
\r
14275 #define SPI2 ((SPI_Type *)SPI2_BASE)
\r
14276 /** Peripheral SPI3 base address */
\r
14277 #define SPI3_BASE (0x40089000u)
\r
14278 /** Peripheral SPI3 base pointer */
\r
14279 #define SPI3 ((SPI_Type *)SPI3_BASE)
\r
14280 /** Peripheral SPI4 base address */
\r
14281 #define SPI4_BASE (0x4008A000u)
\r
14282 /** Peripheral SPI4 base pointer */
\r
14283 #define SPI4 ((SPI_Type *)SPI4_BASE)
\r
14284 /** Peripheral SPI5 base address */
\r
14285 #define SPI5_BASE (0x40096000u)
\r
14286 /** Peripheral SPI5 base pointer */
\r
14287 #define SPI5 ((SPI_Type *)SPI5_BASE)
\r
14288 /** Peripheral SPI6 base address */
\r
14289 #define SPI6_BASE (0x40097000u)
\r
14290 /** Peripheral SPI6 base pointer */
\r
14291 #define SPI6 ((SPI_Type *)SPI6_BASE)
\r
14292 /** Peripheral SPI7 base address */
\r
14293 #define SPI7_BASE (0x40098000u)
\r
14294 /** Peripheral SPI7 base pointer */
\r
14295 #define SPI7 ((SPI_Type *)SPI7_BASE)
\r
14296 /** Peripheral SPI8 base address */
\r
14297 #define SPI8_BASE (0x40099000u)
\r
14298 /** Peripheral SPI8 base pointer */
\r
14299 #define SPI8 ((SPI_Type *)SPI8_BASE)
\r
14300 /** Peripheral SPI9 base address */
\r
14301 #define SPI9_BASE (0x4009A000u)
\r
14302 /** Peripheral SPI9 base pointer */
\r
14303 #define SPI9 ((SPI_Type *)SPI9_BASE)
\r
14304 /** Peripheral SPI10 base address */
\r
14305 #define SPI10_BASE (0x4009F000u)
\r
14306 /** Peripheral SPI10 base pointer */
\r
14307 #define SPI10 ((SPI_Type *)SPI10_BASE)
\r
14308 /** Array initializer of SPI peripheral base addresses */
\r
14309 #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE, SPI9_BASE, SPI10_BASE }
\r
14310 /** Array initializer of SPI peripheral base pointers */
\r
14311 #define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8, SPI9, SPI10 }
\r
14312 /** Interrupt vectors for the SPI peripheral type */
\r
14313 #define SPI_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn, FLEXCOMM10_IRQn }
\r
14317 */ /* end of group SPI_Peripheral_Access_Layer */
\r
14320 /* ----------------------------------------------------------------------------
\r
14321 -- SPIFI Peripheral Access Layer
\r
14322 ---------------------------------------------------------------------------- */
\r
14325 * @addtogroup SPIFI_Peripheral_Access_Layer SPIFI Peripheral Access Layer
\r
14329 /** SPIFI - Register Layout Typedef */
\r
14331 __IO uint32_t CTRL; /**< SPIFI control register, offset: 0x0 */
\r
14332 __IO uint32_t CMD; /**< SPIFI command register, offset: 0x4 */
\r
14333 __IO uint32_t ADDR; /**< SPIFI address register, offset: 0x8 */
\r
14334 __IO uint32_t IDATA; /**< SPIFI intermediate data register, offset: 0xC */
\r
14335 __IO uint32_t CLIMIT; /**< SPIFI limit register, offset: 0x10 */
\r
14336 __IO uint32_t DATA; /**< SPIFI data register, offset: 0x14 */
\r
14337 __IO uint32_t MCMD; /**< SPIFI memory command register, offset: 0x18 */
\r
14338 __IO uint32_t STAT; /**< SPIFI status register, offset: 0x1C */
\r
14341 /* ----------------------------------------------------------------------------
\r
14342 -- SPIFI Register Masks
\r
14343 ---------------------------------------------------------------------------- */
\r
14346 * @addtogroup SPIFI_Register_Masks SPIFI Register Masks
\r
14350 /*! @name CTRL - SPIFI control register */
\r
14352 #define SPIFI_CTRL_TIMEOUT_MASK (0xFFFFU)
\r
14353 #define SPIFI_CTRL_TIMEOUT_SHIFT (0U)
\r
14354 /*! TIMEOUT - This field contains the number of serial clock periods without the processor reading
\r
14355 * data in memory mode, which will cause the SPIFI hardware to terminate the command by driving
\r
14356 * the CS pin high and negating the CMD bit in the Status register. (This allows the flash memory
\r
14357 * to enter a lower-power state.) If the processor reads data from the flash region after a
\r
14358 * time-out, the command in the Memory Command Register is issued again.
\r
14360 #define SPIFI_CTRL_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_TIMEOUT_SHIFT)) & SPIFI_CTRL_TIMEOUT_MASK)
\r
14361 #define SPIFI_CTRL_CSHIGH_MASK (0xF0000U)
\r
14362 #define SPIFI_CTRL_CSHIGH_SHIFT (16U)
\r
14363 /*! CSHIGH - This field controls the minimum CS high time, expressed as a number of serial clock periods minus one.
\r
14365 #define SPIFI_CTRL_CSHIGH(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_CSHIGH_SHIFT)) & SPIFI_CTRL_CSHIGH_MASK)
\r
14366 #define SPIFI_CTRL_D_PRFTCH_DIS_MASK (0x200000U)
\r
14367 #define SPIFI_CTRL_D_PRFTCH_DIS_SHIFT (21U)
\r
14368 /*! D_PRFTCH_DIS - This bit allows conditioning of memory mode prefetches based on the AHB HPROT
\r
14369 * (instruction/data) access information. A 1 in this register means that the SPIFI will not attempt
\r
14370 * a speculative prefetch when it encounters data accesses.
\r
14372 #define SPIFI_CTRL_D_PRFTCH_DIS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_D_PRFTCH_DIS_SHIFT)) & SPIFI_CTRL_D_PRFTCH_DIS_MASK)
\r
14373 #define SPIFI_CTRL_INTEN_MASK (0x400000U)
\r
14374 #define SPIFI_CTRL_INTEN_SHIFT (22U)
\r
14375 /*! INTEN - If this bit is 1 when a command ends, the SPIFI will assert its interrupt request
\r
14376 * output. See INTRQ in the status register for further details.
\r
14378 #define SPIFI_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_INTEN_SHIFT)) & SPIFI_CTRL_INTEN_MASK)
\r
14379 #define SPIFI_CTRL_MODE3_MASK (0x800000U)
\r
14380 #define SPIFI_CTRL_MODE3_SHIFT (23U)
\r
14381 /*! MODE3 - SPI Mode 3 select.
\r
14382 * 0b0..SCK LOW. The SPIFI drives SCK low after the rising edge at which the last bit of each command is
\r
14383 * captured, and keeps it low while CS is HIGH.
\r
14384 * 0b1..SCK HIGH. the SPIFI keeps SCK high after the rising edge for the last bit of each command and while CS is
\r
14385 * HIGH, and drives it low after it drives CS LOW. (Known serial flash devices can handle either mode, but
\r
14386 * some devices may require a particular mode for proper operation.) MODE3, RFCLK, and FBCLK should not all be
\r
14387 * 1, because in this case there is no final falling edge on SCK on which to sample the last data bit of the
\r
14390 #define SPIFI_CTRL_MODE3(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_MODE3_SHIFT)) & SPIFI_CTRL_MODE3_MASK)
\r
14391 #define SPIFI_CTRL_PRFTCH_DIS_MASK (0x8000000U)
\r
14392 #define SPIFI_CTRL_PRFTCH_DIS_SHIFT (27U)
\r
14393 /*! PRFTCH_DIS - Cache prefetching enable. The SPIFI includes an internal cache. A 1 in this bit disables prefetching of cache lines.
\r
14394 * 0b0..Enable. Cache prefetching enabled.
\r
14395 * 0b1..Disable. Disables prefetching of cache lines.
\r
14397 #define SPIFI_CTRL_PRFTCH_DIS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_PRFTCH_DIS_SHIFT)) & SPIFI_CTRL_PRFTCH_DIS_MASK)
\r
14398 #define SPIFI_CTRL_DUAL_MASK (0x10000000U)
\r
14399 #define SPIFI_CTRL_DUAL_SHIFT (28U)
\r
14400 /*! DUAL - Select dual protocol.
\r
14401 * 0b0..Quad protocol. This protocol uses IO3:0.
\r
14402 * 0b1..Dual protocol. This protocol uses IO1:0.
\r
14404 #define SPIFI_CTRL_DUAL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_DUAL_SHIFT)) & SPIFI_CTRL_DUAL_MASK)
\r
14405 #define SPIFI_CTRL_RFCLK_MASK (0x20000000U)
\r
14406 #define SPIFI_CTRL_RFCLK_SHIFT (29U)
\r
14407 /*! RFCLK - Select active clock edge for input data.
\r
14408 * 0b0..Rising edge. Read data is sampled on rising edges on the clock, as in classic SPI operation.
\r
14409 * 0b1..Falling edge. Read data is sampled on falling edges of the clock, allowing a full serial clock of of time
\r
14410 * in order to maximize the serial clock frequency. MODE3, RFCLK, and FBCLK should not all be 1, because in
\r
14411 * this case there is no final falling edge on SCK on which to sample the last data bit of the frame.
\r
14413 #define SPIFI_CTRL_RFCLK(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_RFCLK_SHIFT)) & SPIFI_CTRL_RFCLK_MASK)
\r
14414 #define SPIFI_CTRL_FBCLK_MASK (0x40000000U)
\r
14415 #define SPIFI_CTRL_FBCLK_SHIFT (30U)
\r
14416 /*! FBCLK - Feedback clock select.
\r
14417 * 0b0..Internal clock. The SPIFI samples read data using an internal clock.
\r
14418 * 0b1..Feedback clock. Read data is sampled using a feedback clock from the SCK pin. This allows slightly more
\r
14419 * time for each received bit. MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no
\r
14420 * final falling edge on SCK on which to sample the last data bit of the frame.
\r
14422 #define SPIFI_CTRL_FBCLK(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_FBCLK_SHIFT)) & SPIFI_CTRL_FBCLK_MASK)
\r
14423 #define SPIFI_CTRL_DMAEN_MASK (0x80000000U)
\r
14424 #define SPIFI_CTRL_DMAEN_SHIFT (31U)
\r
14425 /*! DMAEN - A 1 in this bit enables the DMA Request output from the SPIFI. Set this bit only when a
\r
14426 * DMA channel is used to transfer data in peripheral mode. Do not set this bit when a DMA
\r
14427 * channel is used for memory-to-memory transfers from the SPIFI memory area. DMAEN should only be used
\r
14428 * in Command mode.
\r
14430 #define SPIFI_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_DMAEN_SHIFT)) & SPIFI_CTRL_DMAEN_MASK)
\r
14433 /*! @name CMD - SPIFI command register */
\r
14435 #define SPIFI_CMD_DATALEN_MASK (0x3FFFU)
\r
14436 #define SPIFI_CMD_DATALEN_SHIFT (0U)
\r
14437 /*! DATALEN - Except when the POLL bit in this register is 1, this field controls how many data
\r
14438 * bytes are in the command. 0 indicates that the command does not contain a data field.
\r
14440 #define SPIFI_CMD_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_DATALEN_SHIFT)) & SPIFI_CMD_DATALEN_MASK)
\r
14441 #define SPIFI_CMD_POLL_MASK (0x4000U)
\r
14442 #define SPIFI_CMD_POLL_SHIFT (14U)
\r
14443 /*! POLL - This bit should be written as 1 only with an opcode that a) contains an input data field,
\r
14444 * and b) causes the serial flash device to return byte status repetitively (e.g., a Read Status
\r
14445 * command). When this bit is 1, the SPIFI hardware continues to read bytes until the test
\r
14446 * specified by the DATALEN field is met. The hardware tests the bit in each status byte selected by
\r
14447 * DATALEN bits 2:0, until a bit is found that is equal to DATALEN bit 3. When the test succeeds,
\r
14448 * the SPIFI captures the byte that meets this test so that it can be read from the Data
\r
14449 * Register, and terminates the command by raising CS. The end-of-command interrupt can be enabled to
\r
14450 * inform software when this occurs
\r
14452 #define SPIFI_CMD_POLL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_POLL_SHIFT)) & SPIFI_CMD_POLL_MASK)
\r
14453 #define SPIFI_CMD_DOUT_MASK (0x8000U)
\r
14454 #define SPIFI_CMD_DOUT_SHIFT (15U)
\r
14455 /*! DOUT - If the DATALEN field is not zero, this bit controls the direction of the data:
\r
14456 * 0b0..Input from serial flash.
\r
14457 * 0b1..Output to serial flash.
\r
14459 #define SPIFI_CMD_DOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_DOUT_SHIFT)) & SPIFI_CMD_DOUT_MASK)
\r
14460 #define SPIFI_CMD_INTLEN_MASK (0x70000U)
\r
14461 #define SPIFI_CMD_INTLEN_SHIFT (16U)
\r
14462 /*! INTLEN - This field controls how many intermediate bytes precede the data. (Each such byte may
\r
14463 * require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or
\r
14464 * 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control
\r
14465 * information, dummy and delay bytes. See the description of the Intermediate Data register for
\r
14466 * the contents of such bytes.
\r
14468 #define SPIFI_CMD_INTLEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_INTLEN_SHIFT)) & SPIFI_CMD_INTLEN_MASK)
\r
14469 #define SPIFI_CMD_FIELDFORM_MASK (0x180000U)
\r
14470 #define SPIFI_CMD_FIELDFORM_SHIFT (19U)
\r
14471 /*! FIELDFORM - This field controls how the fields of the command are sent.
\r
14472 * 0b00..All serial. All fields of the command are serial.
\r
14473 * 0b01..Quad/dual data. Data field is quad/dual, other fields are serial.
\r
14474 * 0b10..Serial opcode. Opcode field is serial. Other fields are quad/dual.
\r
14475 * 0b11..All quad/dual. All fields of the command are in quad/dual format.
\r
14477 #define SPIFI_CMD_FIELDFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_FIELDFORM_SHIFT)) & SPIFI_CMD_FIELDFORM_MASK)
\r
14478 #define SPIFI_CMD_FRAMEFORM_MASK (0xE00000U)
\r
14479 #define SPIFI_CMD_FRAMEFORM_SHIFT (21U)
\r
14480 /*! FRAMEFORM - This field controls the opcode and address fields.
\r
14481 * 0b000..Reserved.
\r
14482 * 0b001..Opcode. Opcode only, no address.
\r
14483 * 0b010..Opcode one byte. Opcode, least significant byte of address.
\r
14484 * 0b011..Opcode two bytes. Opcode, two least significant bytes of address.
\r
14485 * 0b100..Opcode three bytes. Opcode, three least significant bytes of address.
\r
14486 * 0b101..Opcode four bytes. Opcode, 4 bytes of address.
\r
14487 * 0b110..No opcode three bytes. No opcode, 3 least significant bytes of address.
\r
14488 * 0b111..No opcode four bytes. No opcode, 4 bytes of address.
\r
14490 #define SPIFI_CMD_FRAMEFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_FRAMEFORM_SHIFT)) & SPIFI_CMD_FRAMEFORM_MASK)
\r
14491 #define SPIFI_CMD_OPCODE_MASK (0xFF000000U)
\r
14492 #define SPIFI_CMD_OPCODE_SHIFT (24U)
\r
14493 /*! OPCODE - The opcode of the command (not used for some FRAMEFORM values).
\r
14495 #define SPIFI_CMD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_OPCODE_SHIFT)) & SPIFI_CMD_OPCODE_MASK)
\r
14498 /*! @name ADDR - SPIFI address register */
\r
14500 #define SPIFI_ADDR_ADDRESS_MASK (0xFFFFFFFFU)
\r
14501 #define SPIFI_ADDR_ADDRESS_SHIFT (0U)
\r
14502 /*! ADDRESS - Address.
\r
14504 #define SPIFI_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_ADDR_ADDRESS_SHIFT)) & SPIFI_ADDR_ADDRESS_MASK)
\r
14507 /*! @name IDATA - SPIFI intermediate data register */
\r
14509 #define SPIFI_IDATA_IDATA_MASK (0xFFFFFFFFU)
\r
14510 #define SPIFI_IDATA_IDATA_SHIFT (0U)
\r
14511 /*! IDATA - Value of intermediate bytes.
\r
14513 #define SPIFI_IDATA_IDATA(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_IDATA_IDATA_SHIFT)) & SPIFI_IDATA_IDATA_MASK)
\r
14516 /*! @name CLIMIT - SPIFI limit register */
\r
14518 #define SPIFI_CLIMIT_CLIMIT_MASK (0xFFFFFFFFU)
\r
14519 #define SPIFI_CLIMIT_CLIMIT_SHIFT (0U)
\r
14520 /*! CLIMIT - Zero-based upper limit of cacheable memory
\r
14522 #define SPIFI_CLIMIT_CLIMIT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CLIMIT_CLIMIT_SHIFT)) & SPIFI_CLIMIT_CLIMIT_MASK)
\r
14525 /*! @name DATA - SPIFI data register */
\r
14527 #define SPIFI_DATA_DATA_MASK (0xFFFFFFFFU)
\r
14528 #define SPIFI_DATA_DATA_SHIFT (0U)
\r
14529 /*! DATA - Input or output data
\r
14531 #define SPIFI_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_DATA_DATA_SHIFT)) & SPIFI_DATA_DATA_MASK)
\r
14534 /*! @name MCMD - SPIFI memory command register */
\r
14536 #define SPIFI_MCMD_POLL_MASK (0x4000U)
\r
14537 #define SPIFI_MCMD_POLL_SHIFT (14U)
\r
14538 /*! POLL - This bit should be written as 0.
\r
14540 #define SPIFI_MCMD_POLL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_POLL_SHIFT)) & SPIFI_MCMD_POLL_MASK)
\r
14541 #define SPIFI_MCMD_DOUT_MASK (0x8000U)
\r
14542 #define SPIFI_MCMD_DOUT_SHIFT (15U)
\r
14543 /*! DOUT - This bit should be written as 0.
\r
14545 #define SPIFI_MCMD_DOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_DOUT_SHIFT)) & SPIFI_MCMD_DOUT_MASK)
\r
14546 #define SPIFI_MCMD_INTLEN_MASK (0x70000U)
\r
14547 #define SPIFI_MCMD_INTLEN_SHIFT (16U)
\r
14548 /*! INTLEN - This field controls how many intermediate bytes precede the data. (Each such byte may
\r
14549 * require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or
\r
14550 * 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control
\r
14551 * information, dummy and delay bytes. See the description of the Intermediate Data register for
\r
14552 * the contents of such bytes.
\r
14554 #define SPIFI_MCMD_INTLEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_INTLEN_SHIFT)) & SPIFI_MCMD_INTLEN_MASK)
\r
14555 #define SPIFI_MCMD_FIELDFORM_MASK (0x180000U)
\r
14556 #define SPIFI_MCMD_FIELDFORM_SHIFT (19U)
\r
14557 /*! FIELDFORM - This field controls how the fields of the command are sent.
\r
14558 * 0b00..All serial. All fields of the command are serial.
\r
14559 * 0b01..Quad/dual data. Data field is quad/dual, other fields are serial.
\r
14560 * 0b10..Serial opcode. Opcode field is serial. Other fields are quad/dual.
\r
14561 * 0b11..All quad/dual. All fields of the command are in quad/dual format.
\r
14563 #define SPIFI_MCMD_FIELDFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_FIELDFORM_SHIFT)) & SPIFI_MCMD_FIELDFORM_MASK)
\r
14564 #define SPIFI_MCMD_FRAMEFORM_MASK (0xE00000U)
\r
14565 #define SPIFI_MCMD_FRAMEFORM_SHIFT (21U)
\r
14566 /*! FRAMEFORM - This field controls the opcode and address fields.
\r
14567 * 0b000..Reserved.
\r
14568 * 0b001..Opcode. Opcode only, no address.
\r
14569 * 0b010..Opcode one byte. Opcode, least-significant byte of address.
\r
14570 * 0b011..Opcode two bytes. Opcode, 2 least-significant bytes of address.
\r
14571 * 0b100..Opcode three bytes. Opcode, 3 least-significant bytes of address.
\r
14572 * 0b101..Opcode four bytes. Opcode, 4 bytes of address.
\r
14573 * 0b110..No opcode three bytes. No opcode, 3 least-significant bytes of address.
\r
14574 * 0b111..No opcode, 4 bytes of address.
\r
14576 #define SPIFI_MCMD_FRAMEFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_FRAMEFORM_SHIFT)) & SPIFI_MCMD_FRAMEFORM_MASK)
\r
14577 #define SPIFI_MCMD_OPCODE_MASK (0xFF000000U)
\r
14578 #define SPIFI_MCMD_OPCODE_SHIFT (24U)
\r
14579 /*! OPCODE - The opcode of the command (not used for some FRAMEFORM values).
\r
14581 #define SPIFI_MCMD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_OPCODE_SHIFT)) & SPIFI_MCMD_OPCODE_MASK)
\r
14584 /*! @name STAT - SPIFI status register */
\r
14586 #define SPIFI_STAT_MCINIT_MASK (0x1U)
\r
14587 #define SPIFI_STAT_MCINIT_SHIFT (0U)
\r
14588 /*! MCINIT - This bit is set when software successfully writes the Memory Command register, and is
\r
14589 * cleared by Reset or by writing a 1 to the RESET bit in this register.
\r
14591 #define SPIFI_STAT_MCINIT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_MCINIT_SHIFT)) & SPIFI_STAT_MCINIT_MASK)
\r
14592 #define SPIFI_STAT_CMD_MASK (0x2U)
\r
14593 #define SPIFI_STAT_CMD_SHIFT (1U)
\r
14594 /*! CMD - This bit is 1 when the Command register is written. It is cleared by a hardware reset, a
\r
14595 * write to the RESET bit in this register, or the deassertion of CS which indicates that the
\r
14596 * command has completed communication with the SPI Flash.
\r
14598 #define SPIFI_STAT_CMD(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_CMD_SHIFT)) & SPIFI_STAT_CMD_MASK)
\r
14599 #define SPIFI_STAT_RESET_MASK (0x10U)
\r
14600 #define SPIFI_STAT_RESET_SHIFT (4U)
\r
14601 /*! RESET - Write a 1 to this bit to abort a current command or memory mode. This bit is cleared
\r
14602 * when the hardware is ready for a new command to be written to the Command register.
\r
14604 #define SPIFI_STAT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_RESET_SHIFT)) & SPIFI_STAT_RESET_MASK)
\r
14605 #define SPIFI_STAT_INTRQ_MASK (0x20U)
\r
14606 #define SPIFI_STAT_INTRQ_SHIFT (5U)
\r
14607 /*! INTRQ - This bit reflects the SPIFI interrupt request. Write a 1 to this bit to clear it. This
\r
14608 * bit is set when a CMD was previously 1 and has been cleared due to the deassertion of CS.
\r
14610 #define SPIFI_STAT_INTRQ(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_INTRQ_SHIFT)) & SPIFI_STAT_INTRQ_MASK)
\r
14616 */ /* end of group SPIFI_Register_Masks */
\r
14619 /* SPIFI - Peripheral instance base addresses */
\r
14620 /** Peripheral SPIFI0 base address */
\r
14621 #define SPIFI0_BASE (0x40080000u)
\r
14622 /** Peripheral SPIFI0 base pointer */
\r
14623 #define SPIFI0 ((SPIFI_Type *)SPIFI0_BASE)
\r
14624 /** Array initializer of SPIFI peripheral base addresses */
\r
14625 #define SPIFI_BASE_ADDRS { SPIFI0_BASE }
\r
14626 /** Array initializer of SPIFI peripheral base pointers */
\r
14627 #define SPIFI_BASE_PTRS { SPIFI0 }
\r
14628 /** Interrupt vectors for the SPIFI peripheral type */
\r
14629 #define SPIFI_IRQS { SPIFI0_IRQn }
\r
14633 */ /* end of group SPIFI_Peripheral_Access_Layer */
\r
14636 /* ----------------------------------------------------------------------------
\r
14637 -- SYSCON Peripheral Access Layer
\r
14638 ---------------------------------------------------------------------------- */
\r
14641 * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer
\r
14645 /** SYSCON - Register Layout Typedef */
\r
14647 uint8_t RESERVED_0[16];
\r
14648 __IO uint32_t AHBMATPRIO; /**< AHB multilayer matrix priority control, offset: 0x10 */
\r
14649 uint8_t RESERVED_1[44];
\r
14650 __IO uint32_t SYSTCKCAL; /**< System tick counter calibration, offset: 0x40 */
\r
14651 uint8_t RESERVED_2[4];
\r
14652 __IO uint32_t NMISRC; /**< NMI Source Select, offset: 0x48 */
\r
14653 __IO uint32_t ASYNCAPBCTRL; /**< Asynchronous APB Control, offset: 0x4C */
\r
14654 uint8_t RESERVED_3[112];
\r
14655 __I uint32_t PIOPORCAP[2]; /**< POR captured value of port n, array offset: 0xC0, array step: 0x4 */
\r
14656 uint8_t RESERVED_4[8];
\r
14657 __I uint32_t PIORESCAP[2]; /**< Reset captured value of port n, array offset: 0xD0, array step: 0x4 */
\r
14658 uint8_t RESERVED_5[40];
\r
14659 __IO uint32_t PRESETCTRL[3]; /**< Peripheral reset control n, array offset: 0x100, array step: 0x4 */
\r
14660 uint8_t RESERVED_6[20];
\r
14661 __O uint32_t PRESETCTRLSET[3]; /**< Set bits in PRESETCTRLn, array offset: 0x120, array step: 0x4 */
\r
14662 uint8_t RESERVED_7[20];
\r
14663 __O uint32_t PRESETCTRLCLR[3]; /**< Clear bits in PRESETCTRLn, array offset: 0x140, array step: 0x4 */
\r
14664 uint8_t RESERVED_8[164];
\r
14665 __IO uint32_t SYSRSTSTAT; /**< System reset status register, offset: 0x1F0 */
\r
14666 uint8_t RESERVED_9[12];
\r
14667 __IO uint32_t AHBCLKCTRL[3]; /**< AHB Clock control n, array offset: 0x200, array step: 0x4 */
\r
14668 uint8_t RESERVED_10[20];
\r
14669 __O uint32_t AHBCLKCTRLSET[3]; /**< Set bits in AHBCLKCTRLn, array offset: 0x220, array step: 0x4 */
\r
14670 uint8_t RESERVED_11[20];
\r
14671 __O uint32_t AHBCLKCTRLCLR[3]; /**< Clear bits in AHBCLKCTRLn, array offset: 0x240, array step: 0x4 */
\r
14672 uint8_t RESERVED_12[48];
\r
14673 __IO uint32_t STICKCLKSEL; /**< Systick timer clock source selection, offset: 0x27C */
\r
14674 __IO uint32_t MAINCLKSELA; /**< Main clock source select A, offset: 0x280 */
\r
14675 __IO uint32_t MAINCLKSELB; /**< Main clock source select B, offset: 0x284 */
\r
14676 __IO uint32_t CLKOUTSELA; /**< CLKOUT clock source select A, offset: 0x288 */
\r
14677 uint8_t RESERVED_13[4];
\r
14678 __IO uint32_t SYSPLLCLKSEL; /**< PLL clock source select, offset: 0x290 */
\r
14679 uint8_t RESERVED_14[4];
\r
14680 __IO uint32_t AUDPLLCLKSEL; /**< Audio PLL clock source select, offset: 0x298 */
\r
14681 uint8_t RESERVED_15[4];
\r
14682 __IO uint32_t SPIFICLKSEL; /**< SPIFI clock source select, offset: 0x2A0 */
\r
14683 __IO uint32_t ADCCLKSEL; /**< ADC clock source select, offset: 0x2A4 */
\r
14684 __IO uint32_t USB0CLKSEL; /**< USB0 clock source select, offset: 0x2A8 */
\r
14685 __IO uint32_t USB1CLKSEL; /**< USB1 clock source select, offset: 0x2AC */
\r
14686 __IO uint32_t FCLKSEL[10]; /**< Flexcomm clock source select, array offset: 0x2B0, array step: 0x4 */
\r
14687 __IO uint32_t FCLKSEL10; /**< Flexcomm 10 clock source select, offset: 0x2D8 */
\r
14688 uint8_t RESERVED_16[4];
\r
14689 __IO uint32_t MCLKCLKSEL; /**< MCLK clock source select, offset: 0x2E0 */
\r
14690 uint8_t RESERVED_17[4];
\r
14691 __IO uint32_t FRGCLKSEL; /**< Fractional Rate Generator clock source select, offset: 0x2E8 */
\r
14692 __IO uint32_t DMICCLKSEL; /**< Digital microphone (DMIC) subsystem clock select, offset: 0x2EC */
\r
14693 __IO uint32_t SCTCLKSEL; /**< SCTimer/PWM clock source select, offset: 0x2F0 */
\r
14694 __IO uint32_t LCDCLKSEL; /**< LCD clock source select, offset: 0x2F4 */
\r
14695 __IO uint32_t SDIOCLKSEL; /**< SDIO clock source select, offset: 0x2F8 */
\r
14696 uint8_t RESERVED_18[4];
\r
14697 __IO uint32_t SYSTICKCLKDIV; /**< SYSTICK clock divider, offset: 0x300 */
\r
14698 __IO uint32_t ARMTRACECLKDIV; /**< ARM Trace clock divider, offset: 0x304 */
\r
14699 __IO uint32_t CAN0CLKDIV; /**< MCAN0 clock divider, offset: 0x308 */
\r
14700 __IO uint32_t CAN1CLKDIV; /**< MCAN1 clock divider, offset: 0x30C */
\r
14701 __IO uint32_t SC0CLKDIV; /**< Smartcard0 clock divider, offset: 0x310 */
\r
14702 __IO uint32_t SC1CLKDIV; /**< Smartcard1 clock divider, offset: 0x314 */
\r
14703 uint8_t RESERVED_19[104];
\r
14704 __IO uint32_t AHBCLKDIV; /**< AHB clock divider, offset: 0x380 */
\r
14705 __IO uint32_t CLKOUTDIV; /**< CLKOUT clock divider, offset: 0x384 */
\r
14706 __IO uint32_t FROHFDIV; /**< FROHF clock divider, offset: 0x388 */
\r
14707 uint8_t RESERVED_20[4];
\r
14708 __IO uint32_t SPIFICLKDIV; /**< SPIFI clock divider, offset: 0x390 */
\r
14709 __IO uint32_t ADCCLKDIV; /**< ADC clock divider, offset: 0x394 */
\r
14710 __IO uint32_t USB0CLKDIV; /**< USB0 clock divider, offset: 0x398 */
\r
14711 __IO uint32_t USB1CLKDIV; /**< USB1 clock divider, offset: 0x39C */
\r
14712 __IO uint32_t FRGCTRL; /**< Fractional rate divider, offset: 0x3A0 */
\r
14713 uint8_t RESERVED_21[4];
\r
14714 __IO uint32_t DMICCLKDIV; /**< DMIC clock divider, offset: 0x3A8 */
\r
14715 __IO uint32_t MCLKDIV; /**< I2S MCLK clock divider, offset: 0x3AC */
\r
14716 __IO uint32_t LCDCLKDIV; /**< LCD clock divider, offset: 0x3B0 */
\r
14717 __IO uint32_t SCTCLKDIV; /**< SCT/PWM clock divider, offset: 0x3B4 */
\r
14718 __IO uint32_t EMCCLKDIV; /**< EMC clock divider, offset: 0x3B8 */
\r
14719 __IO uint32_t SDIOCLKDIV; /**< SDIO clock divider, offset: 0x3BC */
\r
14720 uint8_t RESERVED_22[76];
\r
14721 __IO uint32_t USB0CLKCTRL; /**< USB0 clock control, offset: 0x40C */
\r
14722 __IO uint32_t USB0CLKSTAT; /**< USB0 clock status, offset: 0x410 */
\r
14723 uint8_t RESERVED_23[4];
\r
14724 __IO uint32_t FREQMECTRL; /**< Frequency measure register, offset: 0x418 */
\r
14725 uint8_t RESERVED_24[4];
\r
14726 __IO uint32_t MCLKIO; /**< MCLK input/output control, offset: 0x420 */
\r
14727 __IO uint32_t USB1CLKCTRL; /**< USB1 clock control, offset: 0x424 */
\r
14728 __IO uint32_t USB1CLKSTAT; /**< USB1 clock status, offset: 0x428 */
\r
14729 uint8_t RESERVED_25[24];
\r
14730 __IO uint32_t EMCSYSCTRL; /**< EMC system control, offset: 0x444 */
\r
14731 __IO uint32_t EMCDYCTRL; /**< EMC clock delay control, offset: 0x448 */
\r
14732 __IO uint32_t EMCCAL; /**< EMC delay chain calibration control, offset: 0x44C */
\r
14733 __IO uint32_t ETHPHYSEL; /**< Ethernet PHY Selection, offset: 0x450 */
\r
14734 __IO uint32_t ETHSBDCTRL; /**< Ethernet SBD flow control, offset: 0x454 */
\r
14735 uint8_t RESERVED_26[8];
\r
14736 __IO uint32_t SDIOCLKCTRL; /**< SDIO CCLKIN phase and delay control, offset: 0x460 */
\r
14737 uint8_t RESERVED_27[12];
\r
14738 __IO uint32_t KEYMUXSEL; /**< AES key source selection, offset: 0x470 */
\r
14739 uint8_t RESERVED_28[140];
\r
14740 __IO uint32_t FROCTRL; /**< FRO oscillator control, offset: 0x500 */
\r
14741 __IO uint32_t SYSOSCCTRL; /**< System oscillator control, offset: 0x504 */
\r
14742 __IO uint32_t WDTOSCCTRL; /**< Watchdog oscillator control, offset: 0x508 */
\r
14743 __IO uint32_t RTCOSCCTRL; /**< RTC oscillator 32 kHz output control, offset: 0x50C */
\r
14744 uint8_t RESERVED_29[12];
\r
14745 __IO uint32_t USBPLLCTRL; /**< USB PLL control, offset: 0x51C */
\r
14746 __IO uint32_t USBPLLSTAT; /**< USB PLL status, offset: 0x520 */
\r
14747 uint8_t RESERVED_30[92];
\r
14748 __IO uint32_t SYSPLLCTRL; /**< System PLL control, offset: 0x580 */
\r
14749 __IO uint32_t SYSPLLSTAT; /**< PLL status, offset: 0x584 */
\r
14750 __IO uint32_t SYSPLLNDEC; /**< PLL N divider, offset: 0x588 */
\r
14751 __IO uint32_t SYSPLLPDEC; /**< PLL P divider, offset: 0x58C */
\r
14752 __IO uint32_t SYSPLLMDEC; /**< System PLL M divider, offset: 0x590 */
\r
14753 uint8_t RESERVED_31[12];
\r
14754 __IO uint32_t AUDPLLCTRL; /**< Audio PLL control, offset: 0x5A0 */
\r
14755 __IO uint32_t AUDPLLSTAT; /**< Audio PLL status, offset: 0x5A4 */
\r
14756 __IO uint32_t AUDPLLNDEC; /**< Audio PLL N divider, offset: 0x5A8 */
\r
14757 __IO uint32_t AUDPLLPDEC; /**< Audio PLL P divider, offset: 0x5AC */
\r
14758 __IO uint32_t AUDPLLMDEC; /**< Audio PLL M divider, offset: 0x5B0 */
\r
14759 __IO uint32_t AUDPLLFRAC; /**< Audio PLL fractional divider control, offset: 0x5B4 */
\r
14760 uint8_t RESERVED_32[72];
\r
14761 __IO uint32_t PDSLEEPCFG[2]; /**< Sleep configuration register, array offset: 0x600, array step: 0x4 */
\r
14762 uint8_t RESERVED_33[8];
\r
14763 __IO uint32_t PDRUNCFG[2]; /**< Power configuration register, array offset: 0x610, array step: 0x4 */
\r
14764 uint8_t RESERVED_34[8];
\r
14765 __IO uint32_t PDRUNCFGSET[2]; /**< Power configuration set register, array offset: 0x620, array step: 0x4 */
\r
14766 uint8_t RESERVED_35[8];
\r
14767 __IO uint32_t PDRUNCFGCLR[2]; /**< Power configuration clear register, array offset: 0x630, array step: 0x4 */
\r
14768 uint8_t RESERVED_36[72];
\r
14769 __IO uint32_t STARTER[2]; /**< Start logic 0 wake-up enable register, array offset: 0x680, array step: 0x4 */
\r
14770 uint8_t RESERVED_37[24];
\r
14771 __O uint32_t STARTERSET[2]; /**< Set bits in STARTER, array offset: 0x6A0, array step: 0x4 */
\r
14772 uint8_t RESERVED_38[24];
\r
14773 __O uint32_t STARTERCLR[2]; /**< Clear bits in STARTER0, array offset: 0x6C0, array step: 0x4 */
\r
14774 uint8_t RESERVED_39[184];
\r
14775 __IO uint32_t HWWAKE; /**< Configures special cases of hardware wake-up, offset: 0x780 */
\r
14776 uint8_t RESERVED_40[1664];
\r
14777 __IO uint32_t AUTOCGOR; /**< Auto Clock-Gate Override Register, offset: 0xE04 */
\r
14778 uint8_t RESERVED_41[492];
\r
14779 __I uint32_t JTAGIDCODE; /**< JTAG ID code register, offset: 0xFF4 */
\r
14780 __I uint32_t DEVICE_ID0; /**< Part ID register, offset: 0xFF8 */
\r
14781 __I uint32_t DEVICE_ID1; /**< Boot ROM and die revision register, offset: 0xFFC */
\r
14782 uint8_t RESERVED_42[127044];
\r
14783 __IO uint32_t BODCTRL; /**< Brown-Out Detect control, offset: 0x20044 */
\r
14786 /* ----------------------------------------------------------------------------
\r
14787 -- SYSCON Register Masks
\r
14788 ---------------------------------------------------------------------------- */
\r
14791 * @addtogroup SYSCON_Register_Masks SYSCON Register Masks
\r
14795 /*! @name AHBMATPRIO - AHB multilayer matrix priority control */
\r
14797 #define SYSCON_AHBMATPRIO_PRI_ICODE_MASK (0x3U)
\r
14798 #define SYSCON_AHBMATPRIO_PRI_ICODE_SHIFT (0U)
\r
14799 /*! PRI_ICODE - I-Code bus priority.
\r
14801 #define SYSCON_AHBMATPRIO_PRI_ICODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_ICODE_SHIFT)) & SYSCON_AHBMATPRIO_PRI_ICODE_MASK)
\r
14802 #define SYSCON_AHBMATPRIO_PRI_DCODE_MASK (0xCU)
\r
14803 #define SYSCON_AHBMATPRIO_PRI_DCODE_SHIFT (2U)
\r
14804 /*! PRI_DCODE - D-Code bus priority.
\r
14806 #define SYSCON_AHBMATPRIO_PRI_DCODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_DCODE_SHIFT)) & SYSCON_AHBMATPRIO_PRI_DCODE_MASK)
\r
14807 #define SYSCON_AHBMATPRIO_PRI_SYS_MASK (0x30U)
\r
14808 #define SYSCON_AHBMATPRIO_PRI_SYS_SHIFT (4U)
\r
14809 /*! PRI_SYS - System bus priority.
\r
14811 #define SYSCON_AHBMATPRIO_PRI_SYS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SYS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SYS_MASK)
\r
14812 #define SYSCON_AHBMATPRIO_PRI_DMA_MASK (0xC0U)
\r
14813 #define SYSCON_AHBMATPRIO_PRI_DMA_SHIFT (6U)
\r
14814 /*! PRI_DMA - DMA controller priority.
\r
14816 #define SYSCON_AHBMATPRIO_PRI_DMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_DMA_SHIFT)) & SYSCON_AHBMATPRIO_PRI_DMA_MASK)
\r
14817 #define SYSCON_AHBMATPRIO_PRI_ETH_MASK (0x300U)
\r
14818 #define SYSCON_AHBMATPRIO_PRI_ETH_SHIFT (8U)
\r
14819 /*! PRI_ETH - Ethernet DMA priority.
\r
14821 #define SYSCON_AHBMATPRIO_PRI_ETH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_ETH_SHIFT)) & SYSCON_AHBMATPRIO_PRI_ETH_MASK)
\r
14822 #define SYSCON_AHBMATPRIO_PRI_LCD_MASK (0xC00U)
\r
14823 #define SYSCON_AHBMATPRIO_PRI_LCD_SHIFT (10U)
\r
14824 /*! PRI_LCD - LCD DMA priority.
\r
14826 #define SYSCON_AHBMATPRIO_PRI_LCD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_LCD_SHIFT)) & SYSCON_AHBMATPRIO_PRI_LCD_MASK)
\r
14827 #define SYSCON_AHBMATPRIO_PRI_USB0_MASK (0x3000U)
\r
14828 #define SYSCON_AHBMATPRIO_PRI_USB0_SHIFT (12U)
\r
14829 /*! PRI_USB0 - USB0 DMA priority.
\r
14831 #define SYSCON_AHBMATPRIO_PRI_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB0_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB0_MASK)
\r
14832 #define SYSCON_AHBMATPRIO_PRI_USB1_MASK (0xC000U)
\r
14833 #define SYSCON_AHBMATPRIO_PRI_USB1_SHIFT (14U)
\r
14834 /*! PRI_USB1 - USB1 DMA priority.
\r
14836 #define SYSCON_AHBMATPRIO_PRI_USB1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB1_MASK)
\r
14837 #define SYSCON_AHBMATPRIO_PRI_SDIO_MASK (0x30000U)
\r
14838 #define SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT (16U)
\r
14839 /*! PRI_SDIO - SDIO priority.
\r
14841 #define SYSCON_AHBMATPRIO_PRI_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDIO_MASK)
\r
14842 #define SYSCON_AHBMATPRIO_PRI_MCAN1_MASK (0xC0000U)
\r
14843 #define SYSCON_AHBMATPRIO_PRI_MCAN1_SHIFT (18U)
\r
14844 /*! PRI_MCAN1 - MCAN1 priority.
\r
14846 #define SYSCON_AHBMATPRIO_PRI_MCAN1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_MCAN1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_MCAN1_MASK)
\r
14847 #define SYSCON_AHBMATPRIO_PRI_MCAN2_MASK (0x300000U)
\r
14848 #define SYSCON_AHBMATPRIO_PRI_MCAN2_SHIFT (20U)
\r
14849 /*! PRI_MCAN2 - MCAN2 priority.
\r
14851 #define SYSCON_AHBMATPRIO_PRI_MCAN2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_MCAN2_SHIFT)) & SYSCON_AHBMATPRIO_PRI_MCAN2_MASK)
\r
14854 /*! @name SYSTCKCAL - System tick counter calibration */
\r
14856 #define SYSCON_SYSTCKCAL_CAL_MASK (0xFFFFFFU)
\r
14857 #define SYSCON_SYSTCKCAL_CAL_SHIFT (0U)
\r
14858 /*! CAL - System tick timer calibration value.
\r
14860 #define SYSCON_SYSTCKCAL_CAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_CAL_SHIFT)) & SYSCON_SYSTCKCAL_CAL_MASK)
\r
14861 #define SYSCON_SYSTCKCAL_SKEW_MASK (0x1000000U)
\r
14862 #define SYSCON_SYSTCKCAL_SKEW_SHIFT (24U)
\r
14863 /*! SKEW - Initial value for the Systick timer.
\r
14865 #define SYSCON_SYSTCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_SKEW_SHIFT)) & SYSCON_SYSTCKCAL_SKEW_MASK)
\r
14866 #define SYSCON_SYSTCKCAL_NOREF_MASK (0x2000000U)
\r
14867 #define SYSCON_SYSTCKCAL_NOREF_SHIFT (25U)
\r
14868 /*! NOREF - Initial value for the Systick timer.
\r
14870 #define SYSCON_SYSTCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_NOREF_SHIFT)) & SYSCON_SYSTCKCAL_NOREF_MASK)
\r
14873 /*! @name NMISRC - NMI Source Select */
\r
14875 #define SYSCON_NMISRC_IRQM4_MASK (0x3FU)
\r
14876 #define SYSCON_NMISRC_IRQM4_SHIFT (0U)
\r
14877 /*! IRQM4 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the Cortex-M4, if enabled by NMIENM4.
\r
14879 #define SYSCON_NMISRC_IRQM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQM4_SHIFT)) & SYSCON_NMISRC_IRQM4_MASK)
\r
14880 #define SYSCON_NMISRC_NMIENM4_MASK (0x80000000U)
\r
14881 #define SYSCON_NMISRC_NMIENM4_SHIFT (31U)
\r
14882 /*! NMIENM4 - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQM4.
\r
14884 #define SYSCON_NMISRC_NMIENM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENM4_SHIFT)) & SYSCON_NMISRC_NMIENM4_MASK)
\r
14887 /*! @name ASYNCAPBCTRL - Asynchronous APB Control */
\r
14889 #define SYSCON_ASYNCAPBCTRL_ENABLE_MASK (0x1U)
\r
14890 #define SYSCON_ASYNCAPBCTRL_ENABLE_SHIFT (0U)
\r
14891 /*! ENABLE - Enables the asynchronous APB bridge and subsystem.
\r
14892 * 0b0..Disabled. Asynchronous APB bridge is disabled.
\r
14893 * 0b1..Enabled. Asynchronous APB bridge is enabled.
\r
14895 #define SYSCON_ASYNCAPBCTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ASYNCAPBCTRL_ENABLE_SHIFT)) & SYSCON_ASYNCAPBCTRL_ENABLE_MASK)
\r
14898 /*! @name PIOPORCAP - POR captured value of port n */
\r
14900 #define SYSCON_PIOPORCAP_PIOPORCAP_MASK (0xFFFFFFFFU)
\r
14901 #define SYSCON_PIOPORCAP_PIOPORCAP_SHIFT (0U)
\r
14902 /*! PIOPORCAP - State of PIOn_31 through PIOn_0 at power-on reset
\r
14904 #define SYSCON_PIOPORCAP_PIOPORCAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PIOPORCAP_PIOPORCAP_SHIFT)) & SYSCON_PIOPORCAP_PIOPORCAP_MASK)
\r
14907 /* The count of SYSCON_PIOPORCAP */
\r
14908 #define SYSCON_PIOPORCAP_COUNT (2U)
\r
14910 /*! @name PIORESCAP - Reset captured value of port n */
\r
14912 #define SYSCON_PIORESCAP_PIORESCAP_MASK (0xFFFFFFFFU)
\r
14913 #define SYSCON_PIORESCAP_PIORESCAP_SHIFT (0U)
\r
14914 /*! PIORESCAP - State of PIOn_31 through PIOn_0 for resets other than POR.
\r
14916 #define SYSCON_PIORESCAP_PIORESCAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PIORESCAP_PIORESCAP_SHIFT)) & SYSCON_PIORESCAP_PIORESCAP_MASK)
\r
14919 /* The count of SYSCON_PIORESCAP */
\r
14920 #define SYSCON_PIORESCAP_COUNT (2U)
\r
14922 /*! @name PRESETCTRL - Peripheral reset control n */
\r
14924 #define SYSCON_PRESETCTRL_MRT_RST_MASK (0x1U)
\r
14925 #define SYSCON_PRESETCTRL_MRT_RST_SHIFT (0U)
\r
14926 /*! MRT_RST - Multi-rate timer (MRT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
\r
14928 #define SYSCON_PRESETCTRL_MRT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MRT_RST_SHIFT)) & SYSCON_PRESETCTRL_MRT_RST_MASK)
\r
14929 #define SYSCON_PRESETCTRL_LCD_RST_MASK (0x4U)
\r
14930 #define SYSCON_PRESETCTRL_LCD_RST_SHIFT (2U)
\r
14931 /*! LCD_RST - LCD reset control.
\r
14933 #define SYSCON_PRESETCTRL_LCD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_LCD_RST_SHIFT)) & SYSCON_PRESETCTRL_LCD_RST_MASK)
\r
14934 #define SYSCON_PRESETCTRL_SCT0_RST_MASK (0x4U)
\r
14935 #define SYSCON_PRESETCTRL_SCT0_RST_SHIFT (2U)
\r
14936 /*! SCT0_RST - State configurable timer 0 (SCT0) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
\r
14938 #define SYSCON_PRESETCTRL_SCT0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SCT0_RST_SHIFT)) & SYSCON_PRESETCTRL_SCT0_RST_MASK)
\r
14939 #define SYSCON_PRESETCTRL_SDIO_RST_MASK (0x8U)
\r
14940 #define SYSCON_PRESETCTRL_SDIO_RST_SHIFT (3U)
\r
14941 /*! SDIO_RST - SDIO reset control.
\r
14943 #define SYSCON_PRESETCTRL_SDIO_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SDIO_RST_SHIFT)) & SYSCON_PRESETCTRL_SDIO_RST_MASK)
\r
14944 #define SYSCON_PRESETCTRL_USB1H_RST_MASK (0x10U)
\r
14945 #define SYSCON_PRESETCTRL_USB1H_RST_SHIFT (4U)
\r
14946 /*! USB1H_RST - USB1 Host reset control.
\r
14948 #define SYSCON_PRESETCTRL_USB1H_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB1H_RST_SHIFT)) & SYSCON_PRESETCTRL_USB1H_RST_MASK)
\r
14949 #define SYSCON_PRESETCTRL_USB1D_RST_MASK (0x20U)
\r
14950 #define SYSCON_PRESETCTRL_USB1D_RST_SHIFT (5U)
\r
14951 /*! USB1D_RST - USB1 Device reset control.
\r
14953 #define SYSCON_PRESETCTRL_USB1D_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB1D_RST_SHIFT)) & SYSCON_PRESETCTRL_USB1D_RST_MASK)
\r
14954 #define SYSCON_PRESETCTRL_USB1RAM_RST_MASK (0x40U)
\r
14955 #define SYSCON_PRESETCTRL_USB1RAM_RST_SHIFT (6U)
\r
14956 /*! USB1RAM_RST - USB1 RAM reset control.
\r
14958 #define SYSCON_PRESETCTRL_USB1RAM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB1RAM_RST_SHIFT)) & SYSCON_PRESETCTRL_USB1RAM_RST_MASK)
\r
14959 #define SYSCON_PRESETCTRL_EMC_RESET_MASK (0x80U)
\r
14960 #define SYSCON_PRESETCTRL_EMC_RESET_SHIFT (7U)
\r
14961 /*! EMC_RESET - EMC reset control.
\r
14963 #define SYSCON_PRESETCTRL_EMC_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_EMC_RESET_SHIFT)) & SYSCON_PRESETCTRL_EMC_RESET_MASK)
\r
14964 #define SYSCON_PRESETCTRL_MCAN0_RST_MASK (0x80U)
\r
14965 #define SYSCON_PRESETCTRL_MCAN0_RST_SHIFT (7U)
\r
14966 /*! MCAN0_RST - 0 = Clear reset to this function.
\r
14968 #define SYSCON_PRESETCTRL_MCAN0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MCAN0_RST_SHIFT)) & SYSCON_PRESETCTRL_MCAN0_RST_MASK)
\r
14969 #define SYSCON_PRESETCTRL_ETH_RST_MASK (0x100U)
\r
14970 #define SYSCON_PRESETCTRL_ETH_RST_SHIFT (8U)
\r
14971 /*! ETH_RST - Ethernet reset control.
\r
14973 #define SYSCON_PRESETCTRL_ETH_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_ETH_RST_SHIFT)) & SYSCON_PRESETCTRL_ETH_RST_MASK)
\r
14974 #define SYSCON_PRESETCTRL_MCAN1_RST_MASK (0x100U)
\r
14975 #define SYSCON_PRESETCTRL_MCAN1_RST_SHIFT (8U)
\r
14976 /*! MCAN1_RST - 0 = Clear reset to this function.
\r
14978 #define SYSCON_PRESETCTRL_MCAN1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MCAN1_RST_SHIFT)) & SYSCON_PRESETCTRL_MCAN1_RST_MASK)
\r
14979 #define SYSCON_PRESETCTRL_GPIO4_RST_MASK (0x200U)
\r
14980 #define SYSCON_PRESETCTRL_GPIO4_RST_SHIFT (9U)
\r
14981 /*! GPIO4_RST - GPIO4 reset control.
\r
14983 #define SYSCON_PRESETCTRL_GPIO4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO4_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO4_RST_MASK)
\r
14984 #define SYSCON_PRESETCTRL_GPIO5_RST_MASK (0x400U)
\r
14985 #define SYSCON_PRESETCTRL_GPIO5_RST_SHIFT (10U)
\r
14986 /*! GPIO5_RST - GPIO5 reset control.
\r
14988 #define SYSCON_PRESETCTRL_GPIO5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO5_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO5_RST_MASK)
\r
14989 #define SYSCON_PRESETCTRL_SPIFI_RST_MASK (0x400U)
\r
14990 #define SYSCON_PRESETCTRL_SPIFI_RST_SHIFT (10U)
\r
14991 /*! SPIFI_RST - SPIFI reset control.
\r
14993 #define SYSCON_PRESETCTRL_SPIFI_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SPIFI_RST_SHIFT)) & SYSCON_PRESETCTRL_SPIFI_RST_MASK)
\r
14994 #define SYSCON_PRESETCTRL_UTICK_RST_MASK (0x400U)
\r
14995 #define SYSCON_PRESETCTRL_UTICK_RST_SHIFT (10U)
\r
14996 /*! UTICK_RST - Micro-tick Timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
\r
14998 #define SYSCON_PRESETCTRL_UTICK_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_UTICK_RST_SHIFT)) & SYSCON_PRESETCTRL_UTICK_RST_MASK)
\r
14999 #define SYSCON_PRESETCTRL_FC0_RST_MASK (0x800U)
\r
15000 #define SYSCON_PRESETCTRL_FC0_RST_SHIFT (11U)
\r
15001 /*! FC0_RST - Flexcomm 0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
\r
15003 #define SYSCON_PRESETCTRL_FC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL_FC0_RST_MASK)
\r
15004 #define SYSCON_PRESETCTRL_MUX_RST_MASK (0x800U)
\r
15005 #define SYSCON_PRESETCTRL_MUX_RST_SHIFT (11U)
\r
15006 /*! MUX_RST - Input mux reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
\r
15008 #define SYSCON_PRESETCTRL_MUX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MUX_RST_SHIFT)) & SYSCON_PRESETCTRL_MUX_RST_MASK)
\r
15009 #define SYSCON_PRESETCTRL_FC1_RST_MASK (0x1000U)
\r
15010 #define SYSCON_PRESETCTRL_FC1_RST_SHIFT (12U)
\r
15011 /*! FC1_RST - Flexcomm 1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
\r
15013 #define SYSCON_PRESETCTRL_FC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL_FC1_RST_MASK)
\r
15014 #define SYSCON_PRESETCTRL_OTP_RST_MASK (0x1000U)
\r
15015 #define SYSCON_PRESETCTRL_OTP_RST_SHIFT (12U)
\r
15016 /*! OTP_RST - OTP reset control.
\r
15018 #define SYSCON_PRESETCTRL_OTP_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_OTP_RST_SHIFT)) & SYSCON_PRESETCTRL_OTP_RST_MASK)
\r
15019 #define SYSCON_PRESETCTRL_FC2_RST_MASK (0x2000U)
\r
15020 #define SYSCON_PRESETCTRL_FC2_RST_SHIFT (13U)
\r
15021 /*! FC2_RST - Flexcomm 2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
\r
15023 #define SYSCON_PRESETCTRL_FC2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL_FC2_RST_MASK)
\r
15024 #define SYSCON_PRESETCTRL_IOCON_RST_MASK (0x2000U)
\r
15025 #define SYSCON_PRESETCTRL_IOCON_RST_SHIFT (13U)
\r
15026 /*! IOCON_RST - IOCON reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
\r
15028 #define SYSCON_PRESETCTRL_IOCON_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_IOCON_RST_SHIFT)) & SYSCON_PRESETCTRL_IOCON_RST_MASK)
\r
15029 #define SYSCON_PRESETCTRL_RNG_RST_MASK (0x2000U)
\r
15030 #define SYSCON_PRESETCTRL_RNG_RST_SHIFT (13U)
\r
15031 /*! RNG_RST - RNG reset control.
\r
15033 #define SYSCON_PRESETCTRL_RNG_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_RNG_RST_SHIFT)) & SYSCON_PRESETCTRL_RNG_RST_MASK)
\r
15034 #define SYSCON_PRESETCTRL_FC3_RST_MASK (0x4000U)
\r
15035 #define SYSCON_PRESETCTRL_FC3_RST_SHIFT (14U)
\r
15036 /*! FC3_RST - Flexcomm 3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
\r
15038 #define SYSCON_PRESETCTRL_FC3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL_FC3_RST_MASK)
\r
15039 #define SYSCON_PRESETCTRL_FC8_RST_MASK (0x4000U)
\r
15040 #define SYSCON_PRESETCTRL_FC8_RST_SHIFT (14U)
\r
15041 /*! FC8_RST - Flexcomm 8 reset control.
\r
15043 #define SYSCON_PRESETCTRL_FC8_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC8_RST_SHIFT)) & SYSCON_PRESETCTRL_FC8_RST_MASK)
\r
15044 #define SYSCON_PRESETCTRL_GPIO0_RST_MASK (0x4000U)
\r
15045 #define SYSCON_PRESETCTRL_GPIO0_RST_SHIFT (14U)
\r
15046 /*! GPIO0_RST - GPIO0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
\r
15048 #define SYSCON_PRESETCTRL_GPIO0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO0_RST_MASK)
\r
15049 #define SYSCON_PRESETCTRL_FC4_RST_MASK (0x8000U)
\r
15050 #define SYSCON_PRESETCTRL_FC4_RST_SHIFT (15U)
\r
15051 /*! FC4_RST - Flexcomm 4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
\r
15053 #define SYSCON_PRESETCTRL_FC4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL_FC4_RST_MASK)
\r
15054 #define SYSCON_PRESETCTRL_FC9_RST_MASK (0x8000U)
\r
15055 #define SYSCON_PRESETCTRL_FC9_RST_SHIFT (15U)
\r
15056 /*! FC9_RST - Flexcomm 9 reset control.
\r
15058 #define SYSCON_PRESETCTRL_FC9_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC9_RST_SHIFT)) & SYSCON_PRESETCTRL_FC9_RST_MASK)
\r
15059 #define SYSCON_PRESETCTRL_GPIO1_RST_MASK (0x8000U)
\r
15060 #define SYSCON_PRESETCTRL_GPIO1_RST_SHIFT (15U)
\r
15061 /*! GPIO1_RST - GPIO1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
\r
15063 #define SYSCON_PRESETCTRL_GPIO1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO1_RST_MASK)
\r
15064 #define SYSCON_PRESETCTRL_FC5_RST_MASK (0x10000U)
\r
15065 #define SYSCON_PRESETCTRL_FC5_RST_SHIFT (16U)
\r
15066 /*! FC5_RST - Flexcomm 5 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
\r
15068 #define SYSCON_PRESETCTRL_FC5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL_FC5_RST_MASK)
\r
15069 #define SYSCON_PRESETCTRL_GPIO2_RST_MASK (0x10000U)
\r
15070 #define SYSCON_PRESETCTRL_GPIO2_RST_SHIFT (16U)
\r
15071 /*! GPIO2_RST - GPIO2 reset control.
\r
15073 #define SYSCON_PRESETCTRL_GPIO2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO2_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO2_RST_MASK)
\r
15074 #define SYSCON_PRESETCTRL_USB0HMR_RST_MASK (0x10000U)
\r
15075 #define SYSCON_PRESETCTRL_USB0HMR_RST_SHIFT (16U)
\r
15076 /*! USB0HMR_RST - USB0 HOST master reset control.
\r
15078 #define SYSCON_PRESETCTRL_USB0HMR_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB0HMR_RST_SHIFT)) & SYSCON_PRESETCTRL_USB0HMR_RST_MASK)
\r
15079 #define SYSCON_PRESETCTRL_FC6_RST_MASK (0x20000U)
\r
15080 #define SYSCON_PRESETCTRL_FC6_RST_SHIFT (17U)
\r
15081 /*! FC6_RST - Flexcomm 6 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
\r
15083 #define SYSCON_PRESETCTRL_FC6_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL_FC6_RST_MASK)
\r
15084 #define SYSCON_PRESETCTRL_GPIO3_RST_MASK (0x20000U)
\r
15085 #define SYSCON_PRESETCTRL_GPIO3_RST_SHIFT (17U)
\r
15086 /*! GPIO3_RST - GPIO3 reset control.
\r
15088 #define SYSCON_PRESETCTRL_GPIO3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO3_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO3_RST_MASK)
\r
15089 #define SYSCON_PRESETCTRL_USB0HSL_RST_MASK (0x20000U)
\r
15090 #define SYSCON_PRESETCTRL_USB0HSL_RST_SHIFT (17U)
\r
15091 /*! USB0HSL_RST - USB0 HOST slave reset control.
\r
15093 #define SYSCON_PRESETCTRL_USB0HSL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB0HSL_RST_SHIFT)) & SYSCON_PRESETCTRL_USB0HSL_RST_MASK)
\r
15094 #define SYSCON_PRESETCTRL_FC7_RST_MASK (0x40000U)
\r
15095 #define SYSCON_PRESETCTRL_FC7_RST_SHIFT (18U)
\r
15096 /*! FC7_RST - Flexcomm 7 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
\r
15098 #define SYSCON_PRESETCTRL_FC7_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL_FC7_RST_MASK)
\r
15099 #define SYSCON_PRESETCTRL_PINT_RST_MASK (0x40000U)
\r
15100 #define SYSCON_PRESETCTRL_PINT_RST_SHIFT (18U)
\r
15101 /*! PINT_RST - Pin interrupt (PINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
\r
15103 #define SYSCON_PRESETCTRL_PINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL_PINT_RST_MASK)
\r
15104 #define SYSCON_PRESETCTRL_SHA_RST_MASK (0x40000U)
\r
15105 #define SYSCON_PRESETCTRL_SHA_RST_SHIFT (18U)
\r
15106 /*! SHA_RST - SHA reset control.
\r
15108 #define SYSCON_PRESETCTRL_SHA_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SHA_RST_SHIFT)) & SYSCON_PRESETCTRL_SHA_RST_MASK)
\r
15109 #define SYSCON_PRESETCTRL_DMIC_RST_MASK (0x80000U)
\r
15110 #define SYSCON_PRESETCTRL_DMIC_RST_SHIFT (19U)
\r
15111 /*! DMIC_RST - Digital microphone interface reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
\r
15113 #define SYSCON_PRESETCTRL_DMIC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_DMIC_RST_SHIFT)) & SYSCON_PRESETCTRL_DMIC_RST_MASK)
\r
15114 #define SYSCON_PRESETCTRL_GINT_RST_MASK (0x80000U)
\r
15115 #define SYSCON_PRESETCTRL_GINT_RST_SHIFT (19U)
\r
15116 /*! GINT_RST - Grouped interrupt (GINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
\r
15118 #define SYSCON_PRESETCTRL_GINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL_GINT_RST_MASK)
\r
15119 #define SYSCON_PRESETCTRL_SC0_RST_MASK (0x80000U)
\r
15120 #define SYSCON_PRESETCTRL_SC0_RST_SHIFT (19U)
\r
15121 /*! SC0_RST - Smart card 0 reset control.
\r
15123 #define SYSCON_PRESETCTRL_SC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SC0_RST_SHIFT)) & SYSCON_PRESETCTRL_SC0_RST_MASK)
\r
15124 #define SYSCON_PRESETCTRL_DMA_RST_MASK (0x100000U)
\r
15125 #define SYSCON_PRESETCTRL_DMA_RST_SHIFT (20U)
\r
15126 /*! DMA_RST - DMA reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
\r
15128 #define SYSCON_PRESETCTRL_DMA_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_DMA_RST_SHIFT)) & SYSCON_PRESETCTRL_DMA_RST_MASK)
\r
15129 #define SYSCON_PRESETCTRL_SC1_RST_MASK (0x100000U)
\r
15130 #define SYSCON_PRESETCTRL_SC1_RST_SHIFT (20U)
\r
15131 /*! SC1_RST - Smart card 1 reset control.
\r
15133 #define SYSCON_PRESETCTRL_SC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SC1_RST_SHIFT)) & SYSCON_PRESETCTRL_SC1_RST_MASK)
\r
15134 #define SYSCON_PRESETCTRL_CRC_RST_MASK (0x200000U)
\r
15135 #define SYSCON_PRESETCTRL_CRC_RST_SHIFT (21U)
\r
15136 /*! CRC_RST - CRC generator reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
\r
15138 #define SYSCON_PRESETCTRL_CRC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CRC_RST_SHIFT)) & SYSCON_PRESETCTRL_CRC_RST_MASK)
\r
15139 #define SYSCON_PRESETCTRL_FC10_RST_MASK (0x200000U)
\r
15140 #define SYSCON_PRESETCTRL_FC10_RST_SHIFT (21U)
\r
15141 /*! FC10_RST - Flexcomm 10 reset control.
\r
15143 #define SYSCON_PRESETCTRL_FC10_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC10_RST_SHIFT)) & SYSCON_PRESETCTRL_FC10_RST_MASK)
\r
15144 #define SYSCON_PRESETCTRL_CTIMER2_RST_MASK (0x400000U)
\r
15145 #define SYSCON_PRESETCTRL_CTIMER2_RST_SHIFT (22U)
\r
15146 /*! CTIMER2_RST - CTIMER2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function
\r
15148 #define SYSCON_PRESETCTRL_CTIMER2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER2_RST_MASK)
\r
15149 #define SYSCON_PRESETCTRL_WWDT_RST_MASK (0x400000U)
\r
15150 #define SYSCON_PRESETCTRL_WWDT_RST_SHIFT (22U)
\r
15151 /*! WWDT_RST - Watchdog timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
\r
15153 #define SYSCON_PRESETCTRL_WWDT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_WWDT_RST_SHIFT)) & SYSCON_PRESETCTRL_WWDT_RST_MASK)
\r
15154 #define SYSCON_PRESETCTRL_USB0D_RST_MASK (0x2000000U)
\r
15155 #define SYSCON_PRESETCTRL_USB0D_RST_SHIFT (25U)
\r
15156 /*! USB0D_RST - USB0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
\r
15158 #define SYSCON_PRESETCTRL_USB0D_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB0D_RST_SHIFT)) & SYSCON_PRESETCTRL_USB0D_RST_MASK)
\r
15159 #define SYSCON_PRESETCTRL_CTIMER0_RST_MASK (0x4000000U)
\r
15160 #define SYSCON_PRESETCTRL_CTIMER0_RST_SHIFT (26U)
\r
15161 /*! CTIMER0_RST - CTIMER0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
\r
15163 #define SYSCON_PRESETCTRL_CTIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER0_RST_MASK)
\r
15164 #define SYSCON_PRESETCTRL_ADC0_RST_MASK (0x8000000U)
\r
15165 #define SYSCON_PRESETCTRL_ADC0_RST_SHIFT (27U)
\r
15166 /*! ADC0_RST - ADC0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
\r
15168 #define SYSCON_PRESETCTRL_ADC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_ADC0_RST_SHIFT)) & SYSCON_PRESETCTRL_ADC0_RST_MASK)
\r
15169 #define SYSCON_PRESETCTRL_CTIMER1_RST_MASK (0x8000000U)
\r
15170 #define SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT (27U)
\r
15171 /*! CTIMER1_RST - CTIMER1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
\r
15173 #define SYSCON_PRESETCTRL_CTIMER1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER1_RST_MASK)
\r
15176 /* The count of SYSCON_PRESETCTRL */
\r
15177 #define SYSCON_PRESETCTRL_COUNT (3U)
\r
15179 /*! @name PRESETCTRLSET - Set bits in PRESETCTRLn */
\r
15181 #define SYSCON_PRESETCTRLSET_RST_SET_MASK (0xFFFFFFFFU)
\r
15182 #define SYSCON_PRESETCTRLSET_RST_SET_SHIFT (0U)
\r
15183 /*! RST_SET - Writing ones to this register sets the corresponding bit or bits in the PRESETCTRLn
\r
15184 * register, if they are implemented. Bits that do not correspond to defined bits in PRESETCTRLn
\r
15185 * are reserved and only zeroes should be written to them.
\r
15187 #define SYSCON_PRESETCTRLSET_RST_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_RST_SET_SHIFT)) & SYSCON_PRESETCTRLSET_RST_SET_MASK)
\r
15190 /* The count of SYSCON_PRESETCTRLSET */
\r
15191 #define SYSCON_PRESETCTRLSET_COUNT (3U)
\r
15193 /*! @name PRESETCTRLCLR - Clear bits in PRESETCTRLn */
\r
15195 #define SYSCON_PRESETCTRLCLR_RST_CLR_MASK (0xFFFFFFFFU)
\r
15196 #define SYSCON_PRESETCTRLCLR_RST_CLR_SHIFT (0U)
\r
15197 /*! RST_CLR - Writing ones to this register clears the corresponding bit or bits in the PRESETCTRLn
\r
15198 * register, if they are implemented. Bits that do not correspond to defined bits in PRESETCTRLn
\r
15199 * are reserved and only zeroes should be written to them.
\r
15201 #define SYSCON_PRESETCTRLCLR_RST_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_RST_CLR_SHIFT)) & SYSCON_PRESETCTRLCLR_RST_CLR_MASK)
\r
15204 /* The count of SYSCON_PRESETCTRLCLR */
\r
15205 #define SYSCON_PRESETCTRLCLR_COUNT (3U)
\r
15207 /*! @name SYSRSTSTAT - System reset status register */
\r
15209 #define SYSCON_SYSRSTSTAT_POR_MASK (0x1U)
\r
15210 #define SYSCON_SYSRSTSTAT_POR_SHIFT (0U)
\r
15211 /*! POR - POR reset status
\r
15212 * 0b0..No POR detected
\r
15213 * 0b1..POR detected. Writing a one clears this reset.
\r
15215 #define SYSCON_SYSRSTSTAT_POR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_POR_SHIFT)) & SYSCON_SYSRSTSTAT_POR_MASK)
\r
15216 #define SYSCON_SYSRSTSTAT_EXTRST_MASK (0x2U)
\r
15217 #define SYSCON_SYSRSTSTAT_EXTRST_SHIFT (1U)
\r
15218 /*! EXTRST - Status of the external RESET pin. External reset status
\r
15219 * 0b0..No reset event detected.
\r
15220 * 0b1..Reset detected. Writing a one clears this reset.
\r
15222 #define SYSCON_SYSRSTSTAT_EXTRST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_EXTRST_SHIFT)) & SYSCON_SYSRSTSTAT_EXTRST_MASK)
\r
15223 #define SYSCON_SYSRSTSTAT_WDT_MASK (0x4U)
\r
15224 #define SYSCON_SYSRSTSTAT_WDT_SHIFT (2U)
\r
15225 /*! WDT - Status of the Watchdog reset
\r
15226 * 0b0..No WDT reset detected
\r
15227 * 0b1..WDT reset detected. Writing a one clears this reset.
\r
15229 #define SYSCON_SYSRSTSTAT_WDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_WDT_SHIFT)) & SYSCON_SYSRSTSTAT_WDT_MASK)
\r
15230 #define SYSCON_SYSRSTSTAT_BOD_MASK (0x8U)
\r
15231 #define SYSCON_SYSRSTSTAT_BOD_SHIFT (3U)
\r
15232 /*! BOD - Status of the Brown-out detect reset
\r
15233 * 0b0..No BOD reset detected
\r
15234 * 0b1..BOD reset detected. Writing a one clears this reset.
\r
15236 #define SYSCON_SYSRSTSTAT_BOD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_BOD_SHIFT)) & SYSCON_SYSRSTSTAT_BOD_MASK)
\r
15237 #define SYSCON_SYSRSTSTAT_SYSRST_MASK (0x10U)
\r
15238 #define SYSCON_SYSRSTSTAT_SYSRST_SHIFT (4U)
\r
15239 /*! SYSRST - Status of the software system reset
\r
15240 * 0b0..No System reset detected
\r
15241 * 0b1..System reset detected. Writing a one clears this reset.
\r
15243 #define SYSCON_SYSRSTSTAT_SYSRST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_SYSRST_SHIFT)) & SYSCON_SYSRSTSTAT_SYSRST_MASK)
\r
15246 /*! @name AHBCLKCTRL - AHB Clock control n */
\r
15248 #define SYSCON_AHBCLKCTRL_MRT_MASK (0x1U)
\r
15249 #define SYSCON_AHBCLKCTRL_MRT_SHIFT (0U)
\r
15250 /*! MRT - Enables the clock for the Multi-Rate Timer.
\r
15252 #define SYSCON_AHBCLKCTRL_MRT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MRT_SHIFT)) & SYSCON_AHBCLKCTRL_MRT_MASK)
\r
15253 #define SYSCON_AHBCLKCTRL_RIT_MASK (0x2U)
\r
15254 #define SYSCON_AHBCLKCTRL_RIT_SHIFT (1U)
\r
15255 /*! RIT - Enables the clock for the Repetitive Interrupt Timer.
\r
15257 #define SYSCON_AHBCLKCTRL_RIT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_RIT_SHIFT)) & SYSCON_AHBCLKCTRL_RIT_MASK)
\r
15258 #define SYSCON_AHBCLKCTRL_ROM_MASK (0x2U)
\r
15259 #define SYSCON_AHBCLKCTRL_ROM_SHIFT (1U)
\r
15260 /*! ROM - Enables the clock for the Boot ROM. 0 = Disable; 1 = Enable.
\r
15262 #define SYSCON_AHBCLKCTRL_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ROM_SHIFT)) & SYSCON_AHBCLKCTRL_ROM_MASK)
\r
15263 #define SYSCON_AHBCLKCTRL_LCD_MASK (0x4U)
\r
15264 #define SYSCON_AHBCLKCTRL_LCD_SHIFT (2U)
\r
15265 /*! LCD - Enables the clock for the LCD interface.
\r
15267 #define SYSCON_AHBCLKCTRL_LCD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_LCD_SHIFT)) & SYSCON_AHBCLKCTRL_LCD_MASK)
\r
15268 #define SYSCON_AHBCLKCTRL_SCT0_MASK (0x4U)
\r
15269 #define SYSCON_AHBCLKCTRL_SCT0_SHIFT (2U)
\r
15270 /*! SCT0 - Enables the clock for SCT0.
\r
15272 #define SYSCON_AHBCLKCTRL_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SCT0_SHIFT)) & SYSCON_AHBCLKCTRL_SCT0_MASK)
\r
15273 #define SYSCON_AHBCLKCTRL_SDIO_MASK (0x8U)
\r
15274 #define SYSCON_AHBCLKCTRL_SDIO_SHIFT (3U)
\r
15275 /*! SDIO - Enables the clock for the SDIO interface.
\r
15277 #define SYSCON_AHBCLKCTRL_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SDIO_SHIFT)) & SYSCON_AHBCLKCTRL_SDIO_MASK)
\r
15278 #define SYSCON_AHBCLKCTRL_SRAM1_MASK (0x8U)
\r
15279 #define SYSCON_AHBCLKCTRL_SRAM1_SHIFT (3U)
\r
15280 /*! SRAM1 - Enables the clock for SRAM1. 0 = Disable; 1 = Enable.
\r
15282 #define SYSCON_AHBCLKCTRL_SRAM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM1_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM1_MASK)
\r
15283 #define SYSCON_AHBCLKCTRL_SRAM2_MASK (0x10U)
\r
15284 #define SYSCON_AHBCLKCTRL_SRAM2_SHIFT (4U)
\r
15285 /*! SRAM2 - Enables the clock for SRAM2. 0 = Disable; 1 = Enable.
\r
15287 #define SYSCON_AHBCLKCTRL_SRAM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM2_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM2_MASK)
\r
15288 #define SYSCON_AHBCLKCTRL_USB1H_MASK (0x10U)
\r
15289 #define SYSCON_AHBCLKCTRL_USB1H_SHIFT (4U)
\r
15290 /*! USB1H - Enables the clock for the USB1 host interface.
\r
15292 #define SYSCON_AHBCLKCTRL_USB1H(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB1H_SHIFT)) & SYSCON_AHBCLKCTRL_USB1H_MASK)
\r
15293 #define SYSCON_AHBCLKCTRL_SRAM3_MASK (0x20U)
\r
15294 #define SYSCON_AHBCLKCTRL_SRAM3_SHIFT (5U)
\r
15295 /*! SRAM3 - Enables the clock for SRAM3.
\r
15297 #define SYSCON_AHBCLKCTRL_SRAM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM3_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM3_MASK)
\r
15298 #define SYSCON_AHBCLKCTRL_USB1D_MASK (0x20U)
\r
15299 #define SYSCON_AHBCLKCTRL_USB1D_SHIFT (5U)
\r
15300 /*! USB1D - Enables the clock for the USB1 device interface.
\r
15302 #define SYSCON_AHBCLKCTRL_USB1D(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB1D_SHIFT)) & SYSCON_AHBCLKCTRL_USB1D_MASK)
\r
15303 #define SYSCON_AHBCLKCTRL_USB1RAM_MASK (0x40U)
\r
15304 #define SYSCON_AHBCLKCTRL_USB1RAM_SHIFT (6U)
\r
15305 /*! USB1RAM - Enables the clock for the USB1 RAM interface.
\r
15307 #define SYSCON_AHBCLKCTRL_USB1RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB1RAM_SHIFT)) & SYSCON_AHBCLKCTRL_USB1RAM_MASK)
\r
15308 #define SYSCON_AHBCLKCTRL_EMC_MASK (0x80U)
\r
15309 #define SYSCON_AHBCLKCTRL_EMC_SHIFT (7U)
\r
15310 /*! EMC - Enables the clock for the EMC interface.
\r
15312 #define SYSCON_AHBCLKCTRL_EMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_EMC_SHIFT)) & SYSCON_AHBCLKCTRL_EMC_MASK)
\r
15313 #define SYSCON_AHBCLKCTRL_MCAN0_MASK (0x80U)
\r
15314 #define SYSCON_AHBCLKCTRL_MCAN0_SHIFT (7U)
\r
15315 /*! MCAN0 - Enables the clock for MCAN0.
\r
15317 #define SYSCON_AHBCLKCTRL_MCAN0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MCAN0_SHIFT)) & SYSCON_AHBCLKCTRL_MCAN0_MASK)
\r
15318 #define SYSCON_AHBCLKCTRL_ETH_MASK (0x100U)
\r
15319 #define SYSCON_AHBCLKCTRL_ETH_SHIFT (8U)
\r
15320 /*! ETH - Enables the clock for the ethernet interface.
\r
15322 #define SYSCON_AHBCLKCTRL_ETH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ETH_SHIFT)) & SYSCON_AHBCLKCTRL_ETH_MASK)
\r
15323 #define SYSCON_AHBCLKCTRL_MCAN1_MASK (0x100U)
\r
15324 #define SYSCON_AHBCLKCTRL_MCAN1_SHIFT (8U)
\r
15325 /*! MCAN1 - Enables the clock for MCAN1.
\r
15327 #define SYSCON_AHBCLKCTRL_MCAN1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MCAN1_SHIFT)) & SYSCON_AHBCLKCTRL_MCAN1_MASK)
\r
15328 #define SYSCON_AHBCLKCTRL_GPIO4_MASK (0x200U)
\r
15329 #define SYSCON_AHBCLKCTRL_GPIO4_SHIFT (9U)
\r
15330 /*! GPIO4 - Enables the clock for the GPIO4 interface.
\r
15332 #define SYSCON_AHBCLKCTRL_GPIO4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO4_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO4_MASK)
\r
15333 #define SYSCON_AHBCLKCTRL_GPIO5_MASK (0x400U)
\r
15334 #define SYSCON_AHBCLKCTRL_GPIO5_SHIFT (10U)
\r
15335 /*! GPIO5 - Enables the clock for the GPIO5 interface.
\r
15337 #define SYSCON_AHBCLKCTRL_GPIO5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO5_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO5_MASK)
\r
15338 #define SYSCON_AHBCLKCTRL_SPIFI_MASK (0x400U)
\r
15339 #define SYSCON_AHBCLKCTRL_SPIFI_SHIFT (10U)
\r
15340 /*! SPIFI - Enables the clock for the SPIFI. 0 = Disable; 1 = Enable.
\r
15342 #define SYSCON_AHBCLKCTRL_SPIFI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SPIFI_SHIFT)) & SYSCON_AHBCLKCTRL_SPIFI_MASK)
\r
15343 #define SYSCON_AHBCLKCTRL_UTICK_MASK (0x400U)
\r
15344 #define SYSCON_AHBCLKCTRL_UTICK_SHIFT (10U)
\r
15345 /*! UTICK - Enables the clock for the Micro-tick Timer. 0 = Disable; 1 = Enable.
\r
15347 #define SYSCON_AHBCLKCTRL_UTICK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_UTICK_SHIFT)) & SYSCON_AHBCLKCTRL_UTICK_MASK)
\r
15348 #define SYSCON_AHBCLKCTRL_FLEXCOMM0_MASK (0x800U)
\r
15349 #define SYSCON_AHBCLKCTRL_FLEXCOMM0_SHIFT (11U)
\r
15350 /*! FLEXCOMM0 - Enables the clock for Flexcomm 0. 0 = Disable; 1 = Enable.
\r
15352 #define SYSCON_AHBCLKCTRL_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM0_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM0_MASK)
\r
15353 #define SYSCON_AHBCLKCTRL_INPUTMUX_MASK (0x800U)
\r
15354 #define SYSCON_AHBCLKCTRL_INPUTMUX_SHIFT (11U)
\r
15355 /*! INPUTMUX - Enables the clock for the input muxes. 0 = Disable; 1 = Enable.
\r
15357 #define SYSCON_AHBCLKCTRL_INPUTMUX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_INPUTMUX_SHIFT)) & SYSCON_AHBCLKCTRL_INPUTMUX_MASK)
\r
15358 #define SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK (0x1000U)
\r
15359 #define SYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT (12U)
\r
15360 /*! FLEXCOMM1 - Enables the clock for Flexcomm 1. 0 = Disable; 1 = Enable.
\r
15362 #define SYSCON_AHBCLKCTRL_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK)
\r
15363 #define SYSCON_AHBCLKCTRL_OTP_MASK (0x1000U)
\r
15364 #define SYSCON_AHBCLKCTRL_OTP_SHIFT (12U)
\r
15365 /*! OTP - Enables the clock for the OTP interface.
\r
15367 #define SYSCON_AHBCLKCTRL_OTP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_OTP_SHIFT)) & SYSCON_AHBCLKCTRL_OTP_MASK)
\r
15368 #define SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK (0x2000U)
\r
15369 #define SYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT (13U)
\r
15370 /*! FLEXCOMM2 - Enables the clock for Flexcomm 2. 0 = Disable; 1 = Enable.
\r
15372 #define SYSCON_AHBCLKCTRL_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK)
\r
15373 #define SYSCON_AHBCLKCTRL_IOCON_MASK (0x2000U)
\r
15374 #define SYSCON_AHBCLKCTRL_IOCON_SHIFT (13U)
\r
15375 /*! IOCON - Enables the clock for the IOCON block. 0 = Disable; 1 = Enable.
\r
15377 #define SYSCON_AHBCLKCTRL_IOCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL_IOCON_MASK)
\r
15378 #define SYSCON_AHBCLKCTRL_RNG_MASK (0x2000U)
\r
15379 #define SYSCON_AHBCLKCTRL_RNG_SHIFT (13U)
\r
15380 /*! RNG - Enables the clock for the RNG interface.
\r
15382 #define SYSCON_AHBCLKCTRL_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_RNG_SHIFT)) & SYSCON_AHBCLKCTRL_RNG_MASK)
\r
15383 #define SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK (0x4000U)
\r
15384 #define SYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT (14U)
\r
15385 /*! FLEXCOMM3 - Enables the clock for Flexcomm 3. 0 = Disable; 1 = Enable.
\r
15387 #define SYSCON_AHBCLKCTRL_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK)
\r
15388 #define SYSCON_AHBCLKCTRL_FLEXCOMM8_MASK (0x4000U)
\r
15389 #define SYSCON_AHBCLKCTRL_FLEXCOMM8_SHIFT (14U)
\r
15390 /*! FLEXCOMM8 - Enables the clock for the Flexcomm8 interface.
\r
15392 #define SYSCON_AHBCLKCTRL_FLEXCOMM8(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM8_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM8_MASK)
\r
15393 #define SYSCON_AHBCLKCTRL_GPIO0_MASK (0x4000U)
\r
15394 #define SYSCON_AHBCLKCTRL_GPIO0_SHIFT (14U)
\r
15395 /*! GPIO0 - Enables the clock for the GPIO0 port registers. 0 = Disable; 1 = Enable.
\r
15397 #define SYSCON_AHBCLKCTRL_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO0_MASK)
\r
15398 #define SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK (0x8000U)
\r
15399 #define SYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT (15U)
\r
15400 /*! FLEXCOMM4 - Enables the clock for Flexcomm 4. 0 = Disable; 1 = Enable.
\r
15402 #define SYSCON_AHBCLKCTRL_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK)
\r
15403 #define SYSCON_AHBCLKCTRL_FLEXCOMM9_MASK (0x8000U)
\r
15404 #define SYSCON_AHBCLKCTRL_FLEXCOMM9_SHIFT (15U)
\r
15405 /*! FLEXCOMM9 - Enables the clock for the Flexcomm9 interface.
\r
15407 #define SYSCON_AHBCLKCTRL_FLEXCOMM9(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM9_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM9_MASK)
\r
15408 #define SYSCON_AHBCLKCTRL_GPIO1_MASK (0x8000U)
\r
15409 #define SYSCON_AHBCLKCTRL_GPIO1_SHIFT (15U)
\r
15410 /*! GPIO1 - Enables the clock for the GPIO1 port registers. 0 = Disable; 1 = Enable.
\r
15412 #define SYSCON_AHBCLKCTRL_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO1_MASK)
\r
15413 #define SYSCON_AHBCLKCTRL_FLEXCOMM5_MASK (0x10000U)
\r
15414 #define SYSCON_AHBCLKCTRL_FLEXCOMM5_SHIFT (16U)
\r
15415 /*! FLEXCOMM5 - Enables the clock for Flexcomm 5. 0 = Disable; 1 = Enable.
\r
15417 #define SYSCON_AHBCLKCTRL_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM5_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM5_MASK)
\r
15418 #define SYSCON_AHBCLKCTRL_GPIO2_MASK (0x10000U)
\r
15419 #define SYSCON_AHBCLKCTRL_GPIO2_SHIFT (16U)
\r
15420 /*! GPIO2 - Enables the clock for the GPIO2 port registers.
\r
15422 #define SYSCON_AHBCLKCTRL_GPIO2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO2_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO2_MASK)
\r
15423 #define SYSCON_AHBCLKCTRL_USB0HMR_MASK (0x10000U)
\r
15424 #define SYSCON_AHBCLKCTRL_USB0HMR_SHIFT (16U)
\r
15425 /*! USB0HMR - Enables the clock for the USB host master interface.
\r
15427 #define SYSCON_AHBCLKCTRL_USB0HMR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB0HMR_SHIFT)) & SYSCON_AHBCLKCTRL_USB0HMR_MASK)
\r
15428 #define SYSCON_AHBCLKCTRL_FLEXCOMM6_MASK (0x20000U)
\r
15429 #define SYSCON_AHBCLKCTRL_FLEXCOMM6_SHIFT (17U)
\r
15430 /*! FLEXCOMM6 - Enables the clock for Flexcomm 6. 0 = Disable; 1 = Enable.
\r
15432 #define SYSCON_AHBCLKCTRL_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM6_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM6_MASK)
\r
15433 #define SYSCON_AHBCLKCTRL_GPIO3_MASK (0x20000U)
\r
15434 #define SYSCON_AHBCLKCTRL_GPIO3_SHIFT (17U)
\r
15435 /*! GPIO3 - Enables the clock for the GPIO3 port registers.
\r
15437 #define SYSCON_AHBCLKCTRL_GPIO3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO3_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO3_MASK)
\r
15438 #define SYSCON_AHBCLKCTRL_USB0HSL_MASK (0x20000U)
\r
15439 #define SYSCON_AHBCLKCTRL_USB0HSL_SHIFT (17U)
\r
15440 /*! USB0HSL - Enables the clock for the USB host slave interface.
\r
15442 #define SYSCON_AHBCLKCTRL_USB0HSL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB0HSL_SHIFT)) & SYSCON_AHBCLKCTRL_USB0HSL_MASK)
\r
15443 #define SYSCON_AHBCLKCTRL_FLEXCOMM7_MASK (0x40000U)
\r
15444 #define SYSCON_AHBCLKCTRL_FLEXCOMM7_SHIFT (18U)
\r
15445 /*! FLEXCOMM7 - Enables the clock for Flexcomm 7. 0 = Disable; 1 = Enable.
\r
15447 #define SYSCON_AHBCLKCTRL_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM7_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM7_MASK)
\r
15448 #define SYSCON_AHBCLKCTRL_PINT_MASK (0x40000U)
\r
15449 #define SYSCON_AHBCLKCTRL_PINT_SHIFT (18U)
\r
15450 /*! PINT - Enables the clock for the pin interrupt block.0 = Disable; 1 = Enable.
\r
15452 #define SYSCON_AHBCLKCTRL_PINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_PINT_SHIFT)) & SYSCON_AHBCLKCTRL_PINT_MASK)
\r
15453 #define SYSCON_AHBCLKCTRL_SHA_MASK (0x40000U)
\r
15454 #define SYSCON_AHBCLKCTRL_SHA_SHIFT (18U)
\r
15455 /*! SHA - Enables the clock for the SHA interface.
\r
15457 #define SYSCON_AHBCLKCTRL_SHA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SHA_SHIFT)) & SYSCON_AHBCLKCTRL_SHA_MASK)
\r
15458 #define SYSCON_AHBCLKCTRL_DMIC_MASK (0x80000U)
\r
15459 #define SYSCON_AHBCLKCTRL_DMIC_SHIFT (19U)
\r
15460 /*! DMIC - Enables the clock for the digital microphone interface. 0 = Disable; 1 = Enable.
\r
15462 #define SYSCON_AHBCLKCTRL_DMIC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_DMIC_SHIFT)) & SYSCON_AHBCLKCTRL_DMIC_MASK)
\r
15463 #define SYSCON_AHBCLKCTRL_GINT_MASK (0x80000U)
\r
15464 #define SYSCON_AHBCLKCTRL_GINT_SHIFT (19U)
\r
15465 /*! GINT - Enables the clock for the grouped pin interrupt block. 0 = Disable; 1 = Enable.
\r
15467 #define SYSCON_AHBCLKCTRL_GINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GINT_SHIFT)) & SYSCON_AHBCLKCTRL_GINT_MASK)
\r
15468 #define SYSCON_AHBCLKCTRL_SC0_MASK (0x80000U)
\r
15469 #define SYSCON_AHBCLKCTRL_SC0_SHIFT (19U)
\r
15470 /*! SC0 - Enables the clock for the Smart card0 interface.
\r
15472 #define SYSCON_AHBCLKCTRL_SC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SC0_SHIFT)) & SYSCON_AHBCLKCTRL_SC0_MASK)
\r
15473 #define SYSCON_AHBCLKCTRL_DMA_MASK (0x100000U)
\r
15474 #define SYSCON_AHBCLKCTRL_DMA_SHIFT (20U)
\r
15475 /*! DMA - Enables the clock for the DMA controller. 0 = Disable; 1 = Enable.
\r
15477 #define SYSCON_AHBCLKCTRL_DMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_DMA_SHIFT)) & SYSCON_AHBCLKCTRL_DMA_MASK)
\r
15478 #define SYSCON_AHBCLKCTRL_SC1_MASK (0x100000U)
\r
15479 #define SYSCON_AHBCLKCTRL_SC1_SHIFT (20U)
\r
15480 /*! SC1 - Enables the clock for the Smart card1 interface.
\r
15482 #define SYSCON_AHBCLKCTRL_SC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SC1_SHIFT)) & SYSCON_AHBCLKCTRL_SC1_MASK)
\r
15483 #define SYSCON_AHBCLKCTRL_CRC_MASK (0x200000U)
\r
15484 #define SYSCON_AHBCLKCTRL_CRC_SHIFT (21U)
\r
15485 /*! CRC - Enables the clock for the CRC engine. 0 = Disable; 1 = Enable.
\r
15487 #define SYSCON_AHBCLKCTRL_CRC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CRC_SHIFT)) & SYSCON_AHBCLKCTRL_CRC_MASK)
\r
15488 #define SYSCON_AHBCLKCTRL_FLEXCOMM10_MASK (0x200000U)
\r
15489 #define SYSCON_AHBCLKCTRL_FLEXCOMM10_SHIFT (21U)
\r
15490 /*! FLEXCOMM10 - Enables the clock for the Flexcomm10 interface.
\r
15492 #define SYSCON_AHBCLKCTRL_FLEXCOMM10(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM10_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM10_MASK)
\r
15493 #define SYSCON_AHBCLKCTRL_CTIMER2_MASK (0x400000U)
\r
15494 #define SYSCON_AHBCLKCTRL_CTIMER2_SHIFT (22U)
\r
15495 /*! CTIMER2 - Enables the clock for CTIMER 2. 0 = Disable; 1 = Enable.
\r
15497 #define SYSCON_AHBCLKCTRL_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER2_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER2_MASK)
\r
15498 #define SYSCON_AHBCLKCTRL_WWDT_MASK (0x400000U)
\r
15499 #define SYSCON_AHBCLKCTRL_WWDT_SHIFT (22U)
\r
15500 /*! WWDT - Enables the clock for the Watchdog Timer. 0 = Disable; 1 = Enable.
\r
15502 #define SYSCON_AHBCLKCTRL_WWDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_WWDT_SHIFT)) & SYSCON_AHBCLKCTRL_WWDT_MASK)
\r
15503 #define SYSCON_AHBCLKCTRL_RTC_MASK (0x800000U)
\r
15504 #define SYSCON_AHBCLKCTRL_RTC_SHIFT (23U)
\r
15505 /*! RTC - Enables the bus clock for the RTC. 0 = Disable; 1 = Enable.
\r
15507 #define SYSCON_AHBCLKCTRL_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_RTC_SHIFT)) & SYSCON_AHBCLKCTRL_RTC_MASK)
\r
15508 #define SYSCON_AHBCLKCTRL_USB0D_MASK (0x2000000U)
\r
15509 #define SYSCON_AHBCLKCTRL_USB0D_SHIFT (25U)
\r
15510 /*! USB0D - Enables the clock for the USB0 device interface. 0 = Disable; 1 = Enable.
\r
15512 #define SYSCON_AHBCLKCTRL_USB0D(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB0D_SHIFT)) & SYSCON_AHBCLKCTRL_USB0D_MASK)
\r
15513 #define SYSCON_AHBCLKCTRL_CTIMER0_MASK (0x4000000U)
\r
15514 #define SYSCON_AHBCLKCTRL_CTIMER0_SHIFT (26U)
\r
15515 /*! CTIMER0 - Enables the clock for timer CTIMER0. 0 = Disable; 1 = Enable.
\r
15517 #define SYSCON_AHBCLKCTRL_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER0_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER0_MASK)
\r
15518 #define SYSCON_AHBCLKCTRL_ADC0_MASK (0x8000000U)
\r
15519 #define SYSCON_AHBCLKCTRL_ADC0_SHIFT (27U)
\r
15520 /*! ADC0 - Enables the clock for the ADC0 register interface.
\r
15522 #define SYSCON_AHBCLKCTRL_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ADC0_SHIFT)) & SYSCON_AHBCLKCTRL_ADC0_MASK)
\r
15523 #define SYSCON_AHBCLKCTRL_CTIMER1_MASK (0x8000000U)
\r
15524 #define SYSCON_AHBCLKCTRL_CTIMER1_SHIFT (27U)
\r
15525 /*! CTIMER1 - Enables the clock for timer CTIMER1. 0 = Disable; 1 = Enable.
\r
15527 #define SYSCON_AHBCLKCTRL_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER1_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER1_MASK)
\r
15530 /* The count of SYSCON_AHBCLKCTRL */
\r
15531 #define SYSCON_AHBCLKCTRL_COUNT (3U)
\r
15533 /*! @name AHBCLKCTRLSET - Set bits in AHBCLKCTRLn */
\r
15535 #define SYSCON_AHBCLKCTRLSET_CLK_SET_MASK (0xFFFFFFFFU)
\r
15536 #define SYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT (0U)
\r
15537 /*! CLK_SET - Writing ones to this register sets the corresponding bit or bits in the AHBCLKCTRLn
\r
15538 * register, if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRLn
\r
15539 * are reserved and only zeroes should be written to them.
\r
15541 #define SYSCON_AHBCLKCTRLSET_CLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT)) & SYSCON_AHBCLKCTRLSET_CLK_SET_MASK)
\r
15544 /* The count of SYSCON_AHBCLKCTRLSET */
\r
15545 #define SYSCON_AHBCLKCTRLSET_COUNT (3U)
\r
15547 /*! @name AHBCLKCTRLCLR - Clear bits in AHBCLKCTRLn */
\r
15549 #define SYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK (0xFFFFFFFFU)
\r
15550 #define SYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT (0U)
\r
15551 /*! CLK_CLR - Writing ones to this register clears the corresponding bit or bits in the AHBCLKCTRLn
\r
15552 * register, if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRLn
\r
15553 * are reserved and only zeroes should be written to them.
\r
15555 #define SYSCON_AHBCLKCTRLCLR_CLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT)) & SYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK)
\r
15558 /* The count of SYSCON_AHBCLKCTRLCLR */
\r
15559 #define SYSCON_AHBCLKCTRLCLR_COUNT (3U)
\r
15561 /*! @name STICKCLKSEL - Systick timer clock source selection */
\r
15563 #define SYSCON_STICKCLKSEL_SEL_MASK (0x7U)
\r
15564 #define SYSCON_STICKCLKSEL_SEL_SHIFT (0U)
\r
15565 /*! SEL - Systick timer clock source selection
\r
15566 * 0b000..Main clock (main_clk)
\r
15567 * 0b001..Watchdog oscillator (wdt_clk)
\r
15568 * 0b010..RTC oscillator 32 kHz output (32k_clk)
\r
15569 * 0b011..FRO 12 MHz (fro_12m)
\r
15570 * 0b100..Reserved setting
\r
15571 * 0b101..Reserved setting
\r
15572 * 0b110..Reserved setting
\r
15573 * 0b111..None, this may be selected to reduce power when no output is needed.
\r
15575 #define SYSCON_STICKCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STICKCLKSEL_SEL_SHIFT)) & SYSCON_STICKCLKSEL_SEL_MASK)
\r
15578 /*! @name MAINCLKSELA - Main clock source select A */
\r
15580 #define SYSCON_MAINCLKSELA_SEL_MASK (0x3U)
\r
15581 #define SYSCON_MAINCLKSELA_SEL_SHIFT (0U)
\r
15582 /*! SEL - Clock source for main clock source selector A
\r
15583 * 0b00..FRO 12 MHz (fro_12m)
\r
15584 * 0b01..CLKIN (clk_in)
\r
15585 * 0b10..Watchdog oscillator (wdt_clk)
\r
15586 * 0b11..FRO 96 or 48 MHz (fro_hf)
\r
15588 #define SYSCON_MAINCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELA_SEL_SHIFT)) & SYSCON_MAINCLKSELA_SEL_MASK)
\r
15591 /*! @name MAINCLKSELB - Main clock source select B */
\r
15593 #define SYSCON_MAINCLKSELB_SEL_MASK (0x3U)
\r
15594 #define SYSCON_MAINCLKSELB_SEL_SHIFT (0U)
\r
15595 /*! SEL - Clock source for main clock source selector B. Selects the clock source for the main clock.
\r
15596 * 0b00..MAINCLKSELA. Use the clock source selected in MAINCLKSELA register.
\r
15597 * 0b01..Reserved setting
\r
15598 * 0b10..System PLL output (pll_clk)
\r
15599 * 0b11..RTC oscillator 32 kHz output (32k_clk)
\r
15601 #define SYSCON_MAINCLKSELB_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELB_SEL_SHIFT)) & SYSCON_MAINCLKSELB_SEL_MASK)
\r
15604 /*! @name CLKOUTSELA - CLKOUT clock source select A */
\r
15606 #define SYSCON_CLKOUTSELA_SEL_MASK (0x7U)
\r
15607 #define SYSCON_CLKOUTSELA_SEL_SHIFT (0U)
\r
15608 /*! SEL - CLKOUT clock source selection
\r
15609 * 0b000..Main clock (main_clk)
\r
15610 * 0b001..CLKIN (clk_in)
\r
15611 * 0b010..Watchdog oscillator (wdt_clk)
\r
15612 * 0b011..FRO 96 or 48 MHz (fro_hf)
\r
15613 * 0b100..PLL output (pll_clk)
\r
15614 * 0b101..USB PLL clock (usb_pll_clk)
\r
15615 * 0b110..Audio PLL clock (audio_pll_clk)
\r
15616 * 0b111..RTC oscillator 32 kHz output (32k_clk)
\r
15618 #define SYSCON_CLKOUTSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSELA_SEL_SHIFT)) & SYSCON_CLKOUTSELA_SEL_MASK)
\r
15621 /*! @name SYSPLLCLKSEL - PLL clock source select */
\r
15623 #define SYSCON_SYSPLLCLKSEL_SEL_MASK (0x7U)
\r
15624 #define SYSCON_SYSPLLCLKSEL_SEL_SHIFT (0U)
\r
15625 /*! SEL - System PLL clock source selection.
\r
15626 * 0b000..FRO 12 MHz (fro_12m)
\r
15627 * 0b001..CLKIN (clk_in)
\r
15628 * 0b011..RTC oscillator 32 kHz output (32k_clk)
\r
15629 * 0b111..None, this may be selected in order to reduce power when no output is needed.
\r
15631 #define SYSCON_SYSPLLCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCLKSEL_SEL_SHIFT)) & SYSCON_SYSPLLCLKSEL_SEL_MASK)
\r
15634 /*! @name AUDPLLCLKSEL - Audio PLL clock source select */
\r
15636 #define SYSCON_AUDPLLCLKSEL_SEL_MASK (0x7U)
\r
15637 #define SYSCON_AUDPLLCLKSEL_SEL_SHIFT (0U)
\r
15638 /*! SEL - Audio PLL clock source selection.
\r
15639 * 0b000..FRO 12 MHz (fro_12m)
\r
15640 * 0b001..CLKIN (clk_in)
\r
15641 * 0b111..None, this may be selected in order to reduce power when no output is needed.
\r
15643 #define SYSCON_AUDPLLCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCLKSEL_SEL_SHIFT)) & SYSCON_AUDPLLCLKSEL_SEL_MASK)
\r
15646 /*! @name SPIFICLKSEL - SPIFI clock source select */
\r
15648 #define SYSCON_SPIFICLKSEL_SEL_MASK (0x7U)
\r
15649 #define SYSCON_SPIFICLKSEL_SEL_SHIFT (0U)
\r
15650 /*! SEL - System PLL clock source selection
\r
15651 * 0b000..Main clock (main_clk)
\r
15652 * 0b001..System PLL output (pll_clk)
\r
15653 * 0b010..USB PLL clock (usb_pll_clk)
\r
15654 * 0b011..FRO 96 or 48 MHz (fro_hf)
\r
15655 * 0b100..Audio PLL clock (audio_pll_clk)
\r
15656 * 0b111..None, this may be selected in order to reduce power when no output is needed.
\r
15658 #define SYSCON_SPIFICLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKSEL_SEL_SHIFT)) & SYSCON_SPIFICLKSEL_SEL_MASK)
\r
15661 /*! @name ADCCLKSEL - ADC clock source select */
\r
15663 #define SYSCON_ADCCLKSEL_SEL_MASK (0x7U)
\r
15664 #define SYSCON_ADCCLKSEL_SEL_SHIFT (0U)
\r
15665 /*! SEL - ADC clock source selection
\r
15666 * 0b000..FRO 96 or 48 MHz (fro_hf)
\r
15667 * 0b001..System PLL output (pll_clk)
\r
15668 * 0b010..USB PLL clock (usb_pll_clk)
\r
15669 * 0b011..Audio PLL clock (audio_pll_clk)
\r
15670 * 0b111..None, this may be selected in order to reduce power when no output is needed.
\r
15672 #define SYSCON_ADCCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKSEL_SEL_SHIFT)) & SYSCON_ADCCLKSEL_SEL_MASK)
\r
15675 /*! @name USB0CLKSEL - USB0 clock source select */
\r
15677 #define SYSCON_USB0CLKSEL_SEL_MASK (0x7U)
\r
15678 #define SYSCON_USB0CLKSEL_SEL_SHIFT (0U)
\r
15679 /*! SEL - USB0 device clock source selection.
\r
15680 * 0b000..FRO 96 or 48 MHz (fro_hf)
\r
15681 * 0b001..System PLL output (pll_clk)
\r
15682 * 0b010..USB PLL clock (usb_pll_clk)
\r
15683 * 0b111..None, this may be selected in order to reduce power when no output is needed.
\r
15685 #define SYSCON_USB0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSEL_SEL_SHIFT)) & SYSCON_USB0CLKSEL_SEL_MASK)
\r
15688 /*! @name USB1CLKSEL - USB1 clock source select */
\r
15690 #define SYSCON_USB1CLKSEL_SEL_MASK (0x7U)
\r
15691 #define SYSCON_USB1CLKSEL_SEL_SHIFT (0U)
\r
15692 /*! SEL - USB1 PHY clock source selection.
\r
15693 * 0b000..Main clock (main_clk)
\r
15694 * 0b001..System PLL output (pll_clk)
\r
15695 * 0b010..USB PLL clock (usb_pll_clk)
\r
15696 * 0b111..None, this may be selected in order to reduce power when no output is needed.
\r
15698 #define SYSCON_USB1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSEL_SEL_SHIFT)) & SYSCON_USB1CLKSEL_SEL_MASK)
\r
15701 /*! @name FCLKSEL - Flexcomm clock source select */
\r
15703 #define SYSCON_FCLKSEL_SEL_MASK (0x7U)
\r
15704 #define SYSCON_FCLKSEL_SEL_SHIFT (0U)
\r
15705 /*! SEL - Flexcomm clock source selection. One per Flexcomm.
\r
15706 * 0b000..FRO 12 MHz (fro_12m)
\r
15707 * 0b001..FRO HF DIV (fro_hf_div)
\r
15708 * 0b010..Audio PLL clock (audio_pll_clk)
\r
15709 * 0b011..MCLK pin input, when selected in IOCON (mclk_in)
\r
15710 * 0b100..FRG clock, the output of the fractional rate generator (frg_clk)
\r
15711 * 0b111..None, this may be selected in order to reduce power when no output is needed.
\r
15713 #define SYSCON_FCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCLKSEL_SEL_SHIFT)) & SYSCON_FCLKSEL_SEL_MASK)
\r
15716 /* The count of SYSCON_FCLKSEL */
\r
15717 #define SYSCON_FCLKSEL_COUNT (10U)
\r
15719 /*! @name FCLKSEL10 - Flexcomm 10 clock source select */
\r
15721 #define SYSCON_FCLKSEL10_SEL_MASK (0x7U)
\r
15722 #define SYSCON_FCLKSEL10_SEL_SHIFT (0U)
\r
15723 /*! SEL - Flexcomm clock source selection. One per Flexcomm.
\r
15724 * 0b000..Main clock (main_clk)
\r
15725 * 0b001..System PLL output (pll_clk)
\r
15726 * 0b010..USB PLL clock (usb_pll_clk)
\r
15727 * 0b011..FRO 96 or 48 MHz (fro_hf)
\r
15728 * 0b100..Audio PLL clock (audio_pll_clk)
\r
15729 * 0b111..None, this may be selected in order to reduce power when no output is needed.
\r
15731 #define SYSCON_FCLKSEL10_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCLKSEL10_SEL_SHIFT)) & SYSCON_FCLKSEL10_SEL_MASK)
\r
15734 /*! @name MCLKCLKSEL - MCLK clock source select */
\r
15736 #define SYSCON_MCLKCLKSEL_SEL_MASK (0x7U)
\r
15737 #define SYSCON_MCLKCLKSEL_SEL_SHIFT (0U)
\r
15738 /*! SEL - MCLK source select. This may be used by Flexcomms that support I2S, and/or by the digital microphone subsystem.
\r
15739 * 0b000..FRO HF DIV (fro_hf_div)
\r
15740 * 0b001..Audio PLL clock (audio_pll_clk)
\r
15741 * 0b111..None, this may be selected in order to reduce power when no output is needed.
\r
15743 #define SYSCON_MCLKCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKCLKSEL_SEL_SHIFT)) & SYSCON_MCLKCLKSEL_SEL_MASK)
\r
15746 /*! @name FRGCLKSEL - Fractional Rate Generator clock source select */
\r
15748 #define SYSCON_FRGCLKSEL_SEL_MASK (0x7U)
\r
15749 #define SYSCON_FRGCLKSEL_SEL_SHIFT (0U)
\r
15750 /*! SEL - Fractional Rate Generator clock source select.
\r
15751 * 0b000..Main clock (main_clk)
\r
15752 * 0b001..System PLL output (pll_clk)
\r
15753 * 0b010..FRO 12 MHz (fro_12m)
\r
15754 * 0b011..FRO 96 or 48 MHz (fro_hf)
\r
15755 * 0b111..None, this may be selected in order to reduce power when no output is needed.
\r
15757 #define SYSCON_FRGCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCLKSEL_SEL_SHIFT)) & SYSCON_FRGCLKSEL_SEL_MASK)
\r
15760 /*! @name DMICCLKSEL - Digital microphone (DMIC) subsystem clock select */
\r
15762 #define SYSCON_DMICCLKSEL_SEL_MASK (0x7U)
\r
15763 #define SYSCON_DMICCLKSEL_SEL_SHIFT (0U)
\r
15764 /*! SEL - DMIC (audio subsystem) clock source select.
\r
15765 * 0b000..FRO 12 MHz (fro_12m)
\r
15766 * 0b001..FRO HF DIV (fro_hf_div)
\r
15767 * 0b010..Audio PLL clock (audio_pll_clk)
\r
15768 * 0b011..MCLK pin input, when selected in IOCON (mclk_in)
\r
15769 * 0b100..Main clock (main_clk)
\r
15770 * 0b101..Watchdog oscillator (wdt_clk)
\r
15771 * 0b111..None, this may be selected in order to reduce power when no output is needed.
\r
15773 #define SYSCON_DMICCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKSEL_SEL_SHIFT)) & SYSCON_DMICCLKSEL_SEL_MASK)
\r
15776 /*! @name SCTCLKSEL - SCTimer/PWM clock source select */
\r
15778 #define SYSCON_SCTCLKSEL_SEL_MASK (0x7U)
\r
15779 #define SYSCON_SCTCLKSEL_SEL_SHIFT (0U)
\r
15780 /*! SEL - SCT clock source select.
\r
15781 * 0b000..Main clock (main_clk)
\r
15782 * 0b001..System PLL output (pll_clk)
\r
15783 * 0b010..FRO 96 or 48 MHz (fro_hf)
\r
15784 * 0b011..Audio PLL clock (audio_pll_clk)
\r
15785 * 0b111..None, this may be selected in order to reduce power when no output is needed.
\r
15787 #define SYSCON_SCTCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKSEL_SEL_SHIFT)) & SYSCON_SCTCLKSEL_SEL_MASK)
\r
15790 /*! @name LCDCLKSEL - LCD clock source select */
\r
15792 #define SYSCON_LCDCLKSEL_SEL_MASK (0x3U)
\r
15793 #define SYSCON_LCDCLKSEL_SEL_SHIFT (0U)
\r
15794 /*! SEL - LCD clock source select.
\r
15795 * 0b00..Main clock (main_clk)
\r
15796 * 0b01..LCDCLKIN (LCDCLK_EXT)
\r
15797 * 0b10..FRO 96 or 48 MHz (fro_hf)
\r
15798 * 0b11..None, this may be selected in order to reduce power when no output is needed.
\r
15800 #define SYSCON_LCDCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKSEL_SEL_SHIFT)) & SYSCON_LCDCLKSEL_SEL_MASK)
\r
15803 /*! @name SDIOCLKSEL - SDIO clock source select */
\r
15805 #define SYSCON_SDIOCLKSEL_SEL_MASK (0x7U)
\r
15806 #define SYSCON_SDIOCLKSEL_SEL_SHIFT (0U)
\r
15807 /*! SEL - SDIO clock source select.
\r
15808 * 0b000..Main clock (main_clk)
\r
15809 * 0b001..System PLL output (pll_clk)
\r
15810 * 0b010..USB PLL clock (usb_pll_clk)
\r
15811 * 0b011..FRO 96 or 48 MHz (fro_hf)
\r
15812 * 0b100..Audio PLL clock (audio_pll_clk)
\r
15813 * 0b111..None, this may be selected in order to reduce power when no output is needed.
\r
15815 #define SYSCON_SDIOCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKSEL_SEL_SHIFT)) & SYSCON_SDIOCLKSEL_SEL_MASK)
\r
15818 /*! @name SYSTICKCLKDIV - SYSTICK clock divider */
\r
15820 #define SYSCON_SYSTICKCLKDIV_DIV_MASK (0xFFU)
\r
15821 #define SYSCON_SYSTICKCLKDIV_DIV_SHIFT (0U)
\r
15822 /*! DIV - Clock divider value. 0: Divide by 1 up to 255: Divide by 256.
\r
15824 #define SYSCON_SYSTICKCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV_DIV_MASK)
\r
15825 #define SYSCON_SYSTICKCLKDIV_RESET_MASK (0x20000000U)
\r
15826 #define SYSCON_SYSTICKCLKDIV_RESET_SHIFT (29U)
\r
15827 /*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right
\r
15828 * away rather than completing the previous count.
\r
15830 #define SYSCON_SYSTICKCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV_RESET_MASK)
\r
15831 #define SYSCON_SYSTICKCLKDIV_HALT_MASK (0x40000000U)
\r
15832 #define SYSCON_SYSTICKCLKDIV_HALT_SHIFT (30U)
\r
15833 /*! HALT - Halts the divider counter.
\r
15835 #define SYSCON_SYSTICKCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV_HALT_MASK)
\r
15836 #define SYSCON_SYSTICKCLKDIV_REQFLAG_MASK (0x80000000U)
\r
15837 #define SYSCON_SYSTICKCLKDIV_REQFLAG_SHIFT (31U)
\r
15838 /*! REQFLAG - Divider status flag.
\r
15840 #define SYSCON_SYSTICKCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_REQFLAG_SHIFT)) & SYSCON_SYSTICKCLKDIV_REQFLAG_MASK)
\r
15843 /*! @name ARMTRACECLKDIV - ARM Trace clock divider */
\r
15845 #define SYSCON_ARMTRACECLKDIV_DIV_MASK (0xFFU)
\r
15846 #define SYSCON_ARMTRACECLKDIV_DIV_SHIFT (0U)
\r
15847 /*! DIV - Clock divider value.
\r
15849 #define SYSCON_ARMTRACECLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_DIV_SHIFT)) & SYSCON_ARMTRACECLKDIV_DIV_MASK)
\r
15850 #define SYSCON_ARMTRACECLKDIV_RESET_MASK (0x20000000U)
\r
15851 #define SYSCON_ARMTRACECLKDIV_RESET_SHIFT (29U)
\r
15852 /*! RESET - Resets the divider counter.
\r
15854 #define SYSCON_ARMTRACECLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_RESET_SHIFT)) & SYSCON_ARMTRACECLKDIV_RESET_MASK)
\r
15855 #define SYSCON_ARMTRACECLKDIV_HALT_MASK (0x40000000U)
\r
15856 #define SYSCON_ARMTRACECLKDIV_HALT_SHIFT (30U)
\r
15857 /*! HALT - Halts the divider counter.
\r
15859 #define SYSCON_ARMTRACECLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_HALT_SHIFT)) & SYSCON_ARMTRACECLKDIV_HALT_MASK)
\r
15860 #define SYSCON_ARMTRACECLKDIV_REQFLAG_MASK (0x80000000U)
\r
15861 #define SYSCON_ARMTRACECLKDIV_REQFLAG_SHIFT (31U)
\r
15862 /*! REQFLAG - Divider status flag.
\r
15864 #define SYSCON_ARMTRACECLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_REQFLAG_SHIFT)) & SYSCON_ARMTRACECLKDIV_REQFLAG_MASK)
\r
15867 /*! @name CAN0CLKDIV - MCAN0 clock divider */
\r
15869 #define SYSCON_CAN0CLKDIV_DIV_MASK (0xFFU)
\r
15870 #define SYSCON_CAN0CLKDIV_DIV_SHIFT (0U)
\r
15871 /*! DIV - Clock divider value.
\r
15873 #define SYSCON_CAN0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_DIV_SHIFT)) & SYSCON_CAN0CLKDIV_DIV_MASK)
\r
15874 #define SYSCON_CAN0CLKDIV_RESET_MASK (0x20000000U)
\r
15875 #define SYSCON_CAN0CLKDIV_RESET_SHIFT (29U)
\r
15876 /*! RESET - Resets the divider counter.
\r
15878 #define SYSCON_CAN0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_RESET_SHIFT)) & SYSCON_CAN0CLKDIV_RESET_MASK)
\r
15879 #define SYSCON_CAN0CLKDIV_HALT_MASK (0x40000000U)
\r
15880 #define SYSCON_CAN0CLKDIV_HALT_SHIFT (30U)
\r
15881 /*! HALT - Halts the divider counter.
\r
15883 #define SYSCON_CAN0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_HALT_SHIFT)) & SYSCON_CAN0CLKDIV_HALT_MASK)
\r
15884 #define SYSCON_CAN0CLKDIV_REQFLAG_MASK (0x80000000U)
\r
15885 #define SYSCON_CAN0CLKDIV_REQFLAG_SHIFT (31U)
\r
15886 /*! REQFLAG - Divider status flag.
\r
15888 #define SYSCON_CAN0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_REQFLAG_SHIFT)) & SYSCON_CAN0CLKDIV_REQFLAG_MASK)
\r
15891 /*! @name CAN1CLKDIV - MCAN1 clock divider */
\r
15893 #define SYSCON_CAN1CLKDIV_DIV_MASK (0xFFU)
\r
15894 #define SYSCON_CAN1CLKDIV_DIV_SHIFT (0U)
\r
15895 /*! DIV - Clock divider value. 0: Divide by 1 up to 255: Divide by 256.
\r
15897 #define SYSCON_CAN1CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_DIV_SHIFT)) & SYSCON_CAN1CLKDIV_DIV_MASK)
\r
15898 #define SYSCON_CAN1CLKDIV_RESET_MASK (0x20000000U)
\r
15899 #define SYSCON_CAN1CLKDIV_RESET_SHIFT (29U)
\r
15900 /*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right
\r
15901 * away rather than completing the previous count.
\r
15903 #define SYSCON_CAN1CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_RESET_SHIFT)) & SYSCON_CAN1CLKDIV_RESET_MASK)
\r
15904 #define SYSCON_CAN1CLKDIV_HALT_MASK (0x40000000U)
\r
15905 #define SYSCON_CAN1CLKDIV_HALT_SHIFT (30U)
\r
15906 /*! HALT - Halts the divider counter.
\r
15908 #define SYSCON_CAN1CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_HALT_SHIFT)) & SYSCON_CAN1CLKDIV_HALT_MASK)
\r
15909 #define SYSCON_CAN1CLKDIV_REQFLAG_MASK (0x80000000U)
\r
15910 #define SYSCON_CAN1CLKDIV_REQFLAG_SHIFT (31U)
\r
15911 /*! REQFLAG - Divider status flag.
\r
15913 #define SYSCON_CAN1CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_REQFLAG_SHIFT)) & SYSCON_CAN1CLKDIV_REQFLAG_MASK)
\r
15916 /*! @name SC0CLKDIV - Smartcard0 clock divider */
\r
15918 #define SYSCON_SC0CLKDIV_DIV_MASK (0xFFU)
\r
15919 #define SYSCON_SC0CLKDIV_DIV_SHIFT (0U)
\r
15920 /*! DIV - Clock divider value.
\r
15922 #define SYSCON_SC0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_DIV_SHIFT)) & SYSCON_SC0CLKDIV_DIV_MASK)
\r
15923 #define SYSCON_SC0CLKDIV_RESET_MASK (0x20000000U)
\r
15924 #define SYSCON_SC0CLKDIV_RESET_SHIFT (29U)
\r
15925 /*! RESET - Resets the divider counter.
\r
15927 #define SYSCON_SC0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_RESET_SHIFT)) & SYSCON_SC0CLKDIV_RESET_MASK)
\r
15928 #define SYSCON_SC0CLKDIV_HALT_MASK (0x40000000U)
\r
15929 #define SYSCON_SC0CLKDIV_HALT_SHIFT (30U)
\r
15930 /*! HALT - Halts the divider counter.
\r
15932 #define SYSCON_SC0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_HALT_SHIFT)) & SYSCON_SC0CLKDIV_HALT_MASK)
\r
15933 #define SYSCON_SC0CLKDIV_REQFLAG_MASK (0x80000000U)
\r
15934 #define SYSCON_SC0CLKDIV_REQFLAG_SHIFT (31U)
\r
15935 /*! REQFLAG - Divider status flag.
\r
15937 #define SYSCON_SC0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_REQFLAG_SHIFT)) & SYSCON_SC0CLKDIV_REQFLAG_MASK)
\r
15940 /*! @name SC1CLKDIV - Smartcard1 clock divider */
\r
15942 #define SYSCON_SC1CLKDIV_DIV_MASK (0xFFU)
\r
15943 #define SYSCON_SC1CLKDIV_DIV_SHIFT (0U)
\r
15944 /*! DIV - Clock divider value.
\r
15946 #define SYSCON_SC1CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_DIV_SHIFT)) & SYSCON_SC1CLKDIV_DIV_MASK)
\r
15947 #define SYSCON_SC1CLKDIV_RESET_MASK (0x20000000U)
\r
15948 #define SYSCON_SC1CLKDIV_RESET_SHIFT (29U)
\r
15949 /*! RESET - Resets the divider counter.
\r
15951 #define SYSCON_SC1CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_RESET_SHIFT)) & SYSCON_SC1CLKDIV_RESET_MASK)
\r
15952 #define SYSCON_SC1CLKDIV_HALT_MASK (0x40000000U)
\r
15953 #define SYSCON_SC1CLKDIV_HALT_SHIFT (30U)
\r
15954 /*! HALT - Halts the divider counter.
\r
15956 #define SYSCON_SC1CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_HALT_SHIFT)) & SYSCON_SC1CLKDIV_HALT_MASK)
\r
15957 #define SYSCON_SC1CLKDIV_REQFLAG_MASK (0x80000000U)
\r
15958 #define SYSCON_SC1CLKDIV_REQFLAG_SHIFT (31U)
\r
15959 /*! REQFLAG - Divider status flag.
\r
15961 #define SYSCON_SC1CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_REQFLAG_SHIFT)) & SYSCON_SC1CLKDIV_REQFLAG_MASK)
\r
15964 /*! @name AHBCLKDIV - AHB clock divider */
\r
15966 #define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU)
\r
15967 #define SYSCON_AHBCLKDIV_DIV_SHIFT (0U)
\r
15968 /*! DIV - Clock divider value. 0: Divide by 1 up to 255: Divide by 256.
\r
15970 #define SYSCON_AHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK)
\r
15971 #define SYSCON_AHBCLKDIV_REQFLAG_MASK (0x80000000U)
\r
15972 #define SYSCON_AHBCLKDIV_REQFLAG_SHIFT (31U)
\r
15973 /*! REQFLAG - Divider status flag.
\r
15975 #define SYSCON_AHBCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_REQFLAG_SHIFT)) & SYSCON_AHBCLKDIV_REQFLAG_MASK)
\r
15978 /*! @name CLKOUTDIV - CLKOUT clock divider */
\r
15980 #define SYSCON_CLKOUTDIV_DIV_MASK (0xFFU)
\r
15981 #define SYSCON_CLKOUTDIV_DIV_SHIFT (0U)
\r
15982 /*! DIV - Clock divider value. 0: Divide by 1 up to 255: Divide by 256.
\r
15984 #define SYSCON_CLKOUTDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK)
\r
15985 #define SYSCON_CLKOUTDIV_RESET_MASK (0x20000000U)
\r
15986 #define SYSCON_CLKOUTDIV_RESET_SHIFT (29U)
\r
15987 /*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right
\r
15988 * away rather than completing the previous count.
\r
15990 #define SYSCON_CLKOUTDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK)
\r
15991 #define SYSCON_CLKOUTDIV_HALT_MASK (0x40000000U)
\r
15992 #define SYSCON_CLKOUTDIV_HALT_SHIFT (30U)
\r
15993 /*! HALT - Halts the divider counter. The intent is to allow the divider clock source to be changed
\r
15994 * without the risk of a glitch at the output.
\r
15996 #define SYSCON_CLKOUTDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK)
\r
15997 #define SYSCON_CLKOUTDIV_REQFLAG_MASK (0x80000000U)
\r
15998 #define SYSCON_CLKOUTDIV_REQFLAG_SHIFT (31U)
\r
15999 /*! REQFLAG - Divider status flag.
\r
16001 #define SYSCON_CLKOUTDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_REQFLAG_SHIFT)) & SYSCON_CLKOUTDIV_REQFLAG_MASK)
\r
16004 /*! @name FROHFDIV - FROHF clock divider */
\r
16006 #define SYSCON_FROHFDIV_DIV_MASK (0xFFU)
\r
16007 #define SYSCON_FROHFDIV_DIV_SHIFT (0U)
\r
16008 /*! DIV - Clock divider value.
\r
16010 #define SYSCON_FROHFDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_DIV_SHIFT)) & SYSCON_FROHFDIV_DIV_MASK)
\r
16011 #define SYSCON_FROHFDIV_RESET_MASK (0x20000000U)
\r
16012 #define SYSCON_FROHFDIV_RESET_SHIFT (29U)
\r
16013 /*! RESET - Resets the divider counter.
\r
16015 #define SYSCON_FROHFDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_RESET_SHIFT)) & SYSCON_FROHFDIV_RESET_MASK)
\r
16016 #define SYSCON_FROHFDIV_HALT_MASK (0x40000000U)
\r
16017 #define SYSCON_FROHFDIV_HALT_SHIFT (30U)
\r
16018 /*! HALT - Halts the divider counter.
\r
16020 #define SYSCON_FROHFDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_HALT_SHIFT)) & SYSCON_FROHFDIV_HALT_MASK)
\r
16021 #define SYSCON_FROHFDIV_REQFLAG_MASK (0x80000000U)
\r
16022 #define SYSCON_FROHFDIV_REQFLAG_SHIFT (31U)
\r
16023 /*! REQFLAG - Divider status flag.
\r
16025 #define SYSCON_FROHFDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_REQFLAG_SHIFT)) & SYSCON_FROHFDIV_REQFLAG_MASK)
\r
16028 /*! @name SPIFICLKDIV - SPIFI clock divider */
\r
16030 #define SYSCON_SPIFICLKDIV_DIV_MASK (0xFFU)
\r
16031 #define SYSCON_SPIFICLKDIV_DIV_SHIFT (0U)
\r
16032 /*! DIV - Clock divider value.
\r
16034 #define SYSCON_SPIFICLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_DIV_SHIFT)) & SYSCON_SPIFICLKDIV_DIV_MASK)
\r
16035 #define SYSCON_SPIFICLKDIV_RESET_MASK (0x20000000U)
\r
16036 #define SYSCON_SPIFICLKDIV_RESET_SHIFT (29U)
\r
16037 /*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right
\r
16038 * away rather than completing the previous count.
\r
16040 #define SYSCON_SPIFICLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_RESET_SHIFT)) & SYSCON_SPIFICLKDIV_RESET_MASK)
\r
16041 #define SYSCON_SPIFICLKDIV_HALT_MASK (0x40000000U)
\r
16042 #define SYSCON_SPIFICLKDIV_HALT_SHIFT (30U)
\r
16043 /*! HALT - Halts the divider counter. The intent is to allow the divider clock source to be changed
\r
16044 * without the risk of a glitch at the output.
\r
16046 #define SYSCON_SPIFICLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_HALT_SHIFT)) & SYSCON_SPIFICLKDIV_HALT_MASK)
\r
16047 #define SYSCON_SPIFICLKDIV_REQFLAG_MASK (0x80000000U)
\r
16048 #define SYSCON_SPIFICLKDIV_REQFLAG_SHIFT (31U)
\r
16049 /*! REQFLAG - Divider status flag.
\r
16051 #define SYSCON_SPIFICLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_REQFLAG_SHIFT)) & SYSCON_SPIFICLKDIV_REQFLAG_MASK)
\r
16054 /*! @name ADCCLKDIV - ADC clock divider */
\r
16056 #define SYSCON_ADCCLKDIV_DIV_MASK (0xFFU)
\r
16057 #define SYSCON_ADCCLKDIV_DIV_SHIFT (0U)
\r
16058 /*! DIV - Clock divider value.
\r
16060 #define SYSCON_ADCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_DIV_SHIFT)) & SYSCON_ADCCLKDIV_DIV_MASK)
\r
16061 #define SYSCON_ADCCLKDIV_RESET_MASK (0x20000000U)
\r
16062 #define SYSCON_ADCCLKDIV_RESET_SHIFT (29U)
\r
16063 /*! RESET - Resets the divider counter.
\r
16065 #define SYSCON_ADCCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_RESET_SHIFT)) & SYSCON_ADCCLKDIV_RESET_MASK)
\r
16066 #define SYSCON_ADCCLKDIV_HALT_MASK (0x40000000U)
\r
16067 #define SYSCON_ADCCLKDIV_HALT_SHIFT (30U)
\r
16068 /*! HALT - Halts the divider counter.
\r
16070 #define SYSCON_ADCCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_HALT_SHIFT)) & SYSCON_ADCCLKDIV_HALT_MASK)
\r
16071 #define SYSCON_ADCCLKDIV_REQFLAG_MASK (0x80000000U)
\r
16072 #define SYSCON_ADCCLKDIV_REQFLAG_SHIFT (31U)
\r
16073 /*! REQFLAG - Divider status flag.
\r
16075 #define SYSCON_ADCCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_REQFLAG_SHIFT)) & SYSCON_ADCCLKDIV_REQFLAG_MASK)
\r
16078 /*! @name USB0CLKDIV - USB0 clock divider */
\r
16080 #define SYSCON_USB0CLKDIV_DIV_MASK (0xFFU)
\r
16081 #define SYSCON_USB0CLKDIV_DIV_SHIFT (0U)
\r
16082 /*! DIV - Clock divider value.
\r
16084 #define SYSCON_USB0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_DIV_SHIFT)) & SYSCON_USB0CLKDIV_DIV_MASK)
\r
16085 #define SYSCON_USB0CLKDIV_RESET_MASK (0x20000000U)
\r
16086 #define SYSCON_USB0CLKDIV_RESET_SHIFT (29U)
\r
16087 /*! RESET - Resets the divider counter.
\r
16089 #define SYSCON_USB0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_RESET_SHIFT)) & SYSCON_USB0CLKDIV_RESET_MASK)
\r
16090 #define SYSCON_USB0CLKDIV_HALT_MASK (0x40000000U)
\r
16091 #define SYSCON_USB0CLKDIV_HALT_SHIFT (30U)
\r
16092 /*! HALT - Halts the divider counter.
\r
16094 #define SYSCON_USB0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_HALT_SHIFT)) & SYSCON_USB0CLKDIV_HALT_MASK)
\r
16095 #define SYSCON_USB0CLKDIV_REQFLAG_MASK (0x80000000U)
\r
16096 #define SYSCON_USB0CLKDIV_REQFLAG_SHIFT (31U)
\r
16097 /*! REQFLAG - Divider status flag.
\r
16099 #define SYSCON_USB0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_REQFLAG_SHIFT)) & SYSCON_USB0CLKDIV_REQFLAG_MASK)
\r
16102 /*! @name USB1CLKDIV - USB1 clock divider */
\r
16104 #define SYSCON_USB1CLKDIV_DIV_MASK (0xFFU)
\r
16105 #define SYSCON_USB1CLKDIV_DIV_SHIFT (0U)
\r
16106 /*! DIV - Clock divider value.
\r
16108 #define SYSCON_USB1CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_DIV_SHIFT)) & SYSCON_USB1CLKDIV_DIV_MASK)
\r
16109 #define SYSCON_USB1CLKDIV_RESET_MASK (0x20000000U)
\r
16110 #define SYSCON_USB1CLKDIV_RESET_SHIFT (29U)
\r
16111 /*! RESET - Resets the divider counter.
\r
16113 #define SYSCON_USB1CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_RESET_SHIFT)) & SYSCON_USB1CLKDIV_RESET_MASK)
\r
16114 #define SYSCON_USB1CLKDIV_HALT_MASK (0x40000000U)
\r
16115 #define SYSCON_USB1CLKDIV_HALT_SHIFT (30U)
\r
16116 /*! HALT - Halts the divider counter.
\r
16118 #define SYSCON_USB1CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_HALT_SHIFT)) & SYSCON_USB1CLKDIV_HALT_MASK)
\r
16119 #define SYSCON_USB1CLKDIV_REQFLAG_MASK (0x80000000U)
\r
16120 #define SYSCON_USB1CLKDIV_REQFLAG_SHIFT (31U)
\r
16121 /*! REQFLAG - Divider status flag.
\r
16123 #define SYSCON_USB1CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_REQFLAG_SHIFT)) & SYSCON_USB1CLKDIV_REQFLAG_MASK)
\r
16126 /*! @name FRGCTRL - Fractional rate divider */
\r
16128 #define SYSCON_FRGCTRL_DIV_MASK (0xFFU)
\r
16129 #define SYSCON_FRGCTRL_DIV_SHIFT (0U)
\r
16130 /*! DIV - Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set
\r
16131 * to 0xFF to use with the fractional baud rate generator.
\r
16133 #define SYSCON_FRGCTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_DIV_SHIFT)) & SYSCON_FRGCTRL_DIV_MASK)
\r
16134 #define SYSCON_FRGCTRL_MULT_MASK (0xFF00U)
\r
16135 #define SYSCON_FRGCTRL_MULT_SHIFT (8U)
\r
16136 /*! MULT - Numerator of the fractional divider. MULT is equal to the programmed value.
\r
16138 #define SYSCON_FRGCTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_MULT_SHIFT)) & SYSCON_FRGCTRL_MULT_MASK)
\r
16141 /*! @name DMICCLKDIV - DMIC clock divider */
\r
16143 #define SYSCON_DMICCLKDIV_DIV_MASK (0xFFU)
\r
16144 #define SYSCON_DMICCLKDIV_DIV_SHIFT (0U)
\r
16145 /*! DIV - Clock divider value. 0: Divide by 1 up to 255: Divide by 256.
\r
16147 #define SYSCON_DMICCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_DIV_SHIFT)) & SYSCON_DMICCLKDIV_DIV_MASK)
\r
16148 #define SYSCON_DMICCLKDIV_RESET_MASK (0x20000000U)
\r
16149 #define SYSCON_DMICCLKDIV_RESET_SHIFT (29U)
\r
16150 /*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right
\r
16151 * away rather than completing the previous count.
\r
16153 #define SYSCON_DMICCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_RESET_SHIFT)) & SYSCON_DMICCLKDIV_RESET_MASK)
\r
16154 #define SYSCON_DMICCLKDIV_HALT_MASK (0x40000000U)
\r
16155 #define SYSCON_DMICCLKDIV_HALT_SHIFT (30U)
\r
16156 /*! HALT - Halts the divider counter. The intent is to allow the divider clock source to be changed
\r
16157 * without the risk of a glitch at the output.
\r
16159 #define SYSCON_DMICCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_HALT_SHIFT)) & SYSCON_DMICCLKDIV_HALT_MASK)
\r
16160 #define SYSCON_DMICCLKDIV_REQFLAG_MASK (0x80000000U)
\r
16161 #define SYSCON_DMICCLKDIV_REQFLAG_SHIFT (31U)
\r
16162 /*! REQFLAG - Divider status flag.
\r
16164 #define SYSCON_DMICCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_REQFLAG_SHIFT)) & SYSCON_DMICCLKDIV_REQFLAG_MASK)
\r
16167 /*! @name MCLKDIV - I2S MCLK clock divider */
\r
16169 #define SYSCON_MCLKDIV_DIV_MASK (0xFFU)
\r
16170 #define SYSCON_MCLKDIV_DIV_SHIFT (0U)
\r
16171 /*! DIV - Clock divider value. 0: Divide by 1 up to 255: Divide by 256.
\r
16173 #define SYSCON_MCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_DIV_SHIFT)) & SYSCON_MCLKDIV_DIV_MASK)
\r
16174 #define SYSCON_MCLKDIV_RESET_MASK (0x20000000U)
\r
16175 #define SYSCON_MCLKDIV_RESET_SHIFT (29U)
\r
16176 /*! RESET - Resets the divider counter.
\r
16178 #define SYSCON_MCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_RESET_SHIFT)) & SYSCON_MCLKDIV_RESET_MASK)
\r
16179 #define SYSCON_MCLKDIV_HALT_MASK (0x40000000U)
\r
16180 #define SYSCON_MCLKDIV_HALT_SHIFT (30U)
\r
16181 /*! HALT - Halts the divider counter.
\r
16183 #define SYSCON_MCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_HALT_SHIFT)) & SYSCON_MCLKDIV_HALT_MASK)
\r
16184 #define SYSCON_MCLKDIV_REQFLAG_MASK (0x80000000U)
\r
16185 #define SYSCON_MCLKDIV_REQFLAG_SHIFT (31U)
\r
16186 /*! REQFLAG - Divider status flag.
\r
16188 #define SYSCON_MCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_REQFLAG_SHIFT)) & SYSCON_MCLKDIV_REQFLAG_MASK)
\r
16191 /*! @name LCDCLKDIV - LCD clock divider */
\r
16193 #define SYSCON_LCDCLKDIV_DIV_MASK (0xFFU)
\r
16194 #define SYSCON_LCDCLKDIV_DIV_SHIFT (0U)
\r
16195 /*! DIV - Clock divider value.
\r
16197 #define SYSCON_LCDCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_DIV_SHIFT)) & SYSCON_LCDCLKDIV_DIV_MASK)
\r
16198 #define SYSCON_LCDCLKDIV_RESET_MASK (0x20000000U)
\r
16199 #define SYSCON_LCDCLKDIV_RESET_SHIFT (29U)
\r
16200 /*! RESET - Resets the divider counter.
\r
16202 #define SYSCON_LCDCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_RESET_SHIFT)) & SYSCON_LCDCLKDIV_RESET_MASK)
\r
16203 #define SYSCON_LCDCLKDIV_HALT_MASK (0x40000000U)
\r
16204 #define SYSCON_LCDCLKDIV_HALT_SHIFT (30U)
\r
16205 /*! HALT - Halts the divider counter.
\r
16207 #define SYSCON_LCDCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_HALT_SHIFT)) & SYSCON_LCDCLKDIV_HALT_MASK)
\r
16208 #define SYSCON_LCDCLKDIV_REQFLAG_MASK (0x80000000U)
\r
16209 #define SYSCON_LCDCLKDIV_REQFLAG_SHIFT (31U)
\r
16210 /*! REQFLAG - Divider status flag.
\r
16212 #define SYSCON_LCDCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_REQFLAG_SHIFT)) & SYSCON_LCDCLKDIV_REQFLAG_MASK)
\r
16215 /*! @name SCTCLKDIV - SCT/PWM clock divider */
\r
16217 #define SYSCON_SCTCLKDIV_DIV_MASK (0xFFU)
\r
16218 #define SYSCON_SCTCLKDIV_DIV_SHIFT (0U)
\r
16219 /*! DIV - Clock divider value.
\r
16221 #define SYSCON_SCTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_DIV_SHIFT)) & SYSCON_SCTCLKDIV_DIV_MASK)
\r
16222 #define SYSCON_SCTCLKDIV_RESET_MASK (0x20000000U)
\r
16223 #define SYSCON_SCTCLKDIV_RESET_SHIFT (29U)
\r
16224 /*! RESET - Resets the divider counter.
\r
16226 #define SYSCON_SCTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_RESET_SHIFT)) & SYSCON_SCTCLKDIV_RESET_MASK)
\r
16227 #define SYSCON_SCTCLKDIV_HALT_MASK (0x40000000U)
\r
16228 #define SYSCON_SCTCLKDIV_HALT_SHIFT (30U)
\r
16229 /*! HALT - Halts the divider counter.
\r
16231 #define SYSCON_SCTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_HALT_SHIFT)) & SYSCON_SCTCLKDIV_HALT_MASK)
\r
16232 #define SYSCON_SCTCLKDIV_REQFLAG_MASK (0x80000000U)
\r
16233 #define SYSCON_SCTCLKDIV_REQFLAG_SHIFT (31U)
\r
16234 /*! REQFLAG - Divider status flag.
\r
16236 #define SYSCON_SCTCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_REQFLAG_SHIFT)) & SYSCON_SCTCLKDIV_REQFLAG_MASK)
\r
16239 /*! @name EMCCLKDIV - EMC clock divider */
\r
16241 #define SYSCON_EMCCLKDIV_DIV_MASK (0xFFU)
\r
16242 #define SYSCON_EMCCLKDIV_DIV_SHIFT (0U)
\r
16243 /*! DIV - Clock divider value.
\r
16245 #define SYSCON_EMCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_DIV_SHIFT)) & SYSCON_EMCCLKDIV_DIV_MASK)
\r
16246 #define SYSCON_EMCCLKDIV_RESET_MASK (0x20000000U)
\r
16247 #define SYSCON_EMCCLKDIV_RESET_SHIFT (29U)
\r
16248 /*! RESET - Resets the divider counter.
\r
16250 #define SYSCON_EMCCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_RESET_SHIFT)) & SYSCON_EMCCLKDIV_RESET_MASK)
\r
16251 #define SYSCON_EMCCLKDIV_HALT_MASK (0x40000000U)
\r
16252 #define SYSCON_EMCCLKDIV_HALT_SHIFT (30U)
\r
16253 /*! HALT - Halts the divider counter.
\r
16255 #define SYSCON_EMCCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_HALT_SHIFT)) & SYSCON_EMCCLKDIV_HALT_MASK)
\r
16256 #define SYSCON_EMCCLKDIV_REQFLAG_MASK (0x80000000U)
\r
16257 #define SYSCON_EMCCLKDIV_REQFLAG_SHIFT (31U)
\r
16258 /*! REQFLAG - Divider status flag.
\r
16260 #define SYSCON_EMCCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_REQFLAG_SHIFT)) & SYSCON_EMCCLKDIV_REQFLAG_MASK)
\r
16263 /*! @name SDIOCLKDIV - SDIO clock divider */
\r
16265 #define SYSCON_SDIOCLKDIV_DIV_MASK (0xFFU)
\r
16266 #define SYSCON_SDIOCLKDIV_DIV_SHIFT (0U)
\r
16267 /*! DIV - Clock divider value.
\r
16269 #define SYSCON_SDIOCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_DIV_SHIFT)) & SYSCON_SDIOCLKDIV_DIV_MASK)
\r
16270 #define SYSCON_SDIOCLKDIV_RESET_MASK (0x20000000U)
\r
16271 #define SYSCON_SDIOCLKDIV_RESET_SHIFT (29U)
\r
16272 /*! RESET - Resets the divider counter.
\r
16274 #define SYSCON_SDIOCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_RESET_SHIFT)) & SYSCON_SDIOCLKDIV_RESET_MASK)
\r
16275 #define SYSCON_SDIOCLKDIV_HALT_MASK (0x40000000U)
\r
16276 #define SYSCON_SDIOCLKDIV_HALT_SHIFT (30U)
\r
16277 /*! HALT - Halts the divider counter.
\r
16279 #define SYSCON_SDIOCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_HALT_SHIFT)) & SYSCON_SDIOCLKDIV_HALT_MASK)
\r
16280 #define SYSCON_SDIOCLKDIV_REQFLAG_MASK (0x80000000U)
\r
16281 #define SYSCON_SDIOCLKDIV_REQFLAG_SHIFT (31U)
\r
16282 /*! REQFLAG - Divider status flag.
\r
16284 #define SYSCON_SDIOCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_REQFLAG_SHIFT)) & SYSCON_SDIOCLKDIV_REQFLAG_MASK)
\r
16287 /*! @name USB0CLKCTRL - USB0 clock control */
\r
16289 #define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_MASK (0x1U)
\r
16290 #define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_SHIFT (0U)
\r
16291 /*! AP_FS_DEV_CLK - USB0 Device USB0_NEEDCLK signal control.
\r
16293 #define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_MASK)
\r
16294 #define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_MASK (0x2U)
\r
16295 #define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_SHIFT (1U)
\r
16296 /*! POL_FS_DEV_CLK - USB0 Device USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt.
\r
16298 #define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_MASK)
\r
16299 #define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_MASK (0x4U)
\r
16300 #define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_SHIFT (2U)
\r
16301 /*! AP_FS_HOST_CLK - USB0 Host USB0_NEEDCLK signal control.
\r
16303 #define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_MASK)
\r
16304 #define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_MASK (0x8U)
\r
16305 #define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_SHIFT (3U)
\r
16306 /*! POL_FS_HOST_CLK - USB0 Host USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt.
\r
16308 #define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_MASK)
\r
16309 #define SYSCON_USB0CLKCTRL_PU_DISABLE_MASK (0x10U)
\r
16310 #define SYSCON_USB0CLKCTRL_PU_DISABLE_SHIFT (4U)
\r
16311 /*! PU_DISABLE - Internal pull-up disable control.
\r
16313 #define SYSCON_USB0CLKCTRL_PU_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_PU_DISABLE_SHIFT)) & SYSCON_USB0CLKCTRL_PU_DISABLE_MASK)
\r
16316 /*! @name USB0CLKSTAT - USB0 clock status */
\r
16318 #define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_MASK (0x1U)
\r
16319 #define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_SHIFT (0U)
\r
16320 /*! DEV_NEED_CLKST - USB0 Device USB0_NEEDCLK signal status.
\r
16322 #define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_SHIFT)) & SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_MASK)
\r
16323 #define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_MASK (0x2U)
\r
16324 #define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_SHIFT (1U)
\r
16325 /*! HOST_NEED_CLKST - USB0 Host USB0_NEEDCLK signal status.
\r
16327 #define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_SHIFT)) & SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_MASK)
\r
16330 /*! @name FREQMECTRL - Frequency measure register */
\r
16332 #define SYSCON_FREQMECTRL_CAPVAL_MASK (0x3FFFU)
\r
16333 #define SYSCON_FREQMECTRL_CAPVAL_SHIFT (0U)
\r
16334 /*! CAPVAL - Stores the capture result which is used to calculate the frequency of the target clock. This field is read-only.
\r
16336 #define SYSCON_FREQMECTRL_CAPVAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_CAPVAL_SHIFT)) & SYSCON_FREQMECTRL_CAPVAL_MASK)
\r
16337 #define SYSCON_FREQMECTRL_PROG_MASK (0x80000000U)
\r
16338 #define SYSCON_FREQMECTRL_PROG_SHIFT (31U)
\r
16339 /*! PROG - Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit
\r
16340 * when the measurement cycle has completed and there is valid capture data in the CAPVAL field
\r
16343 #define SYSCON_FREQMECTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_PROG_SHIFT)) & SYSCON_FREQMECTRL_PROG_MASK)
\r
16346 /*! @name MCLKIO - MCLK input/output control */
\r
16348 #define SYSCON_MCLKIO_DIR_MASK (0x1U)
\r
16349 #define SYSCON_MCLKIO_DIR_SHIFT (0U)
\r
16350 /*! DIR - MCLK direction control.
\r
16352 #define SYSCON_MCLKIO_DIR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKIO_DIR_SHIFT)) & SYSCON_MCLKIO_DIR_MASK)
\r
16355 /*! @name USB1CLKCTRL - USB1 clock control */
\r
16357 #define SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_MASK (0x1U)
\r
16358 #define SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_SHIFT (0U)
\r
16359 /*! AP_FS_DEV_CLK - USB1 Device need_clock signal control.
\r
16361 #define SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_MASK)
\r
16362 #define SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_MASK (0x2U)
\r
16363 #define SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_SHIFT (1U)
\r
16364 /*! POL_FS_DEV_CLK - USB1 Device need_clock polarity for triggering the USB1 wake-up interrupt.
\r
16366 #define SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_MASK)
\r
16367 #define SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_MASK (0x4U)
\r
16368 #define SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_SHIFT (2U)
\r
16369 /*! AP_FS_HOST_CLK - USB1 Host need_clock signal control.
\r
16371 #define SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_MASK)
\r
16372 #define SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_MASK (0x8U)
\r
16373 #define SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_SHIFT (3U)
\r
16374 /*! POL_FS_HOST_CLK - USB1 Host need_clock polarity for triggering the USB1 wake-up interrupt.
\r
16376 #define SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_MASK)
\r
16377 #define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_MASK (0x10U)
\r
16378 #define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_SHIFT (4U)
\r
16379 /*! HS_DEV_WAKEUP_N - External user wake-up signal for device mode; asserting this signal (active
\r
16380 * low) will result in exiting the low power mode; input to asynchronous control logic.
\r
16382 #define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_SHIFT)) & SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_MASK)
\r
16385 /*! @name USB1CLKSTAT - USB1 clock status */
\r
16387 #define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_MASK (0x1U)
\r
16388 #define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_SHIFT (0U)
\r
16389 /*! DEV_NEED_CLKST - USB1 Device USB1_NEEDCLK signal status.
\r
16391 #define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_SHIFT)) & SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_MASK)
\r
16392 #define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_MASK (0x2U)
\r
16393 #define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_SHIFT (1U)
\r
16394 /*! HOST_NEED_CLKST - USB1 Device host USB1_NEEDCLK signal status.
\r
16396 #define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_SHIFT)) & SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_MASK)
\r
16399 /*! @name EMCSYSCTRL - EMC system control */
\r
16401 #define SYSCON_EMCSYSCTRL_EMCSC_MASK (0x1U)
\r
16402 #define SYSCON_EMCSYSCTRL_EMCSC_SHIFT (0U)
\r
16403 /*! EMCSC - EMC Shift Control.
\r
16405 #define SYSCON_EMCSYSCTRL_EMCSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCSC_SHIFT)) & SYSCON_EMCSYSCTRL_EMCSC_MASK)
\r
16406 #define SYSCON_EMCSYSCTRL_EMCRD_MASK (0x2U)
\r
16407 #define SYSCON_EMCSYSCTRL_EMCRD_SHIFT (1U)
\r
16408 /*! EMCRD - EMC Reset Disable.
\r
16410 #define SYSCON_EMCSYSCTRL_EMCRD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCRD_SHIFT)) & SYSCON_EMCSYSCTRL_EMCRD_MASK)
\r
16411 #define SYSCON_EMCSYSCTRL_EMCBC_MASK (0x4U)
\r
16412 #define SYSCON_EMCSYSCTRL_EMCBC_SHIFT (2U)
\r
16413 /*! EMCBC - External Memory Controller burst control.
\r
16415 #define SYSCON_EMCSYSCTRL_EMCBC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCBC_SHIFT)) & SYSCON_EMCSYSCTRL_EMCBC_MASK)
\r
16416 #define SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_MASK (0x8U)
\r
16417 #define SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_SHIFT (3U)
\r
16418 /*! EMCFBCLKINSEL - External Memory Controller clock select.
\r
16420 #define SYSCON_EMCSYSCTRL_EMCFBCLKINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_SHIFT)) & SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_MASK)
\r
16423 /*! @name EMCDYCTRL - EMC clock delay control */
\r
16425 #define SYSCON_EMCDYCTRL_CMD_DELAY_MASK (0x1FU)
\r
16426 #define SYSCON_EMCDYCTRL_CMD_DELAY_SHIFT (0U)
\r
16427 /*! CMD_DELAY - Programmable delay value for EMC outputs in command delayed mode.
\r
16429 #define SYSCON_EMCDYCTRL_CMD_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDYCTRL_CMD_DELAY_SHIFT)) & SYSCON_EMCDYCTRL_CMD_DELAY_MASK)
\r
16430 #define SYSCON_EMCDYCTRL_FBCLK_DELAY_MASK (0x1F00U)
\r
16431 #define SYSCON_EMCDYCTRL_FBCLK_DELAY_SHIFT (8U)
\r
16432 /*! FBCLK_DELAY - Programmable delay value for the feedback clock that controls input data sampling.
\r
16434 #define SYSCON_EMCDYCTRL_FBCLK_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDYCTRL_FBCLK_DELAY_SHIFT)) & SYSCON_EMCDYCTRL_FBCLK_DELAY_MASK)
\r
16437 /*! @name EMCCAL - EMC delay chain calibration control */
\r
16439 #define SYSCON_EMCCAL_CALVALUE_MASK (0xFFU)
\r
16440 #define SYSCON_EMCCAL_CALVALUE_SHIFT (0U)
\r
16441 /*! CALVALUE - Returns the count of the approximately 50 MHz ring oscillator that occur during 32 clocks of the FRO 12 MHz.
\r
16443 #define SYSCON_EMCCAL_CALVALUE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCAL_CALVALUE_SHIFT)) & SYSCON_EMCCAL_CALVALUE_MASK)
\r
16444 #define SYSCON_EMCCAL_START_MASK (0x4000U)
\r
16445 #define SYSCON_EMCCAL_START_SHIFT (14U)
\r
16446 /*! START - Start control bit for the EMC calibration counter.
\r
16448 #define SYSCON_EMCCAL_START(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCAL_START_SHIFT)) & SYSCON_EMCCAL_START_MASK)
\r
16449 #define SYSCON_EMCCAL_DONE_MASK (0x8000U)
\r
16450 #define SYSCON_EMCCAL_DONE_SHIFT (15U)
\r
16451 /*! DONE - Measurement completion flag.
\r
16453 #define SYSCON_EMCCAL_DONE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCAL_DONE_SHIFT)) & SYSCON_EMCCAL_DONE_MASK)
\r
16456 /*! @name ETHPHYSEL - Ethernet PHY Selection */
\r
16458 #define SYSCON_ETHPHYSEL_PHY_SEL_MASK (0x4U)
\r
16459 #define SYSCON_ETHPHYSEL_PHY_SEL_SHIFT (2U)
\r
16460 /*! PHY_SEL - PHY interface select.
\r
16462 #define SYSCON_ETHPHYSEL_PHY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ETHPHYSEL_PHY_SEL_SHIFT)) & SYSCON_ETHPHYSEL_PHY_SEL_MASK)
\r
16465 /*! @name ETHSBDCTRL - Ethernet SBD flow control */
\r
16467 #define SYSCON_ETHSBDCTRL_SBD_CTRL_MASK (0x3U)
\r
16468 #define SYSCON_ETHSBDCTRL_SBD_CTRL_SHIFT (0U)
\r
16469 /*! SBD_CTRL - Sideband Flow Control.
\r
16471 #define SYSCON_ETHSBDCTRL_SBD_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ETHSBDCTRL_SBD_CTRL_SHIFT)) & SYSCON_ETHSBDCTRL_SBD_CTRL_MASK)
\r
16474 /*! @name SDIOCLKCTRL - SDIO CCLKIN phase and delay control */
\r
16476 #define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (0x3U)
\r
16477 #define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT (0U)
\r
16478 /*! CCLK_DRV_PHASE - Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in.
\r
16480 #define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK)
\r
16481 #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU)
\r
16482 #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT (2U)
\r
16483 /*! CCLK_SAMPLE_PHASE - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in.
\r
16485 #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK)
\r
16486 #define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (0x80U)
\r
16487 #define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT (7U)
\r
16488 /*! PHASE_ACTIVE - sdio_clk by 2, before feeding into ccl_in, cclk_in_sample, and cclk_in_drv.
\r
16490 #define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK)
\r
16491 #define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK (0x1F0000U)
\r
16492 #define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT (16U)
\r
16493 /*! CCLK_DRV_DELAY - Programmable delay value by which cclk_in_drv is delayed with regard to cclk_in.
\r
16495 #define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK)
\r
16496 #define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK (0x800000U)
\r
16497 #define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT (23U)
\r
16498 /*! CCLK_DRV_DELAY_ACTIVE - Enables drive delay, as controlled by the CCLK_DRV_DELAY field.
\r
16500 #define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK)
\r
16501 #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK (0x1F000000U)
\r
16502 #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT (24U)
\r
16503 /*! CCLK_SAMPLE_DELAY - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in.
\r
16505 #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK)
\r
16506 #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK (0x80000000U)
\r
16507 #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT (31U)
\r
16508 /*! CCLK_SAMPLE_DELAY_ACTIVE - Enables sample delay, as controlled by the CCLK_SAMPLE_DELAY field.
\r
16510 #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK)
\r
16513 /*! @name KEYMUXSEL - AES key source selection */
\r
16515 #define SYSCON_KEYMUXSEL_SEL_MASK (0x3U)
\r
16516 #define SYSCON_KEYMUXSEL_SEL_SHIFT (0U)
\r
16517 /*! SEL - PHY interface select.
\r
16519 #define SYSCON_KEYMUXSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_KEYMUXSEL_SEL_SHIFT)) & SYSCON_KEYMUXSEL_SEL_MASK)
\r
16520 #define SYSCON_KEYMUXSEL_LOCK_MASK (0x80U)
\r
16521 #define SYSCON_KEYMUXSEL_LOCK_SHIFT (7U)
\r
16522 /*! LOCK - LOCK stat.
\r
16524 #define SYSCON_KEYMUXSEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_KEYMUXSEL_LOCK_SHIFT)) & SYSCON_KEYMUXSEL_LOCK_MASK)
\r
16527 /*! @name FROCTRL - FRO oscillator control */
\r
16529 #define SYSCON_FROCTRL_SEL_MASK (0x4000U)
\r
16530 #define SYSCON_FROCTRL_SEL_SHIFT (14U)
\r
16531 /*! SEL - Select the FRO HF output frequency.
\r
16533 #define SYSCON_FROCTRL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_SEL_SHIFT)) & SYSCON_FROCTRL_SEL_MASK)
\r
16534 #define SYSCON_FROCTRL_FREQTRIM_MASK (0xFF0000U)
\r
16535 #define SYSCON_FROCTRL_FREQTRIM_SHIFT (16U)
\r
16536 /*! FREQTRIM - Frequency trim.
\r
16538 #define SYSCON_FROCTRL_FREQTRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_FREQTRIM_SHIFT)) & SYSCON_FROCTRL_FREQTRIM_MASK)
\r
16539 #define SYSCON_FROCTRL_USBCLKADJ_MASK (0x1000000U)
\r
16540 #define SYSCON_FROCTRL_USBCLKADJ_SHIFT (24U)
\r
16541 /*! USBCLKADJ - USB clock adjust mode.
\r
16543 #define SYSCON_FROCTRL_USBCLKADJ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_USBCLKADJ_SHIFT)) & SYSCON_FROCTRL_USBCLKADJ_MASK)
\r
16544 #define SYSCON_FROCTRL_USBMODCHG_MASK (0x2000000U)
\r
16545 #define SYSCON_FROCTRL_USBMODCHG_SHIFT (25U)
\r
16546 /*! USBMODCHG - USB Mode value Change flag.
\r
16548 #define SYSCON_FROCTRL_USBMODCHG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_USBMODCHG_SHIFT)) & SYSCON_FROCTRL_USBMODCHG_MASK)
\r
16549 #define SYSCON_FROCTRL_HSPDCLK_MASK (0x40000000U)
\r
16550 #define SYSCON_FROCTRL_HSPDCLK_SHIFT (30U)
\r
16551 /*! HSPDCLK - High speed clock enable.
\r
16553 #define SYSCON_FROCTRL_HSPDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_HSPDCLK_SHIFT)) & SYSCON_FROCTRL_HSPDCLK_MASK)
\r
16556 /*! @name SYSOSCCTRL - System oscillator control */
\r
16558 #define SYSCON_SYSOSCCTRL_FREQRANGE_MASK (0x2U)
\r
16559 #define SYSCON_SYSOSCCTRL_FREQRANGE_SHIFT (1U)
\r
16560 /*! FREQRANGE - Determines frequency range for system oscillator.
\r
16562 #define SYSCON_SYSOSCCTRL_FREQRANGE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSOSCCTRL_FREQRANGE_SHIFT)) & SYSCON_SYSOSCCTRL_FREQRANGE_MASK)
\r
16565 /*! @name WDTOSCCTRL - Watchdog oscillator control */
\r
16567 #define SYSCON_WDTOSCCTRL_DIVSEL_MASK (0x1FU)
\r
16568 #define SYSCON_WDTOSCCTRL_DIVSEL_SHIFT (0U)
\r
16569 /*! DIVSEL - Divider select.
\r
16571 #define SYSCON_WDTOSCCTRL_DIVSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_DIVSEL_SHIFT)) & SYSCON_WDTOSCCTRL_DIVSEL_MASK)
\r
16572 #define SYSCON_WDTOSCCTRL_FREQSEL_MASK (0x3E0U)
\r
16573 #define SYSCON_WDTOSCCTRL_FREQSEL_SHIFT (5U)
\r
16574 /*! FREQSEL - Frequency select.
\r
16576 #define SYSCON_WDTOSCCTRL_FREQSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)) & SYSCON_WDTOSCCTRL_FREQSEL_MASK)
\r
16579 /*! @name RTCOSCCTRL - RTC oscillator 32 kHz output control */
\r
16581 #define SYSCON_RTCOSCCTRL_EN_MASK (0x1U)
\r
16582 #define SYSCON_RTCOSCCTRL_EN_SHIFT (0U)
\r
16583 /*! EN - RTC 32 kHz clock enable.
\r
16585 #define SYSCON_RTCOSCCTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_RTCOSCCTRL_EN_SHIFT)) & SYSCON_RTCOSCCTRL_EN_MASK)
\r
16588 /*! @name USBPLLCTRL - USB PLL control */
\r
16590 #define SYSCON_USBPLLCTRL_MSEL_MASK (0xFFU)
\r
16591 #define SYSCON_USBPLLCTRL_MSEL_SHIFT (0U)
\r
16592 /*! MSEL - PLL feedback Divider value.
\r
16594 #define SYSCON_USBPLLCTRL_MSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_MSEL_SHIFT)) & SYSCON_USBPLLCTRL_MSEL_MASK)
\r
16595 #define SYSCON_USBPLLCTRL_PSEL_MASK (0x300U)
\r
16596 #define SYSCON_USBPLLCTRL_PSEL_SHIFT (8U)
\r
16597 /*! PSEL - PLL Divider value.
\r
16599 #define SYSCON_USBPLLCTRL_PSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_PSEL_SHIFT)) & SYSCON_USBPLLCTRL_PSEL_MASK)
\r
16600 #define SYSCON_USBPLLCTRL_NSEL_MASK (0xC00U)
\r
16601 #define SYSCON_USBPLLCTRL_NSEL_SHIFT (10U)
\r
16602 /*! NSEL - PLL feedback Divider value.
\r
16604 #define SYSCON_USBPLLCTRL_NSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_NSEL_SHIFT)) & SYSCON_USBPLLCTRL_NSEL_MASK)
\r
16605 #define SYSCON_USBPLLCTRL_DIRECT_MASK (0x1000U)
\r
16606 #define SYSCON_USBPLLCTRL_DIRECT_SHIFT (12U)
\r
16607 /*! DIRECT - Direct CCO clock output control.
\r
16608 * 0b0..CCO Clock signal goes through post divider.
\r
16609 * 0b1..CCO Clock signal goes directly to output(s)..
\r
16611 #define SYSCON_USBPLLCTRL_DIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_DIRECT_SHIFT)) & SYSCON_USBPLLCTRL_DIRECT_MASK)
\r
16612 #define SYSCON_USBPLLCTRL_BYPASS_MASK (0x2000U)
\r
16613 #define SYSCON_USBPLLCTRL_BYPASS_SHIFT (13U)
\r
16614 /*! BYPASS - Input clock bypass control.
\r
16615 * 0b0..CCO clock is sent to post dividers..
\r
16616 * 0b1..PLL input clock is sent to post dividers..
\r
16618 #define SYSCON_USBPLLCTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_BYPASS_SHIFT)) & SYSCON_USBPLLCTRL_BYPASS_MASK)
\r
16619 #define SYSCON_USBPLLCTRL_FBSEL_MASK (0x4000U)
\r
16620 #define SYSCON_USBPLLCTRL_FBSEL_SHIFT (14U)
\r
16621 /*! FBSEL - Feedback divider input clock control.
\r
16623 #define SYSCON_USBPLLCTRL_FBSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_FBSEL_SHIFT)) & SYSCON_USBPLLCTRL_FBSEL_MASK)
\r
16626 /*! @name USBPLLSTAT - USB PLL status */
\r
16628 #define SYSCON_USBPLLSTAT_LOCK_MASK (0x1U)
\r
16629 #define SYSCON_USBPLLSTAT_LOCK_SHIFT (0U)
\r
16630 /*! LOCK - USBPLL lock indicator.
\r
16632 #define SYSCON_USBPLLSTAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLSTAT_LOCK_SHIFT)) & SYSCON_USBPLLSTAT_LOCK_MASK)
\r
16635 /*! @name SYSPLLCTRL - System PLL control */
\r
16637 #define SYSCON_SYSPLLCTRL_SELR_MASK (0xFU)
\r
16638 #define SYSCON_SYSPLLCTRL_SELR_SHIFT (0U)
\r
16639 /*! SELR - Bandwidth select R value.
\r
16641 #define SYSCON_SYSPLLCTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELR_SHIFT)) & SYSCON_SYSPLLCTRL_SELR_MASK)
\r
16642 #define SYSCON_SYSPLLCTRL_SELI_MASK (0x3F0U)
\r
16643 #define SYSCON_SYSPLLCTRL_SELI_SHIFT (4U)
\r
16644 /*! SELI - Bandwidth select I value.
\r
16646 #define SYSCON_SYSPLLCTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELI_SHIFT)) & SYSCON_SYSPLLCTRL_SELI_MASK)
\r
16647 #define SYSCON_SYSPLLCTRL_SELP_MASK (0x7C00U)
\r
16648 #define SYSCON_SYSPLLCTRL_SELP_SHIFT (10U)
\r
16649 /*! SELP - Bandwidth select P value.
\r
16651 #define SYSCON_SYSPLLCTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELP_SHIFT)) & SYSCON_SYSPLLCTRL_SELP_MASK)
\r
16652 #define SYSCON_SYSPLLCTRL_BYPASS_MASK (0x8000U)
\r
16653 #define SYSCON_SYSPLLCTRL_BYPASS_SHIFT (15U)
\r
16654 /*! BYPASS - PLL bypass control.
\r
16655 * 0b0..Bypass disabled. PLL CCO is sent to the PLL post-dividers.
\r
16656 * 0b1..Bypass enabled. PLL input clock is sent directly to the PLL output (default).
\r
16658 #define SYSCON_SYSPLLCTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_BYPASS_SHIFT)) & SYSCON_SYSPLLCTRL_BYPASS_MASK)
\r
16659 #define SYSCON_SYSPLLCTRL_UPLIMOFF_MASK (0x20000U)
\r
16660 #define SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT (17U)
\r
16661 /*! UPLIMOFF - Disable upper frequency limiter.
\r
16663 #define SYSCON_SYSPLLCTRL_UPLIMOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT)) & SYSCON_SYSPLLCTRL_UPLIMOFF_MASK)
\r
16664 #define SYSCON_SYSPLLCTRL_DIRECTI_MASK (0x80000U)
\r
16665 #define SYSCON_SYSPLLCTRL_DIRECTI_SHIFT (19U)
\r
16666 /*! DIRECTI - PLL0 direct input enable.
\r
16668 #define SYSCON_SYSPLLCTRL_DIRECTI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT)) & SYSCON_SYSPLLCTRL_DIRECTI_MASK)
\r
16669 #define SYSCON_SYSPLLCTRL_DIRECTO_MASK (0x100000U)
\r
16670 #define SYSCON_SYSPLLCTRL_DIRECTO_SHIFT (20U)
\r
16671 /*! DIRECTO - PLL0 direct output enable.
\r
16672 * 0b0..Disabled. The PLL output divider (P divider) is used to create the PLL output.
\r
16673 * 0b1..Enabled. The PLL output divider (P divider) is bypassed, the PLL CCO output is used as the PLL output.
\r
16675 #define SYSCON_SYSPLLCTRL_DIRECTO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_DIRECTO_SHIFT)) & SYSCON_SYSPLLCTRL_DIRECTO_MASK)
\r
16678 /*! @name SYSPLLSTAT - PLL status */
\r
16680 #define SYSCON_SYSPLLSTAT_LOCK_MASK (0x1U)
\r
16681 #define SYSCON_SYSPLLSTAT_LOCK_SHIFT (0U)
\r
16682 /*! LOCK - PLL lock indicator.
\r
16684 #define SYSCON_SYSPLLSTAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSTAT_LOCK_SHIFT)) & SYSCON_SYSPLLSTAT_LOCK_MASK)
\r
16687 /*! @name SYSPLLNDEC - PLL N divider */
\r
16689 #define SYSCON_SYSPLLNDEC_NDEC_MASK (0x3FFU)
\r
16690 #define SYSCON_SYSPLLNDEC_NDEC_SHIFT (0U)
\r
16691 /*! NDEC - Decoded N-divider coefficient value.
\r
16693 #define SYSCON_SYSPLLNDEC_NDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NDEC_SHIFT)) & SYSCON_SYSPLLNDEC_NDEC_MASK)
\r
16694 #define SYSCON_SYSPLLNDEC_NREQ_MASK (0x400U)
\r
16695 #define SYSCON_SYSPLLNDEC_NREQ_SHIFT (10U)
\r
16696 /*! NREQ - NDEC reload request.
\r
16698 #define SYSCON_SYSPLLNDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NREQ_SHIFT)) & SYSCON_SYSPLLNDEC_NREQ_MASK)
\r
16701 /*! @name SYSPLLPDEC - PLL P divider */
\r
16703 #define SYSCON_SYSPLLPDEC_PDEC_MASK (0x7FU)
\r
16704 #define SYSCON_SYSPLLPDEC_PDEC_SHIFT (0U)
\r
16705 /*! PDEC - Decoded P-divider coefficient value.
\r
16707 #define SYSCON_SYSPLLPDEC_PDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PDEC_SHIFT)) & SYSCON_SYSPLLPDEC_PDEC_MASK)
\r
16708 #define SYSCON_SYSPLLPDEC_PREQ_MASK (0x80U)
\r
16709 #define SYSCON_SYSPLLPDEC_PREQ_SHIFT (7U)
\r
16712 #define SYSCON_SYSPLLPDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PREQ_SHIFT)) & SYSCON_SYSPLLPDEC_PREQ_MASK)
\r
16715 /*! @name SYSPLLMDEC - System PLL M divider */
\r
16717 #define SYSCON_SYSPLLMDEC_MDEC_MASK (0x1FFFFU)
\r
16718 #define SYSCON_SYSPLLMDEC_MDEC_SHIFT (0U)
\r
16719 /*! MDEC - Decoded M-divider coefficient value.
\r
16721 #define SYSCON_SYSPLLMDEC_MDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLMDEC_MDEC_SHIFT)) & SYSCON_SYSPLLMDEC_MDEC_MASK)
\r
16722 #define SYSCON_SYSPLLMDEC_MREQ_MASK (0x20000U)
\r
16723 #define SYSCON_SYSPLLMDEC_MREQ_SHIFT (17U)
\r
16724 /*! MREQ - MDEC reload request.
\r
16726 #define SYSCON_SYSPLLMDEC_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLMDEC_MREQ_SHIFT)) & SYSCON_SYSPLLMDEC_MREQ_MASK)
\r
16729 /*! @name AUDPLLCTRL - Audio PLL control */
\r
16731 #define SYSCON_AUDPLLCTRL_SELR_MASK (0xFU)
\r
16732 #define SYSCON_AUDPLLCTRL_SELR_SHIFT (0U)
\r
16733 /*! SELR - Bandwidth select R value.
\r
16735 #define SYSCON_AUDPLLCTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_SELR_SHIFT)) & SYSCON_AUDPLLCTRL_SELR_MASK)
\r
16736 #define SYSCON_AUDPLLCTRL_SELI_MASK (0x3F0U)
\r
16737 #define SYSCON_AUDPLLCTRL_SELI_SHIFT (4U)
\r
16738 /*! SELI - Bandwidth select I value.
\r
16740 #define SYSCON_AUDPLLCTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_SELI_SHIFT)) & SYSCON_AUDPLLCTRL_SELI_MASK)
\r
16741 #define SYSCON_AUDPLLCTRL_SELP_MASK (0x7C00U)
\r
16742 #define SYSCON_AUDPLLCTRL_SELP_SHIFT (10U)
\r
16745 #define SYSCON_AUDPLLCTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_SELP_SHIFT)) & SYSCON_AUDPLLCTRL_SELP_MASK)
\r
16746 #define SYSCON_AUDPLLCTRL_BYPASS_MASK (0x8000U)
\r
16747 #define SYSCON_AUDPLLCTRL_BYPASS_SHIFT (15U)
\r
16748 /*! BYPASS - PLL bypass control.
\r
16749 * 0b0..Bypass disabled. PLL CCO is sent to the PLL post-dividers.
\r
16750 * 0b1..Bypass enabled. PLL input clock is sent directly to the PLL output (default).
\r
16752 #define SYSCON_AUDPLLCTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_BYPASS_SHIFT)) & SYSCON_AUDPLLCTRL_BYPASS_MASK)
\r
16753 #define SYSCON_AUDPLLCTRL_UPLIMOFF_MASK (0x20000U)
\r
16754 #define SYSCON_AUDPLLCTRL_UPLIMOFF_SHIFT (17U)
\r
16755 /*! UPLIMOFF - Disable upper frequency limiter.
\r
16757 #define SYSCON_AUDPLLCTRL_UPLIMOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_UPLIMOFF_SHIFT)) & SYSCON_AUDPLLCTRL_UPLIMOFF_MASK)
\r
16758 #define SYSCON_AUDPLLCTRL_DIRECTI_MASK (0x80000U)
\r
16759 #define SYSCON_AUDPLLCTRL_DIRECTI_SHIFT (19U)
\r
16760 /*! DIRECTI - PLL direct input enable.
\r
16762 #define SYSCON_AUDPLLCTRL_DIRECTI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_DIRECTI_SHIFT)) & SYSCON_AUDPLLCTRL_DIRECTI_MASK)
\r
16763 #define SYSCON_AUDPLLCTRL_DIRECTO_MASK (0x100000U)
\r
16764 #define SYSCON_AUDPLLCTRL_DIRECTO_SHIFT (20U)
\r
16765 /*! DIRECTO - PLL direct output enable
\r
16766 * 0b0..Disabled. The PLL output divider (P divider) is used to create the PLL output.
\r
16767 * 0b1..Enabled. The PLL output divider (P divider) is bypassed, the PLL CCO output is used as the PLL output.
\r
16769 #define SYSCON_AUDPLLCTRL_DIRECTO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_DIRECTO_SHIFT)) & SYSCON_AUDPLLCTRL_DIRECTO_MASK)
\r
16772 /*! @name AUDPLLSTAT - Audio PLL status */
\r
16774 #define SYSCON_AUDPLLSTAT_LOCK_MASK (0x1U)
\r
16775 #define SYSCON_AUDPLLSTAT_LOCK_SHIFT (0U)
\r
16776 /*! LOCK - PLL lock indicator.
\r
16778 #define SYSCON_AUDPLLSTAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLSTAT_LOCK_SHIFT)) & SYSCON_AUDPLLSTAT_LOCK_MASK)
\r
16781 /*! @name AUDPLLNDEC - Audio PLL N divider */
\r
16783 #define SYSCON_AUDPLLNDEC_NDEC_MASK (0x3FFU)
\r
16784 #define SYSCON_AUDPLLNDEC_NDEC_SHIFT (0U)
\r
16785 /*! NDEC - Decoded N-divider coefficient value.
\r
16787 #define SYSCON_AUDPLLNDEC_NDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLNDEC_NDEC_SHIFT)) & SYSCON_AUDPLLNDEC_NDEC_MASK)
\r
16788 #define SYSCON_AUDPLLNDEC_NREQ_MASK (0x400U)
\r
16789 #define SYSCON_AUDPLLNDEC_NREQ_SHIFT (10U)
\r
16790 /*! NREQ - NDEC reload request.
\r
16792 #define SYSCON_AUDPLLNDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLNDEC_NREQ_SHIFT)) & SYSCON_AUDPLLNDEC_NREQ_MASK)
\r
16795 /*! @name AUDPLLPDEC - Audio PLL P divider */
\r
16797 #define SYSCON_AUDPLLPDEC_PDEC_MASK (0x7FU)
\r
16798 #define SYSCON_AUDPLLPDEC_PDEC_SHIFT (0U)
\r
16799 /*! PDEC - Decoded P-divider coefficient value.
\r
16801 #define SYSCON_AUDPLLPDEC_PDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLPDEC_PDEC_SHIFT)) & SYSCON_AUDPLLPDEC_PDEC_MASK)
\r
16802 #define SYSCON_AUDPLLPDEC_PREQ_MASK (0x80U)
\r
16803 #define SYSCON_AUDPLLPDEC_PREQ_SHIFT (7U)
\r
16804 /*! PREQ - PDEC reload request.
\r
16806 #define SYSCON_AUDPLLPDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLPDEC_PREQ_SHIFT)) & SYSCON_AUDPLLPDEC_PREQ_MASK)
\r
16809 /*! @name AUDPLLMDEC - Audio PLL M divider */
\r
16811 #define SYSCON_AUDPLLMDEC_MDEC_MASK (0x1FFFFU)
\r
16812 #define SYSCON_AUDPLLMDEC_MDEC_SHIFT (0U)
\r
16813 /*! MDEC - Decoded M-divider coefficient value.
\r
16815 #define SYSCON_AUDPLLMDEC_MDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLMDEC_MDEC_SHIFT)) & SYSCON_AUDPLLMDEC_MDEC_MASK)
\r
16816 #define SYSCON_AUDPLLMDEC_MREQ_MASK (0x20000U)
\r
16817 #define SYSCON_AUDPLLMDEC_MREQ_SHIFT (17U)
\r
16818 /*! MREQ - MDEC reload request.
\r
16820 #define SYSCON_AUDPLLMDEC_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLMDEC_MREQ_SHIFT)) & SYSCON_AUDPLLMDEC_MREQ_MASK)
\r
16823 /*! @name AUDPLLFRAC - Audio PLL fractional divider control */
\r
16825 #define SYSCON_AUDPLLFRAC_CTRL_MASK (0x3FFFFFU)
\r
16826 #define SYSCON_AUDPLLFRAC_CTRL_SHIFT (0U)
\r
16827 /*! CTRL - PLL fractional divider control word
\r
16829 #define SYSCON_AUDPLLFRAC_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLFRAC_CTRL_SHIFT)) & SYSCON_AUDPLLFRAC_CTRL_MASK)
\r
16830 #define SYSCON_AUDPLLFRAC_REQ_MASK (0x400000U)
\r
16831 #define SYSCON_AUDPLLFRAC_REQ_SHIFT (22U)
\r
16832 /*! REQ - Writing 1 to REQ signal loads CTRL value into fractional wrapper modulator.
\r
16834 #define SYSCON_AUDPLLFRAC_REQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLFRAC_REQ_SHIFT)) & SYSCON_AUDPLLFRAC_REQ_MASK)
\r
16835 #define SYSCON_AUDPLLFRAC_SEL_EXT_MASK (0x800000U)
\r
16836 #define SYSCON_AUDPLLFRAC_SEL_EXT_SHIFT (23U)
\r
16837 /*! SEL_EXT - Select fractional divider.
\r
16839 #define SYSCON_AUDPLLFRAC_SEL_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLFRAC_SEL_EXT_SHIFT)) & SYSCON_AUDPLLFRAC_SEL_EXT_MASK)
\r
16842 /*! @name PDSLEEPCFG - Sleep configuration register */
\r
16844 #define SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_MASK (0x1U)
\r
16845 #define SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_SHIFT (0U)
\r
16846 /*! PDEN_USB1_PHY - USB1 high speed PHY (also, enable/disable bit 28 in PDRUNCFG0 register).
\r
16848 #define SYSCON_PDSLEEPCFG_PDEN_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_MASK)
\r
16849 #define SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_MASK (0x2U)
\r
16850 #define SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_SHIFT (1U)
\r
16851 /*! PDEN_USB1_PLL - USB PLL (PLL1) power (also, enable/disable bit 26 in PDRUNCFG0 register).
\r
16853 #define SYSCON_PDSLEEPCFG_PDEN_USB1_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_MASK)
\r
16854 #define SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_MASK (0x4U)
\r
16855 #define SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_SHIFT (2U)
\r
16856 /*! PDEN_AUD_PLL - Audio PLL (PLL2) power and fractional divider (also, enable/disable bit 26 in PDRUNCFG0 register).
\r
16858 #define SYSCON_PDSLEEPCFG_PDEN_AUD_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_MASK)
\r
16859 #define SYSCON_PDSLEEPCFG_PDEN_SYSOSC_MASK (0x8U)
\r
16860 #define SYSCON_PDSLEEPCFG_PDEN_SYSOSC_SHIFT (3U)
\r
16861 /*! PDEN_SYSOSC - System Oscillator Power (also, enable/disable bit 9 in PDRUNCFG0 register).
\r
16863 #define SYSCON_PDSLEEPCFG_PDEN_SYSOSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SYSOSC_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SYSOSC_MASK)
\r
16864 #define SYSCON_PDSLEEPCFG_PDEN_FRO_MASK (0x10U)
\r
16865 #define SYSCON_PDSLEEPCFG_PDEN_FRO_SHIFT (4U)
\r
16866 /*! PDEN_FRO - FRO oscillator.
\r
16868 #define SYSCON_PDSLEEPCFG_PDEN_FRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_FRO_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_FRO_MASK)
\r
16869 #define SYSCON_PDSLEEPCFG_PDEN_TS_MASK (0x40U)
\r
16870 #define SYSCON_PDSLEEPCFG_PDEN_TS_SHIFT (6U)
\r
16871 /*! PDEN_TS - Temp sensor.
\r
16873 #define SYSCON_PDSLEEPCFG_PDEN_TS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_TS_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_TS_MASK)
\r
16874 #define SYSCON_PDSLEEPCFG_PDEN_BOD_RST_MASK (0x80U)
\r
16875 #define SYSCON_PDSLEEPCFG_PDEN_BOD_RST_SHIFT (7U)
\r
16876 /*! PDEN_BOD_RST - Brown-out Detect reset.
\r
16878 #define SYSCON_PDSLEEPCFG_PDEN_BOD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_BOD_RST_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_BOD_RST_MASK)
\r
16879 #define SYSCON_PDSLEEPCFG_PDEN_RNG_MASK (0x80U)
\r
16880 #define SYSCON_PDSLEEPCFG_PDEN_RNG_SHIFT (7U)
\r
16881 /*! PDEN_RNG - Random Number Generator Power.
\r
16883 #define SYSCON_PDSLEEPCFG_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_RNG_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_RNG_MASK)
\r
16884 #define SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_MASK (0x100U)
\r
16885 #define SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_SHIFT (8U)
\r
16886 /*! PDEN_BOD_INTR - Brown-out Detect interrupt.
\r
16888 #define SYSCON_PDSLEEPCFG_PDEN_BOD_INTR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_MASK)
\r
16889 #define SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_MASK (0x200U)
\r
16890 #define SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_SHIFT (9U)
\r
16891 /*! PDEN_VD2_ANA - Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1
\r
16892 * register), Temperature Sensor (also, enable/disable bit 6), ADC (also, enable/disable bits 10, 19,
\r
16895 #define SYSCON_PDSLEEPCFG_PDEN_VD2_ANA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_MASK)
\r
16896 #define SYSCON_PDSLEEPCFG_PDEN_ADC0_MASK (0x400U)
\r
16897 #define SYSCON_PDSLEEPCFG_PDEN_ADC0_SHIFT (10U)
\r
16898 /*! PDEN_ADC0 - ADC power.
\r
16900 #define SYSCON_PDSLEEPCFG_PDEN_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_ADC0_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_ADC0_MASK)
\r
16901 #define SYSCON_PDSLEEPCFG_PDEN_SRAMX_MASK (0x2000U)
\r
16902 #define SYSCON_PDSLEEPCFG_PDEN_SRAMX_SHIFT (13U)
\r
16903 /*! PDEN_SRAMX - PDEN_SRAMX controls SRAMX (also enable/disable bit 27).
\r
16905 #define SYSCON_PDSLEEPCFG_PDEN_SRAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SRAMX_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SRAMX_MASK)
\r
16906 #define SYSCON_PDSLEEPCFG_PDEN_SRAM0_MASK (0x4000U)
\r
16907 #define SYSCON_PDSLEEPCFG_PDEN_SRAM0_SHIFT (14U)
\r
16908 /*! PDEN_SRAM0 - PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27).
\r
16910 #define SYSCON_PDSLEEPCFG_PDEN_SRAM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SRAM0_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SRAM0_MASK)
\r
16911 #define SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_MASK (0x8000U)
\r
16912 #define SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_SHIFT (15U)
\r
16913 /*! PDEN_SRAM1_2_3 - PDEN_SRAM1_2_3 controls SRAM1, SRAM2, and SRAM3 (also enable/disable bit 27).
\r
16915 #define SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_MASK)
\r
16916 #define SYSCON_PDSLEEPCFG_PDEN_USB_RAM_MASK (0x10000U)
\r
16917 #define SYSCON_PDSLEEPCFG_PDEN_USB_RAM_SHIFT (16U)
\r
16918 /*! PDEN_USB_RAM - PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27).
\r
16920 #define SYSCON_PDSLEEPCFG_PDEN_USB_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB_RAM_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB_RAM_MASK)
\r
16921 #define SYSCON_PDSLEEPCFG_PDEN_ROM_MASK (0x20000U)
\r
16922 #define SYSCON_PDSLEEPCFG_PDEN_ROM_SHIFT (17U)
\r
16923 /*! PDEN_ROM - ROM (also enable/disable bit 27).
\r
16925 #define SYSCON_PDSLEEPCFG_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_ROM_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_ROM_MASK)
\r
16926 #define SYSCON_PDSLEEPCFG_PDEN_VDDA_MASK (0x80000U)
\r
16927 #define SYSCON_PDSLEEPCFG_PDEN_VDDA_SHIFT (19U)
\r
16928 /*! PDEN_VDDA - Vdda to the ADC, must be enabled for the ADC to work (also enable/disable bit 9, 10, and 23).
\r
16930 #define SYSCON_PDSLEEPCFG_PDEN_VDDA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VDDA_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VDDA_MASK)
\r
16931 #define SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_MASK (0x100000U)
\r
16932 #define SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_SHIFT (20U)
\r
16933 /*! PDEN_WDT_OSC - Watchdog oscillator.
\r
16935 #define SYSCON_PDSLEEPCFG_PDEN_WDT_OSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_MASK)
\r
16936 #define SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_MASK (0x200000U)
\r
16937 #define SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_SHIFT (21U)
\r
16938 /*! PDEN_USB0_PHY - USB0 PHY power (also enable/disable bit 28).
\r
16940 #define SYSCON_PDSLEEPCFG_PDEN_USB0_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_MASK)
\r
16941 #define SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_MASK (0x400000U)
\r
16942 #define SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_SHIFT (22U)
\r
16943 /*! PDEN_SYS_PLL - System PLL (PLL0) power (also enable/disable bit 26).
\r
16945 #define SYSCON_PDSLEEPCFG_PDEN_SYS_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_MASK)
\r
16946 #define SYSCON_PDSLEEPCFG_PDEN_VREFP_MASK (0x800000U)
\r
16947 #define SYSCON_PDSLEEPCFG_PDEN_VREFP_SHIFT (23U)
\r
16948 /*! PDEN_VREFP - VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9, 10, and 19).
\r
16950 #define SYSCON_PDSLEEPCFG_PDEN_VREFP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VREFP_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VREFP_MASK)
\r
16951 #define SYSCON_PDSLEEPCFG_PDEN_VD3_MASK (0x4000000U)
\r
16952 #define SYSCON_PDSLEEPCFG_PDEN_VD3_SHIFT (26U)
\r
16953 /*! PDEN_VD3 - Power control for all PLLs.
\r
16955 #define SYSCON_PDSLEEPCFG_PDEN_VD3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD3_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD3_MASK)
\r
16956 #define SYSCON_PDSLEEPCFG_PDEN_VD4_MASK (0x8000000U)
\r
16957 #define SYSCON_PDSLEEPCFG_PDEN_VD4_SHIFT (27U)
\r
16958 /*! PDEN_VD4 - Power control for all SRAMs and ROM.
\r
16960 #define SYSCON_PDSLEEPCFG_PDEN_VD4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD4_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD4_MASK)
\r
16961 #define SYSCON_PDSLEEPCFG_PDEN_VD5_MASK (0x10000000U)
\r
16962 #define SYSCON_PDSLEEPCFG_PDEN_VD5_SHIFT (28U)
\r
16963 /*! PDEN_VD5 - Power control both USB0 PHY and USB1 PHY.
\r
16965 #define SYSCON_PDSLEEPCFG_PDEN_VD5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD5_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD5_MASK)
\r
16966 #define SYSCON_PDSLEEPCFG_PDEN_VD6_MASK (0x20000000U)
\r
16967 #define SYSCON_PDSLEEPCFG_PDEN_VD6_SHIFT (29U)
\r
16968 /*! PDEN_VD6 - Power control for EEPROM.
\r
16970 #define SYSCON_PDSLEEPCFG_PDEN_VD6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD6_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD6_MASK)
\r
16973 /* The count of SYSCON_PDSLEEPCFG */
\r
16974 #define SYSCON_PDSLEEPCFG_COUNT (2U)
\r
16976 /*! @name PDRUNCFG - Power configuration register */
\r
16978 #define SYSCON_PDRUNCFG_PDEN_USB1_PHY_MASK (0x1U)
\r
16979 #define SYSCON_PDRUNCFG_PDEN_USB1_PHY_SHIFT (0U)
\r
16980 /*! PDEN_USB1_PHY - USB1 high speed PHY (also, enable/disable bit 28 in PDRUNCFG0 register).
\r
16982 #define SYSCON_PDRUNCFG_PDEN_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB1_PHY_MASK)
\r
16983 #define SYSCON_PDRUNCFG_PDEN_USB1_PLL_MASK (0x2U)
\r
16984 #define SYSCON_PDRUNCFG_PDEN_USB1_PLL_SHIFT (1U)
\r
16985 /*! PDEN_USB1_PLL - USB PLL (PLL1) power (also, enable/disable bit 26 in PDRUNCFG0 register).
\r
16987 #define SYSCON_PDRUNCFG_PDEN_USB1_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB1_PLL_MASK)
\r
16988 #define SYSCON_PDRUNCFG_PDEN_AUD_PLL_MASK (0x4U)
\r
16989 #define SYSCON_PDRUNCFG_PDEN_AUD_PLL_SHIFT (2U)
\r
16990 /*! PDEN_AUD_PLL - Audio PLL (PLL2) power and fractional divider (also, enable/disable bit 26 in PDRUNCFG0 register).
\r
16992 #define SYSCON_PDRUNCFG_PDEN_AUD_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_AUD_PLL_MASK)
\r
16993 #define SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK (0x8U)
\r
16994 #define SYSCON_PDRUNCFG_PDEN_SYSOSC_SHIFT (3U)
\r
16995 /*! PDEN_SYSOSC - System Oscillator Power (also, enable/disable bit 9 in PDRUNCFG0 register).
\r
16997 #define SYSCON_PDRUNCFG_PDEN_SYSOSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SYSOSC_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK)
\r
16998 #define SYSCON_PDRUNCFG_PDEN_FRO_MASK (0x10U)
\r
16999 #define SYSCON_PDRUNCFG_PDEN_FRO_SHIFT (4U)
\r
17000 /*! PDEN_FRO - FRO oscillator.
\r
17002 #define SYSCON_PDRUNCFG_PDEN_FRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFG_PDEN_FRO_MASK)
\r
17003 #define SYSCON_PDRUNCFG_PDEN_TS_MASK (0x40U)
\r
17004 #define SYSCON_PDRUNCFG_PDEN_TS_SHIFT (6U)
\r
17005 /*! PDEN_TS - Temp sensor.
\r
17007 #define SYSCON_PDRUNCFG_PDEN_TS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_TS_SHIFT)) & SYSCON_PDRUNCFG_PDEN_TS_MASK)
\r
17008 #define SYSCON_PDRUNCFG_PDEN_BOD_RST_MASK (0x80U)
\r
17009 #define SYSCON_PDRUNCFG_PDEN_BOD_RST_SHIFT (7U)
\r
17010 /*! PDEN_BOD_RST - Brown-out Detect reset.
\r
17012 #define SYSCON_PDRUNCFG_PDEN_BOD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_BOD_RST_SHIFT)) & SYSCON_PDRUNCFG_PDEN_BOD_RST_MASK)
\r
17013 #define SYSCON_PDRUNCFG_PDEN_RNG_MASK (0x80U)
\r
17014 #define SYSCON_PDRUNCFG_PDEN_RNG_SHIFT (7U)
\r
17015 /*! PDEN_RNG - Random Number Generator Power.
\r
17017 #define SYSCON_PDRUNCFG_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_RNG_SHIFT)) & SYSCON_PDRUNCFG_PDEN_RNG_MASK)
\r
17018 #define SYSCON_PDRUNCFG_PDEN_BOD_INTR_MASK (0x100U)
\r
17019 #define SYSCON_PDRUNCFG_PDEN_BOD_INTR_SHIFT (8U)
\r
17020 /*! PDEN_BOD_INTR - Brown-out Detect interrupt.
\r
17022 #define SYSCON_PDRUNCFG_PDEN_BOD_INTR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDRUNCFG_PDEN_BOD_INTR_MASK)
\r
17023 #define SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK (0x200U)
\r
17024 #define SYSCON_PDRUNCFG_PDEN_VD2_ANA_SHIFT (9U)
\r
17025 /*! PDEN_VD2_ANA - Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1
\r
17026 * register), Temperature Sensor (also, enable/disable bit 6), ADC (also, enable/disable bits 10, 19,
\r
17029 #define SYSCON_PDRUNCFG_PDEN_VD2_ANA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK)
\r
17030 #define SYSCON_PDRUNCFG_PDEN_ADC0_MASK (0x400U)
\r
17031 #define SYSCON_PDRUNCFG_PDEN_ADC0_SHIFT (10U)
\r
17032 /*! PDEN_ADC0 - ADC power.
\r
17034 #define SYSCON_PDRUNCFG_PDEN_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_ADC0_SHIFT)) & SYSCON_PDRUNCFG_PDEN_ADC0_MASK)
\r
17035 #define SYSCON_PDRUNCFG_PDEN_SRAMX_MASK (0x2000U)
\r
17036 #define SYSCON_PDRUNCFG_PDEN_SRAMX_SHIFT (13U)
\r
17037 /*! PDEN_SRAMX - PPDEN_SRAMX controls only SRAMX address 0x0 to 0x0000FFFF.Bit 29 (PDEN_VD6)
\r
17038 * controls SRAMX address 0x00010000 to 0x0002FFFF..
\r
17040 #define SYSCON_PDRUNCFG_PDEN_SRAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAMX_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAMX_MASK)
\r
17041 #define SYSCON_PDRUNCFG_PDEN_SRAM0_MASK (0x4000U)
\r
17042 #define SYSCON_PDRUNCFG_PDEN_SRAM0_SHIFT (14U)
\r
17043 /*! PDEN_SRAM0 - PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27).
\r
17045 #define SYSCON_PDRUNCFG_PDEN_SRAM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM0_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM0_MASK)
\r
17046 #define SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_MASK (0x8000U)
\r
17047 #define SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_SHIFT (15U)
\r
17048 /*! PDEN_SRAM1_2_3 - PDEN_SRAM1_2_3 controls SRAM1, SRAM2, and SRAM3 (also enable/disable bit 27).
\r
17050 #define SYSCON_PDRUNCFG_PDEN_SRAM1_2_3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_MASK)
\r
17051 #define SYSCON_PDRUNCFG_PDEN_USB_RAM_MASK (0x10000U)
\r
17052 #define SYSCON_PDRUNCFG_PDEN_USB_RAM_SHIFT (16U)
\r
17053 /*! PDEN_USB_RAM - PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27).
\r
17055 #define SYSCON_PDRUNCFG_PDEN_USB_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB_RAM_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB_RAM_MASK)
\r
17056 #define SYSCON_PDRUNCFG_PDEN_ROM_MASK (0x20000U)
\r
17057 #define SYSCON_PDRUNCFG_PDEN_ROM_SHIFT (17U)
\r
17058 /*! PDEN_ROM - ROM (also enable/disable bit 27).
\r
17060 #define SYSCON_PDRUNCFG_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_ROM_SHIFT)) & SYSCON_PDRUNCFG_PDEN_ROM_MASK)
\r
17061 #define SYSCON_PDRUNCFG_PDEN_VDDA_MASK (0x80000U)
\r
17062 #define SYSCON_PDRUNCFG_PDEN_VDDA_SHIFT (19U)
\r
17063 /*! PDEN_VDDA - Vdda to the ADC, must be enabled for the ADC to work (also enable/disable bit 9, 10, and 23).
\r
17065 #define SYSCON_PDRUNCFG_PDEN_VDDA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VDDA_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VDDA_MASK)
\r
17066 #define SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK (0x100000U)
\r
17067 #define SYSCON_PDRUNCFG_PDEN_WDT_OSC_SHIFT (20U)
\r
17068 /*! PDEN_WDT_OSC - Watchdog oscillator.
\r
17070 #define SYSCON_PDRUNCFG_PDEN_WDT_OSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK)
\r
17071 #define SYSCON_PDRUNCFG_PDEN_USB0_PHY_MASK (0x200000U)
\r
17072 #define SYSCON_PDRUNCFG_PDEN_USB0_PHY_SHIFT (21U)
\r
17073 /*! PDEN_USB0_PHY - USB0 PHY power (also enable/disable bit 28).
\r
17075 #define SYSCON_PDRUNCFG_PDEN_USB0_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB0_PHY_MASK)
\r
17076 #define SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK (0x400000U)
\r
17077 #define SYSCON_PDRUNCFG_PDEN_SYS_PLL_SHIFT (22U)
\r
17078 /*! PDEN_SYS_PLL - System PLL (PLL0) power (also enable/disable bit 26).
\r
17080 #define SYSCON_PDRUNCFG_PDEN_SYS_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK)
\r
17081 #define SYSCON_PDRUNCFG_PDEN_VREFP_MASK (0x800000U)
\r
17082 #define SYSCON_PDRUNCFG_PDEN_VREFP_SHIFT (23U)
\r
17083 /*! PDEN_VREFP - VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9, 10, and 19).
\r
17085 #define SYSCON_PDRUNCFG_PDEN_VREFP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VREFP_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VREFP_MASK)
\r
17086 #define SYSCON_PDRUNCFG_PDEN_VD3_MASK (0x4000000U)
\r
17087 #define SYSCON_PDRUNCFG_PDEN_VD3_SHIFT (26U)
\r
17088 /*! PDEN_VD3 - Power control for all PLLs.
\r
17090 #define SYSCON_PDRUNCFG_PDEN_VD3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD3_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD3_MASK)
\r
17091 #define SYSCON_PDRUNCFG_PDEN_VD4_MASK (0x8000000U)
\r
17092 #define SYSCON_PDRUNCFG_PDEN_VD4_SHIFT (27U)
\r
17093 /*! PDEN_VD4 - Power control for all SRAMs and ROM.
\r
17095 #define SYSCON_PDRUNCFG_PDEN_VD4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD4_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD4_MASK)
\r
17096 #define SYSCON_PDRUNCFG_PDEN_VD5_MASK (0x10000000U)
\r
17097 #define SYSCON_PDRUNCFG_PDEN_VD5_SHIFT (28U)
\r
17098 /*! PDEN_VD5 - Power control both USB0 PHY and USB1 PHY.
\r
17100 #define SYSCON_PDRUNCFG_PDEN_VD5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD5_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD5_MASK)
\r
17101 #define SYSCON_PDRUNCFG_PDEN_VD6_MASK (0x20000000U)
\r
17102 #define SYSCON_PDRUNCFG_PDEN_VD6_SHIFT (29U)
\r
17103 /*! PDEN_VD6 - Power control for OTP and SRAMX from address 0x00010000 to 0x0002FFFF.
\r
17105 #define SYSCON_PDRUNCFG_PDEN_VD6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD6_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD6_MASK)
\r
17108 /* The count of SYSCON_PDRUNCFG */
\r
17109 #define SYSCON_PDRUNCFG_COUNT (2U)
\r
17111 /*! @name PDRUNCFGSET - Power configuration set register */
\r
17113 #define SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_MASK (0x1U)
\r
17114 #define SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_SHIFT (0U)
\r
17115 /*! PDEN_USB1_PHY - USB1 high speed PHY (also, enable/disable bit 28 in PDRUNCFG0 register).
\r
17117 #define SYSCON_PDRUNCFGSET_PDEN_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_MASK)
\r
17118 #define SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_MASK (0x2U)
\r
17119 #define SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_SHIFT (1U)
\r
17120 /*! PDEN_USB1_PLL - USB PLL (PLL1) power (also, enable/disable bit 26 in PDRUNCFG0 register).
\r
17122 #define SYSCON_PDRUNCFGSET_PDEN_USB1_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_MASK)
\r
17123 #define SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_MASK (0x4U)
\r
17124 #define SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_SHIFT (2U)
\r
17125 /*! PDEN_AUD_PLL - Audio PLL (PLL2) power and fractional divider (also, enable/disable bit 26 in PDRUNCFG0 register).
\r
17127 #define SYSCON_PDRUNCFGSET_PDEN_AUD_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_MASK)
\r
17128 #define SYSCON_PDRUNCFGSET_PDEN_SYSOSC_MASK (0x8U)
\r
17129 #define SYSCON_PDRUNCFGSET_PDEN_SYSOSC_SHIFT (3U)
\r
17130 /*! PDEN_SYSOSC - System Oscillator Power (also, enable/disable bit 9 in PDRUNCFG0 register).
\r
17132 #define SYSCON_PDRUNCFGSET_PDEN_SYSOSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SYSOSC_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SYSOSC_MASK)
\r
17133 #define SYSCON_PDRUNCFGSET_PDEN_FRO_MASK (0x10U)
\r
17134 #define SYSCON_PDRUNCFGSET_PDEN_FRO_SHIFT (4U)
\r
17135 /*! PDEN_FRO - FRO oscillator.
\r
17137 #define SYSCON_PDRUNCFGSET_PDEN_FRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_FRO_MASK)
\r
17138 #define SYSCON_PDRUNCFGSET_PDEN_TS_MASK (0x40U)
\r
17139 #define SYSCON_PDRUNCFGSET_PDEN_TS_SHIFT (6U)
\r
17140 /*! PDEN_TS - Temp sensor.
\r
17142 #define SYSCON_PDRUNCFGSET_PDEN_TS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_TS_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_TS_MASK)
\r
17143 #define SYSCON_PDRUNCFGSET_PDEN_BOD_RST_MASK (0x80U)
\r
17144 #define SYSCON_PDRUNCFGSET_PDEN_BOD_RST_SHIFT (7U)
\r
17145 /*! PDEN_BOD_RST - Brown-out Detect reset.
\r
17147 #define SYSCON_PDRUNCFGSET_PDEN_BOD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_BOD_RST_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_BOD_RST_MASK)
\r
17148 #define SYSCON_PDRUNCFGSET_PDEN_RNG_MASK (0x80U)
\r
17149 #define SYSCON_PDRUNCFGSET_PDEN_RNG_SHIFT (7U)
\r
17150 /*! PDEN_RNG - Random Number Generator Power.
\r
17152 #define SYSCON_PDRUNCFGSET_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_RNG_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_RNG_MASK)
\r
17153 #define SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_MASK (0x100U)
\r
17154 #define SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_SHIFT (8U)
\r
17155 /*! PDEN_BOD_INTR - Brown-out Detect interrupt.
\r
17157 #define SYSCON_PDRUNCFGSET_PDEN_BOD_INTR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_MASK)
\r
17158 #define SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_MASK (0x200U)
\r
17159 #define SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_SHIFT (9U)
\r
17160 /*! PDEN_VD2_ANA - Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1
\r
17161 * register), Temperature Sensor (also, enable/disable bit 6), ADC (also, enable/disable bits 10, 19,
\r
17164 #define SYSCON_PDRUNCFGSET_PDEN_VD2_ANA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_MASK)
\r
17165 #define SYSCON_PDRUNCFGSET_PDEN_ADC0_MASK (0x400U)
\r
17166 #define SYSCON_PDRUNCFGSET_PDEN_ADC0_SHIFT (10U)
\r
17167 /*! PDEN_ADC0 - ADC power.
\r
17169 #define SYSCON_PDRUNCFGSET_PDEN_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_ADC0_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_ADC0_MASK)
\r
17170 #define SYSCON_PDRUNCFGSET_PDEN_SRAMX_MASK (0x2000U)
\r
17171 #define SYSCON_PDRUNCFGSET_PDEN_SRAMX_SHIFT (13U)
\r
17172 /*! PDEN_SRAMX - PDEN_SRAMX controls SRAMX (also enable/disable bit 27).
\r
17174 #define SYSCON_PDRUNCFGSET_PDEN_SRAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SRAMX_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SRAMX_MASK)
\r
17175 #define SYSCON_PDRUNCFGSET_PDEN_SRAM0_MASK (0x4000U)
\r
17176 #define SYSCON_PDRUNCFGSET_PDEN_SRAM0_SHIFT (14U)
\r
17177 /*! PDEN_SRAM0 - PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27).
\r
17179 #define SYSCON_PDRUNCFGSET_PDEN_SRAM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SRAM0_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SRAM0_MASK)
\r
17180 #define SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_MASK (0x8000U)
\r
17181 #define SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_SHIFT (15U)
\r
17182 /*! PDEN_SRAM1_2_3 - PDEN_SRAM1_2_3 controls SRAM1, SRAM2, and SRAM3 (also enable/disable bit 27).
\r
17184 #define SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_MASK)
\r
17185 #define SYSCON_PDRUNCFGSET_PDEN_USB_RAM_MASK (0x10000U)
\r
17186 #define SYSCON_PDRUNCFGSET_PDEN_USB_RAM_SHIFT (16U)
\r
17187 /*! PDEN_USB_RAM - PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27).
\r
17189 #define SYSCON_PDRUNCFGSET_PDEN_USB_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB_RAM_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB_RAM_MASK)
\r
17190 #define SYSCON_PDRUNCFGSET_PDEN_ROM_MASK (0x20000U)
\r
17191 #define SYSCON_PDRUNCFGSET_PDEN_ROM_SHIFT (17U)
\r
17192 /*! PDEN_ROM - ROM (also enable/disable bit 27).
\r
17194 #define SYSCON_PDRUNCFGSET_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_ROM_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_ROM_MASK)
\r
17195 #define SYSCON_PDRUNCFGSET_PDEN_VDDA_MASK (0x80000U)
\r
17196 #define SYSCON_PDRUNCFGSET_PDEN_VDDA_SHIFT (19U)
\r
17197 /*! PDEN_VDDA - Vdda to the ADC, must be enabled for the ADC to work (also enable/disable bit 9, 10, and 23).
\r
17199 #define SYSCON_PDRUNCFGSET_PDEN_VDDA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VDDA_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VDDA_MASK)
\r
17200 #define SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_MASK (0x100000U)
\r
17201 #define SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_SHIFT (20U)
\r
17202 /*! PDEN_WDT_OSC - Watchdog oscillator.
\r
17204 #define SYSCON_PDRUNCFGSET_PDEN_WDT_OSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_MASK)
\r
17205 #define SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_MASK (0x200000U)
\r
17206 #define SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_SHIFT (21U)
\r
17207 /*! PDEN_USB0_PHY - USB0 PHY power (also enable/disable bit 28).
\r
17209 #define SYSCON_PDRUNCFGSET_PDEN_USB0_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_MASK)
\r
17210 #define SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_MASK (0x400000U)
\r
17211 #define SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_SHIFT (22U)
\r
17212 /*! PDEN_SYS_PLL - System PLL (PLL0) power (also enable/disable bit 26).
\r
17214 #define SYSCON_PDRUNCFGSET_PDEN_SYS_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_MASK)
\r
17215 #define SYSCON_PDRUNCFGSET_PDEN_VREFP_MASK (0x800000U)
\r
17216 #define SYSCON_PDRUNCFGSET_PDEN_VREFP_SHIFT (23U)
\r
17217 /*! PDEN_VREFP - VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9, 10, and 19).
\r
17219 #define SYSCON_PDRUNCFGSET_PDEN_VREFP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VREFP_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VREFP_MASK)
\r
17220 #define SYSCON_PDRUNCFGSET_PDEN_VD3_MASK (0x4000000U)
\r
17221 #define SYSCON_PDRUNCFGSET_PDEN_VD3_SHIFT (26U)
\r
17222 /*! PDEN_VD3 - Power control for all PLLs.
\r
17224 #define SYSCON_PDRUNCFGSET_PDEN_VD3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD3_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD3_MASK)
\r
17225 #define SYSCON_PDRUNCFGSET_PDEN_VD4_MASK (0x8000000U)
\r
17226 #define SYSCON_PDRUNCFGSET_PDEN_VD4_SHIFT (27U)
\r
17227 /*! PDEN_VD4 - Power control for all SRAMs and ROM.
\r
17229 #define SYSCON_PDRUNCFGSET_PDEN_VD4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD4_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD4_MASK)
\r
17230 #define SYSCON_PDRUNCFGSET_PDEN_VD5_MASK (0x10000000U)
\r
17231 #define SYSCON_PDRUNCFGSET_PDEN_VD5_SHIFT (28U)
\r
17232 /*! PDEN_VD5 - Power control both USB0 PHY and USB1 PHY.
\r
17234 #define SYSCON_PDRUNCFGSET_PDEN_VD5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD5_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD5_MASK)
\r
17235 #define SYSCON_PDRUNCFGSET_PDEN_VD6_MASK (0x20000000U)
\r
17236 #define SYSCON_PDRUNCFGSET_PDEN_VD6_SHIFT (29U)
\r
17237 /*! PDEN_VD6 - Power control for EEPROM.
\r
17239 #define SYSCON_PDRUNCFGSET_PDEN_VD6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD6_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD6_MASK)
\r
17242 /* The count of SYSCON_PDRUNCFGSET */
\r
17243 #define SYSCON_PDRUNCFGSET_COUNT (2U)
\r
17245 /*! @name PDRUNCFGCLR - Power configuration clear register */
\r
17247 #define SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_MASK (0x1U)
\r
17248 #define SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_SHIFT (0U)
\r
17249 /*! PDEN_USB1_PHY - USB1 high speed PHY (also, enable/disable bit 28 in PDRUNCFG0 register).
\r
17251 #define SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_MASK)
\r
17252 #define SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_MASK (0x2U)
\r
17253 #define SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_SHIFT (1U)
\r
17254 /*! PDEN_USB1_PLL - USB PLL (PLL1) power (also, enable/disable bit 26 in PDRUNCFG0 register).
\r
17256 #define SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_MASK)
\r
17257 #define SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_MASK (0x4U)
\r
17258 #define SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_SHIFT (2U)
\r
17259 /*! PDEN_AUD_PLL - Audio PLL (PLL2) power and fractional divider (also, enable/disable bit 26 in PDRUNCFG0 register).
\r
17261 #define SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_MASK)
\r
17262 #define SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_MASK (0x8U)
\r
17263 #define SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_SHIFT (3U)
\r
17264 /*! PDEN_SYSOSC - System Oscillator Power (also, enable/disable bit 9 in PDRUNCFG0 register).
\r
17266 #define SYSCON_PDRUNCFGCLR_PDEN_SYSOSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_MASK)
\r
17267 #define SYSCON_PDRUNCFGCLR_PDEN_FRO_MASK (0x10U)
\r
17268 #define SYSCON_PDRUNCFGCLR_PDEN_FRO_SHIFT (4U)
\r
17269 /*! PDEN_FRO - FRO oscillator.
\r
17271 #define SYSCON_PDRUNCFGCLR_PDEN_FRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_FRO_MASK)
\r
17272 #define SYSCON_PDRUNCFGCLR_PDEN_TS_MASK (0x40U)
\r
17273 #define SYSCON_PDRUNCFGCLR_PDEN_TS_SHIFT (6U)
\r
17274 /*! PDEN_TS - Temp sensor.
\r
17276 #define SYSCON_PDRUNCFGCLR_PDEN_TS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_TS_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_TS_MASK)
\r
17277 #define SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_MASK (0x80U)
\r
17278 #define SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_SHIFT (7U)
\r
17279 /*! PDEN_BOD_RST - Brown-out Detect reset.
\r
17281 #define SYSCON_PDRUNCFGCLR_PDEN_BOD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_MASK)
\r
17282 #define SYSCON_PDRUNCFGCLR_PDEN_RNG_MASK (0x80U)
\r
17283 #define SYSCON_PDRUNCFGCLR_PDEN_RNG_SHIFT (7U)
\r
17284 /*! PDEN_RNG - Random Number Generator Power.
\r
17286 #define SYSCON_PDRUNCFGCLR_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_RNG_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_RNG_MASK)
\r
17287 #define SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_MASK (0x100U)
\r
17288 #define SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_SHIFT (8U)
\r
17289 /*! PDEN_BOD_INTR - Brown-out Detect interrupt.
\r
17291 #define SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_MASK)
\r
17292 #define SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_MASK (0x200U)
\r
17293 #define SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_SHIFT (9U)
\r
17294 /*! PDEN_VD2_ANA - Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1
\r
17295 * register), Temperature Sensor (also, enable/disable bit 6), ADC (also, enable/disable bits 10, 19,
\r
17298 #define SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_MASK)
\r
17299 #define SYSCON_PDRUNCFGCLR_PDEN_ADC0_MASK (0x400U)
\r
17300 #define SYSCON_PDRUNCFGCLR_PDEN_ADC0_SHIFT (10U)
\r
17301 /*! PDEN_ADC0 - ADC power.
\r
17303 #define SYSCON_PDRUNCFGCLR_PDEN_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_ADC0_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_ADC0_MASK)
\r
17304 #define SYSCON_PDRUNCFGCLR_PDEN_SRAMX_MASK (0x2000U)
\r
17305 #define SYSCON_PDRUNCFGCLR_PDEN_SRAMX_SHIFT (13U)
\r
17306 /*! PDEN_SRAMX - PDEN_SRAMX controls SRAMX (also enable/disable bit 27).
\r
17308 #define SYSCON_PDRUNCFGCLR_PDEN_SRAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SRAMX_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SRAMX_MASK)
\r
17309 #define SYSCON_PDRUNCFGCLR_PDEN_SRAM0_MASK (0x4000U)
\r
17310 #define SYSCON_PDRUNCFGCLR_PDEN_SRAM0_SHIFT (14U)
\r
17311 /*! PDEN_SRAM0 - PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27).
\r
17313 #define SYSCON_PDRUNCFGCLR_PDEN_SRAM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SRAM0_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SRAM0_MASK)
\r
17314 #define SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_MASK (0x8000U)
\r
17315 #define SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_SHIFT (15U)
\r
17316 /*! PDEN_SRAM1_2_3 - PDEN_SRAM1_2_3 controls SRAM1, SRAM2, and SRAM3 (also enable/disable bit 27).
\r
17318 #define SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_MASK)
\r
17319 #define SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_MASK (0x10000U)
\r
17320 #define SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_SHIFT (16U)
\r
17321 /*! PDEN_USB_RAM - PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27).
\r
17323 #define SYSCON_PDRUNCFGCLR_PDEN_USB_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_MASK)
\r
17324 #define SYSCON_PDRUNCFGCLR_PDEN_ROM_MASK (0x20000U)
\r
17325 #define SYSCON_PDRUNCFGCLR_PDEN_ROM_SHIFT (17U)
\r
17326 /*! PDEN_ROM - ROM (also enable/disable bit 27).
\r
17328 #define SYSCON_PDRUNCFGCLR_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_ROM_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_ROM_MASK)
\r
17329 #define SYSCON_PDRUNCFGCLR_PDEN_VDDA_MASK (0x80000U)
\r
17330 #define SYSCON_PDRUNCFGCLR_PDEN_VDDA_SHIFT (19U)
\r
17331 /*! PDEN_VDDA - Vdda to the ADC, must be enabled for the ADC to work (also enable/disable bit 9, 10, and 23).
\r
17333 #define SYSCON_PDRUNCFGCLR_PDEN_VDDA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VDDA_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VDDA_MASK)
\r
17334 #define SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_MASK (0x100000U)
\r
17335 #define SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_SHIFT (20U)
\r
17336 /*! PDEN_WDT_OSC - Watchdog oscillator.
\r
17338 #define SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_MASK)
\r
17339 #define SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_MASK (0x200000U)
\r
17340 #define SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_SHIFT (21U)
\r
17341 /*! PDEN_USB0_PHY - USB0 PHY power (also enable/disable bit 28).
\r
17343 #define SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_MASK)
\r
17344 #define SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_MASK (0x400000U)
\r
17345 #define SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_SHIFT (22U)
\r
17346 /*! PDEN_SYS_PLL - System PLL (PLL0) power (also enable/disable bit 26).
\r
17348 #define SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_MASK)
\r
17349 #define SYSCON_PDRUNCFGCLR_PDEN_VREFP_MASK (0x800000U)
\r
17350 #define SYSCON_PDRUNCFGCLR_PDEN_VREFP_SHIFT (23U)
\r
17351 /*! PDEN_VREFP - VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9, 10, and 19).
\r
17353 #define SYSCON_PDRUNCFGCLR_PDEN_VREFP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VREFP_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VREFP_MASK)
\r
17354 #define SYSCON_PDRUNCFGCLR_PDEN_VD3_MASK (0x4000000U)
\r
17355 #define SYSCON_PDRUNCFGCLR_PDEN_VD3_SHIFT (26U)
\r
17356 /*! PDEN_VD3 - Power control for all PLLs.
\r
17358 #define SYSCON_PDRUNCFGCLR_PDEN_VD3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD3_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD3_MASK)
\r
17359 #define SYSCON_PDRUNCFGCLR_PDEN_VD4_MASK (0x8000000U)
\r
17360 #define SYSCON_PDRUNCFGCLR_PDEN_VD4_SHIFT (27U)
\r
17361 /*! PDEN_VD4 - Power control for all SRAMs and ROM.
\r
17363 #define SYSCON_PDRUNCFGCLR_PDEN_VD4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD4_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD4_MASK)
\r
17364 #define SYSCON_PDRUNCFGCLR_PDEN_VD5_MASK (0x10000000U)
\r
17365 #define SYSCON_PDRUNCFGCLR_PDEN_VD5_SHIFT (28U)
\r
17366 /*! PDEN_VD5 - Power control both USB0 PHY and USB1 PHY.
\r
17368 #define SYSCON_PDRUNCFGCLR_PDEN_VD5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD5_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD5_MASK)
\r
17369 #define SYSCON_PDRUNCFGCLR_PDEN_VD6_MASK (0x20000000U)
\r
17370 #define SYSCON_PDRUNCFGCLR_PDEN_VD6_SHIFT (29U)
\r
17371 /*! PDEN_VD6 - Power control for EEPROM.
\r
17373 #define SYSCON_PDRUNCFGCLR_PDEN_VD6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD6_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD6_MASK)
\r
17376 /* The count of SYSCON_PDRUNCFGCLR */
\r
17377 #define SYSCON_PDRUNCFGCLR_COUNT (2U)
\r
17379 /*! @name STARTER - Start logic 0 wake-up enable register */
\r
17381 #define SYSCON_STARTER_PINT4_MASK (0x1U)
\r
17382 #define SYSCON_STARTER_PINT4_SHIFT (0U)
\r
17383 /*! PINT4 - GPIO pin interrupt 4 wake-up.
\r
17385 #define SYSCON_STARTER_PINT4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT4_SHIFT)) & SYSCON_STARTER_PINT4_MASK)
\r
17386 #define SYSCON_STARTER_WDT_BOD_MASK (0x1U)
\r
17387 #define SYSCON_STARTER_WDT_BOD_SHIFT (0U)
\r
17388 /*! WDT_BOD - WWDT and BOD interrupt wake-up.
\r
17390 #define SYSCON_STARTER_WDT_BOD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_WDT_BOD_SHIFT)) & SYSCON_STARTER_WDT_BOD_MASK)
\r
17391 #define SYSCON_STARTER_DMA_MASK (0x2U)
\r
17392 #define SYSCON_STARTER_DMA_SHIFT (1U)
\r
17393 /*! DMA - DMA wake-up.
\r
17395 #define SYSCON_STARTER_DMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_DMA_SHIFT)) & SYSCON_STARTER_DMA_MASK)
\r
17396 #define SYSCON_STARTER_PINT5_MASK (0x2U)
\r
17397 #define SYSCON_STARTER_PINT5_SHIFT (1U)
\r
17398 /*! PINT5 - GPIO pin interrupt 5 wake-up.
\r
17400 #define SYSCON_STARTER_PINT5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT5_SHIFT)) & SYSCON_STARTER_PINT5_MASK)
\r
17401 #define SYSCON_STARTER_GINT0_MASK (0x4U)
\r
17402 #define SYSCON_STARTER_GINT0_SHIFT (2U)
\r
17403 /*! GINT0 - Group interrupt 0 wake-up.
\r
17405 #define SYSCON_STARTER_GINT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT0_SHIFT)) & SYSCON_STARTER_GINT0_MASK)
\r
17406 #define SYSCON_STARTER_PINT6_MASK (0x4U)
\r
17407 #define SYSCON_STARTER_PINT6_SHIFT (2U)
\r
17408 /*! PINT6 - GPIO pin interrupt 6 wake-up.
\r
17410 #define SYSCON_STARTER_PINT6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT6_SHIFT)) & SYSCON_STARTER_PINT6_MASK)
\r
17411 #define SYSCON_STARTER_GINT1_MASK (0x8U)
\r
17412 #define SYSCON_STARTER_GINT1_SHIFT (3U)
\r
17413 /*! GINT1 - Group interrupt 1 wake-up.
\r
17415 #define SYSCON_STARTER_GINT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT1_SHIFT)) & SYSCON_STARTER_GINT1_MASK)
\r
17416 #define SYSCON_STARTER_PINT7_MASK (0x8U)
\r
17417 #define SYSCON_STARTER_PINT7_SHIFT (3U)
\r
17418 /*! PINT7 - GPIO pin interrupt 7 wake-up.
\r
17420 #define SYSCON_STARTER_PINT7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT7_SHIFT)) & SYSCON_STARTER_PINT7_MASK)
\r
17421 #define SYSCON_STARTER_PIN_INT0_MASK (0x10U)
\r
17422 #define SYSCON_STARTER_PIN_INT0_SHIFT (4U)
\r
17423 /*! PIN_INT0 - GPIO pin interrupt 0 wake-up.
\r
17425 #define SYSCON_STARTER_PIN_INT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT0_SHIFT)) & SYSCON_STARTER_PIN_INT0_MASK)
\r
17426 #define SYSCON_STARTER_PIN_INT1_MASK (0x20U)
\r
17427 #define SYSCON_STARTER_PIN_INT1_SHIFT (5U)
\r
17428 /*! PIN_INT1 - GPIO pin interrupt 1 wake-up.
\r
17430 #define SYSCON_STARTER_PIN_INT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT1_SHIFT)) & SYSCON_STARTER_PIN_INT1_MASK)
\r
17431 #define SYSCON_STARTER_PIN_INT2_MASK (0x40U)
\r
17432 #define SYSCON_STARTER_PIN_INT2_SHIFT (6U)
\r
17433 /*! PIN_INT2 - GPIO pin interrupt 2 wake-up.
\r
17435 #define SYSCON_STARTER_PIN_INT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT2_SHIFT)) & SYSCON_STARTER_PIN_INT2_MASK)
\r
17436 #define SYSCON_STARTER_PIN_INT3_MASK (0x80U)
\r
17437 #define SYSCON_STARTER_PIN_INT3_SHIFT (7U)
\r
17438 /*! PIN_INT3 - GPIO pin interrupt 3 wake-up.
\r
17440 #define SYSCON_STARTER_PIN_INT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT3_SHIFT)) & SYSCON_STARTER_PIN_INT3_MASK)
\r
17441 #define SYSCON_STARTER_FLEXCOMM8_MASK (0x100U)
\r
17442 #define SYSCON_STARTER_FLEXCOMM8_SHIFT (8U)
\r
17443 /*! FLEXCOMM8 - Flexcomm Interface 8 wake-up.
\r
17445 #define SYSCON_STARTER_FLEXCOMM8(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM8_SHIFT)) & SYSCON_STARTER_FLEXCOMM8_MASK)
\r
17446 #define SYSCON_STARTER_UTICK_MASK (0x100U)
\r
17447 #define SYSCON_STARTER_UTICK_SHIFT (8U)
\r
17448 /*! UTICK - Micro-tick Timer wake-up.
\r
17450 #define SYSCON_STARTER_UTICK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_UTICK_SHIFT)) & SYSCON_STARTER_UTICK_MASK)
\r
17451 #define SYSCON_STARTER_FLEXCOMM9_MASK (0x200U)
\r
17452 #define SYSCON_STARTER_FLEXCOMM9_SHIFT (9U)
\r
17453 /*! FLEXCOMM9 - Flexcomm Interface 9 wake-up.
\r
17455 #define SYSCON_STARTER_FLEXCOMM9(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM9_SHIFT)) & SYSCON_STARTER_FLEXCOMM9_MASK)
\r
17456 #define SYSCON_STARTER_FLEXCOMM0_MASK (0x4000U)
\r
17457 #define SYSCON_STARTER_FLEXCOMM0_SHIFT (14U)
\r
17458 /*! FLEXCOMM0 - Flexcomm0 peripheral interrupt wake-up.
\r
17460 #define SYSCON_STARTER_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM0_SHIFT)) & SYSCON_STARTER_FLEXCOMM0_MASK)
\r
17461 #define SYSCON_STARTER_FLEXCOMM1_MASK (0x8000U)
\r
17462 #define SYSCON_STARTER_FLEXCOMM1_SHIFT (15U)
\r
17463 /*! FLEXCOMM1 - Flexcomm1 peripheral interrupt wake-up.
\r
17465 #define SYSCON_STARTER_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM1_SHIFT)) & SYSCON_STARTER_FLEXCOMM1_MASK)
\r
17466 #define SYSCON_STARTER_USB1_MASK (0x8000U)
\r
17467 #define SYSCON_STARTER_USB1_SHIFT (15U)
\r
17468 /*! USB1 - USB 1 wake-up.
\r
17470 #define SYSCON_STARTER_USB1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB1_SHIFT)) & SYSCON_STARTER_USB1_MASK)
\r
17471 #define SYSCON_STARTER_FLEXCOMM2_MASK (0x10000U)
\r
17472 #define SYSCON_STARTER_FLEXCOMM2_SHIFT (16U)
\r
17473 /*! FLEXCOMM2 - Flexcomm2 peripheral interrupt wake-up.
\r
17475 #define SYSCON_STARTER_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM2_SHIFT)) & SYSCON_STARTER_FLEXCOMM2_MASK)
\r
17476 #define SYSCON_STARTER_USB1_ACT_MASK (0x10000U)
\r
17477 #define SYSCON_STARTER_USB1_ACT_SHIFT (16U)
\r
17478 /*! USB1_ACT - USB 1 activity wake-up.
\r
17480 #define SYSCON_STARTER_USB1_ACT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB1_ACT_SHIFT)) & SYSCON_STARTER_USB1_ACT_MASK)
\r
17481 #define SYSCON_STARTER_FLEXCOMM3_MASK (0x20000U)
\r
17482 #define SYSCON_STARTER_FLEXCOMM3_SHIFT (17U)
\r
17483 /*! FLEXCOMM3 - Flexcomm3 peripheral interrupt wake-up.
\r
17485 #define SYSCON_STARTER_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM3_SHIFT)) & SYSCON_STARTER_FLEXCOMM3_MASK)
\r
17486 #define SYSCON_STARTER_FLEXCOMM4_MASK (0x40000U)
\r
17487 #define SYSCON_STARTER_FLEXCOMM4_SHIFT (18U)
\r
17488 /*! FLEXCOMM4 - Flexcomm4 peripheral interrupt wake-up.
\r
17490 #define SYSCON_STARTER_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM4_SHIFT)) & SYSCON_STARTER_FLEXCOMM4_MASK)
\r
17491 #define SYSCON_STARTER_FLEXCOMM5_MASK (0x80000U)
\r
17492 #define SYSCON_STARTER_FLEXCOMM5_SHIFT (19U)
\r
17493 /*! FLEXCOMM5 - Flexcomm5 peripheral interrupt wake-up.
\r
17495 #define SYSCON_STARTER_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM5_SHIFT)) & SYSCON_STARTER_FLEXCOMM5_MASK)
\r
17496 #define SYSCON_STARTER_FLEXCOMM6_MASK (0x100000U)
\r
17497 #define SYSCON_STARTER_FLEXCOMM6_SHIFT (20U)
\r
17498 /*! FLEXCOMM6 - Flexcomm6 peripheral interrupt wake-up.
\r
17500 #define SYSCON_STARTER_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM6_SHIFT)) & SYSCON_STARTER_FLEXCOMM6_MASK)
\r
17501 #define SYSCON_STARTER_FLEXCOMM7_MASK (0x200000U)
\r
17502 #define SYSCON_STARTER_FLEXCOMM7_SHIFT (21U)
\r
17503 /*! FLEXCOMM7 - Flexcomm7 peripheral interrupt wake-up.
\r
17505 #define SYSCON_STARTER_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM7_SHIFT)) & SYSCON_STARTER_FLEXCOMM7_MASK)
\r
17506 #define SYSCON_STARTER_DMIC_MASK (0x2000000U)
\r
17507 #define SYSCON_STARTER_DMIC_SHIFT (25U)
\r
17508 /*! DMIC - Digital microphone interrupt wake-up.
\r
17510 #define SYSCON_STARTER_DMIC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_DMIC_SHIFT)) & SYSCON_STARTER_DMIC_MASK)
\r
17511 #define SYSCON_STARTER_HWVAD_MASK (0x4000000U)
\r
17512 #define SYSCON_STARTER_HWVAD_SHIFT (26U)
\r
17513 /*! HWVAD - Hardware voice activity detect interrupt wake-up.
\r
17515 #define SYSCON_STARTER_HWVAD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_HWVAD_SHIFT)) & SYSCON_STARTER_HWVAD_MASK)
\r
17516 #define SYSCON_STARTER_USB0_NEEDCLK_MASK (0x8000000U)
\r
17517 #define SYSCON_STARTER_USB0_NEEDCLK_SHIFT (27U)
\r
17518 /*! USB0_NEEDCLK - USB activity interrupt wake-up.
\r
17520 #define SYSCON_STARTER_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_NEEDCLK_SHIFT)) & SYSCON_STARTER_USB0_NEEDCLK_MASK)
\r
17521 #define SYSCON_STARTER_USB0_MASK (0x10000000U)
\r
17522 #define SYSCON_STARTER_USB0_SHIFT (28U)
\r
17523 /*! USB0 - USB function interrupt wake-up.
\r
17525 #define SYSCON_STARTER_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_SHIFT)) & SYSCON_STARTER_USB0_MASK)
\r
17526 #define SYSCON_STARTER_RTC_MASK (0x20000000U)
\r
17527 #define SYSCON_STARTER_RTC_SHIFT (29U)
\r
17528 /*! RTC - RTC interrupt alarm and wake-up timer.
\r
17530 #define SYSCON_STARTER_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_RTC_SHIFT)) & SYSCON_STARTER_RTC_MASK)
\r
17531 #define SYSCON_STARTER_FLEXCOMM10_MASK (0x40000000U)
\r
17532 #define SYSCON_STARTER_FLEXCOMM10_SHIFT (30U)
\r
17533 /*! FLEXCOMM10 - Flexcomm10 peripheral interrupt wake-up.
\r
17535 #define SYSCON_STARTER_FLEXCOMM10(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM10_SHIFT)) & SYSCON_STARTER_FLEXCOMM10_MASK)
\r
17538 /* The count of SYSCON_STARTER */
\r
17539 #define SYSCON_STARTER_COUNT (2U)
\r
17541 /*! @name STARTERSET - Set bits in STARTER */
\r
17543 #define SYSCON_STARTERSET_START_SET_MASK (0xFFFFFFFFU)
\r
17544 #define SYSCON_STARTERSET_START_SET_SHIFT (0U)
\r
17545 /*! START_SET - Writing ones to this register sets the corresponding bit or bits in the STARTER0 register, if they are implemented.
\r
17547 #define SYSCON_STARTERSET_START_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_START_SET_SHIFT)) & SYSCON_STARTERSET_START_SET_MASK)
\r
17550 /* The count of SYSCON_STARTERSET */
\r
17551 #define SYSCON_STARTERSET_COUNT (2U)
\r
17553 /*! @name STARTERCLR - Clear bits in STARTER0 */
\r
17555 #define SYSCON_STARTERCLR_START_CLR_MASK (0xFFFFFFFFU)
\r
17556 #define SYSCON_STARTERCLR_START_CLR_SHIFT (0U)
\r
17557 /*! START_CLR - Writing ones to this register clears the corresponding bit or bits in the STARTER0 register, if they are implemented.
\r
17559 #define SYSCON_STARTERCLR_START_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_START_CLR_SHIFT)) & SYSCON_STARTERCLR_START_CLR_MASK)
\r
17562 /* The count of SYSCON_STARTERCLR */
\r
17563 #define SYSCON_STARTERCLR_COUNT (2U)
\r
17565 /*! @name HWWAKE - Configures special cases of hardware wake-up */
\r
17567 #define SYSCON_HWWAKE_FORCEWAKE_MASK (0x1U)
\r
17568 #define SYSCON_HWWAKE_FORCEWAKE_SHIFT (0U)
\r
17569 /*! FORCEWAKE - Force peripheral clocking to stay on during Deep Sleep and Power-down modes. When 1,
\r
17570 * clocking to peripherals is prevented from being shut down when the CPU enters Deep Sleep and
\r
17571 * Power-down modes. This is intended to allow a coprocessor to continue operating while the main
\r
17572 * CPU(s) are shut down.
\r
17574 #define SYSCON_HWWAKE_FORCEWAKE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_FORCEWAKE_SHIFT)) & SYSCON_HWWAKE_FORCEWAKE_MASK)
\r
17575 #define SYSCON_HWWAKE_FCWAKE_MASK (0x2U)
\r
17576 #define SYSCON_HWWAKE_FCWAKE_SHIFT (1U)
\r
17577 /*! FCWAKE - Wake for Flexcomms. When 1, any Flexcomm FIFO reaching the level specified by its own
\r
17578 * TXLVL will cause peripheral clocking to wake up temporarily while the related status is
\r
17581 #define SYSCON_HWWAKE_FCWAKE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_FCWAKE_SHIFT)) & SYSCON_HWWAKE_FCWAKE_MASK)
\r
17582 #define SYSCON_HWWAKE_WAKEDMIC_MASK (0x4U)
\r
17583 #define SYSCON_HWWAKE_WAKEDMIC_SHIFT (2U)
\r
17584 /*! WAKEDMIC - Wake for Digital Microphone. When 1, the digital microphone input FIFO reaching the
\r
17585 * level specified by TRIGLVL of either channel will cause peripheral clocking to wake up
\r
17586 * temporarily while the related status is asserted.
\r
17588 #define SYSCON_HWWAKE_WAKEDMIC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_WAKEDMIC_SHIFT)) & SYSCON_HWWAKE_WAKEDMIC_MASK)
\r
17589 #define SYSCON_HWWAKE_WAKEDMA_MASK (0x8U)
\r
17590 #define SYSCON_HWWAKE_WAKEDMA_SHIFT (3U)
\r
17591 /*! WAKEDMA - Wake for DMA. When 1, DMA being busy will cause peripheral clocking to remain running
\r
17592 * until DMA completes. This is generally used in conjunction with bit 1 and/or 2 in order to
\r
17593 * prevent peripheral clocking from being shut down as soon as the cause of wake-up is cleared, but
\r
17594 * before DMA has completed its related activity.
\r
17596 #define SYSCON_HWWAKE_WAKEDMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_WAKEDMA_SHIFT)) & SYSCON_HWWAKE_WAKEDMA_MASK)
\r
17599 /*! @name AUTOCGOR - Auto Clock-Gate Override Register */
\r
17601 #define SYSCON_AUTOCGOR_RAM0X_MASK (0x2U)
\r
17602 #define SYSCON_AUTOCGOR_RAM0X_SHIFT (1U)
\r
17603 /*! RAM0X - When 1, automatic clock gating for RAMX and RAM0 are turned off.
\r
17605 #define SYSCON_AUTOCGOR_RAM0X(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM0X_SHIFT)) & SYSCON_AUTOCGOR_RAM0X_MASK)
\r
17606 #define SYSCON_AUTOCGOR_RAM1_MASK (0x4U)
\r
17607 #define SYSCON_AUTOCGOR_RAM1_SHIFT (2U)
\r
17608 /*! RAM1 - When 1, automatic clock gating for RAM1 are turned off.
\r
17610 #define SYSCON_AUTOCGOR_RAM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM1_SHIFT)) & SYSCON_AUTOCGOR_RAM1_MASK)
\r
17611 #define SYSCON_AUTOCGOR_RAM2_MASK (0x8U)
\r
17612 #define SYSCON_AUTOCGOR_RAM2_SHIFT (3U)
\r
17613 /*! RAM2 - When 1, automatic clock gating for RAM1 are turned off.
\r
17615 #define SYSCON_AUTOCGOR_RAM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM2_SHIFT)) & SYSCON_AUTOCGOR_RAM2_MASK)
\r
17616 #define SYSCON_AUTOCGOR_RAM3_MASK (0x10U)
\r
17617 #define SYSCON_AUTOCGOR_RAM3_SHIFT (4U)
\r
17618 /*! RAM3 - When 1, automatic clock gating for RAM1 are turned off.
\r
17620 #define SYSCON_AUTOCGOR_RAM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM3_SHIFT)) & SYSCON_AUTOCGOR_RAM3_MASK)
\r
17623 /*! @name JTAGIDCODE - JTAG ID code register */
\r
17625 #define SYSCON_JTAGIDCODE_JTAGID_MASK (0xFFFFFFFFU)
\r
17626 #define SYSCON_JTAGIDCODE_JTAGID_SHIFT (0U)
\r
17627 /*! JTAGID - JTAG ID code.
\r
17629 #define SYSCON_JTAGIDCODE_JTAGID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_JTAGIDCODE_JTAGID_SHIFT)) & SYSCON_JTAGIDCODE_JTAGID_MASK)
\r
17632 /*! @name DEVICE_ID0 - Part ID register */
\r
17634 #define SYSCON_DEVICE_ID0_PARTID_MASK (0xFFFFFFFFU)
\r
17635 #define SYSCON_DEVICE_ID0_PARTID_SHIFT (0U)
\r
17636 /*! PARTID - Part ID
\r
17638 #define SYSCON_DEVICE_ID0_PARTID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_PARTID_SHIFT)) & SYSCON_DEVICE_ID0_PARTID_MASK)
\r
17641 /*! @name DEVICE_ID1 - Boot ROM and die revision register */
\r
17643 #define SYSCON_DEVICE_ID1_REVID_MASK (0xFFFFFFFFU)
\r
17644 #define SYSCON_DEVICE_ID1_REVID_SHIFT (0U)
\r
17645 /*! REVID - Revision.
\r
17647 #define SYSCON_DEVICE_ID1_REVID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID1_REVID_SHIFT)) & SYSCON_DEVICE_ID1_REVID_MASK)
\r
17650 /*! @name BODCTRL - Brown-Out Detect control */
\r
17652 #define SYSCON_BODCTRL_BODRSTLEV_MASK (0x3U)
\r
17653 #define SYSCON_BODCTRL_BODRSTLEV_SHIFT (0U)
\r
17654 /*! BODRSTLEV - BOD reset level
\r
17655 * 0b00..Level 0: 1.5 V
\r
17656 * 0b01..Level 1: 1.85 V
\r
17657 * 0b10..Level 2: 2.0 V
\r
17658 * 0b11..Level 3: 2.3 V
\r
17660 #define SYSCON_BODCTRL_BODRSTLEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTLEV_SHIFT)) & SYSCON_BODCTRL_BODRSTLEV_MASK)
\r
17661 #define SYSCON_BODCTRL_BODRSTENA_MASK (0x4U)
\r
17662 #define SYSCON_BODCTRL_BODRSTENA_SHIFT (2U)
\r
17663 /*! BODRSTENA - BOD reset enable
\r
17664 * 0b0..Disable reset function.
\r
17665 * 0b1..Enable reset function.
\r
17667 #define SYSCON_BODCTRL_BODRSTENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTENA_SHIFT)) & SYSCON_BODCTRL_BODRSTENA_MASK)
\r
17668 #define SYSCON_BODCTRL_BODINTLEV_MASK (0x18U)
\r
17669 #define SYSCON_BODCTRL_BODINTLEV_SHIFT (3U)
\r
17670 /*! BODINTLEV - BOD interrupt level
\r
17671 * 0b00..Level 0: 2.05 V
\r
17672 * 0b01..Level 1: 2.45 V
\r
17673 * 0b10..Level 2: 2.75 V
\r
17674 * 0b11..Level 3: 3.05 V
\r
17676 #define SYSCON_BODCTRL_BODINTLEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTLEV_SHIFT)) & SYSCON_BODCTRL_BODINTLEV_MASK)
\r
17677 #define SYSCON_BODCTRL_BODINTENA_MASK (0x20U)
\r
17678 #define SYSCON_BODCTRL_BODINTENA_SHIFT (5U)
\r
17679 /*! BODINTENA - BOD interrupt enable
\r
17680 * 0b0..Disable interrupt function.
\r
17681 * 0b1..Enable interrupt function.
\r
17683 #define SYSCON_BODCTRL_BODINTENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTENA_SHIFT)) & SYSCON_BODCTRL_BODINTENA_MASK)
\r
17684 #define SYSCON_BODCTRL_BODRSTSTAT_MASK (0x40U)
\r
17685 #define SYSCON_BODCTRL_BODRSTSTAT_SHIFT (6U)
\r
17686 /*! BODRSTSTAT - BOD reset status. When 1, a BOD reset has occurred. Cleared by writing 1 to this bit.
\r
17688 #define SYSCON_BODCTRL_BODRSTSTAT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTSTAT_SHIFT)) & SYSCON_BODCTRL_BODRSTSTAT_MASK)
\r
17689 #define SYSCON_BODCTRL_BODINTSTAT_MASK (0x80U)
\r
17690 #define SYSCON_BODCTRL_BODINTSTAT_SHIFT (7U)
\r
17691 /*! BODINTSTAT - BOD interrupt status. When 1, a BOD interrupt has occurred. Cleared by writing 1 to this bit.
\r
17693 #define SYSCON_BODCTRL_BODINTSTAT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTSTAT_SHIFT)) & SYSCON_BODCTRL_BODINTSTAT_MASK)
\r
17699 */ /* end of group SYSCON_Register_Masks */
\r
17702 /* SYSCON - Peripheral instance base addresses */
\r
17703 /** Peripheral SYSCON base address */
\r
17704 #define SYSCON_BASE (0x40000000u)
\r
17705 /** Peripheral SYSCON base pointer */
\r
17706 #define SYSCON ((SYSCON_Type *)SYSCON_BASE)
\r
17707 /** Array initializer of SYSCON peripheral base addresses */
\r
17708 #define SYSCON_BASE_ADDRS { SYSCON_BASE }
\r
17709 /** Array initializer of SYSCON peripheral base pointers */
\r
17710 #define SYSCON_BASE_PTRS { SYSCON }
\r
17714 */ /* end of group SYSCON_Peripheral_Access_Layer */
\r
17717 /* ----------------------------------------------------------------------------
\r
17718 -- USART Peripheral Access Layer
\r
17719 ---------------------------------------------------------------------------- */
\r
17722 * @addtogroup USART_Peripheral_Access_Layer USART Peripheral Access Layer
\r
17726 /** USART - Register Layout Typedef */
\r
17728 __IO uint32_t CFG; /**< USART Configuration register. Basic USART configuration settings that typically are not changed during operation., offset: 0x0 */
\r
17729 __IO uint32_t CTL; /**< USART Control register. USART control settings that are more likely to change during operation., offset: 0x4 */
\r
17730 __IO uint32_t STAT; /**< USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them., offset: 0x8 */
\r
17731 __IO uint32_t INTENSET; /**< Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0xC */
\r
17732 __O uint32_t INTENCLR; /**< Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared., offset: 0x10 */
\r
17733 uint8_t RESERVED_0[12];
\r
17734 __IO uint32_t BRG; /**< Baud Rate Generator register. 16-bit integer baud rate divisor value., offset: 0x20 */
\r
17735 __I uint32_t INTSTAT; /**< Interrupt status register. Reflects interrupts that are currently enabled., offset: 0x24 */
\r
17736 __IO uint32_t OSR; /**< Oversample selection register for asynchronous communication., offset: 0x28 */
\r
17737 __IO uint32_t ADDR; /**< Address register for automatic address matching., offset: 0x2C */
\r
17738 uint8_t RESERVED_1[3536];
\r
17739 __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */
\r
17740 __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */
\r
17741 __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */
\r
17742 uint8_t RESERVED_2[4];
\r
17743 __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */
\r
17744 __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */
\r
17745 __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */
\r
17746 uint8_t RESERVED_3[4];
\r
17747 __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */
\r
17748 uint8_t RESERVED_4[12];
\r
17749 __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */
\r
17750 uint8_t RESERVED_5[12];
\r
17751 __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */
\r
17752 uint8_t RESERVED_6[440];
\r
17753 __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */
\r
17756 /* ----------------------------------------------------------------------------
\r
17757 -- USART Register Masks
\r
17758 ---------------------------------------------------------------------------- */
\r
17761 * @addtogroup USART_Register_Masks USART Register Masks
\r
17765 /*! @name CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during operation. */
\r
17767 #define USART_CFG_ENABLE_MASK (0x1U)
\r
17768 #define USART_CFG_ENABLE_SHIFT (0U)
\r
17769 /*! ENABLE - USART Enable.
\r
17770 * 0b0..Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0,
\r
17771 * all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control
\r
17772 * bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the
\r
17773 * transmitter has been reset and is therefore available.
\r
17774 * 0b1..Enabled. The USART is enabled for operation.
\r
17776 #define USART_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK)
\r
17777 #define USART_CFG_DATALEN_MASK (0xCU)
\r
17778 #define USART_CFG_DATALEN_SHIFT (2U)
\r
17779 /*! DATALEN - Selects the data size for the USART.
\r
17780 * 0b00..7 bit Data length.
\r
17781 * 0b01..8 bit Data length.
\r
17782 * 0b10..9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register.
\r
17783 * 0b11..Reserved.
\r
17785 #define USART_CFG_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK)
\r
17786 #define USART_CFG_PARITYSEL_MASK (0x30U)
\r
17787 #define USART_CFG_PARITYSEL_SHIFT (4U)
\r
17788 /*! PARITYSEL - Selects what type of parity is used by the USART.
\r
17789 * 0b00..No parity.
\r
17790 * 0b01..Reserved.
\r
17791 * 0b10..Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even,
\r
17792 * and the number of 1s in a received character is expected to be even.
\r
17793 * 0b11..Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd,
\r
17794 * and the number of 1s in a received character is expected to be odd.
\r
17796 #define USART_CFG_PARITYSEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK)
\r
17797 #define USART_CFG_STOPLEN_MASK (0x40U)
\r
17798 #define USART_CFG_STOPLEN_SHIFT (6U)
\r
17799 /*! STOPLEN - Number of stop bits appended to transmitted data. Only a single stop bit is required for received data.
\r
17800 * 0b0..1 stop bit.
\r
17801 * 0b1..2 stop bits. This setting should only be used for asynchronous communication.
\r
17803 #define USART_CFG_STOPLEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK)
\r
17804 #define USART_CFG_MODE32K_MASK (0x80U)
\r
17805 #define USART_CFG_MODE32K_SHIFT (7U)
\r
17806 /*! MODE32K - Selects standard or 32 kHz clocking mode.
\r
17807 * 0b0..Disabled. USART uses standard clocking.
\r
17808 * 0b1..Enabled. USART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme.
\r
17810 #define USART_CFG_MODE32K(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK)
\r
17811 #define USART_CFG_LINMODE_MASK (0x100U)
\r
17812 #define USART_CFG_LINMODE_SHIFT (8U)
\r
17813 /*! LINMODE - LIN break mode enable.
\r
17814 * 0b0..Disabled. Break detect and generate is configured for normal operation.
\r
17815 * 0b1..Enabled. Break detect and generate is configured for LIN bus operation.
\r
17817 #define USART_CFG_LINMODE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK)
\r
17818 #define USART_CFG_CTSEN_MASK (0x200U)
\r
17819 #define USART_CFG_CTSEN_SHIFT (9U)
\r
17820 /*! CTSEN - CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input
\r
17821 * pin, or from the USART's own RTS if loopback mode is enabled.
\r
17822 * 0b0..No flow control. The transmitter does not receive any automatic flow control signal.
\r
17823 * 0b1..Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes.
\r
17825 #define USART_CFG_CTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK)
\r
17826 #define USART_CFG_SYNCEN_MASK (0x800U)
\r
17827 #define USART_CFG_SYNCEN_SHIFT (11U)
\r
17828 /*! SYNCEN - Selects synchronous or asynchronous operation.
\r
17829 * 0b0..Asynchronous mode.
\r
17830 * 0b1..Synchronous mode.
\r
17832 #define USART_CFG_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK)
\r
17833 #define USART_CFG_CLKPOL_MASK (0x1000U)
\r
17834 #define USART_CFG_CLKPOL_SHIFT (12U)
\r
17835 /*! CLKPOL - Selects the clock polarity and sampling edge of received data in synchronous mode.
\r
17836 * 0b0..Falling edge. Un_RXD is sampled on the falling edge of SCLK.
\r
17837 * 0b1..Rising edge. Un_RXD is sampled on the rising edge of SCLK.
\r
17839 #define USART_CFG_CLKPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK)
\r
17840 #define USART_CFG_SYNCMST_MASK (0x4000U)
\r
17841 #define USART_CFG_SYNCMST_SHIFT (14U)
\r
17842 /*! SYNCMST - Synchronous mode Master select.
\r
17843 * 0b0..Slave. When synchronous mode is enabled, the USART is a slave.
\r
17844 * 0b1..Master. When synchronous mode is enabled, the USART is a master.
\r
17846 #define USART_CFG_SYNCMST(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK)
\r
17847 #define USART_CFG_LOOP_MASK (0x8000U)
\r
17848 #define USART_CFG_LOOP_SHIFT (15U)
\r
17849 /*! LOOP - Selects data loopback mode.
\r
17850 * 0b0..Normal operation.
\r
17851 * 0b1..Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial
\r
17852 * data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD
\r
17853 * and Un_RTS activity will also appear on external pins if these functions are configured to appear on device
\r
17854 * pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN.
\r
17856 #define USART_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK)
\r
17857 #define USART_CFG_OETA_MASK (0x40000U)
\r
17858 #define USART_CFG_OETA_SHIFT (18U)
\r
17859 /*! OETA - Output Enable Turnaround time enable for RS-485 operation.
\r
17860 * 0b0..Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission.
\r
17861 * 0b1..Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the
\r
17862 * end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins
\r
17863 * before it is deasserted.
\r
17865 #define USART_CFG_OETA(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK)
\r
17866 #define USART_CFG_AUTOADDR_MASK (0x80000U)
\r
17867 #define USART_CFG_AUTOADDR_SHIFT (19U)
\r
17868 /*! AUTOADDR - Automatic Address matching enable.
\r
17869 * 0b0..Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the
\r
17870 * possibility of versatile addressing (e.g. respond to more than one address).
\r
17871 * 0b1..Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in
\r
17872 * the ADDR register as the address to match.
\r
17874 #define USART_CFG_AUTOADDR(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK)
\r
17875 #define USART_CFG_OESEL_MASK (0x100000U)
\r
17876 #define USART_CFG_OESEL_SHIFT (20U)
\r
17877 /*! OESEL - Output Enable Select.
\r
17878 * 0b0..Standard. The RTS signal is used as the standard flow control function.
\r
17879 * 0b1..RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver.
\r
17881 #define USART_CFG_OESEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK)
\r
17882 #define USART_CFG_OEPOL_MASK (0x200000U)
\r
17883 #define USART_CFG_OEPOL_SHIFT (21U)
\r
17884 /*! OEPOL - Output Enable Polarity.
\r
17885 * 0b0..Low. If selected by OESEL, the output enable is active low.
\r
17886 * 0b1..High. If selected by OESEL, the output enable is active high.
\r
17888 #define USART_CFG_OEPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK)
\r
17889 #define USART_CFG_RXPOL_MASK (0x400000U)
\r
17890 #define USART_CFG_RXPOL_SHIFT (22U)
\r
17891 /*! RXPOL - Receive data polarity.
\r
17892 * 0b0..Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start
\r
17893 * bit is 0, data is not inverted, and the stop bit is 1.
\r
17894 * 0b1..Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is
\r
17895 * 0, start bit is 1, data is inverted, and the stop bit is 0.
\r
17897 #define USART_CFG_RXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK)
\r
17898 #define USART_CFG_TXPOL_MASK (0x800000U)
\r
17899 #define USART_CFG_TXPOL_SHIFT (23U)
\r
17900 /*! TXPOL - Transmit data polarity.
\r
17901 * 0b0..Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is
\r
17902 * 0, data is not inverted, and the stop bit is 1.
\r
17903 * 0b1..Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value
\r
17904 * is 0, start bit is 1, data is inverted, and the stop bit is 0.
\r
17906 #define USART_CFG_TXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK)
\r
17909 /*! @name CTL - USART Control register. USART control settings that are more likely to change during operation. */
\r
17911 #define USART_CTL_TXBRKEN_MASK (0x2U)
\r
17912 #define USART_CTL_TXBRKEN_SHIFT (1U)
\r
17913 /*! TXBRKEN - Break Enable.
\r
17914 * 0b0..Normal operation.
\r
17915 * 0b1..Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit
\r
17916 * is cleared. A break may be sent without danger of corrupting any currently transmitting character if the
\r
17917 * transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled
\r
17918 * (TXDISINT in STAT = 1) before writing 1 to TXBRKEN.
\r
17920 #define USART_CTL_TXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK)
\r
17921 #define USART_CTL_ADDRDET_MASK (0x4U)
\r
17922 #define USART_CTL_ADDRDET_SHIFT (2U)
\r
17923 /*! ADDRDET - Enable address detect mode.
\r
17924 * 0b0..Disabled. The USART presents all incoming data.
\r
17925 * 0b1..Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data
\r
17926 * (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally,
\r
17927 * generating a received data interrupt. Software can then check the data to see if this is an address that
\r
17928 * should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled
\r
17931 #define USART_CTL_ADDRDET(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK)
\r
17932 #define USART_CTL_TXDIS_MASK (0x40U)
\r
17933 #define USART_CTL_TXDIS_SHIFT (6U)
\r
17934 /*! TXDIS - Transmit Disable.
\r
17935 * 0b0..Not disabled. USART transmitter is not disabled.
\r
17936 * 0b1..Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This
\r
17937 * feature can be used to facilitate software flow control.
\r
17939 #define USART_CTL_TXDIS(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK)
\r
17940 #define USART_CTL_CC_MASK (0x100U)
\r
17941 #define USART_CTL_CC_SHIFT (8U)
\r
17942 /*! CC - Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode.
\r
17943 * 0b0..Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to
\r
17944 * complete a character that is being received.
\r
17945 * 0b1..Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on
\r
17946 * Un_RxD independently from transmission on Un_TXD).
\r
17948 #define USART_CTL_CC(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK)
\r
17949 #define USART_CTL_CLRCCONRX_MASK (0x200U)
\r
17950 #define USART_CTL_CLRCCONRX_SHIFT (9U)
\r
17951 /*! CLRCCONRX - Clear Continuous Clock.
\r
17952 * 0b0..No effect. No effect on the CC bit.
\r
17953 * 0b1..Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time.
\r
17955 #define USART_CTL_CLRCCONRX(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK)
\r
17956 #define USART_CTL_AUTOBAUD_MASK (0x10000U)
\r
17957 #define USART_CTL_AUTOBAUD_SHIFT (16U)
\r
17958 /*! AUTOBAUD - Autobaud enable.
\r
17959 * 0b0..Disabled. USART is in normal operating mode.
\r
17960 * 0b1..Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The
\r
17961 * first start bit of RX is measured and used the update the BRG register to match the received data rate.
\r
17962 * AUTOBAUD is cleared once this process is complete, or if there is an AERR.
\r
17964 #define USART_CTL_AUTOBAUD(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK)
\r
17967 /*! @name STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. */
\r
17969 #define USART_STAT_RXIDLE_MASK (0x2U)
\r
17970 #define USART_STAT_RXIDLE_SHIFT (1U)
\r
17971 /*! RXIDLE - Receiver Idle. When 0, indicates that the receiver is currently in the process of
\r
17972 * receiving data. When 1, indicates that the receiver is not currently in the process of receiving
\r
17975 #define USART_STAT_RXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK)
\r
17976 #define USART_STAT_TXIDLE_MASK (0x8U)
\r
17977 #define USART_STAT_TXIDLE_SHIFT (3U)
\r
17978 /*! TXIDLE - Transmitter Idle. When 0, indicates that the transmitter is currently in the process of
\r
17979 * sending data.When 1, indicate that the transmitter is not currently in the process of sending
\r
17982 #define USART_STAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK)
\r
17983 #define USART_STAT_CTS_MASK (0x10U)
\r
17984 #define USART_STAT_CTS_SHIFT (4U)
\r
17985 /*! CTS - This bit reflects the current state of the CTS signal, regardless of the setting of the
\r
17986 * CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode
\r
17989 #define USART_STAT_CTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK)
\r
17990 #define USART_STAT_DELTACTS_MASK (0x20U)
\r
17991 #define USART_STAT_DELTACTS_SHIFT (5U)
\r
17992 /*! DELTACTS - This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software.
\r
17994 #define USART_STAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK)
\r
17995 #define USART_STAT_TXDISSTAT_MASK (0x40U)
\r
17996 #define USART_STAT_TXDISSTAT_SHIFT (6U)
\r
17997 /*! TXDISSTAT - Transmitter Disabled Status flag. When 1, this bit indicates that the USART
\r
17998 * transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1).
\r
18000 #define USART_STAT_TXDISSTAT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK)
\r
18001 #define USART_STAT_RXBRK_MASK (0x400U)
\r
18002 #define USART_STAT_RXBRK_SHIFT (10U)
\r
18003 /*! RXBRK - Received Break. This bit reflects the current state of the receiver break detection
\r
18004 * logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also
\r
18005 * be set when this condition occurs because the stop bit(s) for the character would be missing.
\r
18006 * RXBRK is cleared when the Un_RXD pin goes high.
\r
18008 #define USART_STAT_RXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK)
\r
18009 #define USART_STAT_DELTARXBRK_MASK (0x800U)
\r
18010 #define USART_STAT_DELTARXBRK_SHIFT (11U)
\r
18011 /*! DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs. Cleared by software.
\r
18013 #define USART_STAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK)
\r
18014 #define USART_STAT_START_MASK (0x1000U)
\r
18015 #define USART_STAT_START_SHIFT (12U)
\r
18016 /*! START - This bit is set when a start is detected on the receiver input. Its purpose is primarily
\r
18017 * to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected.
\r
18018 * Cleared by software.
\r
18020 #define USART_STAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK)
\r
18021 #define USART_STAT_FRAMERRINT_MASK (0x2000U)
\r
18022 #define USART_STAT_FRAMERRINT_SHIFT (13U)
\r
18023 /*! FRAMERRINT - Framing Error interrupt flag. This flag is set when a character is received with a
\r
18024 * missing stop bit at the expected location. This could be an indication of a baud rate or
\r
18025 * configuration mismatch with the transmitting source.
\r
18027 #define USART_STAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK)
\r
18028 #define USART_STAT_PARITYERRINT_MASK (0x4000U)
\r
18029 #define USART_STAT_PARITYERRINT_SHIFT (14U)
\r
18030 /*! PARITYERRINT - Parity Error interrupt flag. This flag is set when a parity error is detected in a received character.
\r
18032 #define USART_STAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK)
\r
18033 #define USART_STAT_RXNOISEINT_MASK (0x8000U)
\r
18034 #define USART_STAT_RXNOISEINT_SHIFT (15U)
\r
18035 /*! RXNOISEINT - Received Noise interrupt flag. Three samples of received data are taken in order to
\r
18036 * determine the value of each received data bit, except in synchronous mode. This acts as a
\r
18037 * noise filter if one sample disagrees. This flag is set when a received data bit contains one
\r
18038 * disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or
\r
18039 * loss of synchronization during data reception.
\r
18041 #define USART_STAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK)
\r
18042 #define USART_STAT_ABERR_MASK (0x10000U)
\r
18043 #define USART_STAT_ABERR_SHIFT (16U)
\r
18044 /*! ABERR - Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the
\r
18045 * end of the start bit that is being measured, essentially an auto baud time-out.
\r
18047 #define USART_STAT_ABERR(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK)
\r
18050 /*! @name INTENSET - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */
\r
18052 #define USART_INTENSET_TXIDLEEN_MASK (0x8U)
\r
18053 #define USART_INTENSET_TXIDLEEN_SHIFT (3U)
\r
18054 /*! TXIDLEEN - When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1).
\r
18056 #define USART_INTENSET_TXIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK)
\r
18057 #define USART_INTENSET_DELTACTSEN_MASK (0x20U)
\r
18058 #define USART_INTENSET_DELTACTSEN_SHIFT (5U)
\r
18059 /*! DELTACTSEN - When 1, enables an interrupt when there is a change in the state of the CTS input.
\r
18061 #define USART_INTENSET_DELTACTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK)
\r
18062 #define USART_INTENSET_TXDISEN_MASK (0x40U)
\r
18063 #define USART_INTENSET_TXDISEN_SHIFT (6U)
\r
18064 /*! TXDISEN - When 1, enables an interrupt when the transmitter is fully disabled as indicated by
\r
18065 * the TXDISINT flag in STAT. See description of the TXDISINT bit for details.
\r
18067 #define USART_INTENSET_TXDISEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK)
\r
18068 #define USART_INTENSET_DELTARXBRKEN_MASK (0x800U)
\r
18069 #define USART_INTENSET_DELTARXBRKEN_SHIFT (11U)
\r
18070 /*! DELTARXBRKEN - When 1, enables an interrupt when a change of state has occurred in the detection
\r
18071 * of a received break condition (break condition asserted or deasserted).
\r
18073 #define USART_INTENSET_DELTARXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK)
\r
18074 #define USART_INTENSET_STARTEN_MASK (0x1000U)
\r
18075 #define USART_INTENSET_STARTEN_SHIFT (12U)
\r
18076 /*! STARTEN - When 1, enables an interrupt when a received start bit has been detected.
\r
18078 #define USART_INTENSET_STARTEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK)
\r
18079 #define USART_INTENSET_FRAMERREN_MASK (0x2000U)
\r
18080 #define USART_INTENSET_FRAMERREN_SHIFT (13U)
\r
18081 /*! FRAMERREN - When 1, enables an interrupt when a framing error has been detected.
\r
18083 #define USART_INTENSET_FRAMERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK)
\r
18084 #define USART_INTENSET_PARITYERREN_MASK (0x4000U)
\r
18085 #define USART_INTENSET_PARITYERREN_SHIFT (14U)
\r
18086 /*! PARITYERREN - When 1, enables an interrupt when a parity error has been detected.
\r
18088 #define USART_INTENSET_PARITYERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK)
\r
18089 #define USART_INTENSET_RXNOISEEN_MASK (0x8000U)
\r
18090 #define USART_INTENSET_RXNOISEEN_SHIFT (15U)
\r
18091 /*! RXNOISEEN - When 1, enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354.
\r
18093 #define USART_INTENSET_RXNOISEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK)
\r
18094 #define USART_INTENSET_ABERREN_MASK (0x10000U)
\r
18095 #define USART_INTENSET_ABERREN_SHIFT (16U)
\r
18096 /*! ABERREN - When 1, enables an interrupt when an auto baud error occurs.
\r
18098 #define USART_INTENSET_ABERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK)
\r
18101 /*! @name INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. */
\r
18103 #define USART_INTENCLR_TXIDLECLR_MASK (0x8U)
\r
18104 #define USART_INTENCLR_TXIDLECLR_SHIFT (3U)
\r
18105 /*! TXIDLECLR - Writing 1 clears the corresponding bit in the INTENSET register.
\r
18107 #define USART_INTENCLR_TXIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK)
\r
18108 #define USART_INTENCLR_DELTACTSCLR_MASK (0x20U)
\r
18109 #define USART_INTENCLR_DELTACTSCLR_SHIFT (5U)
\r
18110 /*! DELTACTSCLR - Writing 1 clears the corresponding bit in the INTENSET register.
\r
18112 #define USART_INTENCLR_DELTACTSCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK)
\r
18113 #define USART_INTENCLR_TXDISCLR_MASK (0x40U)
\r
18114 #define USART_INTENCLR_TXDISCLR_SHIFT (6U)
\r
18115 /*! TXDISCLR - Writing 1 clears the corresponding bit in the INTENSET register.
\r
18117 #define USART_INTENCLR_TXDISCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK)
\r
18118 #define USART_INTENCLR_DELTARXBRKCLR_MASK (0x800U)
\r
18119 #define USART_INTENCLR_DELTARXBRKCLR_SHIFT (11U)
\r
18120 /*! DELTARXBRKCLR - Writing 1 clears the corresponding bit in the INTENSET register.
\r
18122 #define USART_INTENCLR_DELTARXBRKCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK)
\r
18123 #define USART_INTENCLR_STARTCLR_MASK (0x1000U)
\r
18124 #define USART_INTENCLR_STARTCLR_SHIFT (12U)
\r
18125 /*! STARTCLR - Writing 1 clears the corresponding bit in the INTENSET register.
\r
18127 #define USART_INTENCLR_STARTCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK)
\r
18128 #define USART_INTENCLR_FRAMERRCLR_MASK (0x2000U)
\r
18129 #define USART_INTENCLR_FRAMERRCLR_SHIFT (13U)
\r
18130 /*! FRAMERRCLR - Writing 1 clears the corresponding bit in the INTENSET register.
\r
18132 #define USART_INTENCLR_FRAMERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK)
\r
18133 #define USART_INTENCLR_PARITYERRCLR_MASK (0x4000U)
\r
18134 #define USART_INTENCLR_PARITYERRCLR_SHIFT (14U)
\r
18135 /*! PARITYERRCLR - Writing 1 clears the corresponding bit in the INTENSET register.
\r
18137 #define USART_INTENCLR_PARITYERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK)
\r
18138 #define USART_INTENCLR_RXNOISECLR_MASK (0x8000U)
\r
18139 #define USART_INTENCLR_RXNOISECLR_SHIFT (15U)
\r
18140 /*! RXNOISECLR - Writing 1 clears the corresponding bit in the INTENSET register.
\r
18142 #define USART_INTENCLR_RXNOISECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK)
\r
18143 #define USART_INTENCLR_ABERRCLR_MASK (0x10000U)
\r
18144 #define USART_INTENCLR_ABERRCLR_SHIFT (16U)
\r
18145 /*! ABERRCLR - Writing 1 clears the corresponding bit in the INTENSET register.
\r
18147 #define USART_INTENCLR_ABERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK)
\r
18150 /*! @name BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. */
\r
18152 #define USART_BRG_BRGVAL_MASK (0xFFFFU)
\r
18153 #define USART_BRG_BRGVAL_SHIFT (0U)
\r
18154 /*! BRGVAL - This value is used to divide the USART input clock to determine the baud rate, based on
\r
18155 * the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is
\r
18156 * divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART
\r
18157 * function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function.
\r
18159 #define USART_BRG_BRGVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK)
\r
18162 /*! @name INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. */
\r
18164 #define USART_INTSTAT_TXIDLE_MASK (0x8U)
\r
18165 #define USART_INTSTAT_TXIDLE_SHIFT (3U)
\r
18166 /*! TXIDLE - Transmitter Idle status.
\r
18168 #define USART_INTSTAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK)
\r
18169 #define USART_INTSTAT_DELTACTS_MASK (0x20U)
\r
18170 #define USART_INTSTAT_DELTACTS_SHIFT (5U)
\r
18171 /*! DELTACTS - This bit is set when a change in the state of the CTS input is detected.
\r
18173 #define USART_INTSTAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK)
\r
18174 #define USART_INTSTAT_TXDISINT_MASK (0x40U)
\r
18175 #define USART_INTSTAT_TXDISINT_SHIFT (6U)
\r
18176 /*! TXDISINT - Transmitter Disabled Interrupt flag.
\r
18178 #define USART_INTSTAT_TXDISINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK)
\r
18179 #define USART_INTSTAT_DELTARXBRK_MASK (0x800U)
\r
18180 #define USART_INTSTAT_DELTARXBRK_SHIFT (11U)
\r
18181 /*! DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs.
\r
18183 #define USART_INTSTAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK)
\r
18184 #define USART_INTSTAT_START_MASK (0x1000U)
\r
18185 #define USART_INTSTAT_START_SHIFT (12U)
\r
18186 /*! START - This bit is set when a start is detected on the receiver input.
\r
18188 #define USART_INTSTAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK)
\r
18189 #define USART_INTSTAT_FRAMERRINT_MASK (0x2000U)
\r
18190 #define USART_INTSTAT_FRAMERRINT_SHIFT (13U)
\r
18191 /*! FRAMERRINT - Framing Error interrupt flag.
\r
18193 #define USART_INTSTAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK)
\r
18194 #define USART_INTSTAT_PARITYERRINT_MASK (0x4000U)
\r
18195 #define USART_INTSTAT_PARITYERRINT_SHIFT (14U)
\r
18196 /*! PARITYERRINT - Parity Error interrupt flag.
\r
18198 #define USART_INTSTAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK)
\r
18199 #define USART_INTSTAT_RXNOISEINT_MASK (0x8000U)
\r
18200 #define USART_INTSTAT_RXNOISEINT_SHIFT (15U)
\r
18201 /*! RXNOISEINT - Received Noise interrupt flag.
\r
18203 #define USART_INTSTAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK)
\r
18204 #define USART_INTSTAT_ABERRINT_MASK (0x10000U)
\r
18205 #define USART_INTSTAT_ABERRINT_SHIFT (16U)
\r
18206 /*! ABERRINT - Auto baud Error Interrupt flag.
\r
18208 #define USART_INTSTAT_ABERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK)
\r
18211 /*! @name OSR - Oversample selection register for asynchronous communication. */
\r
18213 #define USART_OSR_OSRVAL_MASK (0xFU)
\r
18214 #define USART_OSR_OSRVAL_SHIFT (0U)
\r
18215 /*! OSRVAL - Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to
\r
18216 * transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive
\r
18217 * each data bit. 0xF= 16 function clocks are used to transmit and receive each data bit.
\r
18219 #define USART_OSR_OSRVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK)
\r
18222 /*! @name ADDR - Address register for automatic address matching. */
\r
18224 #define USART_ADDR_ADDRESS_MASK (0xFFU)
\r
18225 #define USART_ADDR_ADDRESS_SHIFT (0U)
\r
18226 /*! ADDRESS - 8-bit address used with automatic address matching. Used when address detection is
\r
18227 * enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1).
\r
18229 #define USART_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK)
\r
18232 /*! @name FIFOCFG - FIFO configuration and enable register. */
\r
18234 #define USART_FIFOCFG_ENABLETX_MASK (0x1U)
\r
18235 #define USART_FIFOCFG_ENABLETX_SHIFT (0U)
\r
18236 /*! ENABLETX - Enable the transmit FIFO.
\r
18237 * 0b0..The transmit FIFO is not enabled.
\r
18238 * 0b1..The transmit FIFO is enabled.
\r
18240 #define USART_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK)
\r
18241 #define USART_FIFOCFG_ENABLERX_MASK (0x2U)
\r
18242 #define USART_FIFOCFG_ENABLERX_SHIFT (1U)
\r
18243 /*! ENABLERX - Enable the receive FIFO.
\r
18244 * 0b0..The receive FIFO is not enabled.
\r
18245 * 0b1..The receive FIFO is enabled.
\r
18247 #define USART_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK)
\r
18248 #define USART_FIFOCFG_SIZE_MASK (0x30U)
\r
18249 #define USART_FIFOCFG_SIZE_SHIFT (4U)
\r
18250 /*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16
\r
18251 * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART.
\r
18253 #define USART_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK)
\r
18254 #define USART_FIFOCFG_DMATX_MASK (0x1000U)
\r
18255 #define USART_FIFOCFG_DMATX_SHIFT (12U)
\r
18256 /*! DMATX - DMA configuration for transmit.
\r
18257 * 0b0..DMA is not used for the transmit function.
\r
18258 * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled.
\r
18260 #define USART_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK)
\r
18261 #define USART_FIFOCFG_DMARX_MASK (0x2000U)
\r
18262 #define USART_FIFOCFG_DMARX_SHIFT (13U)
\r
18263 /*! DMARX - DMA configuration for receive.
\r
18264 * 0b0..DMA is not used for the receive function.
\r
18265 * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled.
\r
18267 #define USART_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK)
\r
18268 #define USART_FIFOCFG_WAKETX_MASK (0x4000U)
\r
18269 #define USART_FIFOCFG_WAKETX_SHIFT (14U)
\r
18270 /*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power
\r
18271 * modes (up to power-down, as long as the peripheral function works in that power mode) without
\r
18272 * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The
\r
18273 * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware
\r
18274 * Wake-up control register.
\r
18275 * 0b0..Only enabled interrupts will wake up the device form reduced power modes.
\r
18276 * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in
\r
18277 * FIFOTRIG, even when the TXLVL interrupt is not enabled.
\r
18279 #define USART_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK)
\r
18280 #define USART_FIFOCFG_WAKERX_MASK (0x8000U)
\r
18281 #define USART_FIFOCFG_WAKERX_SHIFT (15U)
\r
18282 /*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power
\r
18283 * modes (up to power-down, as long as the peripheral function works in that power mode) without
\r
18284 * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The
\r
18285 * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware
\r
18286 * Wake-up control register.
\r
18287 * 0b0..Only enabled interrupts will wake up the device form reduced power modes.
\r
18288 * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in
\r
18289 * FIFOTRIG, even when the RXLVL interrupt is not enabled.
\r
18291 #define USART_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK)
\r
18292 #define USART_FIFOCFG_EMPTYTX_MASK (0x10000U)
\r
18293 #define USART_FIFOCFG_EMPTYTX_SHIFT (16U)
\r
18294 /*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied.
\r
18296 #define USART_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK)
\r
18297 #define USART_FIFOCFG_EMPTYRX_MASK (0x20000U)
\r
18298 #define USART_FIFOCFG_EMPTYRX_SHIFT (17U)
\r
18299 /*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied.
\r
18301 #define USART_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK)
\r
18304 /*! @name FIFOSTAT - FIFO status register. */
\r
18306 #define USART_FIFOSTAT_TXERR_MASK (0x1U)
\r
18307 #define USART_FIFOSTAT_TXERR_SHIFT (0U)
\r
18308 /*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow
\r
18309 * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is
\r
18310 * needed. Cleared by writing a 1 to this bit.
\r
18312 #define USART_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK)
\r
18313 #define USART_FIFOSTAT_RXERR_MASK (0x2U)
\r
18314 #define USART_FIFOSTAT_RXERR_SHIFT (1U)
\r
18315 /*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA
\r
18316 * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit.
\r
18318 #define USART_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK)
\r
18319 #define USART_FIFOSTAT_PERINT_MASK (0x8U)
\r
18320 #define USART_FIFOSTAT_PERINT_SHIFT (3U)
\r
18321 /*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted
\r
18322 * an interrupt. The details can be found by reading the peripheral's STAT register.
\r
18324 #define USART_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK)
\r
18325 #define USART_FIFOSTAT_TXEMPTY_MASK (0x10U)
\r
18326 #define USART_FIFOSTAT_TXEMPTY_SHIFT (4U)
\r
18327 /*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data.
\r
18329 #define USART_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK)
\r
18330 #define USART_FIFOSTAT_TXNOTFULL_MASK (0x20U)
\r
18331 #define USART_FIFOSTAT_TXNOTFULL_SHIFT (5U)
\r
18332 /*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be
\r
18333 * written. When 0, the transmit FIFO is full and another write would cause it to overflow.
\r
18335 #define USART_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK)
\r
18336 #define USART_FIFOSTAT_RXNOTEMPTY_MASK (0x40U)
\r
18337 #define USART_FIFOSTAT_RXNOTEMPTY_SHIFT (6U)
\r
18338 /*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty.
\r
18340 #define USART_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK)
\r
18341 #define USART_FIFOSTAT_RXFULL_MASK (0x80U)
\r
18342 #define USART_FIFOSTAT_RXFULL_SHIFT (7U)
\r
18343 /*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to
\r
18344 * prevent the peripheral from causing an overflow.
\r
18346 #define USART_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK)
\r
18347 #define USART_FIFOSTAT_TXLVL_MASK (0x1F00U)
\r
18348 #define USART_FIFOSTAT_TXLVL_SHIFT (8U)
\r
18349 /*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY
\r
18350 * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at
\r
18351 * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be
\r
18354 #define USART_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK)
\r
18355 #define USART_FIFOSTAT_RXLVL_MASK (0x1F0000U)
\r
18356 #define USART_FIFOSTAT_RXLVL_SHIFT (16U)
\r
18357 /*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and
\r
18358 * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the
\r
18359 * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be
\r
18362 #define USART_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK)
\r
18365 /*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */
\r
18367 #define USART_FIFOTRIG_TXLVLENA_MASK (0x1U)
\r
18368 #define USART_FIFOTRIG_TXLVLENA_SHIFT (0U)
\r
18369 /*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled
\r
18370 * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set.
\r
18371 * 0b0..Transmit FIFO level does not generate a FIFO level trigger.
\r
18372 * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register.
\r
18374 #define USART_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK)
\r
18375 #define USART_FIFOTRIG_RXLVLENA_MASK (0x2U)
\r
18376 #define USART_FIFOTRIG_RXLVLENA_SHIFT (1U)
\r
18377 /*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled
\r
18378 * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set.
\r
18379 * 0b0..Receive FIFO level does not generate a FIFO level trigger.
\r
18380 * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register.
\r
18382 #define USART_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK)
\r
18383 #define USART_FIFOTRIG_TXLVL_MASK (0xF00U)
\r
18384 #define USART_FIFOTRIG_TXLVL_SHIFT (8U)
\r
18385 /*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled
\r
18386 * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to
\r
18387 * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO
\r
18388 * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX
\r
18389 * FIFO level decreases to 15 entries (is no longer full).
\r
18391 #define USART_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK)
\r
18392 #define USART_FIFOTRIG_RXLVL_MASK (0xF0000U)
\r
18393 #define USART_FIFOTRIG_RXLVL_SHIFT (16U)
\r
18394 /*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data
\r
18395 * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level
\r
18396 * can wake up the device just enough to perform DMA, then return to the reduced power mode. See
\r
18397 * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no
\r
18398 * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX
\r
18399 * FIFO has received 16 entries (has become full).
\r
18401 #define USART_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK)
\r
18404 /*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */
\r
18406 #define USART_FIFOINTENSET_TXERR_MASK (0x1U)
\r
18407 #define USART_FIFOINTENSET_TXERR_SHIFT (0U)
\r
18408 /*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register.
\r
18409 * 0b0..No interrupt will be generated for a transmit error.
\r
18410 * 0b1..An interrupt will be generated when a transmit error occurs.
\r
18412 #define USART_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK)
\r
18413 #define USART_FIFOINTENSET_RXERR_MASK (0x2U)
\r
18414 #define USART_FIFOINTENSET_RXERR_SHIFT (1U)
\r
18415 /*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register.
\r
18416 * 0b0..No interrupt will be generated for a receive error.
\r
18417 * 0b1..An interrupt will be generated when a receive error occurs.
\r
18419 #define USART_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK)
\r
18420 #define USART_FIFOINTENSET_TXLVL_MASK (0x4U)
\r
18421 #define USART_FIFOINTENSET_TXLVL_SHIFT (2U)
\r
18422 /*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level
\r
18423 * specified by the TXLVL field in the FIFOTRIG register.
\r
18424 * 0b0..No interrupt will be generated based on the TX FIFO level.
\r
18425 * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases
\r
18426 * to the level specified by TXLVL in the FIFOTRIG register.
\r
18428 #define USART_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK)
\r
18429 #define USART_FIFOINTENSET_RXLVL_MASK (0x8U)
\r
18430 #define USART_FIFOINTENSET_RXLVL_SHIFT (3U)
\r
18431 /*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level
\r
18432 * specified by the TXLVL field in the FIFOTRIG register.
\r
18433 * 0b0..No interrupt will be generated based on the RX FIFO level.
\r
18434 * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level
\r
18435 * increases to the level specified by RXLVL in the FIFOTRIG register.
\r
18437 #define USART_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK)
\r
18440 /*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */
\r
18442 #define USART_FIFOINTENCLR_TXERR_MASK (0x1U)
\r
18443 #define USART_FIFOINTENCLR_TXERR_SHIFT (0U)
\r
18444 /*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register.
\r
18446 #define USART_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK)
\r
18447 #define USART_FIFOINTENCLR_RXERR_MASK (0x2U)
\r
18448 #define USART_FIFOINTENCLR_RXERR_SHIFT (1U)
\r
18449 /*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register.
\r
18451 #define USART_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK)
\r
18452 #define USART_FIFOINTENCLR_TXLVL_MASK (0x4U)
\r
18453 #define USART_FIFOINTENCLR_TXLVL_SHIFT (2U)
\r
18454 /*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register.
\r
18456 #define USART_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK)
\r
18457 #define USART_FIFOINTENCLR_RXLVL_MASK (0x8U)
\r
18458 #define USART_FIFOINTENCLR_RXLVL_SHIFT (3U)
\r
18459 /*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register.
\r
18461 #define USART_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK)
\r
18464 /*! @name FIFOINTSTAT - FIFO interrupt status register. */
\r
18466 #define USART_FIFOINTSTAT_TXERR_MASK (0x1U)
\r
18467 #define USART_FIFOINTSTAT_TXERR_SHIFT (0U)
\r
18468 /*! TXERR - TX FIFO error.
\r
18470 #define USART_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK)
\r
18471 #define USART_FIFOINTSTAT_RXERR_MASK (0x2U)
\r
18472 #define USART_FIFOINTSTAT_RXERR_SHIFT (1U)
\r
18473 /*! RXERR - RX FIFO error.
\r
18475 #define USART_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK)
\r
18476 #define USART_FIFOINTSTAT_TXLVL_MASK (0x4U)
\r
18477 #define USART_FIFOINTSTAT_TXLVL_SHIFT (2U)
\r
18478 /*! TXLVL - Transmit FIFO level interrupt.
\r
18480 #define USART_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK)
\r
18481 #define USART_FIFOINTSTAT_RXLVL_MASK (0x8U)
\r
18482 #define USART_FIFOINTSTAT_RXLVL_SHIFT (3U)
\r
18483 /*! RXLVL - Receive FIFO level interrupt.
\r
18485 #define USART_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK)
\r
18486 #define USART_FIFOINTSTAT_PERINT_MASK (0x10U)
\r
18487 #define USART_FIFOINTSTAT_PERINT_SHIFT (4U)
\r
18488 /*! PERINT - Peripheral interrupt.
\r
18490 #define USART_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK)
\r
18493 /*! @name FIFOWR - FIFO write data. */
\r
18495 #define USART_FIFOWR_TXDATA_MASK (0x1FFU)
\r
18496 #define USART_FIFOWR_TXDATA_SHIFT (0U)
\r
18497 /*! TXDATA - Transmit data to the FIFO.
\r
18499 #define USART_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK)
\r
18502 /*! @name FIFORD - FIFO read data. */
\r
18504 #define USART_FIFORD_RXDATA_MASK (0x1FFU)
\r
18505 #define USART_FIFORD_RXDATA_SHIFT (0U)
\r
18506 /*! RXDATA - Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings.
\r
18508 #define USART_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK)
\r
18509 #define USART_FIFORD_FRAMERR_MASK (0x2000U)
\r
18510 #define USART_FIFORD_FRAMERR_SHIFT (13U)
\r
18511 /*! FRAMERR - Framing Error status flag. This bit reflects the status for the data it is read along
\r
18512 * with from the FIFO, and indicates that the character was received with a missing stop bit at
\r
18513 * the expected location. This could be an indication of a baud rate or configuration mismatch
\r
18514 * with the transmitting source.
\r
18516 #define USART_FIFORD_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK)
\r
18517 #define USART_FIFORD_PARITYERR_MASK (0x4000U)
\r
18518 #define USART_FIFORD_PARITYERR_SHIFT (14U)
\r
18519 /*! PARITYERR - Parity Error status flag. This bit reflects the status for the data it is read along
\r
18520 * with from the FIFO. This bit will be set when a parity error is detected in a received
\r
18523 #define USART_FIFORD_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK)
\r
18524 #define USART_FIFORD_RXNOISE_MASK (0x8000U)
\r
18525 #define USART_FIFORD_RXNOISE_SHIFT (15U)
\r
18526 /*! RXNOISE - Received Noise flag. See description of the RxNoiseInt bit in Table 354.
\r
18528 #define USART_FIFORD_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK)
\r
18531 /*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */
\r
18533 #define USART_FIFORDNOPOP_RXDATA_MASK (0x1FFU)
\r
18534 #define USART_FIFORDNOPOP_RXDATA_SHIFT (0U)
\r
18535 /*! RXDATA - Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings.
\r
18537 #define USART_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK)
\r
18538 #define USART_FIFORDNOPOP_FRAMERR_MASK (0x2000U)
\r
18539 #define USART_FIFORDNOPOP_FRAMERR_SHIFT (13U)
\r
18540 /*! FRAMERR - Framing Error status flag. This bit reflects the status for the data it is read along
\r
18541 * with from the FIFO, and indicates that the character was received with a missing stop bit at
\r
18542 * the expected location. This could be an indication of a baud rate or configuration mismatch
\r
18543 * with the transmitting source.
\r
18545 #define USART_FIFORDNOPOP_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK)
\r
18546 #define USART_FIFORDNOPOP_PARITYERR_MASK (0x4000U)
\r
18547 #define USART_FIFORDNOPOP_PARITYERR_SHIFT (14U)
\r
18548 /*! PARITYERR - Parity Error status flag. This bit reflects the status for the data it is read along
\r
18549 * with from the FIFO. This bit will be set when a parity error is detected in a received
\r
18552 #define USART_FIFORDNOPOP_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK)
\r
18553 #define USART_FIFORDNOPOP_RXNOISE_MASK (0x8000U)
\r
18554 #define USART_FIFORDNOPOP_RXNOISE_SHIFT (15U)
\r
18555 /*! RXNOISE - Received Noise flag. See description of the RxNoiseInt bit in Table 354.
\r
18557 #define USART_FIFORDNOPOP_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK)
\r
18560 /*! @name ID - Peripheral identification register. */
\r
18562 #define USART_ID_APERTURE_MASK (0xFFU)
\r
18563 #define USART_ID_APERTURE_SHIFT (0U)
\r
18564 /*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture.
\r
18566 #define USART_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_APERTURE_SHIFT)) & USART_ID_APERTURE_MASK)
\r
18567 #define USART_ID_MINOR_REV_MASK (0xF00U)
\r
18568 #define USART_ID_MINOR_REV_SHIFT (8U)
\r
18569 /*! MINOR_REV - Minor revision of module implementation.
\r
18571 #define USART_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MINOR_REV_SHIFT)) & USART_ID_MINOR_REV_MASK)
\r
18572 #define USART_ID_MAJOR_REV_MASK (0xF000U)
\r
18573 #define USART_ID_MAJOR_REV_SHIFT (12U)
\r
18574 /*! MAJOR_REV - Major revision of module implementation.
\r
18576 #define USART_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MAJOR_REV_SHIFT)) & USART_ID_MAJOR_REV_MASK)
\r
18577 #define USART_ID_ID_MASK (0xFFFF0000U)
\r
18578 #define USART_ID_ID_SHIFT (16U)
\r
18579 /*! ID - Module identifier for the selected function.
\r
18581 #define USART_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_ID_SHIFT)) & USART_ID_ID_MASK)
\r
18587 */ /* end of group USART_Register_Masks */
\r
18590 /* USART - Peripheral instance base addresses */
\r
18591 /** Peripheral USART0 base address */
\r
18592 #define USART0_BASE (0x40086000u)
\r
18593 /** Peripheral USART0 base pointer */
\r
18594 #define USART0 ((USART_Type *)USART0_BASE)
\r
18595 /** Peripheral USART1 base address */
\r
18596 #define USART1_BASE (0x40087000u)
\r
18597 /** Peripheral USART1 base pointer */
\r
18598 #define USART1 ((USART_Type *)USART1_BASE)
\r
18599 /** Peripheral USART2 base address */
\r
18600 #define USART2_BASE (0x40088000u)
\r
18601 /** Peripheral USART2 base pointer */
\r
18602 #define USART2 ((USART_Type *)USART2_BASE)
\r
18603 /** Peripheral USART3 base address */
\r
18604 #define USART3_BASE (0x40089000u)
\r
18605 /** Peripheral USART3 base pointer */
\r
18606 #define USART3 ((USART_Type *)USART3_BASE)
\r
18607 /** Peripheral USART4 base address */
\r
18608 #define USART4_BASE (0x4008A000u)
\r
18609 /** Peripheral USART4 base pointer */
\r
18610 #define USART4 ((USART_Type *)USART4_BASE)
\r
18611 /** Peripheral USART5 base address */
\r
18612 #define USART5_BASE (0x40096000u)
\r
18613 /** Peripheral USART5 base pointer */
\r
18614 #define USART5 ((USART_Type *)USART5_BASE)
\r
18615 /** Peripheral USART6 base address */
\r
18616 #define USART6_BASE (0x40097000u)
\r
18617 /** Peripheral USART6 base pointer */
\r
18618 #define USART6 ((USART_Type *)USART6_BASE)
\r
18619 /** Peripheral USART7 base address */
\r
18620 #define USART7_BASE (0x40098000u)
\r
18621 /** Peripheral USART7 base pointer */
\r
18622 #define USART7 ((USART_Type *)USART7_BASE)
\r
18623 /** Peripheral USART8 base address */
\r
18624 #define USART8_BASE (0x40099000u)
\r
18625 /** Peripheral USART8 base pointer */
\r
18626 #define USART8 ((USART_Type *)USART8_BASE)
\r
18627 /** Peripheral USART9 base address */
\r
18628 #define USART9_BASE (0x4009A000u)
\r
18629 /** Peripheral USART9 base pointer */
\r
18630 #define USART9 ((USART_Type *)USART9_BASE)
\r
18631 /** Array initializer of USART peripheral base addresses */
\r
18632 #define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE, USART8_BASE, USART9_BASE }
\r
18633 /** Array initializer of USART peripheral base pointers */
\r
18634 #define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7, USART8, USART9 }
\r
18635 /** Interrupt vectors for the USART peripheral type */
\r
18636 #define USART_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn }
\r
18640 */ /* end of group USART_Peripheral_Access_Layer */
\r
18643 /* ----------------------------------------------------------------------------
\r
18644 -- USB Peripheral Access Layer
\r
18645 ---------------------------------------------------------------------------- */
\r
18648 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
\r
18652 /** USB - Register Layout Typedef */
\r
18654 __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */
\r
18655 __IO uint32_t INFO; /**< USB Info register, offset: 0x4 */
\r
18656 __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */
\r
18657 __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */
\r
18658 __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */
\r
18659 __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */
\r
18660 __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */
\r
18661 __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */
\r
18662 __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */
\r
18663 __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */
\r
18664 __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */
\r
18665 uint8_t RESERVED_0[8];
\r
18666 __IO uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */
\r
18669 /* ----------------------------------------------------------------------------
\r
18670 -- USB Register Masks
\r
18671 ---------------------------------------------------------------------------- */
\r
18674 * @addtogroup USB_Register_Masks USB Register Masks
\r
18678 /*! @name DEVCMDSTAT - USB Device Command/Status register */
\r
18680 #define USB_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU)
\r
18681 #define USB_DEVCMDSTAT_DEV_ADDR_SHIFT (0U)
\r
18682 /*! DEV_ADDR - USB device address. After bus reset, the address is reset to 0x00. If the enable bit
\r
18683 * is set, the device will respond on packets for function address DEV_ADDR. When receiving a
\r
18684 * SetAddress Control Request from the USB host, software must program the new address before
\r
18685 * completing the status phase of the SetAddress Control Request.
\r
18687 #define USB_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USB_DEVCMDSTAT_DEV_ADDR_MASK)
\r
18688 #define USB_DEVCMDSTAT_DEV_EN_MASK (0x80U)
\r
18689 #define USB_DEVCMDSTAT_DEV_EN_SHIFT (7U)
\r
18690 /*! DEV_EN - USB device enable. If this bit is set, the HW will start responding on packets for function address DEV_ADDR.
\r
18692 #define USB_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_EN_SHIFT)) & USB_DEVCMDSTAT_DEV_EN_MASK)
\r
18693 #define USB_DEVCMDSTAT_SETUP_MASK (0x100U)
\r
18694 #define USB_DEVCMDSTAT_SETUP_SHIFT (8U)
\r
18695 /*! SETUP - SETUP token received. If a SETUP token is received and acknowledged by the device, this
\r
18696 * bit is set. As long as this bit is set all received IN and OUT tokens will be NAKed by HW. SW
\r
18697 * must clear this bit by writing a one. If this bit is zero, HW will handle the tokens to the
\r
18698 * CTRL EP0 as indicated by the CTRL EP0 IN and OUT data information programmed by SW.
\r
18700 #define USB_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_SETUP_SHIFT)) & USB_DEVCMDSTAT_SETUP_MASK)
\r
18701 #define USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U)
\r
18702 #define USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U)
\r
18703 /*! FORCE_NEEDCLK - Forces the NEEDCLK output to always be on:
\r
18704 * 0b0..USB_NEEDCLK has normal function.
\r
18705 * 0b1..USB_NEEDCLK always 1. Clock will not be stopped in case of suspend.
\r
18707 #define USB_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK)
\r
18708 #define USB_DEVCMDSTAT_LPM_SUP_MASK (0x800U)
\r
18709 #define USB_DEVCMDSTAT_LPM_SUP_SHIFT (11U)
\r
18710 /*! LPM_SUP - LPM Supported:
\r
18711 * 0b0..LPM not supported.
\r
18712 * 0b1..LPM supported.
\r
18714 #define USB_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUP_SHIFT)) & USB_DEVCMDSTAT_LPM_SUP_MASK)
\r
18715 #define USB_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U)
\r
18716 #define USB_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U)
\r
18717 /*! INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP
\r
18718 * 0b0..Only acknowledged packets generate an interrupt
\r
18719 * 0b1..Both acknowledged and NAKed packets generate interrupts.
\r
18721 #define USB_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AO_MASK)
\r
18722 #define USB_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U)
\r
18723 #define USB_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U)
\r
18724 /*! INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP
\r
18725 * 0b0..Only acknowledged packets generate an interrupt
\r
18726 * 0b1..Both acknowledged and NAKed packets generate interrupts.
\r
18728 #define USB_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AI_MASK)
\r
18729 #define USB_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U)
\r
18730 #define USB_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U)
\r
18731 /*! INTONNAK_CO - Interrupt on NAK for control OUT EP
\r
18732 * 0b0..Only acknowledged packets generate an interrupt
\r
18733 * 0b1..Both acknowledged and NAKed packets generate interrupts.
\r
18735 #define USB_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CO_MASK)
\r
18736 #define USB_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U)
\r
18737 #define USB_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U)
\r
18738 /*! INTONNAK_CI - Interrupt on NAK for control IN EP
\r
18739 * 0b0..Only acknowledged packets generate an interrupt
\r
18740 * 0b1..Both acknowledged and NAKed packets generate interrupts.
\r
18742 #define USB_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CI_MASK)
\r
18743 #define USB_DEVCMDSTAT_DCON_MASK (0x10000U)
\r
18744 #define USB_DEVCMDSTAT_DCON_SHIFT (16U)
\r
18745 /*! DCON - Device status - connect. The connect bit must be set by SW to indicate that the device
\r
18746 * must signal a connect. The pull-up resistor on USB_DP will be enabled when this bit is set and
\r
18747 * the VBUSDEBOUNCED bit is one.
\r
18749 #define USB_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_SHIFT)) & USB_DEVCMDSTAT_DCON_MASK)
\r
18750 #define USB_DEVCMDSTAT_DSUS_MASK (0x20000U)
\r
18751 #define USB_DEVCMDSTAT_DSUS_SHIFT (17U)
\r
18752 /*! DSUS - Device status - suspend. The suspend bit indicates the current suspend state. It is set
\r
18753 * to 1 when the device hasn't seen any activity on its upstream port for more than 3
\r
18754 * milliseconds. It is reset to 0 on any activity. When the device is suspended (Suspend bit DSUS = 1) and
\r
18755 * the software writes a 0 to it, the device will generate a remote wake-up. This will only happen
\r
18756 * when the device is connected (Connect bit = 1). When the device is not connected or not
\r
18757 * suspended, a writing a 0 has no effect. Writing a 1 never has an effect.
\r
18759 #define USB_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_SHIFT)) & USB_DEVCMDSTAT_DSUS_MASK)
\r
18760 #define USB_DEVCMDSTAT_LPM_SUS_MASK (0x80000U)
\r
18761 #define USB_DEVCMDSTAT_LPM_SUS_SHIFT (19U)
\r
18762 /*! LPM_SUS - Device status - LPM Suspend. This bit represents the current LPM suspend state. It is
\r
18763 * set to 1 by HW when the device has acknowledged the LPM request from the USB host and the
\r
18764 * Token Retry Time of 10 ms has elapsed. When the device is in the LPM suspended state (LPM suspend
\r
18765 * bit = 1) and the software writes a zero to this bit, the device will generate a remote
\r
18766 * walk-up. Software can only write a zero to this bit when the LPM_REWP bit is set to 1. HW resets this
\r
18767 * bit when it receives a host initiated resume. HW only updates the LPM_SUS bit when the
\r
18768 * LPM_SUPP bit is equal to one.
\r
18770 #define USB_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUS_SHIFT)) & USB_DEVCMDSTAT_LPM_SUS_MASK)
\r
18771 #define USB_DEVCMDSTAT_LPM_REWP_MASK (0x100000U)
\r
18772 #define USB_DEVCMDSTAT_LPM_REWP_SHIFT (20U)
\r
18773 /*! LPM_REWP - LPM Remote Wake-up Enabled by USB host. HW sets this bit to one when the bRemoteWake
\r
18774 * bit in the LPM extended token is set to 1. HW will reset this bit to 0 when it receives the
\r
18775 * host initiated LPM resume, when a remote wake-up is sent by the device or when a USB bus reset
\r
18776 * is received. Software can use this bit to check if the remote wake-up feature is enabled by the
\r
18777 * host for the LPM transaction.
\r
18779 #define USB_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_REWP_SHIFT)) & USB_DEVCMDSTAT_LPM_REWP_MASK)
\r
18780 #define USB_DEVCMDSTAT_DCON_C_MASK (0x1000000U)
\r
18781 #define USB_DEVCMDSTAT_DCON_C_SHIFT (24U)
\r
18782 /*! DCON_C - Device status - connect change. The Connect Change bit is set when the device's pull-up
\r
18783 * resistor is disconnected because VBus disappeared. The bit is reset by writing a one to it.
\r
18785 #define USB_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_C_SHIFT)) & USB_DEVCMDSTAT_DCON_C_MASK)
\r
18786 #define USB_DEVCMDSTAT_DSUS_C_MASK (0x2000000U)
\r
18787 #define USB_DEVCMDSTAT_DSUS_C_SHIFT (25U)
\r
18788 /*! DSUS_C - Device status - suspend change. The suspend change bit is set to 1 when the suspend bit
\r
18789 * toggles. The suspend bit can toggle because: - The device goes in the suspended state - The
\r
18790 * device is disconnected - The device receives resume signaling on its upstream port. The bit is
\r
18791 * reset by writing a one to it.
\r
18793 #define USB_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_C_SHIFT)) & USB_DEVCMDSTAT_DSUS_C_MASK)
\r
18794 #define USB_DEVCMDSTAT_DRES_C_MASK (0x4000000U)
\r
18795 #define USB_DEVCMDSTAT_DRES_C_SHIFT (26U)
\r
18796 /*! DRES_C - Device status - reset change. This bit is set when the device received a bus reset. On
\r
18797 * a bus reset the device will automatically go to the default state (unconfigured and responding
\r
18798 * to address 0). The bit is reset by writing a one to it.
\r
18800 #define USB_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DRES_C_SHIFT)) & USB_DEVCMDSTAT_DRES_C_MASK)
\r
18801 #define USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK (0x10000000U)
\r
18802 #define USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT (28U)
\r
18803 /*! VBUSDEBOUNCED - This bit indicates if Vbus is detected or not. The bit raises immediately when
\r
18804 * Vbus becomes high. It drops to zero if Vbus is low for at least 3 ms. If this bit is high and
\r
18805 * the DCon bit is set, the HW will enable the pull-up resistor to signal a connect.
\r
18807 #define USB_DEVCMDSTAT_VBUSDEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT)) & USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK)
\r
18810 /*! @name INFO - USB Info register */
\r
18812 #define USB_INFO_FRAME_NR_MASK (0x7FFU)
\r
18813 #define USB_INFO_FRAME_NR_SHIFT (0U)
\r
18814 /*! FRAME_NR - Frame number. This contains the frame number of the last successfully received SOF.
\r
18815 * In case no SOF was received by the device at the beginning of a frame, the frame number
\r
18816 * returned is that of the last successfully received SOF. In case the SOF frame number contained a CRC
\r
18817 * error, the frame number returned will be the corrupted frame number as received by the device.
\r
18819 #define USB_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_FRAME_NR_SHIFT)) & USB_INFO_FRAME_NR_MASK)
\r
18820 #define USB_INFO_ERR_CODE_MASK (0x7800U)
\r
18821 #define USB_INFO_ERR_CODE_SHIFT (11U)
\r
18822 /*! ERR_CODE - The error code which last occurred:
\r
18823 * 0b0000..No error
\r
18824 * 0b0001..PID encoding error
\r
18825 * 0b0010..PID unknown
\r
18826 * 0b0011..Packet unexpected
\r
18827 * 0b0100..Token CRC error
\r
18828 * 0b0101..Data CRC error
\r
18829 * 0b0110..Time out
\r
18831 * 0b1000..Truncated EOP
\r
18832 * 0b1001..Sent/Received NAK
\r
18833 * 0b1010..Sent Stall
\r
18834 * 0b1011..Overrun
\r
18835 * 0b1100..Sent empty packet
\r
18836 * 0b1101..Bitstuff error
\r
18837 * 0b1110..Sync error
\r
18838 * 0b1111..Wrong data toggle
\r
18840 #define USB_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_ERR_CODE_SHIFT)) & USB_INFO_ERR_CODE_MASK)
\r
18841 #define USB_INFO_MINREV_MASK (0xFF0000U)
\r
18842 #define USB_INFO_MINREV_SHIFT (16U)
\r
18843 /*! MINREV - Minor Revision.
\r
18845 #define USB_INFO_MINREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MINREV_SHIFT)) & USB_INFO_MINREV_MASK)
\r
18846 #define USB_INFO_MAJREV_MASK (0xFF000000U)
\r
18847 #define USB_INFO_MAJREV_SHIFT (24U)
\r
18848 /*! MAJREV - Major Revision.
\r
18850 #define USB_INFO_MAJREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MAJREV_SHIFT)) & USB_INFO_MAJREV_MASK)
\r
18853 /*! @name EPLISTSTART - USB EP Command/Status List start address */
\r
18855 #define USB_EPLISTSTART_EP_LIST_MASK (0xFFFFFF00U)
\r
18856 #define USB_EPLISTSTART_EP_LIST_SHIFT (8U)
\r
18857 /*! EP_LIST - Start address of the USB EP Command/Status List.
\r
18859 #define USB_EPLISTSTART_EP_LIST(x) (((uint32_t)(((uint32_t)(x)) << USB_EPLISTSTART_EP_LIST_SHIFT)) & USB_EPLISTSTART_EP_LIST_MASK)
\r
18862 /*! @name DATABUFSTART - USB Data buffer start address */
\r
18864 #define USB_DATABUFSTART_DA_BUF_MASK (0xFFC00000U)
\r
18865 #define USB_DATABUFSTART_DA_BUF_SHIFT (22U)
\r
18866 /*! DA_BUF - Start address of the buffer pointer page where all endpoint data buffers are located.
\r
18868 #define USB_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_DATABUFSTART_DA_BUF_SHIFT)) & USB_DATABUFSTART_DA_BUF_MASK)
\r
18871 /*! @name LPM - USB Link Power Management register */
\r
18873 #define USB_LPM_HIRD_HW_MASK (0xFU)
\r
18874 #define USB_LPM_HIRD_HW_SHIFT (0U)
\r
18875 /*! HIRD_HW - Host Initiated Resume Duration - HW. This is the HIRD value from the last received LPM token
\r
18877 #define USB_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_HW_SHIFT)) & USB_LPM_HIRD_HW_MASK)
\r
18878 #define USB_LPM_HIRD_SW_MASK (0xF0U)
\r
18879 #define USB_LPM_HIRD_SW_SHIFT (4U)
\r
18880 /*! HIRD_SW - Host Initiated Resume Duration - SW. This is the time duration required by the USB
\r
18881 * device system to come out of LPM initiated suspend after receiving the host initiated LPM resume.
\r
18883 #define USB_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_SW_SHIFT)) & USB_LPM_HIRD_SW_MASK)
\r
18884 #define USB_LPM_DATA_PENDING_MASK (0x100U)
\r
18885 #define USB_LPM_DATA_PENDING_SHIFT (8U)
\r
18886 /*! DATA_PENDING - As long as this bit is set to one and LPM supported bit is set to one, HW will
\r
18887 * return a NYET handshake on every LPM token it receives. If LPM supported bit is set to one and
\r
18888 * this bit is zero, HW will return an ACK handshake on every LPM token it receives. If SW has
\r
18889 * still data pending and LPM is supported, it must set this bit to 1.
\r
18891 #define USB_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_DATA_PENDING_SHIFT)) & USB_LPM_DATA_PENDING_MASK)
\r
18894 /*! @name EPSKIP - USB Endpoint skip */
\r
18896 #define USB_EPSKIP_SKIP_MASK (0x3FFU)
\r
18897 #define USB_EPSKIP_SKIP_SHIFT (0U)
\r
18898 /*! SKIP - Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must
\r
18899 * deactivate the buffer assigned to this endpoint and return control back to software. When HW has
\r
18900 * deactivated the endpoint, it will clear this bit, but it will not modify the EPINUSE bit. An
\r
18901 * interrupt will be generated when the Active bit goes from 1 to 0. Note: In case of double-buffering,
\r
18902 * HW will only clear the Active bit of the buffer indicated by the EPINUSE bit.
\r
18904 #define USB_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USB_EPSKIP_SKIP_SHIFT)) & USB_EPSKIP_SKIP_MASK)
\r
18907 /*! @name EPINUSE - USB Endpoint Buffer in use */
\r
18909 #define USB_EPINUSE_BUF_MASK (0x3FCU)
\r
18910 #define USB_EPINUSE_BUF_SHIFT (2U)
\r
18911 /*! BUF - Buffer in use: This register has one bit per physical endpoint. 0: HW is accessing buffer
\r
18912 * 0. 1: HW is accessing buffer 1.
\r
18914 #define USB_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_EPINUSE_BUF_SHIFT)) & USB_EPINUSE_BUF_MASK)
\r
18917 /*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */
\r
18919 #define USB_EPBUFCFG_BUF_SB_MASK (0x3FCU)
\r
18920 #define USB_EPBUFCFG_BUF_SB_SHIFT (2U)
\r
18921 /*! BUF_SB - Buffer usage: This register has one bit per physical endpoint. 0: Single-buffer. 1:
\r
18922 * Double-buffer. If the bit is set to single-buffer (0), it will not toggle the corresponding
\r
18923 * EPINUSE bit when it clears the active bit. If the bit is set to double-buffer (1), HW will toggle
\r
18924 * the EPINUSE bit when it clears the Active bit for the buffer.
\r
18926 #define USB_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USB_EPBUFCFG_BUF_SB_SHIFT)) & USB_EPBUFCFG_BUF_SB_MASK)
\r
18929 /*! @name INTSTAT - USB interrupt status register */
\r
18931 #define USB_INTSTAT_EP0OUT_MASK (0x1U)
\r
18932 #define USB_INTSTAT_EP0OUT_SHIFT (0U)
\r
18933 /*! EP0OUT - Interrupt status register bit for the Control EP0 OUT direction. This bit will be set
\r
18934 * if NBytes transitions to zero or the skip bit is set by software or a SETUP packet is
\r
18935 * successfully received for the control EP0. If the IntOnNAK_CO is set, this bit will also be set when a
\r
18936 * NAK is transmitted for the Control EP0 OUT direction. Software can clear this bit by writing a
\r
18939 #define USB_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0OUT_SHIFT)) & USB_INTSTAT_EP0OUT_MASK)
\r
18940 #define USB_INTSTAT_EP0IN_MASK (0x2U)
\r
18941 #define USB_INTSTAT_EP0IN_SHIFT (1U)
\r
18942 /*! EP0IN - Interrupt status register bit for the Control EP0 IN direction. This bit will be set if
\r
18943 * NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_CI is set, this
\r
18944 * bit will also be set when a NAK is transmitted for the Control EP0 IN direction. Software can
\r
18945 * clear this bit by writing a one to it.
\r
18947 #define USB_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0IN_SHIFT)) & USB_INTSTAT_EP0IN_MASK)
\r
18948 #define USB_INTSTAT_EP1OUT_MASK (0x4U)
\r
18949 #define USB_INTSTAT_EP1OUT_SHIFT (2U)
\r
18950 /*! EP1OUT - Interrupt status register bit for the EP1 OUT direction. This bit will be set if the
\r
18951 * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes
\r
18952 * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be
\r
18953 * set when a NAK is transmitted for the EP1 OUT direction. Software can clear this bit by
\r
18954 * writing a one to it.
\r
18956 #define USB_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1OUT_SHIFT)) & USB_INTSTAT_EP1OUT_MASK)
\r
18957 #define USB_INTSTAT_EP1IN_MASK (0x8U)
\r
18958 #define USB_INTSTAT_EP1IN_SHIFT (3U)
\r
18959 /*! EP1IN - Interrupt status register bit for the EP1 IN direction. This bit will be set if the
\r
18960 * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions
\r
18961 * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be
\r
18962 * set when a NAK is transmitted for the EP1 IN direction. Software can clear this bit by writing
\r
18965 #define USB_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1IN_SHIFT)) & USB_INTSTAT_EP1IN_MASK)
\r
18966 #define USB_INTSTAT_EP2OUT_MASK (0x10U)
\r
18967 #define USB_INTSTAT_EP2OUT_SHIFT (4U)
\r
18968 /*! EP2OUT - Interrupt status register bit for the EP2 OUT direction. This bit will be set if the
\r
18969 * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes
\r
18970 * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be
\r
18971 * set when a NAK is transmitted for the EP2 OUT direction. Software can clear this bit by
\r
18972 * writing a one to it.
\r
18974 #define USB_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2OUT_SHIFT)) & USB_INTSTAT_EP2OUT_MASK)
\r
18975 #define USB_INTSTAT_EP2IN_MASK (0x20U)
\r
18976 #define USB_INTSTAT_EP2IN_SHIFT (5U)
\r
18977 /*! EP2IN - Interrupt status register bit for the EP2 IN direction. This bit will be set if the
\r
18978 * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions
\r
18979 * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be
\r
18980 * set when a NAK is transmitted for the EP2 IN direction. Software can clear this bit by writing
\r
18983 #define USB_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2IN_SHIFT)) & USB_INTSTAT_EP2IN_MASK)
\r
18984 #define USB_INTSTAT_EP3OUT_MASK (0x40U)
\r
18985 #define USB_INTSTAT_EP3OUT_SHIFT (6U)
\r
18986 /*! EP3OUT - Interrupt status register bit for the EP3 OUT direction. This bit will be set if the
\r
18987 * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes
\r
18988 * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be
\r
18989 * set when a NAK is transmitted for the EP3 OUT direction. Software can clear this bit by
\r
18990 * writing a one to it.
\r
18992 #define USB_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3OUT_SHIFT)) & USB_INTSTAT_EP3OUT_MASK)
\r
18993 #define USB_INTSTAT_EP3IN_MASK (0x80U)
\r
18994 #define USB_INTSTAT_EP3IN_SHIFT (7U)
\r
18995 /*! EP3IN - Interrupt status register bit for the EP3 IN direction. This bit will be set if the
\r
18996 * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions
\r
18997 * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be
\r
18998 * set when a NAK is transmitted for the EP3 IN direction. Software can clear this bit by writing
\r
19001 #define USB_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3IN_SHIFT)) & USB_INTSTAT_EP3IN_MASK)
\r
19002 #define USB_INTSTAT_EP4OUT_MASK (0x100U)
\r
19003 #define USB_INTSTAT_EP4OUT_SHIFT (8U)
\r
19004 /*! EP4OUT - Interrupt status register bit for the EP4 OUT direction. This bit will be set if the
\r
19005 * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes
\r
19006 * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be
\r
19007 * set when a NAK is transmitted for the EP4 OUT direction. Software can clear this bit by
\r
19008 * writing a one to it.
\r
19010 #define USB_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4OUT_SHIFT)) & USB_INTSTAT_EP4OUT_MASK)
\r
19011 #define USB_INTSTAT_EP4IN_MASK (0x200U)
\r
19012 #define USB_INTSTAT_EP4IN_SHIFT (9U)
\r
19013 /*! EP4IN - Interrupt status register bit for the EP4 IN direction. This bit will be set if the
\r
19014 * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions
\r
19015 * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be
\r
19016 * set when a NAK is transmitted for the EP4 IN direction. Software can clear this bit by writing
\r
19019 #define USB_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4IN_SHIFT)) & USB_INTSTAT_EP4IN_MASK)
\r
19020 #define USB_INTSTAT_FRAME_INT_MASK (0x40000000U)
\r
19021 #define USB_INTSTAT_FRAME_INT_SHIFT (30U)
\r
19022 /*! FRAME_INT - Frame interrupt. This bit is set to one every millisecond when the VbusDebounced bit
\r
19023 * and the DCON bit are set. This bit can be used by software when handling isochronous
\r
19024 * endpoints. Software can clear this bit by writing a one to it.
\r
19026 #define USB_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_FRAME_INT_SHIFT)) & USB_INTSTAT_FRAME_INT_MASK)
\r
19027 #define USB_INTSTAT_DEV_INT_MASK (0x80000000U)
\r
19028 #define USB_INTSTAT_DEV_INT_SHIFT (31U)
\r
19029 /*! DEV_INT - Device status interrupt. This bit is set by HW when one of the bits in the Device
\r
19030 * Status Change register are set. Software can clear this bit by writing a one to it.
\r
19032 #define USB_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_DEV_INT_SHIFT)) & USB_INTSTAT_DEV_INT_MASK)
\r
19035 /*! @name INTEN - USB interrupt enable register */
\r
19037 #define USB_INTEN_EP_INT_EN_MASK (0x3FFU)
\r
19038 #define USB_INTEN_EP_INT_EN_SHIFT (0U)
\r
19039 /*! EP_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW
\r
19040 * interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing
\r
19043 #define USB_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_EP_INT_EN_SHIFT)) & USB_INTEN_EP_INT_EN_MASK)
\r
19044 #define USB_INTEN_FRAME_INT_EN_MASK (0x40000000U)
\r
19045 #define USB_INTEN_FRAME_INT_EN_SHIFT (30U)
\r
19046 /*! FRAME_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW
\r
19047 * interrupt is generated on the interrupt line indicated by the corresponding USB interrupt
\r
19050 #define USB_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_FRAME_INT_EN_SHIFT)) & USB_INTEN_FRAME_INT_EN_MASK)
\r
19051 #define USB_INTEN_DEV_INT_EN_MASK (0x80000000U)
\r
19052 #define USB_INTEN_DEV_INT_EN_SHIFT (31U)
\r
19053 /*! DEV_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW
\r
19054 * interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing
\r
19057 #define USB_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_DEV_INT_EN_SHIFT)) & USB_INTEN_DEV_INT_EN_MASK)
\r
19060 /*! @name INTSETSTAT - USB set interrupt status register */
\r
19062 #define USB_INTSETSTAT_EP_SET_INT_MASK (0x3FFU)
\r
19063 #define USB_INTSETSTAT_EP_SET_INT_SHIFT (0U)
\r
19064 /*! EP_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt
\r
19065 * status bit is set. When this register is read, the same value as the USB interrupt status register
\r
19068 #define USB_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_EP_SET_INT_SHIFT)) & USB_INTSETSTAT_EP_SET_INT_MASK)
\r
19069 #define USB_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U)
\r
19070 #define USB_INTSETSTAT_FRAME_SET_INT_SHIFT (30U)
\r
19071 /*! FRAME_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt
\r
19072 * status bit is set. When this register is read, the same value as the USB interrupt status
\r
19073 * register is returned.
\r
19075 #define USB_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USB_INTSETSTAT_FRAME_SET_INT_MASK)
\r
19076 #define USB_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U)
\r
19077 #define USB_INTSETSTAT_DEV_SET_INT_SHIFT (31U)
\r
19078 /*! DEV_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt
\r
19079 * status bit is set. When this register is read, the same value as the USB interrupt status
\r
19080 * register is returned.
\r
19082 #define USB_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_DEV_SET_INT_SHIFT)) & USB_INTSETSTAT_DEV_SET_INT_MASK)
\r
19085 /*! @name EPTOGGLE - USB Endpoint toggle register */
\r
19087 #define USB_EPTOGGLE_TOGGLE_MASK (0x3FFU)
\r
19088 #define USB_EPTOGGLE_TOGGLE_SHIFT (0U)
\r
19089 /*! TOGGLE - Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint.
\r
19091 #define USB_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USB_EPTOGGLE_TOGGLE_SHIFT)) & USB_EPTOGGLE_TOGGLE_MASK)
\r
19097 */ /* end of group USB_Register_Masks */
\r
19100 /* USB - Peripheral instance base addresses */
\r
19101 /** Peripheral USB0 base address */
\r
19102 #define USB0_BASE (0x40084000u)
\r
19103 /** Peripheral USB0 base pointer */
\r
19104 #define USB0 ((USB_Type *)USB0_BASE)
\r
19105 /** Array initializer of USB peripheral base addresses */
\r
19106 #define USB_BASE_ADDRS { USB0_BASE }
\r
19107 /** Array initializer of USB peripheral base pointers */
\r
19108 #define USB_BASE_PTRS { USB0 }
\r
19109 /** Interrupt vectors for the USB peripheral type */
\r
19110 #define USB_IRQS { USB0_IRQn }
\r
19111 #define USB_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn }
\r
19115 */ /* end of group USB_Peripheral_Access_Layer */
\r
19118 /* ----------------------------------------------------------------------------
\r
19119 -- USBFSH Peripheral Access Layer
\r
19120 ---------------------------------------------------------------------------- */
\r
19123 * @addtogroup USBFSH_Peripheral_Access_Layer USBFSH Peripheral Access Layer
\r
19127 /** USBFSH - Register Layout Typedef */
\r
19129 __I uint32_t HCREVISION; /**< BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC), offset: 0x0 */
\r
19130 __IO uint32_t HCCONTROL; /**< Defines the operating modes of the HC, offset: 0x4 */
\r
19131 __IO uint32_t HCCOMMANDSTATUS; /**< This register is used to receive the commands from the Host Controller Driver (HCD), offset: 0x8 */
\r
19132 __IO uint32_t HCINTERRUPTSTATUS; /**< Indicates the status on various events that cause hardware interrupts by setting the appropriate bits, offset: 0xC */
\r
19133 __IO uint32_t HCINTERRUPTENABLE; /**< Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt, offset: 0x10 */
\r
19134 __IO uint32_t HCINTERRUPTDISABLE; /**< The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt, offset: 0x14 */
\r
19135 __IO uint32_t HCHCCA; /**< Contains the physical address of the host controller communication area, offset: 0x18 */
\r
19136 __I uint32_t HCPERIODCURRENTED; /**< Contains the physical address of the current isochronous or interrupt endpoint descriptor, offset: 0x1C */
\r
19137 __IO uint32_t HCCONTROLHEADED; /**< Contains the physical address of the first endpoint descriptor of the control list, offset: 0x20 */
\r
19138 __IO uint32_t HCCONTROLCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the control list, offset: 0x24 */
\r
19139 __IO uint32_t HCBULKHEADED; /**< Contains the physical address of the first endpoint descriptor of the bulk list, offset: 0x28 */
\r
19140 __IO uint32_t HCBULKCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the bulk list, offset: 0x2C */
\r
19141 __I uint32_t HCDONEHEAD; /**< Contains the physical address of the last transfer descriptor added to the 'Done' queue, offset: 0x30 */
\r
19142 __IO uint32_t HCFMINTERVAL; /**< Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun, offset: 0x34 */
\r
19143 __I uint32_t HCFMREMAINING; /**< A 14-bit counter showing the bit time remaining in the current frame, offset: 0x38 */
\r
19144 __I uint32_t HCFMNUMBER; /**< Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD, offset: 0x3C */
\r
19145 __IO uint32_t HCPERIODICSTART; /**< Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list, offset: 0x40 */
\r
19146 __IO uint32_t HCLSTHRESHOLD; /**< Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF, offset: 0x44 */
\r
19147 __IO uint32_t HCRHDESCRIPTORA; /**< First of the two registers which describes the characteristics of the root hub, offset: 0x48 */
\r
19148 __IO uint32_t HCRHDESCRIPTORB; /**< Second of the two registers which describes the characteristics of the Root Hub, offset: 0x4C */
\r
19149 __IO uint32_t HCRHSTATUS; /**< This register is divided into two parts, offset: 0x50 */
\r
19150 __IO uint32_t HCRHPORTSTATUS; /**< Controls and reports the port events on a per-port basis, offset: 0x54 */
\r
19151 uint8_t RESERVED_0[4];
\r
19152 __IO uint32_t PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x5C */
\r
19155 /* ----------------------------------------------------------------------------
\r
19156 -- USBFSH Register Masks
\r
19157 ---------------------------------------------------------------------------- */
\r
19160 * @addtogroup USBFSH_Register_Masks USBFSH Register Masks
\r
19164 /*! @name HCREVISION - BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC) */
\r
19166 #define USBFSH_HCREVISION_REV_MASK (0xFFU)
\r
19167 #define USBFSH_HCREVISION_REV_SHIFT (0U)
\r
19168 /*! REV - Revision.
\r
19170 #define USBFSH_HCREVISION_REV(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCREVISION_REV_SHIFT)) & USBFSH_HCREVISION_REV_MASK)
\r
19173 /*! @name HCCONTROL - Defines the operating modes of the HC */
\r
19175 #define USBFSH_HCCONTROL_CBSR_MASK (0x3U)
\r
19176 #define USBFSH_HCCONTROL_CBSR_SHIFT (0U)
\r
19177 /*! CBSR - ControlBulkServiceRatio.
\r
19179 #define USBFSH_HCCONTROL_CBSR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CBSR_SHIFT)) & USBFSH_HCCONTROL_CBSR_MASK)
\r
19180 #define USBFSH_HCCONTROL_PLE_MASK (0x4U)
\r
19181 #define USBFSH_HCCONTROL_PLE_SHIFT (2U)
\r
19182 /*! PLE - PeriodicListEnable.
\r
19184 #define USBFSH_HCCONTROL_PLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_PLE_SHIFT)) & USBFSH_HCCONTROL_PLE_MASK)
\r
19185 #define USBFSH_HCCONTROL_IE_MASK (0x8U)
\r
19186 #define USBFSH_HCCONTROL_IE_SHIFT (3U)
\r
19187 /*! IE - IsochronousEnable.
\r
19189 #define USBFSH_HCCONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IE_SHIFT)) & USBFSH_HCCONTROL_IE_MASK)
\r
19190 #define USBFSH_HCCONTROL_CLE_MASK (0x10U)
\r
19191 #define USBFSH_HCCONTROL_CLE_SHIFT (4U)
\r
19192 /*! CLE - ControlListEnable.
\r
19194 #define USBFSH_HCCONTROL_CLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CLE_SHIFT)) & USBFSH_HCCONTROL_CLE_MASK)
\r
19195 #define USBFSH_HCCONTROL_BLE_MASK (0x20U)
\r
19196 #define USBFSH_HCCONTROL_BLE_SHIFT (5U)
\r
19197 /*! BLE - BulkListEnable This bit is set to enable the processing of the Bulk list in the next Frame.
\r
19199 #define USBFSH_HCCONTROL_BLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_BLE_SHIFT)) & USBFSH_HCCONTROL_BLE_MASK)
\r
19200 #define USBFSH_HCCONTROL_HCFS_MASK (0xC0U)
\r
19201 #define USBFSH_HCCONTROL_HCFS_SHIFT (6U)
\r
19202 /*! HCFS - HostControllerFunctionalState for USB 00b: USBRESET 01b: USBRESUME 10b: USBOPERATIONAL
\r
19203 * 11b: USBSUSPEND A transition to USBOPERATIONAL from another state causes SOFgeneration to begin
\r
19206 #define USBFSH_HCCONTROL_HCFS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_HCFS_SHIFT)) & USBFSH_HCCONTROL_HCFS_MASK)
\r
19207 #define USBFSH_HCCONTROL_IR_MASK (0x100U)
\r
19208 #define USBFSH_HCCONTROL_IR_SHIFT (8U)
\r
19209 /*! IR - InterruptRouting This bit determines the routing of interrupts generated by events registered in HcInterruptStatus.
\r
19211 #define USBFSH_HCCONTROL_IR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IR_SHIFT)) & USBFSH_HCCONTROL_IR_MASK)
\r
19212 #define USBFSH_HCCONTROL_RWC_MASK (0x200U)
\r
19213 #define USBFSH_HCCONTROL_RWC_SHIFT (9U)
\r
19214 /*! RWC - RemoteWakeupConnected This bit indicates whether HC supports remote wake-up signaling.
\r
19216 #define USBFSH_HCCONTROL_RWC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWC_SHIFT)) & USBFSH_HCCONTROL_RWC_MASK)
\r
19217 #define USBFSH_HCCONTROL_RWE_MASK (0x400U)
\r
19218 #define USBFSH_HCCONTROL_RWE_SHIFT (10U)
\r
19219 /*! RWE - RemoteWakeupEnable This bit is used by HCD to enable or disable the remote wake-up feature
\r
19220 * upon the detection of upstream resume signaling.
\r
19222 #define USBFSH_HCCONTROL_RWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWE_SHIFT)) & USBFSH_HCCONTROL_RWE_MASK)
\r
19225 /*! @name HCCOMMANDSTATUS - This register is used to receive the commands from the Host Controller Driver (HCD) */
\r
19227 #define USBFSH_HCCOMMANDSTATUS_HCR_MASK (0x1U)
\r
19228 #define USBFSH_HCCOMMANDSTATUS_HCR_SHIFT (0U)
\r
19229 /*! HCR - HostControllerReset This bit is set by HCD to initiate a software reset of HC.
\r
19231 #define USBFSH_HCCOMMANDSTATUS_HCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_HCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_HCR_MASK)
\r
19232 #define USBFSH_HCCOMMANDSTATUS_CLF_MASK (0x2U)
\r
19233 #define USBFSH_HCCOMMANDSTATUS_CLF_SHIFT (1U)
\r
19234 /*! CLF - ControlListFilled This bit is used to indicate whether there are any TDs on the Control list.
\r
19236 #define USBFSH_HCCOMMANDSTATUS_CLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_CLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_CLF_MASK)
\r
19237 #define USBFSH_HCCOMMANDSTATUS_BLF_MASK (0x4U)
\r
19238 #define USBFSH_HCCOMMANDSTATUS_BLF_SHIFT (2U)
\r
19239 /*! BLF - BulkListFilled This bit is used to indicate whether there are any TDs on the Bulk list.
\r
19241 #define USBFSH_HCCOMMANDSTATUS_BLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_BLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_BLF_MASK)
\r
19242 #define USBFSH_HCCOMMANDSTATUS_OCR_MASK (0x8U)
\r
19243 #define USBFSH_HCCOMMANDSTATUS_OCR_SHIFT (3U)
\r
19244 /*! OCR - OwnershipChangeRequest This bit is set by an OS HCD to request a change of control of the HC.
\r
19246 #define USBFSH_HCCOMMANDSTATUS_OCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_OCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_OCR_MASK)
\r
19247 #define USBFSH_HCCOMMANDSTATUS_SOC_MASK (0xC0U)
\r
19248 #define USBFSH_HCCOMMANDSTATUS_SOC_SHIFT (6U)
\r
19249 /*! SOC - SchedulingOverrunCount These bits are incremented on each scheduling overrun error.
\r
19251 #define USBFSH_HCCOMMANDSTATUS_SOC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_SOC_SHIFT)) & USBFSH_HCCOMMANDSTATUS_SOC_MASK)
\r
19254 /*! @name HCINTERRUPTSTATUS - Indicates the status on various events that cause hardware interrupts by setting the appropriate bits */
\r
19256 #define USBFSH_HCINTERRUPTSTATUS_SO_MASK (0x1U)
\r
19257 #define USBFSH_HCINTERRUPTSTATUS_SO_SHIFT (0U)
\r
19258 /*! SO - SchedulingOverrun This bit is set when the USB schedule for the current Frame overruns and
\r
19259 * after the update of HccaFrameNumber.
\r
19261 #define USBFSH_HCINTERRUPTSTATUS_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SO_MASK)
\r
19262 #define USBFSH_HCINTERRUPTSTATUS_WDH_MASK (0x2U)
\r
19263 #define USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT (1U)
\r
19264 /*! WDH - WritebackDoneHead This bit is set immediately after HC has written HcDoneHead to HccaDoneHead.
\r
19266 #define USBFSH_HCINTERRUPTSTATUS_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_WDH_MASK)
\r
19267 #define USBFSH_HCINTERRUPTSTATUS_SF_MASK (0x4U)
\r
19268 #define USBFSH_HCINTERRUPTSTATUS_SF_SHIFT (2U)
\r
19269 /*! SF - StartofFrame This bit is set by HC at each start of a frame and after the update of HccaFrameNumber.
\r
19271 #define USBFSH_HCINTERRUPTSTATUS_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SF_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SF_MASK)
\r
19272 #define USBFSH_HCINTERRUPTSTATUS_RD_MASK (0x8U)
\r
19273 #define USBFSH_HCINTERRUPTSTATUS_RD_SHIFT (3U)
\r
19274 /*! RD - ResumeDetected This bit is set when HC detects that a device on the USB is asserting resume signaling.
\r
19276 #define USBFSH_HCINTERRUPTSTATUS_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RD_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RD_MASK)
\r
19277 #define USBFSH_HCINTERRUPTSTATUS_UE_MASK (0x10U)
\r
19278 #define USBFSH_HCINTERRUPTSTATUS_UE_SHIFT (4U)
\r
19279 /*! UE - UnrecoverableError This bit is set when HC detects a system error not related to USB.
\r
19281 #define USBFSH_HCINTERRUPTSTATUS_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_UE_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_UE_MASK)
\r
19282 #define USBFSH_HCINTERRUPTSTATUS_FNO_MASK (0x20U)
\r
19283 #define USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT (5U)
\r
19284 /*! FNO - FrameNumberOverflow This bit is set when the MSb of HcFmNumber (bit 15) changes value,
\r
19285 * from 0 to 1 or from 1 to 0, and after HccaFrameNumber has been updated.
\r
19287 #define USBFSH_HCINTERRUPTSTATUS_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_FNO_MASK)
\r
19288 #define USBFSH_HCINTERRUPTSTATUS_RHSC_MASK (0x40U)
\r
19289 #define USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT (6U)
\r
19290 /*! RHSC - RootHubStatusChange This bit is set when the content of HcRhStatus or the content of any
\r
19291 * of HcRhPortStatus[NumberofDownstreamPort] has changed.
\r
19293 #define USBFSH_HCINTERRUPTSTATUS_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RHSC_MASK)
\r
19294 #define USBFSH_HCINTERRUPTSTATUS_OC_MASK (0xFFFFFC00U)
\r
19295 #define USBFSH_HCINTERRUPTSTATUS_OC_SHIFT (10U)
\r
19296 /*! OC - OwnershipChange This bit is set by HC when HCD sets the OwnershipChangeRequest field in HcCommandStatus.
\r
19298 #define USBFSH_HCINTERRUPTSTATUS_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_OC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_OC_MASK)
\r
19301 /*! @name HCINTERRUPTENABLE - Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt */
\r
19303 #define USBFSH_HCINTERRUPTENABLE_SO_MASK (0x1U)
\r
19304 #define USBFSH_HCINTERRUPTENABLE_SO_SHIFT (0U)
\r
19305 /*! SO - Scheduling Overrun interrupt.
\r
19307 #define USBFSH_HCINTERRUPTENABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SO_MASK)
\r
19308 #define USBFSH_HCINTERRUPTENABLE_WDH_MASK (0x2U)
\r
19309 #define USBFSH_HCINTERRUPTENABLE_WDH_SHIFT (1U)
\r
19310 /*! WDH - HcDoneHead Writeback interrupt.
\r
19312 #define USBFSH_HCINTERRUPTENABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTENABLE_WDH_MASK)
\r
19313 #define USBFSH_HCINTERRUPTENABLE_SF_MASK (0x4U)
\r
19314 #define USBFSH_HCINTERRUPTENABLE_SF_SHIFT (2U)
\r
19315 /*! SF - Start of Frame interrupt.
\r
19317 #define USBFSH_HCINTERRUPTENABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SF_MASK)
\r
19318 #define USBFSH_HCINTERRUPTENABLE_RD_MASK (0x8U)
\r
19319 #define USBFSH_HCINTERRUPTENABLE_RD_SHIFT (3U)
\r
19320 /*! RD - Resume Detect interrupt.
\r
19322 #define USBFSH_HCINTERRUPTENABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RD_MASK)
\r
19323 #define USBFSH_HCINTERRUPTENABLE_UE_MASK (0x10U)
\r
19324 #define USBFSH_HCINTERRUPTENABLE_UE_SHIFT (4U)
\r
19325 /*! UE - Unrecoverable Error interrupt.
\r
19327 #define USBFSH_HCINTERRUPTENABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_UE_MASK)
\r
19328 #define USBFSH_HCINTERRUPTENABLE_FNO_MASK (0x20U)
\r
19329 #define USBFSH_HCINTERRUPTENABLE_FNO_SHIFT (5U)
\r
19330 /*! FNO - Frame Number Overflow interrupt.
\r
19332 #define USBFSH_HCINTERRUPTENABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_FNO_MASK)
\r
19333 #define USBFSH_HCINTERRUPTENABLE_RHSC_MASK (0x40U)
\r
19334 #define USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT (6U)
\r
19335 /*! RHSC - Root Hub Status Change interrupt.
\r
19337 #define USBFSH_HCINTERRUPTENABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RHSC_MASK)
\r
19338 #define USBFSH_HCINTERRUPTENABLE_OC_MASK (0x40000000U)
\r
19339 #define USBFSH_HCINTERRUPTENABLE_OC_SHIFT (30U)
\r
19340 /*! OC - Ownership Change interrupt.
\r
19342 #define USBFSH_HCINTERRUPTENABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_OC_MASK)
\r
19343 #define USBFSH_HCINTERRUPTENABLE_MIE_MASK (0x80000000U)
\r
19344 #define USBFSH_HCINTERRUPTENABLE_MIE_SHIFT (31U)
\r
19345 /*! MIE - Master Interrupt Enable.
\r
19347 #define USBFSH_HCINTERRUPTENABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_MIE_MASK)
\r
19350 /*! @name HCINTERRUPTDISABLE - The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt */
\r
19352 #define USBFSH_HCINTERRUPTDISABLE_SO_MASK (0x1U)
\r
19353 #define USBFSH_HCINTERRUPTDISABLE_SO_SHIFT (0U)
\r
19354 /*! SO - Scheduling Overrun interrupt.
\r
19356 #define USBFSH_HCINTERRUPTDISABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SO_MASK)
\r
19357 #define USBFSH_HCINTERRUPTDISABLE_WDH_MASK (0x2U)
\r
19358 #define USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT (1U)
\r
19359 /*! WDH - HcDoneHead Writeback interrupt.
\r
19361 #define USBFSH_HCINTERRUPTDISABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_WDH_MASK)
\r
19362 #define USBFSH_HCINTERRUPTDISABLE_SF_MASK (0x4U)
\r
19363 #define USBFSH_HCINTERRUPTDISABLE_SF_SHIFT (2U)
\r
19364 /*! SF - Start of Frame interrupt.
\r
19366 #define USBFSH_HCINTERRUPTDISABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SF_MASK)
\r
19367 #define USBFSH_HCINTERRUPTDISABLE_RD_MASK (0x8U)
\r
19368 #define USBFSH_HCINTERRUPTDISABLE_RD_SHIFT (3U)
\r
19369 /*! RD - Resume Detect interrupt.
\r
19371 #define USBFSH_HCINTERRUPTDISABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RD_MASK)
\r
19372 #define USBFSH_HCINTERRUPTDISABLE_UE_MASK (0x10U)
\r
19373 #define USBFSH_HCINTERRUPTDISABLE_UE_SHIFT (4U)
\r
19374 /*! UE - Unrecoverable Error interrupt.
\r
19376 #define USBFSH_HCINTERRUPTDISABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_UE_MASK)
\r
19377 #define USBFSH_HCINTERRUPTDISABLE_FNO_MASK (0x20U)
\r
19378 #define USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT (5U)
\r
19379 /*! FNO - Frame Number Overflow interrupt.
\r
19381 #define USBFSH_HCINTERRUPTDISABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_FNO_MASK)
\r
19382 #define USBFSH_HCINTERRUPTDISABLE_RHSC_MASK (0x40U)
\r
19383 #define USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT (6U)
\r
19384 /*! RHSC - Root Hub Status Change interrupt.
\r
19386 #define USBFSH_HCINTERRUPTDISABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RHSC_MASK)
\r
19387 #define USBFSH_HCINTERRUPTDISABLE_OC_MASK (0x40000000U)
\r
19388 #define USBFSH_HCINTERRUPTDISABLE_OC_SHIFT (30U)
\r
19389 /*! OC - Ownership Change interrupt.
\r
19391 #define USBFSH_HCINTERRUPTDISABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_OC_MASK)
\r
19392 #define USBFSH_HCINTERRUPTDISABLE_MIE_MASK (0x80000000U)
\r
19393 #define USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT (31U)
\r
19394 /*! MIE - A 0 written to this field is ignored by HC.
\r
19396 #define USBFSH_HCINTERRUPTDISABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_MIE_MASK)
\r
19399 /*! @name HCHCCA - Contains the physical address of the host controller communication area */
\r
19401 #define USBFSH_HCHCCA_HCCA_MASK (0xFFFFFF00U)
\r
19402 #define USBFSH_HCHCCA_HCCA_SHIFT (8U)
\r
19403 /*! HCCA - Base address of the Host Controller Communication Area.
\r
19405 #define USBFSH_HCHCCA_HCCA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCHCCA_HCCA_SHIFT)) & USBFSH_HCHCCA_HCCA_MASK)
\r
19408 /*! @name HCPERIODCURRENTED - Contains the physical address of the current isochronous or interrupt endpoint descriptor */
\r
19410 #define USBFSH_HCPERIODCURRENTED_PCED_MASK (0xFFFFFFF0U)
\r
19411 #define USBFSH_HCPERIODCURRENTED_PCED_SHIFT (4U)
\r
19412 /*! PCED - The content of this register is updated by HC after a periodic ED is processed.
\r
19414 #define USBFSH_HCPERIODCURRENTED_PCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODCURRENTED_PCED_SHIFT)) & USBFSH_HCPERIODCURRENTED_PCED_MASK)
\r
19417 /*! @name HCCONTROLHEADED - Contains the physical address of the first endpoint descriptor of the control list */
\r
19419 #define USBFSH_HCCONTROLHEADED_CHED_MASK (0xFFFFFFF0U)
\r
19420 #define USBFSH_HCCONTROLHEADED_CHED_SHIFT (4U)
\r
19421 /*! CHED - HC traverses the Control list starting with the HcControlHeadED pointer.
\r
19423 #define USBFSH_HCCONTROLHEADED_CHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLHEADED_CHED_SHIFT)) & USBFSH_HCCONTROLHEADED_CHED_MASK)
\r
19426 /*! @name HCCONTROLCURRENTED - Contains the physical address of the current endpoint descriptor of the control list */
\r
19428 #define USBFSH_HCCONTROLCURRENTED_CCED_MASK (0xFFFFFFF0U)
\r
19429 #define USBFSH_HCCONTROLCURRENTED_CCED_SHIFT (4U)
\r
19430 /*! CCED - ControlCurrentED.
\r
19432 #define USBFSH_HCCONTROLCURRENTED_CCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLCURRENTED_CCED_SHIFT)) & USBFSH_HCCONTROLCURRENTED_CCED_MASK)
\r
19435 /*! @name HCBULKHEADED - Contains the physical address of the first endpoint descriptor of the bulk list */
\r
19437 #define USBFSH_HCBULKHEADED_BHED_MASK (0xFFFFFFF0U)
\r
19438 #define USBFSH_HCBULKHEADED_BHED_SHIFT (4U)
\r
19439 /*! BHED - BulkHeadED HC traverses the bulk list starting with the HcBulkHeadED pointer.
\r
19441 #define USBFSH_HCBULKHEADED_BHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKHEADED_BHED_SHIFT)) & USBFSH_HCBULKHEADED_BHED_MASK)
\r
19444 /*! @name HCBULKCURRENTED - Contains the physical address of the current endpoint descriptor of the bulk list */
\r
19446 #define USBFSH_HCBULKCURRENTED_BCED_MASK (0xFFFFFFF0U)
\r
19447 #define USBFSH_HCBULKCURRENTED_BCED_SHIFT (4U)
\r
19448 /*! BCED - BulkCurrentED This is advanced to the next ED after the HC has served the current one.
\r
19450 #define USBFSH_HCBULKCURRENTED_BCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKCURRENTED_BCED_SHIFT)) & USBFSH_HCBULKCURRENTED_BCED_MASK)
\r
19453 /*! @name HCDONEHEAD - Contains the physical address of the last transfer descriptor added to the 'Done' queue */
\r
19455 #define USBFSH_HCDONEHEAD_DH_MASK (0xFFFFFFF0U)
\r
19456 #define USBFSH_HCDONEHEAD_DH_SHIFT (4U)
\r
19457 /*! DH - DoneHead When a TD is completed, HC writes the content of HcDoneHead to the NextTD field of the TD.
\r
19459 #define USBFSH_HCDONEHEAD_DH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCDONEHEAD_DH_SHIFT)) & USBFSH_HCDONEHEAD_DH_MASK)
\r
19462 /*! @name HCFMINTERVAL - Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun */
\r
19464 #define USBFSH_HCFMINTERVAL_FI_MASK (0x3FFFU)
\r
19465 #define USBFSH_HCFMINTERVAL_FI_SHIFT (0U)
\r
19466 /*! FI - FrameInterval This specifies the interval between two consecutive SOFs in bit times.
\r
19468 #define USBFSH_HCFMINTERVAL_FI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FI_SHIFT)) & USBFSH_HCFMINTERVAL_FI_MASK)
\r
19469 #define USBFSH_HCFMINTERVAL_FSMPS_MASK (0x7FFF0000U)
\r
19470 #define USBFSH_HCFMINTERVAL_FSMPS_SHIFT (16U)
\r
19471 /*! FSMPS - FSLargestDataPacket This field specifies a value which is loaded into the Largest Data
\r
19472 * Packet Counter at the beginning of each frame.
\r
19474 #define USBFSH_HCFMINTERVAL_FSMPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FSMPS_SHIFT)) & USBFSH_HCFMINTERVAL_FSMPS_MASK)
\r
19475 #define USBFSH_HCFMINTERVAL_FIT_MASK (0x80000000U)
\r
19476 #define USBFSH_HCFMINTERVAL_FIT_SHIFT (31U)
\r
19477 /*! FIT - FrameIntervalToggle HCD toggles this bit whenever it loads a new value to FrameInterval.
\r
19479 #define USBFSH_HCFMINTERVAL_FIT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FIT_SHIFT)) & USBFSH_HCFMINTERVAL_FIT_MASK)
\r
19482 /*! @name HCFMREMAINING - A 14-bit counter showing the bit time remaining in the current frame */
\r
19484 #define USBFSH_HCFMREMAINING_FR_MASK (0x3FFFU)
\r
19485 #define USBFSH_HCFMREMAINING_FR_SHIFT (0U)
\r
19486 /*! FR - FrameRemaining This counter is decremented at each bit time.
\r
19488 #define USBFSH_HCFMREMAINING_FR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FR_SHIFT)) & USBFSH_HCFMREMAINING_FR_MASK)
\r
19489 #define USBFSH_HCFMREMAINING_FRT_MASK (0x80000000U)
\r
19490 #define USBFSH_HCFMREMAINING_FRT_SHIFT (31U)
\r
19491 /*! FRT - FrameRemainingToggle This bit is loaded from the FrameIntervalToggle field of HcFmInterval
\r
19492 * whenever FrameRemaining reaches 0.
\r
19494 #define USBFSH_HCFMREMAINING_FRT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FRT_SHIFT)) & USBFSH_HCFMREMAINING_FRT_MASK)
\r
19497 /*! @name HCFMNUMBER - Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD */
\r
19499 #define USBFSH_HCFMNUMBER_FN_MASK (0xFFFFU)
\r
19500 #define USBFSH_HCFMNUMBER_FN_SHIFT (0U)
\r
19501 /*! FN - FrameNumber This is incremented when HcFmRemaining is re-loaded.
\r
19503 #define USBFSH_HCFMNUMBER_FN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMNUMBER_FN_SHIFT)) & USBFSH_HCFMNUMBER_FN_MASK)
\r
19506 /*! @name HCPERIODICSTART - Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list */
\r
19508 #define USBFSH_HCPERIODICSTART_PS_MASK (0x3FFFU)
\r
19509 #define USBFSH_HCPERIODICSTART_PS_SHIFT (0U)
\r
19510 /*! PS - PeriodicStart After a hardware reset, this field is cleared and then set by HCD during the HC initialization.
\r
19512 #define USBFSH_HCPERIODICSTART_PS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODICSTART_PS_SHIFT)) & USBFSH_HCPERIODICSTART_PS_MASK)
\r
19515 /*! @name HCLSTHRESHOLD - Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF */
\r
19517 #define USBFSH_HCLSTHRESHOLD_LST_MASK (0xFFFU)
\r
19518 #define USBFSH_HCLSTHRESHOLD_LST_SHIFT (0U)
\r
19519 /*! LST - LSThreshold This field contains a value which is compared to the FrameRemaining field
\r
19520 * prior to initiating a Low Speed transaction.
\r
19522 #define USBFSH_HCLSTHRESHOLD_LST(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCLSTHRESHOLD_LST_SHIFT)) & USBFSH_HCLSTHRESHOLD_LST_MASK)
\r
19525 /*! @name HCRHDESCRIPTORA - First of the two registers which describes the characteristics of the root hub */
\r
19527 #define USBFSH_HCRHDESCRIPTORA_NDP_MASK (0xFFU)
\r
19528 #define USBFSH_HCRHDESCRIPTORA_NDP_SHIFT (0U)
\r
19529 /*! NDP - NumberDownstreamPorts These bits specify the number of downstream ports supported by the root hub.
\r
19531 #define USBFSH_HCRHDESCRIPTORA_NDP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NDP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NDP_MASK)
\r
19532 #define USBFSH_HCRHDESCRIPTORA_PSM_MASK (0x100U)
\r
19533 #define USBFSH_HCRHDESCRIPTORA_PSM_SHIFT (8U)
\r
19534 /*! PSM - PowerSwitchingMode This bit is used to specify how the power switching of the root hub ports is controlled.
\r
19536 #define USBFSH_HCRHDESCRIPTORA_PSM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_PSM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_PSM_MASK)
\r
19537 #define USBFSH_HCRHDESCRIPTORA_NPS_MASK (0x200U)
\r
19538 #define USBFSH_HCRHDESCRIPTORA_NPS_SHIFT (9U)
\r
19539 /*! NPS - NoPowerSwitching These bits are used to specify whether power switching is supported or port are always powered.
\r
19541 #define USBFSH_HCRHDESCRIPTORA_NPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NPS_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NPS_MASK)
\r
19542 #define USBFSH_HCRHDESCRIPTORA_DT_MASK (0x400U)
\r
19543 #define USBFSH_HCRHDESCRIPTORA_DT_SHIFT (10U)
\r
19544 /*! DT - DeviceType This bit specifies that the root hub is not a compound device.
\r
19546 #define USBFSH_HCRHDESCRIPTORA_DT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_DT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_DT_MASK)
\r
19547 #define USBFSH_HCRHDESCRIPTORA_OCPM_MASK (0x800U)
\r
19548 #define USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT (11U)
\r
19549 /*! OCPM - OverCurrentProtectionMode This bit describes how the overcurrent status for the root hub ports are reported.
\r
19551 #define USBFSH_HCRHDESCRIPTORA_OCPM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_OCPM_MASK)
\r
19552 #define USBFSH_HCRHDESCRIPTORA_NOCP_MASK (0x1000U)
\r
19553 #define USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT (12U)
\r
19554 /*! NOCP - NoOverCurrentProtection This bit describes how the overcurrent status for the root hub ports are reported.
\r
19556 #define USBFSH_HCRHDESCRIPTORA_NOCP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NOCP_MASK)
\r
19557 #define USBFSH_HCRHDESCRIPTORA_POTPGT_MASK (0xFF000000U)
\r
19558 #define USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT (24U)
\r
19559 /*! POTPGT - PowerOnToPowerGoodTime This byte specifies the duration the HCD has to wait before
\r
19560 * accessing a powered-on port of the root hub.
\r
19562 #define USBFSH_HCRHDESCRIPTORA_POTPGT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_POTPGT_MASK)
\r
19565 /*! @name HCRHDESCRIPTORB - Second of the two registers which describes the characteristics of the Root Hub */
\r
19567 #define USBFSH_HCRHDESCRIPTORB_DR_MASK (0xFFFFU)
\r
19568 #define USBFSH_HCRHDESCRIPTORB_DR_SHIFT (0U)
\r
19569 /*! DR - DeviceRemovable Each bit is dedicated to a port of the Root Hub.
\r
19571 #define USBFSH_HCRHDESCRIPTORB_DR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_DR_SHIFT)) & USBFSH_HCRHDESCRIPTORB_DR_MASK)
\r
19572 #define USBFSH_HCRHDESCRIPTORB_PPCM_MASK (0xFFFF0000U)
\r
19573 #define USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT (16U)
\r
19574 /*! PPCM - PortPowerControlMask Each bit indicates if a port is affected by a global power control
\r
19575 * command when PowerSwitchingMode is set.
\r
19577 #define USBFSH_HCRHDESCRIPTORB_PPCM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT)) & USBFSH_HCRHDESCRIPTORB_PPCM_MASK)
\r
19580 /*! @name HCRHSTATUS - This register is divided into two parts */
\r
19582 #define USBFSH_HCRHSTATUS_LPS_MASK (0x1U)
\r
19583 #define USBFSH_HCRHSTATUS_LPS_SHIFT (0U)
\r
19584 /*! LPS - (read) LocalPowerStatus The Root Hub does not support the local power status feature;
\r
19585 * thus, this bit is always read as 0.
\r
19587 #define USBFSH_HCRHSTATUS_LPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPS_SHIFT)) & USBFSH_HCRHSTATUS_LPS_MASK)
\r
19588 #define USBFSH_HCRHSTATUS_OCI_MASK (0x2U)
\r
19589 #define USBFSH_HCRHSTATUS_OCI_SHIFT (1U)
\r
19590 /*! OCI - OverCurrentIndicator This bit reports overcurrent conditions when the global reporting is implemented.
\r
19592 #define USBFSH_HCRHSTATUS_OCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCI_SHIFT)) & USBFSH_HCRHSTATUS_OCI_MASK)
\r
19593 #define USBFSH_HCRHSTATUS_DRWE_MASK (0x8000U)
\r
19594 #define USBFSH_HCRHSTATUS_DRWE_SHIFT (15U)
\r
19595 /*! DRWE - (read) DeviceRemoteWakeupEnable This bit enables a ConnectStatusChange bit as a resume
\r
19596 * event, causing a USBSUSPEND to USBRESUME state transition and setting the ResumeDetected
\r
19599 #define USBFSH_HCRHSTATUS_DRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_DRWE_SHIFT)) & USBFSH_HCRHSTATUS_DRWE_MASK)
\r
19600 #define USBFSH_HCRHSTATUS_LPSC_MASK (0x10000U)
\r
19601 #define USBFSH_HCRHSTATUS_LPSC_SHIFT (16U)
\r
19602 /*! LPSC - (read) LocalPowerStatusChange The root hub does not support the local power status feature.
\r
19604 #define USBFSH_HCRHSTATUS_LPSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPSC_SHIFT)) & USBFSH_HCRHSTATUS_LPSC_MASK)
\r
19605 #define USBFSH_HCRHSTATUS_OCIC_MASK (0x20000U)
\r
19606 #define USBFSH_HCRHSTATUS_OCIC_SHIFT (17U)
\r
19607 /*! OCIC - OverCurrentIndicatorChange This bit is set by hardware when a change has occurred to the OCI field of this register.
\r
19609 #define USBFSH_HCRHSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCIC_SHIFT)) & USBFSH_HCRHSTATUS_OCIC_MASK)
\r
19610 #define USBFSH_HCRHSTATUS_CRWE_MASK (0x80000000U)
\r
19611 #define USBFSH_HCRHSTATUS_CRWE_SHIFT (31U)
\r
19612 /*! CRWE - (write) ClearRemoteWakeupEnable Writing a 1 clears DeviceRemoveWakeupEnable.
\r
19614 #define USBFSH_HCRHSTATUS_CRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_CRWE_SHIFT)) & USBFSH_HCRHSTATUS_CRWE_MASK)
\r
19617 /*! @name HCRHPORTSTATUS - Controls and reports the port events on a per-port basis */
\r
19619 #define USBFSH_HCRHPORTSTATUS_CCS_MASK (0x1U)
\r
19620 #define USBFSH_HCRHPORTSTATUS_CCS_SHIFT (0U)
\r
19621 /*! CCS - (read) CurrentConnectStatus This bit reflects the current state of the downstream port.
\r
19623 #define USBFSH_HCRHPORTSTATUS_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CCS_SHIFT)) & USBFSH_HCRHPORTSTATUS_CCS_MASK)
\r
19624 #define USBFSH_HCRHPORTSTATUS_PES_MASK (0x2U)
\r
19625 #define USBFSH_HCRHPORTSTATUS_PES_SHIFT (1U)
\r
19626 /*! PES - (read) PortEnableStatus This bit indicates whether the port is enabled or disabled.
\r
19628 #define USBFSH_HCRHPORTSTATUS_PES(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PES_SHIFT)) & USBFSH_HCRHPORTSTATUS_PES_MASK)
\r
19629 #define USBFSH_HCRHPORTSTATUS_PSS_MASK (0x4U)
\r
19630 #define USBFSH_HCRHPORTSTATUS_PSS_SHIFT (2U)
\r
19631 /*! PSS - (read) PortSuspendStatus This bit indicates the port is suspended or in the resume sequence.
\r
19633 #define USBFSH_HCRHPORTSTATUS_PSS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSS_MASK)
\r
19634 #define USBFSH_HCRHPORTSTATUS_POCI_MASK (0x8U)
\r
19635 #define USBFSH_HCRHPORTSTATUS_POCI_SHIFT (3U)
\r
19636 /*! POCI - (read) PortOverCurrentIndicator This bit is only valid when the Root Hub is configured in
\r
19637 * such a way that overcurrent conditions are reported on a per-port basis.
\r
19639 #define USBFSH_HCRHPORTSTATUS_POCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_POCI_SHIFT)) & USBFSH_HCRHPORTSTATUS_POCI_MASK)
\r
19640 #define USBFSH_HCRHPORTSTATUS_PRS_MASK (0x10U)
\r
19641 #define USBFSH_HCRHPORTSTATUS_PRS_SHIFT (4U)
\r
19642 /*! PRS - (read) PortResetStatus When this bit is set by a write to SetPortReset, port reset signaling is asserted.
\r
19644 #define USBFSH_HCRHPORTSTATUS_PRS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRS_MASK)
\r
19645 #define USBFSH_HCRHPORTSTATUS_PPS_MASK (0x100U)
\r
19646 #define USBFSH_HCRHPORTSTATUS_PPS_SHIFT (8U)
\r
19647 /*! PPS - (read) PortPowerStatus This bit reflects the porta's power status, regardless of the type
\r
19648 * of power switching implemented.
\r
19650 #define USBFSH_HCRHPORTSTATUS_PPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PPS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PPS_MASK)
\r
19651 #define USBFSH_HCRHPORTSTATUS_LSDA_MASK (0x200U)
\r
19652 #define USBFSH_HCRHPORTSTATUS_LSDA_SHIFT (9U)
\r
19653 /*! LSDA - (read) LowSpeedDeviceAttached This bit indicates the speed of the device attached to this port.
\r
19655 #define USBFSH_HCRHPORTSTATUS_LSDA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_LSDA_SHIFT)) & USBFSH_HCRHPORTSTATUS_LSDA_MASK)
\r
19656 #define USBFSH_HCRHPORTSTATUS_CSC_MASK (0x10000U)
\r
19657 #define USBFSH_HCRHPORTSTATUS_CSC_SHIFT (16U)
\r
19658 /*! CSC - ConnectStatusChange This bit is set whenever a connect or disconnect event occurs.
\r
19660 #define USBFSH_HCRHPORTSTATUS_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_CSC_MASK)
\r
19661 #define USBFSH_HCRHPORTSTATUS_PESC_MASK (0x20000U)
\r
19662 #define USBFSH_HCRHPORTSTATUS_PESC_SHIFT (17U)
\r
19663 /*! PESC - PortEnableStatusChange This bit is set when hardware events cause the PortEnableStatus bit to be cleared.
\r
19665 #define USBFSH_HCRHPORTSTATUS_PESC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PESC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PESC_MASK)
\r
19666 #define USBFSH_HCRHPORTSTATUS_PSSC_MASK (0x40000U)
\r
19667 #define USBFSH_HCRHPORTSTATUS_PSSC_SHIFT (18U)
\r
19668 /*! PSSC - PortSuspendStatusChange This bit is set when the full resume sequence is completed.
\r
19670 #define USBFSH_HCRHPORTSTATUS_PSSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSSC_MASK)
\r
19671 #define USBFSH_HCRHPORTSTATUS_OCIC_MASK (0x80000U)
\r
19672 #define USBFSH_HCRHPORTSTATUS_OCIC_SHIFT (19U)
\r
19673 /*! OCIC - PortOverCurrentIndicatorChange This bit is valid only if overcurrent conditions are reported on a per-port basis.
\r
19675 #define USBFSH_HCRHPORTSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_OCIC_SHIFT)) & USBFSH_HCRHPORTSTATUS_OCIC_MASK)
\r
19676 #define USBFSH_HCRHPORTSTATUS_PRSC_MASK (0x100000U)
\r
19677 #define USBFSH_HCRHPORTSTATUS_PRSC_SHIFT (20U)
\r
19678 /*! PRSC - PortResetStatusChange This bit is set at the end of the 10 ms port reset signal.
\r
19680 #define USBFSH_HCRHPORTSTATUS_PRSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRSC_MASK)
\r
19683 /*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */
\r
19685 #define USBFSH_PORTMODE_ID_MASK (0x1U)
\r
19686 #define USBFSH_PORTMODE_ID_SHIFT (0U)
\r
19687 /*! ID - Port ID pin value.
\r
19689 #define USBFSH_PORTMODE_ID(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_SHIFT)) & USBFSH_PORTMODE_ID_MASK)
\r
19690 #define USBFSH_PORTMODE_ID_EN_MASK (0x100U)
\r
19691 #define USBFSH_PORTMODE_ID_EN_SHIFT (8U)
\r
19692 /*! ID_EN - Port ID pin pull-up enable.
\r
19694 #define USBFSH_PORTMODE_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_EN_SHIFT)) & USBFSH_PORTMODE_ID_EN_MASK)
\r
19695 #define USBFSH_PORTMODE_DEV_ENABLE_MASK (0x10000U)
\r
19696 #define USBFSH_PORTMODE_DEV_ENABLE_SHIFT (16U)
\r
19697 /*! DEV_ENABLE - 1: device 0: host.
\r
19699 #define USBFSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBFSH_PORTMODE_DEV_ENABLE_MASK)
\r
19705 */ /* end of group USBFSH_Register_Masks */
\r
19708 /* USBFSH - Peripheral instance base addresses */
\r
19709 /** Peripheral USBFSH base address */
\r
19710 #define USBFSH_BASE (0x400A2000u)
\r
19711 /** Peripheral USBFSH base pointer */
\r
19712 #define USBFSH ((USBFSH_Type *)USBFSH_BASE)
\r
19713 /** Array initializer of USBFSH peripheral base addresses */
\r
19714 #define USBFSH_BASE_ADDRS { USBFSH_BASE }
\r
19715 /** Array initializer of USBFSH peripheral base pointers */
\r
19716 #define USBFSH_BASE_PTRS { USBFSH }
\r
19717 /** Interrupt vectors for the USBFSH peripheral type */
\r
19718 #define USBFSH_IRQS { USB0_IRQn }
\r
19719 #define USBFSH_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn }
\r
19723 */ /* end of group USBFSH_Peripheral_Access_Layer */
\r
19726 /* ----------------------------------------------------------------------------
\r
19727 -- USBHSD Peripheral Access Layer
\r
19728 ---------------------------------------------------------------------------- */
\r
19731 * @addtogroup USBHSD_Peripheral_Access_Layer USBHSD Peripheral Access Layer
\r
19735 /** USBHSD - Register Layout Typedef */
\r
19737 __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */
\r
19738 __I uint32_t INFO; /**< USB Info register, offset: 0x4 */
\r
19739 __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */
\r
19740 __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */
\r
19741 __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */
\r
19742 __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */
\r
19743 __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */
\r
19744 __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */
\r
19745 __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */
\r
19746 __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */
\r
19747 __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */
\r
19748 uint8_t RESERVED_0[8];
\r
19749 __I uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */
\r
19752 /* ----------------------------------------------------------------------------
\r
19753 -- USBHSD Register Masks
\r
19754 ---------------------------------------------------------------------------- */
\r
19757 * @addtogroup USBHSD_Register_Masks USBHSD Register Masks
\r
19761 /*! @name DEVCMDSTAT - USB Device Command/Status register */
\r
19763 #define USBHSD_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU)
\r
19764 #define USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT (0U)
\r
19765 /*! DEV_ADDR - USB device address.
\r
19767 #define USBHSD_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_ADDR_MASK)
\r
19768 #define USBHSD_DEVCMDSTAT_DEV_EN_MASK (0x80U)
\r
19769 #define USBHSD_DEVCMDSTAT_DEV_EN_SHIFT (7U)
\r
19770 /*! DEV_EN - USB device enable.
\r
19772 #define USBHSD_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_EN_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_EN_MASK)
\r
19773 #define USBHSD_DEVCMDSTAT_SETUP_MASK (0x100U)
\r
19774 #define USBHSD_DEVCMDSTAT_SETUP_SHIFT (8U)
\r
19775 /*! SETUP - SETUP token received.
\r
19777 #define USBHSD_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_SETUP_SHIFT)) & USBHSD_DEVCMDSTAT_SETUP_MASK)
\r
19778 #define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U)
\r
19779 #define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U)
\r
19780 /*! FORCE_NEEDCLK - Forces the NEEDCLK output to always be on:.
\r
19782 #define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK)
\r
19783 #define USBHSD_DEVCMDSTAT_FORCE_VBUS_MASK (0x400U)
\r
19784 #define USBHSD_DEVCMDSTAT_FORCE_VBUS_SHIFT (10U)
\r
19785 /*! FORCE_VBUS - If this bit is set to 1, the VBUS voltage indicators from the PHY are overruled.
\r
19787 #define USBHSD_DEVCMDSTAT_FORCE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_VBUS_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_VBUS_MASK)
\r
19788 #define USBHSD_DEVCMDSTAT_LPM_SUP_MASK (0x800U)
\r
19789 #define USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT (11U)
\r
19790 /*! LPM_SUP - LPM Supported:.
\r
19792 #define USBHSD_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUP_MASK)
\r
19793 #define USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U)
\r
19794 #define USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U)
\r
19795 /*! INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP:.
\r
19797 #define USBHSD_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK)
\r
19798 #define USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U)
\r
19799 #define USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U)
\r
19800 /*! INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP:.
\r
19802 #define USBHSD_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK)
\r
19803 #define USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U)
\r
19804 #define USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U)
\r
19805 /*! INTONNAK_CO - Interrupt on NAK for control OUT EP:.
\r
19807 #define USBHSD_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK)
\r
19808 #define USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U)
\r
19809 #define USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U)
\r
19810 /*! INTONNAK_CI - Interrupt on NAK for control IN EP:.
\r
19812 #define USBHSD_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK)
\r
19813 #define USBHSD_DEVCMDSTAT_DCON_MASK (0x10000U)
\r
19814 #define USBHSD_DEVCMDSTAT_DCON_SHIFT (16U)
\r
19815 /*! DCON - Device status - connect.
\r
19817 #define USBHSD_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_MASK)
\r
19818 #define USBHSD_DEVCMDSTAT_DSUS_MASK (0x20000U)
\r
19819 #define USBHSD_DEVCMDSTAT_DSUS_SHIFT (17U)
\r
19820 /*! DSUS - Device status - suspend.
\r
19822 #define USBHSD_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_MASK)
\r
19823 #define USBHSD_DEVCMDSTAT_LPM_SUS_MASK (0x80000U)
\r
19824 #define USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT (19U)
\r
19825 /*! LPM_SUS - Device status - LPM Suspend.
\r
19827 #define USBHSD_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUS_MASK)
\r
19828 #define USBHSD_DEVCMDSTAT_LPM_REWP_MASK (0x100000U)
\r
19829 #define USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT (20U)
\r
19830 /*! LPM_REWP - LPM Remote Wake-up Enabled by USB host.
\r
19832 #define USBHSD_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_REWP_MASK)
\r
19833 #define USBHSD_DEVCMDSTAT_Speed_MASK (0xC00000U)
\r
19834 #define USBHSD_DEVCMDSTAT_Speed_SHIFT (22U)
\r
19835 /*! Speed - This field indicates the speed at which the device operates: 00b: reserved 01b:
\r
19836 * full-speed 10b: high-speed 11b: super-speed (reserved for future use).
\r
19838 #define USBHSD_DEVCMDSTAT_Speed(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_Speed_SHIFT)) & USBHSD_DEVCMDSTAT_Speed_MASK)
\r
19839 #define USBHSD_DEVCMDSTAT_DCON_C_MASK (0x1000000U)
\r
19840 #define USBHSD_DEVCMDSTAT_DCON_C_SHIFT (24U)
\r
19841 /*! DCON_C - Device status - connect change.
\r
19843 #define USBHSD_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_C_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_C_MASK)
\r
19844 #define USBHSD_DEVCMDSTAT_DSUS_C_MASK (0x2000000U)
\r
19845 #define USBHSD_DEVCMDSTAT_DSUS_C_SHIFT (25U)
\r
19846 /*! DSUS_C - Device status - suspend change.
\r
19848 #define USBHSD_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_C_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_C_MASK)
\r
19849 #define USBHSD_DEVCMDSTAT_DRES_C_MASK (0x4000000U)
\r
19850 #define USBHSD_DEVCMDSTAT_DRES_C_SHIFT (26U)
\r
19851 /*! DRES_C - Device status - reset change.
\r
19853 #define USBHSD_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DRES_C_SHIFT)) & USBHSD_DEVCMDSTAT_DRES_C_MASK)
\r
19854 #define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK (0x10000000U)
\r
19855 #define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT (28U)
\r
19856 /*! VBUS_DEBOUNCED - This bit indicates if VBUS is detected or not.
\r
19858 #define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT)) & USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK)
\r
19859 #define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK (0xE0000000U)
\r
19860 #define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT (29U)
\r
19861 /*! PHY_TEST_MODE - This field is written by firmware to put the PHY into a test mode as defined by the USB2.
\r
19863 #define USBHSD_DEVCMDSTAT_PHY_TEST_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT)) & USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK)
\r
19866 /*! @name INFO - USB Info register */
\r
19868 #define USBHSD_INFO_FRAME_NR_MASK (0x7FFU)
\r
19869 #define USBHSD_INFO_FRAME_NR_SHIFT (0U)
\r
19870 /*! FRAME_NR - Frame number.
\r
19872 #define USBHSD_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_FRAME_NR_SHIFT)) & USBHSD_INFO_FRAME_NR_MASK)
\r
19873 #define USBHSD_INFO_ERR_CODE_MASK (0x7800U)
\r
19874 #define USBHSD_INFO_ERR_CODE_SHIFT (11U)
\r
19875 /*! ERR_CODE - The error code which last occurred:.
\r
19877 #define USBHSD_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_ERR_CODE_SHIFT)) & USBHSD_INFO_ERR_CODE_MASK)
\r
19878 #define USBHSD_INFO_Minrev_MASK (0xFF0000U)
\r
19879 #define USBHSD_INFO_Minrev_SHIFT (16U)
\r
19880 /*! Minrev - Minor revision.
\r
19882 #define USBHSD_INFO_Minrev(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_Minrev_SHIFT)) & USBHSD_INFO_Minrev_MASK)
\r
19883 #define USBHSD_INFO_Majrev_MASK (0xFF000000U)
\r
19884 #define USBHSD_INFO_Majrev_SHIFT (24U)
\r
19885 /*! Majrev - Major revision.
\r
19887 #define USBHSD_INFO_Majrev(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_Majrev_SHIFT)) & USBHSD_INFO_Majrev_MASK)
\r
19890 /*! @name EPLISTSTART - USB EP Command/Status List start address */
\r
19892 #define USBHSD_EPLISTSTART_EP_LIST_PRG_MASK (0xFFF00U)
\r
19893 #define USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT (8U)
\r
19894 /*! EP_LIST_PRG - Programmable portion of the USB EP Command/Status List address.
\r
19896 #define USBHSD_EPLISTSTART_EP_LIST_PRG(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_PRG_MASK)
\r
19897 #define USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK (0xFFF00000U)
\r
19898 #define USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT (20U)
\r
19899 /*! EP_LIST_FIXED - Fixed portion of USB EP Command/Status List address.
\r
19901 #define USBHSD_EPLISTSTART_EP_LIST_FIXED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK)
\r
19904 /*! @name DATABUFSTART - USB Data buffer start address */
\r
19906 #define USBHSD_DATABUFSTART_DA_BUF_MASK (0xFFFC0000U)
\r
19907 #define USBHSD_DATABUFSTART_DA_BUF_SHIFT (18U)
\r
19908 /*! DA_BUF - Start address of the memory page where all endpoint data buffers are located.
\r
19910 #define USBHSD_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DATABUFSTART_DA_BUF_SHIFT)) & USBHSD_DATABUFSTART_DA_BUF_MASK)
\r
19913 /*! @name LPM - USB Link Power Management register */
\r
19915 #define USBHSD_LPM_HIRD_HW_MASK (0xFU)
\r
19916 #define USBHSD_LPM_HIRD_HW_SHIFT (0U)
\r
19917 /*! HIRD_HW - Host Initiated Resume Duration - HW.
\r
19919 #define USBHSD_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_HW_SHIFT)) & USBHSD_LPM_HIRD_HW_MASK)
\r
19920 #define USBHSD_LPM_HIRD_SW_MASK (0xF0U)
\r
19921 #define USBHSD_LPM_HIRD_SW_SHIFT (4U)
\r
19922 /*! HIRD_SW - Host Initiated Resume Duration - SW.
\r
19924 #define USBHSD_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_SW_SHIFT)) & USBHSD_LPM_HIRD_SW_MASK)
\r
19925 #define USBHSD_LPM_DATA_PENDING_MASK (0x100U)
\r
19926 #define USBHSD_LPM_DATA_PENDING_SHIFT (8U)
\r
19927 /*! DATA_PENDING - As long as this bit is set to one and LPM supported bit is set to one, HW will
\r
19928 * return a NYET handshake on every LPM token it receives.
\r
19930 #define USBHSD_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_DATA_PENDING_SHIFT)) & USBHSD_LPM_DATA_PENDING_MASK)
\r
19933 /*! @name EPSKIP - USB Endpoint skip */
\r
19935 #define USBHSD_EPSKIP_SKIP_MASK (0xFFFU)
\r
19936 #define USBHSD_EPSKIP_SKIP_SHIFT (0U)
\r
19937 /*! SKIP - Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must
\r
19938 * deactivate the buffer assigned to this endpoint and return control back to software.
\r
19940 #define USBHSD_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPSKIP_SKIP_SHIFT)) & USBHSD_EPSKIP_SKIP_MASK)
\r
19943 /*! @name EPINUSE - USB Endpoint Buffer in use */
\r
19945 #define USBHSD_EPINUSE_BUF_MASK (0xFFCU)
\r
19946 #define USBHSD_EPINUSE_BUF_SHIFT (2U)
\r
19947 /*! BUF - Buffer in use: This register has one bit per physical endpoint.
\r
19949 #define USBHSD_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPINUSE_BUF_SHIFT)) & USBHSD_EPINUSE_BUF_MASK)
\r
19952 /*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */
\r
19954 #define USBHSD_EPBUFCFG_BUF_SB_MASK (0xFFCU)
\r
19955 #define USBHSD_EPBUFCFG_BUF_SB_SHIFT (2U)
\r
19956 /*! BUF_SB - Buffer usage: This register has one bit per physical endpoint.
\r
19958 #define USBHSD_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPBUFCFG_BUF_SB_SHIFT)) & USBHSD_EPBUFCFG_BUF_SB_MASK)
\r
19961 /*! @name INTSTAT - USB interrupt status register */
\r
19963 #define USBHSD_INTSTAT_EP0OUT_MASK (0x1U)
\r
19964 #define USBHSD_INTSTAT_EP0OUT_SHIFT (0U)
\r
19965 /*! EP0OUT - Interrupt status register bit for the Control EP0 OUT direction.
\r
19967 #define USBHSD_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0OUT_SHIFT)) & USBHSD_INTSTAT_EP0OUT_MASK)
\r
19968 #define USBHSD_INTSTAT_EP0IN_MASK (0x2U)
\r
19969 #define USBHSD_INTSTAT_EP0IN_SHIFT (1U)
\r
19970 /*! EP0IN - Interrupt status register bit for the Control EP0 IN direction.
\r
19972 #define USBHSD_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0IN_SHIFT)) & USBHSD_INTSTAT_EP0IN_MASK)
\r
19973 #define USBHSD_INTSTAT_EP1OUT_MASK (0x4U)
\r
19974 #define USBHSD_INTSTAT_EP1OUT_SHIFT (2U)
\r
19975 /*! EP1OUT - Interrupt status register bit for the EP1 OUT direction.
\r
19977 #define USBHSD_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1OUT_SHIFT)) & USBHSD_INTSTAT_EP1OUT_MASK)
\r
19978 #define USBHSD_INTSTAT_EP1IN_MASK (0x8U)
\r
19979 #define USBHSD_INTSTAT_EP1IN_SHIFT (3U)
\r
19980 /*! EP1IN - Interrupt status register bit for the EP1 IN direction.
\r
19982 #define USBHSD_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1IN_SHIFT)) & USBHSD_INTSTAT_EP1IN_MASK)
\r
19983 #define USBHSD_INTSTAT_EP2OUT_MASK (0x10U)
\r
19984 #define USBHSD_INTSTAT_EP2OUT_SHIFT (4U)
\r
19985 /*! EP2OUT - Interrupt status register bit for the EP2 OUT direction.
\r
19987 #define USBHSD_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2OUT_SHIFT)) & USBHSD_INTSTAT_EP2OUT_MASK)
\r
19988 #define USBHSD_INTSTAT_EP2IN_MASK (0x20U)
\r
19989 #define USBHSD_INTSTAT_EP2IN_SHIFT (5U)
\r
19990 /*! EP2IN - Interrupt status register bit for the EP2 IN direction.
\r
19992 #define USBHSD_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2IN_SHIFT)) & USBHSD_INTSTAT_EP2IN_MASK)
\r
19993 #define USBHSD_INTSTAT_EP3OUT_MASK (0x40U)
\r
19994 #define USBHSD_INTSTAT_EP3OUT_SHIFT (6U)
\r
19995 /*! EP3OUT - Interrupt status register bit for the EP3 OUT direction.
\r
19997 #define USBHSD_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3OUT_SHIFT)) & USBHSD_INTSTAT_EP3OUT_MASK)
\r
19998 #define USBHSD_INTSTAT_EP3IN_MASK (0x80U)
\r
19999 #define USBHSD_INTSTAT_EP3IN_SHIFT (7U)
\r
20000 /*! EP3IN - Interrupt status register bit for the EP3 IN direction.
\r
20002 #define USBHSD_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3IN_SHIFT)) & USBHSD_INTSTAT_EP3IN_MASK)
\r
20003 #define USBHSD_INTSTAT_EP4OUT_MASK (0x100U)
\r
20004 #define USBHSD_INTSTAT_EP4OUT_SHIFT (8U)
\r
20005 /*! EP4OUT - Interrupt status register bit for the EP4 OUT direction.
\r
20007 #define USBHSD_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4OUT_SHIFT)) & USBHSD_INTSTAT_EP4OUT_MASK)
\r
20008 #define USBHSD_INTSTAT_EP4IN_MASK (0x200U)
\r
20009 #define USBHSD_INTSTAT_EP4IN_SHIFT (9U)
\r
20010 /*! EP4IN - Interrupt status register bit for the EP4 IN direction.
\r
20012 #define USBHSD_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4IN_SHIFT)) & USBHSD_INTSTAT_EP4IN_MASK)
\r
20013 #define USBHSD_INTSTAT_EP5OUT_MASK (0x400U)
\r
20014 #define USBHSD_INTSTAT_EP5OUT_SHIFT (10U)
\r
20015 /*! EP5OUT - Interrupt status register bit for the EP5 OUT direction.
\r
20017 #define USBHSD_INTSTAT_EP5OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5OUT_SHIFT)) & USBHSD_INTSTAT_EP5OUT_MASK)
\r
20018 #define USBHSD_INTSTAT_EP5IN_MASK (0x800U)
\r
20019 #define USBHSD_INTSTAT_EP5IN_SHIFT (11U)
\r
20020 /*! EP5IN - Interrupt status register bit for the EP5 IN direction.
\r
20022 #define USBHSD_INTSTAT_EP5IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5IN_SHIFT)) & USBHSD_INTSTAT_EP5IN_MASK)
\r
20023 #define USBHSD_INTSTAT_FRAME_INT_MASK (0x40000000U)
\r
20024 #define USBHSD_INTSTAT_FRAME_INT_SHIFT (30U)
\r
20025 /*! FRAME_INT - Frame interrupt.
\r
20027 #define USBHSD_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_FRAME_INT_SHIFT)) & USBHSD_INTSTAT_FRAME_INT_MASK)
\r
20028 #define USBHSD_INTSTAT_DEV_INT_MASK (0x80000000U)
\r
20029 #define USBHSD_INTSTAT_DEV_INT_SHIFT (31U)
\r
20030 /*! DEV_INT - Device status interrupt.
\r
20032 #define USBHSD_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_DEV_INT_SHIFT)) & USBHSD_INTSTAT_DEV_INT_MASK)
\r
20035 /*! @name INTEN - USB interrupt enable register */
\r
20037 #define USBHSD_INTEN_EP_INT_EN_MASK (0xFFFU)
\r
20038 #define USBHSD_INTEN_EP_INT_EN_SHIFT (0U)
\r
20039 /*! EP_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW
\r
20040 * interrupt is generated on the interrupt line.
\r
20042 #define USBHSD_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_EP_INT_EN_SHIFT)) & USBHSD_INTEN_EP_INT_EN_MASK)
\r
20043 #define USBHSD_INTEN_FRAME_INT_EN_MASK (0x40000000U)
\r
20044 #define USBHSD_INTEN_FRAME_INT_EN_SHIFT (30U)
\r
20045 /*! FRAME_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW
\r
20046 * interrupt is generated on the interrupt line.
\r
20048 #define USBHSD_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_FRAME_INT_EN_SHIFT)) & USBHSD_INTEN_FRAME_INT_EN_MASK)
\r
20049 #define USBHSD_INTEN_DEV_INT_EN_MASK (0x80000000U)
\r
20050 #define USBHSD_INTEN_DEV_INT_EN_SHIFT (31U)
\r
20051 /*! DEV_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW
\r
20052 * interrupt is generated on the interrupt line.
\r
20054 #define USBHSD_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_DEV_INT_EN_SHIFT)) & USBHSD_INTEN_DEV_INT_EN_MASK)
\r
20057 /*! @name INTSETSTAT - USB set interrupt status register */
\r
20059 #define USBHSD_INTSETSTAT_EP_SET_INT_MASK (0xFFFU)
\r
20060 #define USBHSD_INTSETSTAT_EP_SET_INT_SHIFT (0U)
\r
20061 /*! EP_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set.
\r
20063 #define USBHSD_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_EP_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_EP_SET_INT_MASK)
\r
20064 #define USBHSD_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U)
\r
20065 #define USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT (30U)
\r
20066 /*! FRAME_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set.
\r
20068 #define USBHSD_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_FRAME_SET_INT_MASK)
\r
20069 #define USBHSD_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U)
\r
20070 #define USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT (31U)
\r
20071 /*! DEV_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set.
\r
20073 #define USBHSD_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_DEV_SET_INT_MASK)
\r
20076 /*! @name EPTOGGLE - USB Endpoint toggle register */
\r
20078 #define USBHSD_EPTOGGLE_TOGGLE_MASK (0x3FFFFFFFU)
\r
20079 #define USBHSD_EPTOGGLE_TOGGLE_SHIFT (0U)
\r
20080 /*! TOGGLE - Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint.
\r
20082 #define USBHSD_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPTOGGLE_TOGGLE_SHIFT)) & USBHSD_EPTOGGLE_TOGGLE_MASK)
\r
20088 */ /* end of group USBHSD_Register_Masks */
\r
20091 /* USBHSD - Peripheral instance base addresses */
\r
20092 /** Peripheral USBHSD base address */
\r
20093 #define USBHSD_BASE (0x40094000u)
\r
20094 /** Peripheral USBHSD base pointer */
\r
20095 #define USBHSD ((USBHSD_Type *)USBHSD_BASE)
\r
20096 /** Array initializer of USBHSD peripheral base addresses */
\r
20097 #define USBHSD_BASE_ADDRS { USBHSD_BASE }
\r
20098 /** Array initializer of USBHSD peripheral base pointers */
\r
20099 #define USBHSD_BASE_PTRS { USBHSD }
\r
20100 /** Interrupt vectors for the USBHSD peripheral type */
\r
20101 #define USBHSD_IRQS { USB1_IRQn }
\r
20102 #define USBHSD_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn }
\r
20106 */ /* end of group USBHSD_Peripheral_Access_Layer */
\r
20109 /* ----------------------------------------------------------------------------
\r
20110 -- USBHSH Peripheral Access Layer
\r
20111 ---------------------------------------------------------------------------- */
\r
20114 * @addtogroup USBHSH_Peripheral_Access_Layer USBHSH Peripheral Access Layer
\r
20118 /** USBHSH - Register Layout Typedef */
\r
20120 __I uint32_t CAPLENGTH_CHIPID; /**< This register contains the offset value towards the start of the operational register space and the version number of the IP block, offset: 0x0 */
\r
20121 __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x4 */
\r
20122 __I uint32_t HCCPARAMS; /**< Host Controller Capability Parameters, offset: 0x8 */
\r
20123 __IO uint32_t FLADJ_FRINDEX; /**< Frame Length Adjustment, offset: 0xC */
\r
20124 __IO uint32_t ATL_PTD_BASE_ADDR; /**< Memory base address where ATL PTD0 is stored, offset: 0x10 */
\r
20125 __IO uint32_t ISO_PTD_BASE_ADDR; /**< Memory base address where ISO PTD0 is stored, offset: 0x14 */
\r
20126 __IO uint32_t INT_PTD_BASE_ADDR; /**< Memory base address where INT PTD0 is stored, offset: 0x18 */
\r
20127 __IO uint32_t DATA_PAYLOAD_BASE_ADDR; /**< Memory base address that indicates the start of the data payload buffers, offset: 0x1C */
\r
20128 __IO uint32_t USBCMD; /**< USB Command register, offset: 0x20 */
\r
20129 __IO uint32_t USBSTS; /**< USB Interrupt Status register, offset: 0x24 */
\r
20130 __IO uint32_t USBINTR; /**< USB Interrupt Enable register, offset: 0x28 */
\r
20131 __IO uint32_t PORTSC1; /**< Port Status and Control register, offset: 0x2C */
\r
20132 __IO uint32_t ATL_PTD_DONE_MAP; /**< Done map for each ATL PTD, offset: 0x30 */
\r
20133 __IO uint32_t ATL_PTD_SKIP_MAP; /**< Skip map for each ATL PTD, offset: 0x34 */
\r
20134 __IO uint32_t ISO_PTD_DONE_MAP; /**< Done map for each ISO PTD, offset: 0x38 */
\r
20135 __IO uint32_t ISO_PTD_SKIP_MAP; /**< Skip map for each ISO PTD, offset: 0x3C */
\r
20136 __IO uint32_t INT_PTD_DONE_MAP; /**< Done map for each INT PTD, offset: 0x40 */
\r
20137 __IO uint32_t INT_PTD_SKIP_MAP; /**< Skip map for each INT PTD, offset: 0x44 */
\r
20138 __IO uint32_t LASTPTD; /**< Marks the last PTD in the list for ISO, INT and ATL, offset: 0x48 */
\r
20139 uint8_t RESERVED_0[4];
\r
20140 __IO uint32_t PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x50 */
\r
20143 /* ----------------------------------------------------------------------------
\r
20144 -- USBHSH Register Masks
\r
20145 ---------------------------------------------------------------------------- */
\r
20148 * @addtogroup USBHSH_Register_Masks USBHSH Register Masks
\r
20152 /*! @name CAPLENGTH_CHIPID - This register contains the offset value towards the start of the operational register space and the version number of the IP block */
\r
20154 #define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK (0xFFU)
\r
20155 #define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT (0U)
\r
20156 /*! CAPLENGTH - Capability Length: This is used as an offset.
\r
20158 #define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK)
\r
20159 #define USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK (0xFFFF0000U)
\r
20160 #define USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT (16U)
\r
20161 /*! CHIPID - Chip identification: indicates major and minor revision of the IP: [31:24] = Major
\r
20162 * revision [23:16] = Minor revision Major revisions used: 0x01: USB2.
\r
20164 #define USBHSH_CAPLENGTH_CHIPID_CHIPID(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK)
\r
20167 /*! @name HCSPARAMS - Host Controller Structural Parameters */
\r
20169 #define USBHSH_HCSPARAMS_N_PORTS_MASK (0xFU)
\r
20170 #define USBHSH_HCSPARAMS_N_PORTS_SHIFT (0U)
\r
20171 /*! N_PORTS - This register specifies the number of physical downstream ports implemented on this host controller.
\r
20173 #define USBHSH_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_N_PORTS_SHIFT)) & USBHSH_HCSPARAMS_N_PORTS_MASK)
\r
20174 #define USBHSH_HCSPARAMS_PPC_MASK (0x10U)
\r
20175 #define USBHSH_HCSPARAMS_PPC_SHIFT (4U)
\r
20176 /*! PPC - This field indicates whether the host controller implementation includes port power control.
\r
20178 #define USBHSH_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_PPC_SHIFT)) & USBHSH_HCSPARAMS_PPC_MASK)
\r
20179 #define USBHSH_HCSPARAMS_P_INDICATOR_MASK (0x10000U)
\r
20180 #define USBHSH_HCSPARAMS_P_INDICATOR_SHIFT (16U)
\r
20181 /*! P_INDICATOR - This bit indicates whether the ports support port indicator control.
\r
20183 #define USBHSH_HCSPARAMS_P_INDICATOR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_P_INDICATOR_SHIFT)) & USBHSH_HCSPARAMS_P_INDICATOR_MASK)
\r
20186 /*! @name HCCPARAMS - Host Controller Capability Parameters */
\r
20188 #define USBHSH_HCCPARAMS_LPMC_MASK (0x20000U)
\r
20189 #define USBHSH_HCCPARAMS_LPMC_SHIFT (17U)
\r
20190 /*! LPMC - Link Power Management Capability.
\r
20192 #define USBHSH_HCCPARAMS_LPMC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCCPARAMS_LPMC_SHIFT)) & USBHSH_HCCPARAMS_LPMC_MASK)
\r
20195 /*! @name FLADJ_FRINDEX - Frame Length Adjustment */
\r
20197 #define USBHSH_FLADJ_FRINDEX_FLADJ_MASK (0x3FU)
\r
20198 #define USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT (0U)
\r
20199 /*! FLADJ - Frame Length Timing Value.
\r
20201 #define USBHSH_FLADJ_FRINDEX_FLADJ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT)) & USBHSH_FLADJ_FRINDEX_FLADJ_MASK)
\r
20202 #define USBHSH_FLADJ_FRINDEX_FRINDEX_MASK (0x3FFF0000U)
\r
20203 #define USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT (16U)
\r
20204 /*! FRINDEX - Frame Index: Bits 29 to16 in this register are used for the frame number field in the SOF packet.
\r
20206 #define USBHSH_FLADJ_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT)) & USBHSH_FLADJ_FRINDEX_FRINDEX_MASK)
\r
20209 /*! @name ATL_PTD_BASE_ADDR - Memory base address where ATL PTD0 is stored */
\r
20211 #define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_MASK (0x1F0U)
\r
20212 #define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_SHIFT (4U)
\r
20213 /*! ATL_CUR - This indicates the current PTD that is used by the hardware when it is processing the ATL list.
\r
20215 #define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_SHIFT)) & USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_MASK)
\r
20216 #define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_MASK (0xFFFFFE00U)
\r
20217 #define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_SHIFT (9U)
\r
20218 /*! ATL_BASE - Base address to be used by the hardware to find the start of the ATL list.
\r
20220 #define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_SHIFT)) & USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_MASK)
\r
20223 /*! @name ISO_PTD_BASE_ADDR - Memory base address where ISO PTD0 is stored */
\r
20225 #define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_MASK (0x3E0U)
\r
20226 #define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_SHIFT (5U)
\r
20227 /*! ISO_FIRST - This indicates the first PTD that is used by the hardware when it is processing the ISO list.
\r
20229 #define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_SHIFT)) & USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_MASK)
\r
20230 #define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_MASK (0xFFFFFC00U)
\r
20231 #define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_SHIFT (10U)
\r
20232 /*! ISO_BASE - Base address to be used by the hardware to find the start of the ISO list.
\r
20234 #define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_SHIFT)) & USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_MASK)
\r
20237 /*! @name INT_PTD_BASE_ADDR - Memory base address where INT PTD0 is stored */
\r
20239 #define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_MASK (0x3E0U)
\r
20240 #define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_SHIFT (5U)
\r
20241 /*! INT_FIRST - This indicates the first PTD that is used by the hardware when it is processing the INT list.
\r
20243 #define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_SHIFT)) & USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_MASK)
\r
20244 #define USBHSH_INT_PTD_BASE_ADDR_INT_BASE_MASK (0xFFFFFC00U)
\r
20245 #define USBHSH_INT_PTD_BASE_ADDR_INT_BASE_SHIFT (10U)
\r
20246 /*! INT_BASE - Base address to be used by the hardware to find the start of the INT list.
\r
20248 #define USBHSH_INT_PTD_BASE_ADDR_INT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_BASE_ADDR_INT_BASE_SHIFT)) & USBHSH_INT_PTD_BASE_ADDR_INT_BASE_MASK)
\r
20251 /*! @name DATA_PAYLOAD_BASE_ADDR - Memory base address that indicates the start of the data payload buffers */
\r
20253 #define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_MASK (0xFFFF0000U)
\r
20254 #define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_SHIFT (16U)
\r
20255 /*! DAT_BASE - Base address to be used by the hardware to find the start of the data payload section.
\r
20257 #define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_SHIFT)) & USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_MASK)
\r
20260 /*! @name USBCMD - USB Command register */
\r
20262 #define USBHSH_USBCMD_RS_MASK (0x1U)
\r
20263 #define USBHSH_USBCMD_RS_SHIFT (0U)
\r
20264 /*! RS - Run/Stop: 1b = Run.
\r
20266 #define USBHSH_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_RS_SHIFT)) & USBHSH_USBCMD_RS_MASK)
\r
20267 #define USBHSH_USBCMD_HCRESET_MASK (0x2U)
\r
20268 #define USBHSH_USBCMD_HCRESET_SHIFT (1U)
\r
20269 /*! HCRESET - Host Controller Reset: This control bit is used by the software to reset the host controller.
\r
20271 #define USBHSH_USBCMD_HCRESET(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HCRESET_SHIFT)) & USBHSH_USBCMD_HCRESET_MASK)
\r
20272 #define USBHSH_USBCMD_FLS_MASK (0xCU)
\r
20273 #define USBHSH_USBCMD_FLS_SHIFT (2U)
\r
20274 /*! FLS - Frame List Size: This field specifies the size of the frame list.
\r
20276 #define USBHSH_USBCMD_FLS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_FLS_SHIFT)) & USBHSH_USBCMD_FLS_MASK)
\r
20277 #define USBHSH_USBCMD_LHCR_MASK (0x80U)
\r
20278 #define USBHSH_USBCMD_LHCR_SHIFT (7U)
\r
20279 /*! LHCR - Light Host Controller Reset: This bit allows the driver software to reset the host
\r
20280 * controller without affecting the state of the ports.
\r
20282 #define USBHSH_USBCMD_LHCR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LHCR_SHIFT)) & USBHSH_USBCMD_LHCR_MASK)
\r
20283 #define USBHSH_USBCMD_ATL_EN_MASK (0x100U)
\r
20284 #define USBHSH_USBCMD_ATL_EN_SHIFT (8U)
\r
20285 /*! ATL_EN - ATL List enabled.
\r
20287 #define USBHSH_USBCMD_ATL_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ATL_EN_SHIFT)) & USBHSH_USBCMD_ATL_EN_MASK)
\r
20288 #define USBHSH_USBCMD_ISO_EN_MASK (0x200U)
\r
20289 #define USBHSH_USBCMD_ISO_EN_SHIFT (9U)
\r
20290 /*! ISO_EN - ISO List enabled.
\r
20292 #define USBHSH_USBCMD_ISO_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ISO_EN_SHIFT)) & USBHSH_USBCMD_ISO_EN_MASK)
\r
20293 #define USBHSH_USBCMD_INT_EN_MASK (0x400U)
\r
20294 #define USBHSH_USBCMD_INT_EN_SHIFT (10U)
\r
20295 /*! INT_EN - INT List enabled.
\r
20297 #define USBHSH_USBCMD_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_INT_EN_SHIFT)) & USBHSH_USBCMD_INT_EN_MASK)
\r
20298 #define USBHSH_USBCMD_HIRD_MASK (0xF000000U)
\r
20299 #define USBHSH_USBCMD_HIRD_SHIFT (24U)
\r
20300 /*! HIRD - Host-Initiated Resume Duration.
\r
20302 #define USBHSH_USBCMD_HIRD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HIRD_SHIFT)) & USBHSH_USBCMD_HIRD_MASK)
\r
20305 /*! @name USBSTS - USB Interrupt Status register */
\r
20307 #define USBHSH_USBSTS_PCD_MASK (0x4U)
\r
20308 #define USBHSH_USBSTS_PCD_SHIFT (2U)
\r
20309 /*! PCD - Port Change Detect: The host controller sets this bit to logic 1 when any port has a
\r
20310 * change bit transition from a 0 to a one or a Force Port Resume bit transition from a 0 to a 1 as a
\r
20311 * result of a J-K transition detected on a suspended port.
\r
20313 #define USBHSH_USBSTS_PCD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_PCD_SHIFT)) & USBHSH_USBSTS_PCD_MASK)
\r
20314 #define USBHSH_USBSTS_FLR_MASK (0x8U)
\r
20315 #define USBHSH_USBSTS_FLR_SHIFT (3U)
\r
20316 /*! FLR - Frame List Rollover: The host controller sets this bit to logic 1 when the frame list
\r
20317 * index rolls over its maximum value to 0.
\r
20319 #define USBHSH_USBSTS_FLR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_FLR_SHIFT)) & USBHSH_USBSTS_FLR_MASK)
\r
20320 #define USBHSH_USBSTS_ATL_IRQ_MASK (0x10000U)
\r
20321 #define USBHSH_USBSTS_ATL_IRQ_SHIFT (16U)
\r
20322 /*! ATL_IRQ - ATL IRQ: Indicates that an ATL PTD (with I-bit set) was completed.
\r
20324 #define USBHSH_USBSTS_ATL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ATL_IRQ_SHIFT)) & USBHSH_USBSTS_ATL_IRQ_MASK)
\r
20325 #define USBHSH_USBSTS_ISO_IRQ_MASK (0x20000U)
\r
20326 #define USBHSH_USBSTS_ISO_IRQ_SHIFT (17U)
\r
20327 /*! ISO_IRQ - ISO IRQ: Indicates that an ISO PTD (with I-bit set) was completed.
\r
20329 #define USBHSH_USBSTS_ISO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ISO_IRQ_SHIFT)) & USBHSH_USBSTS_ISO_IRQ_MASK)
\r
20330 #define USBHSH_USBSTS_INT_IRQ_MASK (0x40000U)
\r
20331 #define USBHSH_USBSTS_INT_IRQ_SHIFT (18U)
\r
20332 /*! INT_IRQ - INT IRQ: Indicates that an INT PTD (with I-bit set) was completed.
\r
20334 #define USBHSH_USBSTS_INT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_INT_IRQ_SHIFT)) & USBHSH_USBSTS_INT_IRQ_MASK)
\r
20335 #define USBHSH_USBSTS_SOF_IRQ_MASK (0x80000U)
\r
20336 #define USBHSH_USBSTS_SOF_IRQ_SHIFT (19U)
\r
20337 /*! SOF_IRQ - SOF interrupt: Every time when the host sends a Start of Frame token on the USB bus, this bit is set.
\r
20339 #define USBHSH_USBSTS_SOF_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_SOF_IRQ_SHIFT)) & USBHSH_USBSTS_SOF_IRQ_MASK)
\r
20342 /*! @name USBINTR - USB Interrupt Enable register */
\r
20344 #define USBHSH_USBINTR_PCDE_MASK (0x4U)
\r
20345 #define USBHSH_USBINTR_PCDE_SHIFT (2U)
\r
20346 /*! PCDE - Port Change Detect Interrupt Enable: 1: enable 0: disable.
\r
20348 #define USBHSH_USBINTR_PCDE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_PCDE_SHIFT)) & USBHSH_USBINTR_PCDE_MASK)
\r
20349 #define USBHSH_USBINTR_FLRE_MASK (0x8U)
\r
20350 #define USBHSH_USBINTR_FLRE_SHIFT (3U)
\r
20351 /*! FLRE - Frame List Rollover Interrupt Enable: 1: enable 0: disable.
\r
20353 #define USBHSH_USBINTR_FLRE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_FLRE_SHIFT)) & USBHSH_USBINTR_FLRE_MASK)
\r
20354 #define USBHSH_USBINTR_ATL_IRQ_E_MASK (0x10000U)
\r
20355 #define USBHSH_USBINTR_ATL_IRQ_E_SHIFT (16U)
\r
20356 /*! ATL_IRQ_E - ATL IRQ Enable bit: 1: enable 0: disable.
\r
20358 #define USBHSH_USBINTR_ATL_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ATL_IRQ_E_SHIFT)) & USBHSH_USBINTR_ATL_IRQ_E_MASK)
\r
20359 #define USBHSH_USBINTR_ISO_IRQ_E_MASK (0x20000U)
\r
20360 #define USBHSH_USBINTR_ISO_IRQ_E_SHIFT (17U)
\r
20361 /*! ISO_IRQ_E - ISO IRQ Enable bit: 1: enable 0: disable.
\r
20363 #define USBHSH_USBINTR_ISO_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ISO_IRQ_E_SHIFT)) & USBHSH_USBINTR_ISO_IRQ_E_MASK)
\r
20364 #define USBHSH_USBINTR_INT_IRQ_E_MASK (0x40000U)
\r
20365 #define USBHSH_USBINTR_INT_IRQ_E_SHIFT (18U)
\r
20366 /*! INT_IRQ_E - INT IRQ Enable bit: 1: enable 0: disable.
\r
20368 #define USBHSH_USBINTR_INT_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_INT_IRQ_E_SHIFT)) & USBHSH_USBINTR_INT_IRQ_E_MASK)
\r
20369 #define USBHSH_USBINTR_SOF_E_MASK (0x80000U)
\r
20370 #define USBHSH_USBINTR_SOF_E_SHIFT (19U)
\r
20371 /*! SOF_E - SOF Interrupt Enable bit: 1: enable 0: disable.
\r
20373 #define USBHSH_USBINTR_SOF_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_SOF_E_SHIFT)) & USBHSH_USBINTR_SOF_E_MASK)
\r
20376 /*! @name PORTSC1 - Port Status and Control register */
\r
20378 #define USBHSH_PORTSC1_CCS_MASK (0x1U)
\r
20379 #define USBHSH_PORTSC1_CCS_SHIFT (0U)
\r
20380 /*! CCS - Current Connect Status: Logic 1 indicates a device is present on the port.
\r
20382 #define USBHSH_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CCS_SHIFT)) & USBHSH_PORTSC1_CCS_MASK)
\r
20383 #define USBHSH_PORTSC1_CSC_MASK (0x2U)
\r
20384 #define USBHSH_PORTSC1_CSC_SHIFT (1U)
\r
20385 /*! CSC - Connect Status Change: Logic 1 means that the value of CCS has changed.
\r
20387 #define USBHSH_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CSC_SHIFT)) & USBHSH_PORTSC1_CSC_MASK)
\r
20388 #define USBHSH_PORTSC1_PED_MASK (0x4U)
\r
20389 #define USBHSH_PORTSC1_PED_SHIFT (2U)
\r
20390 /*! PED - Port Enabled/Disabled.
\r
20392 #define USBHSH_PORTSC1_PED(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PED_SHIFT)) & USBHSH_PORTSC1_PED_MASK)
\r
20393 #define USBHSH_PORTSC1_PEDC_MASK (0x8U)
\r
20394 #define USBHSH_PORTSC1_PEDC_SHIFT (3U)
\r
20395 /*! PEDC - Port Enabled/Disabled Change: Logic 1 means that the value of PED has changed.
\r
20397 #define USBHSH_PORTSC1_PEDC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PEDC_SHIFT)) & USBHSH_PORTSC1_PEDC_MASK)
\r
20398 #define USBHSH_PORTSC1_OCA_MASK (0x10U)
\r
20399 #define USBHSH_PORTSC1_OCA_SHIFT (4U)
\r
20400 /*! OCA - Over-current active: Logic 1 means that this port has an over-current condition.
\r
20402 #define USBHSH_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCA_SHIFT)) & USBHSH_PORTSC1_OCA_MASK)
\r
20403 #define USBHSH_PORTSC1_OCC_MASK (0x20U)
\r
20404 #define USBHSH_PORTSC1_OCC_SHIFT (5U)
\r
20405 /*! OCC - Over-current change: Logic 1 means that the value of OCA has changed.
\r
20407 #define USBHSH_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCC_SHIFT)) & USBHSH_PORTSC1_OCC_MASK)
\r
20408 #define USBHSH_PORTSC1_FPR_MASK (0x40U)
\r
20409 #define USBHSH_PORTSC1_FPR_SHIFT (6U)
\r
20410 /*! FPR - Force Port Resume: Logic 1 means resume (K-state) detected or driven on the port.
\r
20412 #define USBHSH_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_FPR_SHIFT)) & USBHSH_PORTSC1_FPR_MASK)
\r
20413 #define USBHSH_PORTSC1_SUSP_MASK (0x80U)
\r
20414 #define USBHSH_PORTSC1_SUSP_SHIFT (7U)
\r
20415 /*! SUSP - Suspend: Logic 1 means port is in the suspend state.
\r
20417 #define USBHSH_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUSP_SHIFT)) & USBHSH_PORTSC1_SUSP_MASK)
\r
20418 #define USBHSH_PORTSC1_PR_MASK (0x100U)
\r
20419 #define USBHSH_PORTSC1_PR_SHIFT (8U)
\r
20420 /*! PR - Port Reset: Logic 1 means the port is in the reset state.
\r
20422 #define USBHSH_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PR_SHIFT)) & USBHSH_PORTSC1_PR_MASK)
\r
20423 #define USBHSH_PORTSC1_SUS_L1_MASK (0x200U)
\r
20424 #define USBHSH_PORTSC1_SUS_L1_SHIFT (9U)
\r
20425 /*! SUS_L1 - Suspend using L1 0b = Suspend using L2 1b = Suspend using L1 When this bit is set to a
\r
20426 * 1 and a non-zero value is specified in the Device Address field, the host controller will
\r
20427 * generate an LPM Token to enter the L1 state whenever software writes a one to the Suspend bit, as
\r
20428 * well as L1 exit timing during any device or host-initiated resume.
\r
20430 #define USBHSH_PORTSC1_SUS_L1(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUS_L1_SHIFT)) & USBHSH_PORTSC1_SUS_L1_MASK)
\r
20431 #define USBHSH_PORTSC1_LS_MASK (0xC00U)
\r
20432 #define USBHSH_PORTSC1_LS_SHIFT (10U)
\r
20433 /*! LS - Line Status: This field reflects the current logical levels of the DP (bit 11) and DM (bit 10) signal lines.
\r
20435 #define USBHSH_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_LS_SHIFT)) & USBHSH_PORTSC1_LS_MASK)
\r
20436 #define USBHSH_PORTSC1_PP_MASK (0x1000U)
\r
20437 #define USBHSH_PORTSC1_PP_SHIFT (12U)
\r
20438 /*! PP - Port Power: The function of this bit depends on the value of the Port Power Control (PPC) bit in the HCSPARAMS register.
\r
20440 #define USBHSH_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PP_SHIFT)) & USBHSH_PORTSC1_PP_MASK)
\r
20441 #define USBHSH_PORTSC1_PIC_MASK (0xC000U)
\r
20442 #define USBHSH_PORTSC1_PIC_SHIFT (14U)
\r
20443 /*! PIC - Port Indicator Control : Writing to this field has no effect if the P_INDICATOR bit in the
\r
20444 * HCSPARAMS register is logic 0.
\r
20446 #define USBHSH_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PIC_SHIFT)) & USBHSH_PORTSC1_PIC_MASK)
\r
20447 #define USBHSH_PORTSC1_PTC_MASK (0xF0000U)
\r
20448 #define USBHSH_PORTSC1_PTC_SHIFT (16U)
\r
20449 /*! PTC - Port Test Control: A non-zero value indicates that the port is operating in the test mode as indicated by the value.
\r
20451 #define USBHSH_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PTC_SHIFT)) & USBHSH_PORTSC1_PTC_MASK)
\r
20452 #define USBHSH_PORTSC1_PSPD_MASK (0x300000U)
\r
20453 #define USBHSH_PORTSC1_PSPD_SHIFT (20U)
\r
20454 /*! PSPD - Port Speed: 00b: Low-speed 01b: Full-speed 10b: High-speed 11b: Reserved.
\r
20456 #define USBHSH_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PSPD_SHIFT)) & USBHSH_PORTSC1_PSPD_MASK)
\r
20457 #define USBHSH_PORTSC1_WOO_MASK (0x400000U)
\r
20458 #define USBHSH_PORTSC1_WOO_SHIFT (22U)
\r
20459 /*! WOO - Wake on overcurrent enable: Writing this bit to a one enables the port to be sensitive to
\r
20460 * overcurrent conditions as wake-up events.
\r
20462 #define USBHSH_PORTSC1_WOO(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_WOO_SHIFT)) & USBHSH_PORTSC1_WOO_MASK)
\r
20463 #define USBHSH_PORTSC1_SUS_STAT_MASK (0x1800000U)
\r
20464 #define USBHSH_PORTSC1_SUS_STAT_SHIFT (23U)
\r
20465 /*! SUS_STAT - These two bits are used by software to determine whether the most recent L1 suspend
\r
20466 * request was successful: 00b: Success-state transition was successful (ACK) 01b: Not Yet -
\r
20467 * Device was unable to enter the L1 state at this time (NYET) 10b: Not supported - Device does not
\r
20468 * support the L1 state (STALL) 11b: Timeout/Error - Device failed to respond or an error occurred.
\r
20470 #define USBHSH_PORTSC1_SUS_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUS_STAT_SHIFT)) & USBHSH_PORTSC1_SUS_STAT_MASK)
\r
20471 #define USBHSH_PORTSC1_DEV_ADD_MASK (0xFE000000U)
\r
20472 #define USBHSH_PORTSC1_DEV_ADD_SHIFT (25U)
\r
20473 /*! DEV_ADD - Device Address for LPM tokens.
\r
20475 #define USBHSH_PORTSC1_DEV_ADD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_DEV_ADD_SHIFT)) & USBHSH_PORTSC1_DEV_ADD_MASK)
\r
20478 /*! @name ATL_PTD_DONE_MAP - Done map for each ATL PTD */
\r
20480 #define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_MASK (0xFFFFFFFFU)
\r
20481 #define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_SHIFT (0U)
\r
20482 /*! ATL_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed.
\r
20484 #define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_SHIFT)) & USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_MASK)
\r
20487 /*! @name ATL_PTD_SKIP_MAP - Skip map for each ATL PTD */
\r
20489 #define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_MASK (0xFFFFFFFFU)
\r
20490 #define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_SHIFT (0U)
\r
20491 /*! ATL_SKIP - When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be
\r
20492 * skipped, independent of the V bit setting.
\r
20494 #define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_SHIFT)) & USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_MASK)
\r
20497 /*! @name ISO_PTD_DONE_MAP - Done map for each ISO PTD */
\r
20499 #define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_MASK (0xFFFFFFFFU)
\r
20500 #define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_SHIFT (0U)
\r
20501 /*! ISO_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed.
\r
20503 #define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_SHIFT)) & USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_MASK)
\r
20506 /*! @name ISO_PTD_SKIP_MAP - Skip map for each ISO PTD */
\r
20508 #define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_MASK (0xFFFFFFFFU)
\r
20509 #define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_SHIFT (0U)
\r
20510 /*! ISO_SKIP - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed.
\r
20512 #define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_SHIFT)) & USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_MASK)
\r
20515 /*! @name INT_PTD_DONE_MAP - Done map for each INT PTD */
\r
20517 #define USBHSH_INT_PTD_DONE_MAP_INT_DONE_MASK (0xFFFFFFFFU)
\r
20518 #define USBHSH_INT_PTD_DONE_MAP_INT_DONE_SHIFT (0U)
\r
20519 /*! INT_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed.
\r
20521 #define USBHSH_INT_PTD_DONE_MAP_INT_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_DONE_MAP_INT_DONE_SHIFT)) & USBHSH_INT_PTD_DONE_MAP_INT_DONE_MASK)
\r
20524 /*! @name INT_PTD_SKIP_MAP - Skip map for each INT PTD */
\r
20526 #define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_MASK (0xFFFFFFFFU)
\r
20527 #define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_SHIFT (0U)
\r
20528 /*! INT_SKIP - When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be
\r
20529 * skipped, independent of the V bit setting.
\r
20531 #define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_SHIFT)) & USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_MASK)
\r
20534 /*! @name LASTPTD - Marks the last PTD in the list for ISO, INT and ATL */
\r
20536 #define USBHSH_LASTPTD_ATL_LAST_MASK (0x1FU)
\r
20537 #define USBHSH_LASTPTD_ATL_LAST_SHIFT (0U)
\r
20538 /*! ATL_LAST - If hardware has reached this PTD and the J bit is not set, it will go to PTD0 as the next PTD to be processed.
\r
20540 #define USBHSH_LASTPTD_ATL_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_ATL_LAST_SHIFT)) & USBHSH_LASTPTD_ATL_LAST_MASK)
\r
20541 #define USBHSH_LASTPTD_ISO_LAST_MASK (0x1F00U)
\r
20542 #define USBHSH_LASTPTD_ISO_LAST_SHIFT (8U)
\r
20543 /*! ISO_LAST - This indicates the last PTD in the ISO list.
\r
20545 #define USBHSH_LASTPTD_ISO_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_ISO_LAST_SHIFT)) & USBHSH_LASTPTD_ISO_LAST_MASK)
\r
20546 #define USBHSH_LASTPTD_INT_LAST_MASK (0x1F0000U)
\r
20547 #define USBHSH_LASTPTD_INT_LAST_SHIFT (16U)
\r
20548 /*! INT_LAST - This indicates the last PTD in the INT list.
\r
20550 #define USBHSH_LASTPTD_INT_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_INT_LAST_SHIFT)) & USBHSH_LASTPTD_INT_LAST_MASK)
\r
20553 /*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */
\r
20555 #define USBHSH_PORTMODE_ID0_MASK (0x1U)
\r
20556 #define USBHSH_PORTMODE_ID0_SHIFT (0U)
\r
20557 /*! ID0 - Port 0 ID pin value.
\r
20559 #define USBHSH_PORTMODE_ID0(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_ID0_SHIFT)) & USBHSH_PORTMODE_ID0_MASK)
\r
20560 #define USBHSH_PORTMODE_ID0_EN_MASK (0x100U)
\r
20561 #define USBHSH_PORTMODE_ID0_EN_SHIFT (8U)
\r
20562 /*! ID0_EN - Port 0 ID pin pull-up enable.
\r
20564 #define USBHSH_PORTMODE_ID0_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_ID0_EN_SHIFT)) & USBHSH_PORTMODE_ID0_EN_MASK)
\r
20565 #define USBHSH_PORTMODE_DEV_ENABLE_MASK (0x10000U)
\r
20566 #define USBHSH_PORTMODE_DEV_ENABLE_SHIFT (16U)
\r
20567 /*! DEV_ENABLE - If this bit is set to one, one of the ports will behave as a USB device.
\r
20569 #define USBHSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBHSH_PORTMODE_DEV_ENABLE_MASK)
\r
20570 #define USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK (0x40000U)
\r
20571 #define USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT (18U)
\r
20572 /*! SW_CTRL_PDCOM - This bit indicates if the PHY power-down input is controlled by software or by hardware.
\r
20574 #define USBHSH_PORTMODE_SW_CTRL_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK)
\r
20575 #define USBHSH_PORTMODE_SW_PDCOM_MASK (0x80000U)
\r
20576 #define USBHSH_PORTMODE_SW_PDCOM_SHIFT (19U)
\r
20577 /*! SW_PDCOM - This bit is only used when SW_CTRL_PDCOM is set to 1b.
\r
20579 #define USBHSH_PORTMODE_SW_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_PDCOM_MASK)
\r
20585 */ /* end of group USBHSH_Register_Masks */
\r
20588 /* USBHSH - Peripheral instance base addresses */
\r
20589 /** Peripheral USBHSH base address */
\r
20590 #define USBHSH_BASE (0x400A3000u)
\r
20591 /** Peripheral USBHSH base pointer */
\r
20592 #define USBHSH ((USBHSH_Type *)USBHSH_BASE)
\r
20593 /** Array initializer of USBHSH peripheral base addresses */
\r
20594 #define USBHSH_BASE_ADDRS { USBHSH_BASE }
\r
20595 /** Array initializer of USBHSH peripheral base pointers */
\r
20596 #define USBHSH_BASE_PTRS { USBHSH }
\r
20597 /** Interrupt vectors for the USBHSH peripheral type */
\r
20598 #define USBHSH_IRQS { USB1_IRQn }
\r
20599 #define USBHSH_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn }
\r
20603 */ /* end of group USBHSH_Peripheral_Access_Layer */
\r
20606 /* ----------------------------------------------------------------------------
\r
20607 -- UTICK Peripheral Access Layer
\r
20608 ---------------------------------------------------------------------------- */
\r
20611 * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer
\r
20615 /** UTICK - Register Layout Typedef */
\r
20617 __IO uint32_t CTRL; /**< Control register., offset: 0x0 */
\r
20618 __IO uint32_t STAT; /**< Status register., offset: 0x4 */
\r
20619 __IO uint32_t CFG; /**< Capture configuration register., offset: 0x8 */
\r
20620 __O uint32_t CAPCLR; /**< Capture clear register., offset: 0xC */
\r
20621 __I uint32_t CAP[4]; /**< Capture register ., array offset: 0x10, array step: 0x4 */
\r
20624 /* ----------------------------------------------------------------------------
\r
20625 -- UTICK Register Masks
\r
20626 ---------------------------------------------------------------------------- */
\r
20629 * @addtogroup UTICK_Register_Masks UTICK Register Masks
\r
20633 /*! @name CTRL - Control register. */
\r
20635 #define UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU)
\r
20636 #define UTICK_CTRL_DELAYVAL_SHIFT (0U)
\r
20637 /*! DELAYVAL - Tick interval value. The delay will be equal to DELAYVAL + 1 periods of the timer
\r
20638 * clock. The minimum usable value is 1, for a delay of 2 timer clocks. A value of 0 stops the timer.
\r
20640 #define UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK)
\r
20641 #define UTICK_CTRL_REPEAT_MASK (0x80000000U)
\r
20642 #define UTICK_CTRL_REPEAT_SHIFT (31U)
\r
20643 /*! REPEAT - Repeat delay. 0 = One-time delay. 1 = Delay repeats continuously.
\r
20645 #define UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK)
\r
20648 /*! @name STAT - Status register. */
\r
20650 #define UTICK_STAT_INTR_MASK (0x1U)
\r
20651 #define UTICK_STAT_INTR_SHIFT (0U)
\r
20652 /*! INTR - Interrupt flag. 0 = No interrupt is pending. 1 = An interrupt is pending. A write of any
\r
20653 * value to this register clears this flag.
\r
20655 #define UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK)
\r
20656 #define UTICK_STAT_ACTIVE_MASK (0x2U)
\r
20657 #define UTICK_STAT_ACTIVE_SHIFT (1U)
\r
20658 /*! ACTIVE - Active flag. 0 = The Micro-Tick Timer is stopped. 1 = The Micro-Tick Timer is currently active.
\r
20660 #define UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK)
\r
20663 /*! @name CFG - Capture configuration register. */
\r
20665 #define UTICK_CFG_CAPEN0_MASK (0x1U)
\r
20666 #define UTICK_CFG_CAPEN0_SHIFT (0U)
\r
20667 /*! CAPEN0 - Enable Capture 0. 1 = Enabled, 0 = Disabled.
\r
20669 #define UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK)
\r
20670 #define UTICK_CFG_CAPEN1_MASK (0x2U)
\r
20671 #define UTICK_CFG_CAPEN1_SHIFT (1U)
\r
20672 /*! CAPEN1 - Enable Capture 1. 1 = Enabled, 0 = Disabled.
\r
20674 #define UTICK_CFG_CAPEN1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK)
\r
20675 #define UTICK_CFG_CAPEN2_MASK (0x4U)
\r
20676 #define UTICK_CFG_CAPEN2_SHIFT (2U)
\r
20677 /*! CAPEN2 - Enable Capture 2. 1 = Enabled, 0 = Disabled.
\r
20679 #define UTICK_CFG_CAPEN2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK)
\r
20680 #define UTICK_CFG_CAPEN3_MASK (0x8U)
\r
20681 #define UTICK_CFG_CAPEN3_SHIFT (3U)
\r
20682 /*! CAPEN3 - Enable Capture 3. 1 = Enabled, 0 = Disabled.
\r
20684 #define UTICK_CFG_CAPEN3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK)
\r
20685 #define UTICK_CFG_CAPPOL0_MASK (0x100U)
\r
20686 #define UTICK_CFG_CAPPOL0_SHIFT (8U)
\r
20687 /*! CAPPOL0 - Capture Polarity 0. 0 = Positive edge capture, 1 = Negative edge capture.
\r
20689 #define UTICK_CFG_CAPPOL0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK)
\r
20690 #define UTICK_CFG_CAPPOL1_MASK (0x200U)
\r
20691 #define UTICK_CFG_CAPPOL1_SHIFT (9U)
\r
20692 /*! CAPPOL1 - Capture Polarity 1. 0 = Positive edge capture, 1 = Negative edge capture.
\r
20694 #define UTICK_CFG_CAPPOL1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK)
\r
20695 #define UTICK_CFG_CAPPOL2_MASK (0x400U)
\r
20696 #define UTICK_CFG_CAPPOL2_SHIFT (10U)
\r
20697 /*! CAPPOL2 - Capture Polarity 2. 0 = Positive edge capture, 1 = Negative edge capture.
\r
20699 #define UTICK_CFG_CAPPOL2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK)
\r
20700 #define UTICK_CFG_CAPPOL3_MASK (0x800U)
\r
20701 #define UTICK_CFG_CAPPOL3_SHIFT (11U)
\r
20702 /*! CAPPOL3 - Capture Polarity 3. 0 = Positive edge capture, 1 = Negative edge capture.
\r
20704 #define UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK)
\r
20707 /*! @name CAPCLR - Capture clear register. */
\r
20709 #define UTICK_CAPCLR_CAPCLR0_MASK (0x1U)
\r
20710 #define UTICK_CAPCLR_CAPCLR0_SHIFT (0U)
\r
20711 /*! CAPCLR0 - Clear capture 0. Writing 1 to this bit clears the CAP0 register value.
\r
20713 #define UTICK_CAPCLR_CAPCLR0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK)
\r
20714 #define UTICK_CAPCLR_CAPCLR1_MASK (0x2U)
\r
20715 #define UTICK_CAPCLR_CAPCLR1_SHIFT (1U)
\r
20716 /*! CAPCLR1 - Clear capture 1. Writing 1 to this bit clears the CAP1 register value.
\r
20718 #define UTICK_CAPCLR_CAPCLR1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK)
\r
20719 #define UTICK_CAPCLR_CAPCLR2_MASK (0x4U)
\r
20720 #define UTICK_CAPCLR_CAPCLR2_SHIFT (2U)
\r
20721 /*! CAPCLR2 - Clear capture 2. Writing 1 to this bit clears the CAP2 register value.
\r
20723 #define UTICK_CAPCLR_CAPCLR2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK)
\r
20724 #define UTICK_CAPCLR_CAPCLR3_MASK (0x8U)
\r
20725 #define UTICK_CAPCLR_CAPCLR3_SHIFT (3U)
\r
20726 /*! CAPCLR3 - Clear capture 3. Writing 1 to this bit clears the CAP3 register value.
\r
20728 #define UTICK_CAPCLR_CAPCLR3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK)
\r
20731 /*! @name CAP - Capture register . */
\r
20733 #define UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU)
\r
20734 #define UTICK_CAP_CAP_VALUE_SHIFT (0U)
\r
20735 /*! CAP_VALUE - Capture value for the related capture event (UTICK_CAPn. Note: the value is 1 lower
\r
20736 * than the actual value of the Micro-tick Timer at the moment of the capture event.
\r
20738 #define UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK)
\r
20739 #define UTICK_CAP_VALID_MASK (0x80000000U)
\r
20740 #define UTICK_CAP_VALID_SHIFT (31U)
\r
20741 /*! VALID - Capture Valid. When 1, a value has been captured based on a transition of the related
\r
20742 * UTICK_CAPn pin. Cleared by writing to the related bit in the CAPCLR register.
\r
20744 #define UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK)
\r
20747 /* The count of UTICK_CAP */
\r
20748 #define UTICK_CAP_COUNT (4U)
\r
20753 */ /* end of group UTICK_Register_Masks */
\r
20756 /* UTICK - Peripheral instance base addresses */
\r
20757 /** Peripheral UTICK0 base address */
\r
20758 #define UTICK0_BASE (0x4000E000u)
\r
20759 /** Peripheral UTICK0 base pointer */
\r
20760 #define UTICK0 ((UTICK_Type *)UTICK0_BASE)
\r
20761 /** Array initializer of UTICK peripheral base addresses */
\r
20762 #define UTICK_BASE_ADDRS { UTICK0_BASE }
\r
20763 /** Array initializer of UTICK peripheral base pointers */
\r
20764 #define UTICK_BASE_PTRS { UTICK0 }
\r
20765 /** Interrupt vectors for the UTICK peripheral type */
\r
20766 #define UTICK_IRQS { UTICK0_IRQn }
\r
20770 */ /* end of group UTICK_Peripheral_Access_Layer */
\r
20773 /* ----------------------------------------------------------------------------
\r
20774 -- WWDT Peripheral Access Layer
\r
20775 ---------------------------------------------------------------------------- */
\r
20778 * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer
\r
20782 /** WWDT - Register Layout Typedef */
\r
20784 __IO uint32_t MOD; /**< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer., offset: 0x0 */
\r
20785 __IO uint32_t TC; /**< Watchdog timer constant register. This 24-bit register determines the time-out value., offset: 0x4 */
\r
20786 __O uint32_t FEED; /**< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC., offset: 0x8 */
\r
20787 __I uint32_t TV; /**< Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer., offset: 0xC */
\r
20788 uint8_t RESERVED_0[4];
\r
20789 __IO uint32_t WARNINT; /**< Watchdog Warning Interrupt compare value., offset: 0x14 */
\r
20790 __IO uint32_t WINDOW; /**< Watchdog Window compare value., offset: 0x18 */
\r
20793 /* ----------------------------------------------------------------------------
\r
20794 -- WWDT Register Masks
\r
20795 ---------------------------------------------------------------------------- */
\r
20798 * @addtogroup WWDT_Register_Masks WWDT Register Masks
\r
20802 /*! @name MOD - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
\r
20804 #define WWDT_MOD_WDEN_MASK (0x1U)
\r
20805 #define WWDT_MOD_WDEN_SHIFT (0U)
\r
20806 /*! WDEN - Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the
\r
20807 * watchdog timer will run permanently.
\r
20808 * 0b0..Stop. The watchdog timer is stopped.
\r
20809 * 0b1..Run. The watchdog timer is running.
\r
20811 #define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK)
\r
20812 #define WWDT_MOD_WDRESET_MASK (0x2U)
\r
20813 #define WWDT_MOD_WDRESET_SHIFT (1U)
\r
20814 /*! WDRESET - Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0.
\r
20815 * 0b0..Interrupt. A watchdog time-out will not cause a chip reset.
\r
20816 * 0b1..Reset. A watchdog time-out will cause a chip reset.
\r
20818 #define WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK)
\r
20819 #define WWDT_MOD_WDTOF_MASK (0x4U)
\r
20820 #define WWDT_MOD_WDTOF_SHIFT (2U)
\r
20821 /*! WDTOF - Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by
\r
20822 * events associated with WDPROTECT. Cleared by software writing a 0 to this bit position. Causes a
\r
20823 * chip reset if WDRESET = 1.
\r
20825 #define WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK)
\r
20826 #define WWDT_MOD_WDINT_MASK (0x8U)
\r
20827 #define WWDT_MOD_WDINT_SHIFT (3U)
\r
20828 /*! WDINT - Warning interrupt flag. Set when the timer is at or below the value in WDWARNINT.
\r
20829 * Cleared by software writing a 1 to this bit position. Note that this bit cannot be cleared while the
\r
20830 * WARNINT value is equal to the value of the TV register. This can occur if the value of
\r
20831 * WARNINT is 0 and the WDRESET bit is 0 when TV decrements to 0.
\r
20833 #define WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK)
\r
20834 #define WWDT_MOD_WDPROTECT_MASK (0x10U)
\r
20835 #define WWDT_MOD_WDPROTECT_SHIFT (4U)
\r
20836 /*! WDPROTECT - Watchdog update mode. This bit can be set once by software and is only cleared by a reset.
\r
20837 * 0b0..Flexible. The watchdog time-out value (TC) can be changed at any time.
\r
20838 * 0b1..Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW.
\r
20840 #define WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK)
\r
20841 #define WWDT_MOD_LOCK_MASK (0x20U)
\r
20842 #define WWDT_MOD_LOCK_SHIFT (5U)
\r
20843 /*! LOCK - Once this bit is set to one and a watchdog feed is performed, disabling or powering down
\r
20844 * the watchdog oscillator is prevented by hardware. This bit can be set once by software and is
\r
20845 * only cleared by any reset.
\r
20847 #define WWDT_MOD_LOCK(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_LOCK_SHIFT)) & WWDT_MOD_LOCK_MASK)
\r
20850 /*! @name TC - Watchdog timer constant register. This 24-bit register determines the time-out value. */
\r
20852 #define WWDT_TC_COUNT_MASK (0xFFFFFFU)
\r
20853 #define WWDT_TC_COUNT_SHIFT (0U)
\r
20854 /*! COUNT - Watchdog time-out value.
\r
20856 #define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK)
\r
20859 /*! @name FEED - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. */
\r
20861 #define WWDT_FEED_FEED_MASK (0xFFU)
\r
20862 #define WWDT_FEED_FEED_SHIFT (0U)
\r
20863 /*! FEED - Feed value should be 0xAA followed by 0x55.
\r
20865 #define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK)
\r
20868 /*! @name TV - Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */
\r
20870 #define WWDT_TV_COUNT_MASK (0xFFFFFFU)
\r
20871 #define WWDT_TV_COUNT_SHIFT (0U)
\r
20872 /*! COUNT - Counter timer value.
\r
20874 #define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK)
\r
20877 /*! @name WARNINT - Watchdog Warning Interrupt compare value. */
\r
20879 #define WWDT_WARNINT_WARNINT_MASK (0x3FFU)
\r
20880 #define WWDT_WARNINT_WARNINT_SHIFT (0U)
\r
20881 /*! WARNINT - Watchdog warning interrupt compare value.
\r
20883 #define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK)
\r
20886 /*! @name WINDOW - Watchdog Window compare value. */
\r
20888 #define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU)
\r
20889 #define WWDT_WINDOW_WINDOW_SHIFT (0U)
\r
20890 /*! WINDOW - Watchdog window value.
\r
20892 #define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK)
\r
20898 */ /* end of group WWDT_Register_Masks */
\r
20901 /* WWDT - Peripheral instance base addresses */
\r
20902 /** Peripheral WWDT base address */
\r
20903 #define WWDT_BASE (0x4000C000u)
\r
20904 /** Peripheral WWDT base pointer */
\r
20905 #define WWDT ((WWDT_Type *)WWDT_BASE)
\r
20906 /** Array initializer of WWDT peripheral base addresses */
\r
20907 #define WWDT_BASE_ADDRS { WWDT_BASE }
\r
20908 /** Array initializer of WWDT peripheral base pointers */
\r
20909 #define WWDT_BASE_PTRS { WWDT }
\r
20910 /** Interrupt vectors for the WWDT peripheral type */
\r
20911 #define WWDT_IRQS { WDT_BOD_IRQn }
\r
20915 */ /* end of group WWDT_Peripheral_Access_Layer */
\r
20919 ** End of section using anonymous unions
\r
20922 #if defined(__ARMCC_VERSION)
\r
20923 #if (__ARMCC_VERSION >= 6010050)
\r
20924 #pragma clang diagnostic pop
\r
20928 #elif defined(__GNUC__)
\r
20929 /* leave anonymous unions enabled */
\r
20930 #elif defined(__IAR_SYSTEMS_ICC__)
\r
20931 #pragma language=default
\r
20933 #error Not supported compiler type
\r
20938 */ /* end of group Peripheral_access_layer */
\r
20941 /* ----------------------------------------------------------------------------
\r
20942 -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
\r
20943 ---------------------------------------------------------------------------- */
\r
20946 * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
\r
20950 #if defined(__ARMCC_VERSION)
\r
20951 #if (__ARMCC_VERSION >= 6010050)
\r
20952 #pragma clang system_header
\r
20954 #elif defined(__IAR_SYSTEMS_ICC__)
\r
20955 #pragma system_include
\r
20959 * @brief Mask and left-shift a bit field value for use in a register bit range.
\r
20960 * @param field Name of the register bit field.
\r
20961 * @param value Value of the bit field.
\r
20962 * @return Masked and shifted value.
\r
20964 #define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK))
\r
20966 * @brief Mask and right-shift a register value to extract a bit field value.
\r
20967 * @param field Name of the register bit field.
\r
20968 * @param value Value of the register.
\r
20969 * @return Masked and shifted bit field value.
\r
20971 #define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT))
\r
20975 */ /* end of group Bit_Field_Generic_Macros */
\r
20978 /* ----------------------------------------------------------------------------
\r
20979 -- SDK Compatibility
\r
20980 ---------------------------------------------------------------------------- */
\r
20983 * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
\r
20987 /** EMC CS base address */
\r
20988 #define EMC_CS0_BASE (0x80000000u)
\r
20989 #define EMC_CS1_BASE (0x88000000u)
\r
20990 #define EMC_CS2_BASE (0x90000000u)
\r
20991 #define EMC_CS3_BASE (0x98000000u)
\r
20992 #define EMC_DYCS0_BASE (0xA0000000u)
\r
20993 #define EMC_DYCS1_BASE (0xA8000000u)
\r
20994 #define EMC_DYCS2_BASE (0xB0000000u)
\r
20995 #define EMC_DYCS3_BASE (0xB8000000u)
\r
20996 #define EMC_CS_ADDRESS {EMC_CS0_BASE, EMC_CS1_BASE, EMC_CS2_BASE, EMC_CS3_BASE}
\r
20997 #define EMC_DYCS_ADDRESS {EMC_DYCS0_BASE, EMC_DYCS1_BASE, EMC_DYCS2_BASE, EMC_DYCS3_BASE}
\r
21001 uint32_t (*otpInit)(void); /** Initializes OTP controller */
\r
21002 uint32_t (*otpEnableBankWriteMask)(uint32_t bankMask); /** Unlock one or more OTP banks for write access */
\r
21003 uint32_t (*otpDisableBankWriteMask)(uint32_t bankMask); /** Lock one or more OTP banks for write access */
\r
21004 uint32_t (*otpEnableBankWriteLock)(uint32_t bankIndex, uint32_t regEnableMask, uint32_t regDisableMask,
\r
21005 uint32_t lockWrite); /** Locks or unlocks write access to a register of an OTP bank and the write lock */
\r
21006 uint32_t (*otpEnableBankReadLock)(uint32_t bankIndex, uint32_t regEnableMask, uint32_t regDisableMask,
\r
21007 uint32_t lockWrite); /** Locks or unlocks read access to a register of an OTP bank and the write lock */
\r
21008 uint32_t (*otpProgramReg)(uint32_t bankIndex, uint32_t regIndex, uint32_t value); /** Program a single register in an OTP bank */
\r
21009 uint32_t RESERVED_0[5];
\r
21010 uint32_t (*rngRead)(void); /** Returns 32-bit number from hardware random number generator */
\r
21011 uint32_t (*otpGetDriverVersion)(void); /** Returns the version of the OTP driver in ROM */
\r
21016 __I uint32_t usbdApiBase; /** USB API Base */
\r
21017 uint32_t RESERVED_0[13];
\r
21018 __I OTP_API_Type *otpApiBase; /** OTP API Base */
\r
21019 __I uint32_t aesApiBase; /** AES API Base */
\r
21020 __I uint32_t secureApiBase; /** Secure API Base */
\r
21023 /** ROM API base address */
\r
21024 #define ROM_API_BASE (0x03000200u)
\r
21025 /** ROM API base pointer */
\r
21026 #define ROM_API (*(ROM_API_Type**) ROM_API_BASE)
\r
21027 /** OTP API base pointer */
\r
21028 #define OTP_API (ROM_API->otpApiBase)
\r
21030 /** Used for selecting the address of FROHF setting API in ROM */
\r
21031 #define FSL_FROHF_SETTING_API_ADDRESS_DETERMINE_BY_ROM_VERSION 1U
\r
21032 #define FSL_ROM_VERSION_0A 0U
\r
21033 #define FSL_ROM_VERSION_1B 1U
\r
21034 #define FSL_ROM_VERSION_0A_FRO_SETTING_ADDR 0x03007933U
\r
21035 #define FSL_ROM_VERSION_1B_FRO_SETTING_ADDR 0x03008D9BU
\r
21038 * @brief Get the chip value.
\r
21040 * @return chip version, 0x0: 0A version chip, 0x1: 1B version chip, 0xFF: invalid version.
\r
21042 static inline uint32_t Chip_GetVersion(void)
\r
21044 uint8_t romVersion = 0U;
\r
21045 uint32_t command[5] = {0U}, result[4] = {0U};
\r
21046 uint32_t syscon_iap_entry_location = 0x03000205;
\r
21048 command[0] = 55U;
\r
21051 ((void (*)(uint32_t cmd[5], uint32_t stat[4]))syscon_iap_entry_location)(command, result);
\r
21053 romVersion = (uint8_t)(result[1]);
\r
21055 if (0U == result[0])
\r
21057 if (romVersion == FSL_ROM_VERSION_1B)
\r
21059 return FSL_ROM_VERSION_1B;
\r
21061 else if (romVersion == FSL_ROM_VERSION_0A)
\r
21063 return FSL_ROM_VERSION_0A;
\r
21078 */ /* end of group SDK_Compatibility_Symbols */
\r
21081 #endif /* _LPC54018_H_ */
\r
projects / freertos / blob