2 ** ###################################################################
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3 ** Version: rev. 1.2, 2017-06-08
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7 ** Chip specific module features.
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9 ** Copyright 2016 Freescale Semiconductor, Inc.
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10 ** Copyright 2016-2019 NXP
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11 ** All rights reserved.
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13 ** SPDX-License-Identifier: BSD-3-Clause
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15 ** http: www.nxp.com
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16 ** mail: support@nxp.com
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19 ** - rev. 1.0 (2016-08-12)
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21 ** - rev. 1.1 (2016-11-25)
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22 ** Update CANFD and Classic CAN register.
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23 ** Add MAC TIMERSTAMP registers.
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24 ** - rev. 1.2 (2017-06-08)
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25 ** Remove RTC_CTRL_RTC_OSC_BYPASS.
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26 ** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV.
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27 ** Remove RESET and HALT from SYSCON_AHBCLKDIV.
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29 ** ###################################################################
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32 #ifndef _LPC54018_FEATURES_H_
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33 #define _LPC54018_FEATURES_H_
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35 /* SOC module features */
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37 /* @brief ADC availability on the SoC. */
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38 #define FSL_FEATURE_SOC_ADC_COUNT (1)
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39 /* @brief ASYNC_SYSCON availability on the SoC. */
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40 #define FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT (1)
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41 /* @brief CAN availability on the SoC. */
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42 #define FSL_FEATURE_SOC_LPC_CAN_COUNT (2)
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43 /* @brief CRC availability on the SoC. */
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44 #define FSL_FEATURE_SOC_CRC_COUNT (1)
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45 /* @brief CTIMER availability on the SoC. */
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46 #define FSL_FEATURE_SOC_CTIMER_COUNT (5)
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47 /* @brief DMA availability on the SoC. */
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48 #define FSL_FEATURE_SOC_DMA_COUNT (1)
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49 /* @brief DMIC availability on the SoC. */
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50 #define FSL_FEATURE_SOC_DMIC_COUNT (1)
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51 /* @brief EMC availability on the SoC. */
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52 #define FSL_FEATURE_SOC_EMC_COUNT (1)
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53 /* @brief ENET availability on the SoC. */
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54 #define FSL_FEATURE_SOC_LPC_ENET_COUNT (1)
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55 /* @brief FLEXCOMM availability on the SoC. */
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56 #define FSL_FEATURE_SOC_FLEXCOMM_COUNT (11)
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57 /* @brief GINT availability on the SoC. */
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58 #define FSL_FEATURE_SOC_GINT_COUNT (2)
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59 /* @brief GPIO availability on the SoC. */
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60 #define FSL_FEATURE_SOC_GPIO_COUNT (1)
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61 /* @brief I2C availability on the SoC. */
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62 #define FSL_FEATURE_SOC_I2C_COUNT (10)
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63 /* @brief I2S availability on the SoC. */
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64 #define FSL_FEATURE_SOC_I2S_COUNT (2)
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65 /* @brief INPUTMUX availability on the SoC. */
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66 #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)
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67 /* @brief IOCON availability on the SoC. */
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68 #define FSL_FEATURE_SOC_IOCON_COUNT (1)
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69 /* @brief LCD availability on the SoC. */
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70 #define FSL_FEATURE_SOC_LCD_COUNT (1)
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71 /* @brief MRT availability on the SoC. */
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72 #define FSL_FEATURE_SOC_MRT_COUNT (1)
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73 /* @brief PINT availability on the SoC. */
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74 #define FSL_FEATURE_SOC_PINT_COUNT (1)
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75 /* @brief RIT availability on the SoC. */
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76 #define FSL_FEATURE_SOC_RIT_COUNT (1)
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77 /* @brief RNG availability on the SoC. */
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78 #define FSL_FEATURE_SOC_LPC_RNG_COUNT (1)
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79 /* @brief RTC availability on the SoC. */
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80 #define FSL_FEATURE_SOC_RTC_COUNT (1)
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81 /* @brief SCT availability on the SoC. */
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82 #define FSL_FEATURE_SOC_SCT_COUNT (1)
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83 /* @brief SDIF availability on the SoC. */
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84 #define FSL_FEATURE_SOC_SDIF_COUNT (1)
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85 /* @brief SHA availability on the SoC. */
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86 #define FSL_FEATURE_SOC_SHA_COUNT (1)
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87 /* @brief SMARTCARD availability on the SoC. */
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88 #define FSL_FEATURE_SOC_SMARTCARD_COUNT (2)
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89 /* @brief SPI availability on the SoC. */
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90 #define FSL_FEATURE_SOC_SPI_COUNT (11)
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91 /* @brief SPIFI availability on the SoC. */
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92 #define FSL_FEATURE_SOC_SPIFI_COUNT (1)
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93 /* @brief SYSCON availability on the SoC. */
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94 #define FSL_FEATURE_SOC_SYSCON_COUNT (1)
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95 /* @brief USART availability on the SoC. */
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96 #define FSL_FEATURE_SOC_USART_COUNT (10)
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97 /* @brief USB availability on the SoC. */
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98 #define FSL_FEATURE_SOC_USB_COUNT (1)
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99 /* @brief USBFSH availability on the SoC. */
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100 #define FSL_FEATURE_SOC_USBFSH_COUNT (1)
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101 /* @brief USBHSD availability on the SoC. */
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102 #define FSL_FEATURE_SOC_USBHSD_COUNT (1)
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103 /* @brief USBHSH availability on the SoC. */
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104 #define FSL_FEATURE_SOC_USBHSH_COUNT (1)
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105 /* @brief UTICK availability on the SoC. */
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106 #define FSL_FEATURE_SOC_UTICK_COUNT (1)
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107 /* @brief WWDT availability on the SoC. */
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108 #define FSL_FEATURE_SOC_WWDT_COUNT (1)
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110 /* ADC module features */
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112 /* @brief Do not has input select (register INSEL). */
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113 #define FSL_FEATURE_ADC_HAS_NO_INSEL (0)
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114 /* @brief Has ASYNMODE bitfile in CTRL reigster. */
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115 #define FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE (1)
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116 /* @brief Has ASYNMODE bitfile in CTRL reigster. */
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117 #define FSL_FEATURE_ADC_HAS_CTRL_RESOL (1)
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118 /* @brief Has ASYNMODE bitfile in CTRL reigster. */
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119 #define FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL (1)
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120 /* @brief Has ASYNMODE bitfile in CTRL reigster. */
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121 #define FSL_FEATURE_ADC_HAS_CTRL_TSAMP (1)
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122 /* @brief Has ASYNMODE bitfile in CTRL reigster. */
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123 #define FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE (0)
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124 /* @brief Has ASYNMODE bitfile in CTRL reigster. */
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125 #define FSL_FEATURE_ADC_HAS_CTRL_CALMODE (0)
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126 /* @brief Has startup register. */
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127 #define FSL_FEATURE_ADC_HAS_STARTUP_REG (1)
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128 /* @brief Has ADTrim register */
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129 #define FSL_FEATURE_ADC_HAS_TRIM_REG (0)
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130 /* @brief Has Calibration register. */
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131 #define FSL_FEATURE_ADC_HAS_CALIB_REG (1)
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133 /* CAN module features */
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135 /* @brief Support CANFD or not */
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136 #define FSL_FEATURE_CAN_SUPPORT_CANFD (1)
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138 /* DMA module features */
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140 /* @brief Number of channels */
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141 #define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (30)
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142 /* @brief Align size of DMA descriptor */
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143 #define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512)
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144 /* @brief DMA head link descriptor table align size */
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145 #define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U)
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147 /* FLEXCOMM module features */
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149 /* @brief FLEXCOMM0 USART INDEX 0 */
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150 #define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0)
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151 /* @brief FLEXCOMM0 SPI INDEX 0 */
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152 #define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0)
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153 /* @brief FLEXCOMM0 I2C INDEX 0 */
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154 #define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0)
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155 /* @brief FLEXCOMM1 USART INDEX 1 */
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156 #define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1)
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157 /* @brief FLEXCOMM1 SPI INDEX 1 */
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158 #define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1)
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159 /* @brief FLEXCOMM1 I2C INDEX 1 */
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160 #define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1)
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161 /* @brief FLEXCOMM2 USART INDEX 2 */
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162 #define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2)
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163 /* @brief FLEXCOMM2 SPI INDEX 2 */
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164 #define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2)
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165 /* @brief FLEXCOMM2 I2C INDEX 2 */
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166 #define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2)
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167 /* @brief FLEXCOMM3 USART INDEX 3 */
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168 #define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3)
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169 /* @brief FLEXCOMM3 SPI INDEX 3 */
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170 #define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3)
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171 /* @brief FLEXCOMM3 I2C INDEX 3 */
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172 #define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3)
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173 /* @brief FLEXCOMM4 USART INDEX 4 */
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174 #define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4)
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175 /* @brief FLEXCOMM4 SPI INDEX 4 */
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176 #define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4)
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177 /* @brief FLEXCOMM4 I2C INDEX 4 */
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178 #define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4)
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179 /* @brief FLEXCOMM5 USART INDEX 5 */
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180 #define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5)
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181 /* @brief FLEXCOMM5 SPI INDEX 5 */
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182 #define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5)
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183 /* @brief FLEXCOMM5 I2C INDEX 5 */
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184 #define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5)
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185 /* @brief FLEXCOMM6 USART INDEX 6 */
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186 #define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6)
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187 /* @brief FLEXCOMM6 SPI INDEX 6 */
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188 #define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6)
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189 /* @brief FLEXCOMM6 I2C INDEX 6 */
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190 #define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6)
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191 /* @brief FLEXCOMM7 I2S INDEX 0 */
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192 #define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (0)
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193 /* @brief FLEXCOMM7 USART INDEX 7 */
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194 #define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7)
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195 /* @brief FLEXCOMM7 SPI INDEX 7 */
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196 #define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7)
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197 /* @brief FLEXCOMM7 I2C INDEX 7 */
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198 #define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7)
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199 /* @brief FLEXCOMM7 I2S INDEX 1 */
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200 #define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (1)
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201 /* @brief FLEXCOMM4 USART INDEX 8 */
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202 #define FSL_FEATURE_FLEXCOMM8_USART_INDEX (8)
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203 /* @brief FLEXCOMM4 SPI INDEX 8 */
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204 #define FSL_FEATURE_FLEXCOMM8_SPI_INDEX (8)
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205 /* @brief FLEXCOMM4 I2C INDEX 8 */
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206 #define FSL_FEATURE_FLEXCOMM8_I2C_INDEX (8)
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207 /* @brief FLEXCOMM5 USART INDEX 9 */
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208 #define FSL_FEATURE_FLEXCOMM9_USART_INDEX (9)
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209 /* @brief FLEXCOMM5 SPI INDEX 9 */
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210 #define FSL_FEATURE_FLEXCOMM9_SPI_INDEX (9)
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211 /* @brief FLEXCOMM5 I2C INDEX 9 */
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212 #define FSL_FEATURE_FLEXCOMM9_I2C_INDEX (9)
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213 /* @brief I2S has DMIC interconnection */
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214 #define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) \
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215 (((x) == FLEXCOMM0) ? (0) : \
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216 (((x) == FLEXCOMM1) ? (0) : \
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217 (((x) == FLEXCOMM2) ? (0) : \
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218 (((x) == FLEXCOMM3) ? (0) : \
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219 (((x) == FLEXCOMM4) ? (0) : \
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220 (((x) == FLEXCOMM5) ? (0) : \
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221 (((x) == FLEXCOMM6) ? (0) : \
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222 (((x) == FLEXCOMM7) ? (1) : \
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223 (((x) == FLEXCOMM8) ? (0) : \
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224 (((x) == FLEXCOMM9) ? (0) : \
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225 (((x) == FLEXCOMM10) ? (0) : (-1))))))))))))
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227 /* I2S module features */
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229 /* @brief I2S support dual channel transfer */
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230 #define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (1)
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231 /* @brief I2S has DMIC interconnection */
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232 #define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (1)
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234 /* IOCON module features */
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236 /* @brief Func bit field width */
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237 #define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4)
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239 /* MRT module features */
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241 /* @brief number of channels. */
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242 #define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4)
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244 /* interrupt module features */
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246 /* @brief Lowest interrupt request number. */
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247 #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
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248 /* @brief Highest interrupt request number. */
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249 #define FSL_FEATURE_INTERRUPT_IRQ_MAX (105)
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251 /* PINT module features */
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253 /* @brief Number of connected outputs */
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254 #define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8)
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256 /* RIT module features */
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258 /* @brief RIT has no reset control */
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259 #define FSL_FEATURE_RIT_HAS_NO_RESET (1)
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261 /* RTC module features */
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263 /* @brief RTC has no reset control */
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264 #define FSL_FEATURE_RTC_HAS_NO_RESET (1)
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266 /* SCT module features */
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268 /* @brief Number of events */
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269 #define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16)
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270 /* @brief Number of states */
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271 #define FSL_FEATURE_SCT_NUMBER_OF_STATES (16)
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272 /* @brief Number of match capture */
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273 #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16)
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274 /* @brief Number of outputs */
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275 #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10)
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277 /* SDIF module features */
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279 /* @brief FIFO depth, every location is a WORD */
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280 #define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64)
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281 /* @brief Max DMA buffer size */
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282 #define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096)
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283 /* @brief Max source clock in HZ */
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284 #define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000)
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286 /* SPIFI module features */
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288 /* @brief SPIFI start address */
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289 #define FSL_FEATURE_SPIFI_START_ADDR (0x10000000)
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290 /* @brief SPIFI end address */
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291 #define FSL_FEATURE_SPIFI_END_ADDR (0x17FFFFFF)
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293 /* SYSCON module features */
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295 /* @brief Pointer to ROM IAP entry functions */
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296 #define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205)
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298 /* SysTick module features */
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300 /* @brief Systick has external reference clock. */
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301 #define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0)
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302 /* @brief Systick external reference clock is core clock divided by this value. */
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303 #define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0)
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305 /* USB module features */
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307 /* @brief Size of the USB dedicated RAM */
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308 #define FSL_FEATURE_USB_USB_RAM (0x00002000)
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309 /* @brief Base address of the USB dedicated RAM */
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310 #define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x40100000)
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311 /* @brief USB version */
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312 #define FSL_FEATURE_USB_VERSION (200)
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313 /* @brief Number of the endpoint in USB FS */
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314 #define FSL_FEATURE_USB_EP_NUM (5)
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316 /* USBFSH module features */
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318 /* @brief Size of the USB dedicated RAM */
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319 #define FSL_FEATURE_USBFSH_USB_RAM (0x00002000)
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320 /* @brief Base address of the USB dedicated RAM */
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321 #define FSL_FEATURE_USBFSH_USB_RAM_BASE_ADDRESS (0x40100000)
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322 /* @brief USBFSH version */
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323 #define FSL_FEATURE_USBFSH_VERSION (200)
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325 /* USBHSD module features */
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327 /* @brief Size of the USB dedicated RAM */
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328 #define FSL_FEATURE_USBHSD_USB_RAM (0x00002000)
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329 /* @brief Base address of the USB dedicated RAM */
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330 #define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40100000)
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331 /* @brief USBHSD version */
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332 #define FSL_FEATURE_USBHSD_VERSION (300)
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333 /* @brief Number of the endpoint in USB HS */
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334 #define FSL_FEATURE_USBHSD_EP_NUM (6)
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335 /* @brief Resetting interrupt endpoint resets DATAx sequence to DATA.1 */
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336 #define FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK (1)
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338 /* USBHSH module features */
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340 /* @brief Size of the USB dedicated RAM */
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341 #define FSL_FEATURE_USBHSH_USB_RAM (0x00002000)
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342 /* @brief Base address of the USB dedicated RAM */
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343 #define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000)
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344 /* @brief USBHSH version */
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345 #define FSL_FEATURE_USBHSH_VERSION (300)
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347 #endif /* _LPC54018_FEATURES_H_ */
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