2 ** ###################################################################
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3 ** Processors: LPC54018JBD208
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6 ** Compilers: GNU C Compiler
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7 ** IAR ANSI C/C++ Compiler for ARM
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8 ** Keil ARM C/C++ Compiler
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9 ** MCUXpresso Compiler
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11 ** Reference manual: LPC540xx/LPC54S0xx User manual Rev.0.8 5 June 2018
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12 ** Version: rev. 1.2, 2017-06-08
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16 ** Provides a system configuration function and a global variable that
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17 ** contains the system frequency. It configures the device and initializes
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18 ** the oscillator (PLL) that is part of the microcontroller device.
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20 ** Copyright 2016 Freescale Semiconductor, Inc.
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21 ** Copyright 2016-2019 NXP
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22 ** All rights reserved.
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24 ** SPDX-License-Identifier: BSD-3-Clause
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26 ** http: www.nxp.com
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27 ** mail: support@nxp.com
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30 ** - rev. 1.0 (2016-08-12)
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32 ** - rev. 1.1 (2016-11-25)
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33 ** Update CANFD and Classic CAN register.
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34 ** Add MAC TIMERSTAMP registers.
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35 ** - rev. 1.2 (2017-06-08)
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36 ** Remove RTC_CTRL_RTC_OSC_BYPASS.
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37 ** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV.
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38 ** Remove RESET and HALT from SYSCON_AHBCLKDIV.
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40 ** ###################################################################
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47 * @brief Device specific configuration file for LPC54018 (implementation file)
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49 * Provides a system configuration function and a global variable that contains
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50 * the system frequency. It configures the device and initializes the oscillator
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51 * (PLL) that is part of the microcontroller device.
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55 #include "fsl_device_registers.h"
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57 #define NVALMAX (0x100)
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58 #define PVALMAX (0x20)
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59 #define MVALMAX (0x8000)
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60 #define PLL_MDEC_VAL_P (0) /* MDEC is in bits 16:0 */
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61 #define PLL_MDEC_VAL_M (0x1FFFFUL << PLL_MDEC_VAL_P)
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62 #define PLL_NDEC_VAL_P (0) /* NDEC is in bits 9:0 */
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63 #define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P)
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64 #define PLL_PDEC_VAL_P (0) /* PDEC is in bits 6:0 */
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65 #define PLL_PDEC_VAL_M (0x7FUL << PLL_PDEC_VAL_P)
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67 extern void *__Vectors;
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69 static const uint8_t wdtFreqLookup[32] = {0, 8, 12, 15, 18, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 41, 42, 44, 45, 46,
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70 48, 49, 50, 52, 53, 54, 56, 57, 58, 59, 60, 61};
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71 /* Get WATCH DOG Clk */
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72 static uint32_t getWdtOscFreq(void)
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74 uint8_t freq_sel, div_sel;
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75 if (SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK)
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81 div_sel = (uint8_t)((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_DIVSEL_MASK) + 1UL) << 1UL;
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82 freq_sel = wdtFreqLookup[((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_FREQSEL_MASK) >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)];
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83 return ((uint32_t) freq_sel * 50000U)/((uint32_t)div_sel);
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86 /* Find decoded N value for raw NDEC value */
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87 static uint32_t pllDecodeN(uint32_t NDEC)
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106 for (i = NVALMAX; i >= 3UL; i--)
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108 x = (((x ^ (x >> 2UL) ^ (x >> 3UL) ^ (x >> 4UL)) & 1UL) << 7UL) | ((x >> 1UL) & 0x7FUL);
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109 if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC)
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111 /* Decoded value of NDEC */
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114 if (n != 0xFFFFFFFFUL)
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124 /* Find decoded P value for raw PDEC value */
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125 static uint32_t pllDecodeP(uint32_t PDEC)
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143 for (i = PVALMAX; i >= 3UL; i--)
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145 x = (((x ^ (x >> 2UL)) & 1UL) << 4UL) | ((x >> 1UL) & 0xFUL);
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146 if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC)
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148 /* Decoded value of PDEC */
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151 if (p != 0xFFFFFFFFUL)
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161 /* Find decoded M value for raw MDEC value */
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162 static uint32_t pllDecodeM(uint32_t MDEC)
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181 for (i = MVALMAX; i >= 3UL; i--)
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183 x = (((x ^ (x >> 1UL)) & 1UL) << 14UL) | ((x >> 1UL) & 0x3FFFUL);
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184 if ((x & (PLL_MDEC_VAL_M >> PLL_MDEC_VAL_P)) == MDEC)
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186 /* Decoded value of MDEC */
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189 if (m != 0xFFFFFFFFUL)
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199 /* Get predivider (N) from PLL NDEC setting */
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200 static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg)
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202 uint32_t preDiv = 1;
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204 /* Direct input is not used? */
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205 if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTI_MASK) == 0UL)
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207 /* Decode NDEC value to get (N) pre divider */
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208 preDiv = pllDecodeN(nDecReg & 0x3FFUL);
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214 /* Adjusted by 1, directi is used to bypass */
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218 /* Get postdivider (P) from PLL PDEC setting */
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219 static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg)
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221 uint32_t postDiv = 1;
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223 /* Direct input is not used? */
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224 if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTO_MASK) == 0UL)
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226 /* Decode PDEC value to get (P) post divider */
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227 postDiv = 2UL * pllDecodeP(pDecReg & 0x7FUL);
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228 if (postDiv == 0UL)
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233 /* Adjusted by 1, directo is used to bypass */
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237 /* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */
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238 static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg)
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240 uint32_t mMult = 1;
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242 /* Decode MDEC value to get (M) multiplier */
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243 mMult = pllDecodeM(mDecReg & 0x1FFFFUL);
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253 /* ----------------------------------------------------------------------------
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255 ---------------------------------------------------------------------------- */
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257 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
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259 /* ----------------------------------------------------------------------------
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261 ---------------------------------------------------------------------------- */
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263 void SystemInit (void) {
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264 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
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265 SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
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266 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
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268 #if defined(__MCUXPRESSO)
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269 extern void(*const g_pfnVectors[]) (void);
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270 SCB->VTOR = (uint32_t) &g_pfnVectors;
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272 extern void *__Vectors;
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273 SCB->VTOR = (uint32_t) &__Vectors;
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275 SYSCON->ARMTRACECLKDIV = 0;
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276 /* Optionally enable RAM banks that may be off by default at reset */
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277 #if !defined(DONT_ENABLE_DISABLED_RAMBANKS)
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278 SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL_SRAM1_MASK | SYSCON_AHBCLKCTRL_SRAM2_MASK | SYSCON_AHBCLKCTRL_SRAM3_MASK;
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281 SYSCON->MAINCLKSELA = 0U;
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282 SYSCON->MAINCLKSELB = 0U;
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286 /* ----------------------------------------------------------------------------
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287 -- SystemCoreClockUpdate()
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288 ---------------------------------------------------------------------------- */
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290 void SystemCoreClockUpdate (void) {
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291 uint32_t clkRate = 0;
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292 uint32_t prediv, postdiv;
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295 switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK)
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297 case 0x00: /* MAINCLKSELA clock (main_clk_a)*/
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298 switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK)
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300 case 0x00: /* FRO 12 MHz (fro_12m) */
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301 clkRate = CLK_FRO_12MHZ;
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303 case 0x01: /* CLKIN Source (clk_in) */
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304 clkRate = CLK_CLK_IN;
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306 case 0x02: /* Watchdog oscillator (wdt_clk) */
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307 clkRate = getWdtOscFreq();
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309 default: /* = 0x03 = FRO 96 or 48 MHz (fro_hf) */
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310 if ((SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK) == SYSCON_FROCTRL_SEL_MASK)
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312 clkRate = CLK_FRO_96MHZ;
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316 clkRate = CLK_FRO_48MHZ;
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321 case 0x02: /* System PLL clock (pll_clk)*/
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322 switch (SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK)
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324 case 0x00: /* FRO 12 MHz (fro_12m) */
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325 clkRate = CLK_FRO_12MHZ;
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327 case 0x01: /* CLKIN Source (clk_in) */
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328 clkRate = CLK_CLK_IN;
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330 case 0x02: /* Watchdog oscillator (wdt_clk) */
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331 clkRate = getWdtOscFreq();
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333 case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
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334 clkRate = CLK_RTC_32K_CLK;
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339 if ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_BYPASS_MASK) == 0UL)
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341 /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */
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342 prediv = findPllPreDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLNDEC);
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343 postdiv = findPllPostDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLPDEC);
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344 /* Adjust input clock */
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345 clkRate = clkRate / prediv;
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347 /* MDEC used for rate */
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348 workRate = (uint64_t)(clkRate) * (uint64_t)findPllMMult(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLMDEC);
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349 clkRate = (uint32_t)(workRate / ((uint64_t)postdiv));
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350 clkRate = clkRate * 2; /* PLL CCO output is divided by 2 before to M-Divider */
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353 case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
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354 clkRate = CLK_RTC_32K_CLK;
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359 SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFFUL) + 1UL);
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362 /* ----------------------------------------------------------------------------
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363 -- SystemInitHook()
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364 ---------------------------------------------------------------------------- */
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366 __attribute__ ((weak)) void SystemInitHook (void) {
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367 /* Void implementation of the weak function. */
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