2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
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3 * Copyright 2016 - 2019 , NXP
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4 * All rights reserved.
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7 * SPDX-License-Identifier: BSD-3-Clause
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10 #ifndef _FSL_CLOCK_H_
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11 #define _FSL_CLOCK_H_
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13 #include "fsl_common.h"
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15 /*! @addtogroup clock */
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20 /*******************************************************************************
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22 *****************************************************************************/
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24 /*! @name Driver version */
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26 /*! @brief CLOCK driver version 2.3.1. */
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27 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 1))
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30 /*! @brief Configure whether driver controls clock
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32 * When set to 0, peripheral drivers will enable clock in initialize function
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33 * and disable clock in de-initialize function. When set to 1, peripheral
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34 * driver will not control the clock, application could control the clock out of
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37 * @note All drivers share this feature switcher. If it is set to 1, application
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38 * should handle clock enable and disable for all drivers.
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40 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
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41 #define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
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45 * @brief User-defined the size of cache for CLOCK_PllGetConfig() function.
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47 * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function
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48 * would cache the recent calulation and accelerate the execution to get the
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51 #ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT
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52 #define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U
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55 /* Definition for delay API in clock driver, users can redefine it to the real application. */
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56 #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
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57 #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (180000000UL)
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60 /*! @brief Clock ip name array for ADC. */
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61 #define ADC_CLOCKS \
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65 /*! @brief Clock ip name array for ROM. */
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66 #define ROM_CLOCKS \
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70 /*! @brief Clock ip name array for SRAM. */
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71 #define SRAM_CLOCKS \
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73 kCLOCK_Sram1, kCLOCK_Sram2, kCLOCK_Sram3 \
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75 /*! @brief Clock ip name array for FLASH. */
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76 #define FLASH_CLOCKS \
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80 /*! @brief Clock ip name array for FMC. */
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81 #define FMC_CLOCKS \
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85 /*! @brief Clock ip name array for EEPROM. */
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86 #define EEPROM_CLOCKS \
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90 /*! @brief Clock ip name array for SPIFI. */
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91 #define SPIFI_CLOCKS \
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95 /*! @brief Clock ip name array for INPUTMUX. */
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96 #define INPUTMUX_CLOCKS \
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100 /*! @brief Clock ip name array for IOCON. */
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101 #define IOCON_CLOCKS \
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105 /*! @brief Clock ip name array for GPIO. */
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106 #define GPIO_CLOCKS \
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108 kCLOCK_Gpio0, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 \
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110 /*! @brief Clock ip name array for PINT. */
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111 #define PINT_CLOCKS \
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115 /*! @brief Clock ip name array for GINT. */
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116 #define GINT_CLOCKS \
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118 kCLOCK_Gint, kCLOCK_Gint \
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120 /*! @brief Clock ip name array for DMA. */
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121 #define DMA_CLOCKS \
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125 /*! @brief Clock ip name array for CRC. */
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126 #define CRC_CLOCKS \
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130 /*! @brief Clock ip name array for WWDT. */
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131 #define WWDT_CLOCKS \
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135 /*! @brief Clock ip name array for RTC. */
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136 #define RTC_CLOCKS \
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140 /*! @brief Clock ip name array for ADC0. */
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141 #define ADC0_CLOCKS \
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145 /*! @brief Clock ip name array for MRT. */
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146 #define MRT_CLOCKS \
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150 /*! @brief Clock ip name array for RIT. */
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151 #define RIT_CLOCKS \
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155 /*! @brief Clock ip name array for SCT0. */
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156 #define SCT_CLOCKS \
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160 /*! @brief Clock ip name array for MCAN. */
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161 #define MCAN_CLOCKS \
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163 kCLOCK_Mcan0, kCLOCK_Mcan1 \
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165 /*! @brief Clock ip name array for UTICK. */
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166 #define UTICK_CLOCKS \
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170 /*! @brief Clock ip name array for FLEXCOMM. */
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171 #define FLEXCOMM_CLOCKS \
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173 kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, kCLOCK_FlexComm4, kCLOCK_FlexComm5, \
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174 kCLOCK_FlexComm6, kCLOCK_FlexComm7, kCLOCK_FlexComm8, kCLOCK_FlexComm9, kCLOCK_FlexComm10 \
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176 /*! @brief Clock ip name array for LPUART. */
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177 #define LPUART_CLOCKS \
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179 kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \
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180 kCLOCK_MinUart6, kCLOCK_MinUart7, kCLOCK_MinUart8, kCLOCK_MinUart9 \
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183 /*! @brief Clock ip name array for BI2C. */
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184 #define BI2C_CLOCKS \
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186 kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, \
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187 kCLOCK_BI2c7, kCLOCK_BI2c8, kCLOCK_BI2c9 \
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189 /*! @brief Clock ip name array for LSPI. */
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190 #define LPSI_CLOCKS \
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192 kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, \
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193 kCLOCK_LSpi7, kCLOCK_LSpi8, kCLOCK_LSpi9 \
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195 /*! @brief Clock ip name array for FLEXI2S. */
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196 #define FLEXI2S_CLOCKS \
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198 kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \
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199 kCLOCK_FlexI2s6, kCLOCK_FlexI2s7, kCLOCK_FlexI2s8, kCLOCK_FlexI2s9 \
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201 /*! @brief Clock ip name array for DMIC. */
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202 #define DMIC_CLOCKS \
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206 /*! @brief Clock ip name array for CT32B. */
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207 #define CTIMER_CLOCKS \
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209 kCLOCK_Ct32b0, kCLOCK_Ct32b1, kCLOCK_Ct32b2, kCLOCK_Ct32b3, kCLOCK_Ct32b4 \
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211 /*! @brief Clock ip name array for LCD. */
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212 #define LCD_CLOCKS \
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216 /*! @brief Clock ip name array for SDIO. */
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217 #define SDIO_CLOCKS \
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221 /*! @brief Clock ip name array for USBRAM. */
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222 #define USBRAM_CLOCKS \
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226 /*! @brief Clock ip name array for EMC. */
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227 #define EMC_CLOCKS \
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231 /*! @brief Clock ip name array for ETH. */
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232 #define ETH_CLOCKS \
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236 /*! @brief Clock ip name array for AES. */
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237 #define AES_CLOCKS \
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241 /*! @brief Clock ip name array for OTP. */
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242 #define OTP_CLOCKS \
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246 /*! @brief Clock ip name array for RNG. */
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247 #define RNG_CLOCKS \
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251 /*! @brief Clock ip name array for USBHMR0. */
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252 #define USBHMR0_CLOCKS \
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256 /*! @brief Clock ip name array for USBHSL0. */
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257 #define USBHSL0_CLOCKS \
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261 /*! @brief Clock ip name array for SHA0. */
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262 #define SHA0_CLOCKS \
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266 /*! @brief Clock ip name array for SMARTCARD. */
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267 #define SMARTCARD_CLOCKS \
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269 kCLOCK_SmartCard0, kCLOCK_SmartCard1 \
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271 /*! @brief Clock ip name array for USBD. */
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272 #define USBD_CLOCKS \
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274 kCLOCK_Usbd0, kCLOCK_Usbh1, kCLOCK_Usbd1 \
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276 /*! @brief Clock ip name array for USBH. */
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277 #define USBH_CLOCKS \
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281 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
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282 /*------------------------------------------------------------------------------
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283 clock_ip_name_t definition:
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284 ------------------------------------------------------------------------------*/
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286 #define CLK_GATE_REG_OFFSET_SHIFT 8U
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287 #define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U
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288 #define CLK_GATE_BIT_SHIFT_SHIFT 0U
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289 #define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU
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291 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \
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292 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
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293 (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
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295 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
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296 #define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
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298 #define AHB_CLK_CTRL0 0
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299 #define AHB_CLK_CTRL1 1
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300 #define AHB_CLK_CTRL2 2
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301 #define ASYNC_CLK_CTRL0 3
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303 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
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304 typedef enum _clock_ip_name
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306 kCLOCK_IpInvalid = 0U,
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307 kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1),
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308 kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3),
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309 kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4),
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310 kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5),
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311 kCLOCK_Spifi = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 10),
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312 kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11),
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313 kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13),
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314 kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14),
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315 kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15),
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316 kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16),
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317 kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17),
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318 kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18),
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319 kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19),
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320 kCLOCK_Dma = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20),
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321 kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21),
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322 kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22),
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323 kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23),
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324 kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27),
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325 kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0),
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326 kCLOCK_Rit = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1),
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327 kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2),
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328 kCLOCK_Mcan0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 7),
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329 kCLOCK_Mcan1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 8),
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330 kCLOCK_Utick = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10),
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331 kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
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332 kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
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333 kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
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334 kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
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335 kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
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336 kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
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337 kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
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338 kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
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339 kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
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340 kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
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341 kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
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342 kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
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343 kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
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344 kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
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345 kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
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346 kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
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347 kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
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348 kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
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349 kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
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350 kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
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351 kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
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352 kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
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353 kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
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354 kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
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355 kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
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356 kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
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357 kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
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358 kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
\r
359 kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
\r
360 kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
\r
361 kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
\r
362 kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
\r
363 kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
\r
364 kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
\r
365 kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
\r
366 kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
\r
367 kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
\r
368 kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
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369 kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
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370 kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
\r
371 kCLOCK_DMic = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 19),
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372 kCLOCK_Ct32b2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22),
\r
373 kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25),
\r
374 kCLOCK_Ct32b0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26),
\r
375 kCLOCK_Ct32b1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27),
\r
376 kCLOCK_BodyBias0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 29),
\r
377 kCLOCK_EzhArchB0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31),
\r
378 kCLOCK_Lcd = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2),
\r
379 kCLOCK_Sdio = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 3),
\r
380 kCLOCK_Usbh1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 4),
\r
381 kCLOCK_Usbd1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 5),
\r
382 kCLOCK_UsbRam1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 6),
\r
383 kCLOCK_Emc = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 7),
\r
384 kCLOCK_Eth = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 8),
\r
385 kCLOCK_Gpio4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 9),
\r
386 kCLOCK_Gpio5 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 10),
\r
387 kCLOCK_Aes = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 11),
\r
388 kCLOCK_Otp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 12),
\r
389 kCLOCK_Rng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13),
\r
390 kCLOCK_FlexComm8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
\r
391 kCLOCK_FlexComm9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
\r
392 kCLOCK_MinUart8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
\r
393 kCLOCK_MinUart9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
\r
394 kCLOCK_LSpi8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
\r
395 kCLOCK_LSpi9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
\r
396 kCLOCK_BI2c8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
\r
397 kCLOCK_BI2c9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
\r
398 kCLOCK_FlexI2s8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
\r
399 kCLOCK_FlexI2s9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
\r
400 kCLOCK_Usbhmr0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16),
\r
401 kCLOCK_Usbhsl0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17),
\r
402 kCLOCK_Sha0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18),
\r
403 kCLOCK_SmartCard0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 19),
\r
404 kCLOCK_SmartCard1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 20),
\r
405 kCLOCK_FlexComm10 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 21),
\r
407 kCLOCK_Ct32b3 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 13),
\r
408 kCLOCK_Ct32b4 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 14)
\r
411 /*! @brief Clock name used to get clock frequency. */
\r
412 typedef enum _clock_name
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414 kCLOCK_CoreSysClk, /*!< Core/system clock (aka MAIN_CLK) */
\r
415 kCLOCK_BusClk, /*!< Bus clock (AHB clock) */
\r
416 kCLOCK_ClockOut, /*!< CLOCKOUT */
\r
417 kCLOCK_FroHf, /*!< FRO48/96 */
\r
418 kCLOCK_UsbPll, /*!< USB1 PLL */
\r
419 kCLOCK_Mclk, /*!< MCLK */
\r
420 kCLOCK_Fro12M, /*!< FRO12M */
\r
421 kCLOCK_ExtClk, /*!< External Clock */
\r
422 kCLOCK_PllOut, /*!< PLL Output */
\r
423 kCLOCK_UsbClk, /*!< USB input */
\r
424 kCLOCK_WdtOsc, /*!< Watchdog Oscillator */
\r
425 kCLOCK_Frg, /*!< Frg Clock */
\r
426 kCLOCK_AsyncApbClk, /*!< Async APB clock */
\r
430 * Clock source selections for the asynchronous APB clock
\r
432 typedef enum _async_clock_src
\r
434 kCLOCK_AsyncMainClk = 0, /*!< Main System clock */
\r
435 kCLOCK_AsyncFro12Mhz, /*!< 12MHz FRO */
\r
436 kCLOCK_AsyncAudioPllClk,
\r
437 kCLOCK_AsyncI2cClkFc6,
\r
439 } async_clock_src_t;
\r
441 /*! @brief Clock Mux Switches
\r
442 * The encoding is as follows each connection identified is 32bits wide while 24bits are valuable
\r
443 * starting from LSB upwards
\r
445 * [4 bits for choice, 0 means invalid choice] [8 bits mux ID]*
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449 #define CLK_ATTACH_ID(mux, sel, pos) ((((uint32_t)(mux) << 0U) | (((uint32_t)(sel) + 1U) & 0xFU) << 8U) << ((pos)*12U))
\r
450 #define MUX_A(mux, sel) CLK_ATTACH_ID((mux), (sel), 0U)
\r
451 #define MUX_B(mux, sel, selector) (CLK_ATTACH_ID((mux), (sel), 1U) | ((selector) << 24U))
\r
453 #define GET_ID_ITEM(connection) ((connection)&0xFFFU)
\r
454 #define GET_ID_NEXT_ITEM(connection) ((connection) >> 12U)
\r
455 #define GET_ID_ITEM_MUX(connection) ((uint8_t)((connection)&0xFFU))
\r
456 #define GET_ID_ITEM_SEL(connection) ((uint8_t)((((connection)&0xF00U) >> 8U) - 1U))
\r
457 #define GET_ID_SELECTOR(connection) ((connection)&0xF000000U)
\r
459 #define CM_STICKCLKSEL 0
\r
460 #define CM_MAINCLKSELA 1
\r
461 #define CM_MAINCLKSELB 2
\r
462 #define CM_CLKOUTCLKSELA 3
\r
463 #define CM_SYSPLLCLKSEL 5
\r
464 #define CM_AUDPLLCLKSEL 7
\r
465 #define CM_SPIFICLKSEL 9
\r
466 #define CM_ADCASYNCCLKSEL 10
\r
467 #define CM_USB0CLKSEL 11
\r
468 #define CM_USB1CLKSEL 12
\r
469 #define CM_FXCOMCLKSEL0 13
\r
470 #define CM_FXCOMCLKSEL1 14
\r
471 #define CM_FXCOMCLKSEL2 15
\r
472 #define CM_FXCOMCLKSEL3 16
\r
473 #define CM_FXCOMCLKSEL4 17
\r
474 #define CM_FXCOMCLKSEL5 18
\r
475 #define CM_FXCOMCLKSEL6 19
\r
476 #define CM_FXCOMCLKSEL7 20
\r
477 #define CM_FXCOMCLKSEL8 21
\r
478 #define CM_FXCOMCLKSEL9 22
\r
479 #define CM_FXCOMCLKSEL10 23
\r
480 #define CM_MCLKCLKSEL 25
\r
481 #define CM_FRGCLKSEL 27
\r
482 #define CM_DMICCLKSEL 28
\r
483 #define CM_SCTCLKSEL 29
\r
484 #define CM_LCDCLKSEL 30
\r
485 #define CM_SDIOCLKSEL 31
\r
487 #define CM_ASYNCAPB 32U
\r
489 typedef enum _clock_attach_id
\r
492 kSYSTICK_DIV_CLK_to_SYSTICKCLK = MUX_A(CM_STICKCLKSEL, 0),
\r
493 kWDT_OSC_to_SYSTICKCLK = MUX_A(CM_STICKCLKSEL, 1),
\r
494 kOSC32K_to_SYSTICKCLK = MUX_A(CM_STICKCLKSEL, 2),
\r
495 kFRO12M_to_SYSTICKCLK = MUX_A(CM_STICKCLKSEL, 3),
\r
496 kNONE_to_SYSTICKCLK = MUX_A(CM_STICKCLKSEL, 7),
\r
498 kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0, 0),
\r
499 kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0, 0),
\r
500 kWDT_OSC_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0, 0),
\r
501 kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0, 0),
\r
502 kSYS_PLL_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 2, 0),
\r
503 kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 3, 0),
\r
505 kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 0),
\r
506 kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 1),
\r
507 kWDT_OSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 2),
\r
508 kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 3),
\r
509 kSYS_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 4),
\r
510 kUSB_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 5),
\r
511 kAUDIO_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 6),
\r
512 kOSC32K_OSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 7),
\r
514 kFRO12M_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 0),
\r
515 kEXT_CLK_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 1),
\r
516 kWDT_OSC_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 2),
\r
517 kOSC32K_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 3),
\r
518 kNONE_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 7),
\r
520 kFRO12M_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 0),
\r
521 kEXT_CLK_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 1),
\r
522 kNONE_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 7),
\r
524 kMAIN_CLK_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 0),
\r
525 kSYS_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 1),
\r
526 kUSB_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 2),
\r
527 kFRO_HF_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 3),
\r
528 kAUDIO_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 4),
\r
529 kNONE_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 7),
\r
531 kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0),
\r
532 kSYS_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1),
\r
533 kUSB_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2),
\r
534 kAUDIO_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 3),
\r
535 kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7),
\r
537 kFRO_HF_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 0),
\r
538 kSYS_PLL_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 1),
\r
539 kUSB_PLL_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 2),
\r
540 kNONE_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 7),
\r
542 kFRO_HF_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 0),
\r
543 kSYS_PLL_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 1),
\r
544 kUSB_PLL_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 2),
\r
545 kNONE_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 7),
\r
547 kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0),
\r
548 kFRO_HF_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1),
\r
549 kAUDIO_PLL_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2),
\r
550 kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3),
\r
551 kFRG_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4),
\r
552 kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7),
\r
554 kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0),
\r
555 kFRO_HF_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1),
\r
556 kAUDIO_PLL_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2),
\r
557 kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3),
\r
558 kFRG_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4),
\r
559 kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7),
\r
561 kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0),
\r
562 kFRO_HF_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1),
\r
563 kAUDIO_PLL_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2),
\r
564 kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3),
\r
565 kFRG_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4),
\r
566 kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7),
\r
568 kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0),
\r
569 kFRO_HF_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1),
\r
570 kAUDIO_PLL_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2),
\r
571 kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3),
\r
572 kFRG_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4),
\r
573 kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7),
\r
575 kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0),
\r
576 kFRO_HF_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1),
\r
577 kAUDIO_PLL_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2),
\r
578 kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3),
\r
579 kFRG_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4),
\r
580 kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7),
\r
582 kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0),
\r
583 kFRO_HF_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1),
\r
584 kAUDIO_PLL_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2),
\r
585 kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3),
\r
586 kFRG_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4),
\r
587 kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7),
\r
589 kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0),
\r
590 kFRO_HF_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1),
\r
591 kAUDIO_PLL_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2),
\r
592 kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3),
\r
593 kFRG_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4),
\r
594 kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7),
\r
596 kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0),
\r
597 kFRO_HF_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1),
\r
598 kAUDIO_PLL_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2),
\r
599 kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3),
\r
600 kFRG_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4),
\r
601 kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7),
\r
603 kFRO12M_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 0),
\r
604 kFRO_HF_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 1),
\r
605 kAUDIO_PLL_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 2),
\r
606 kMCLK_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 3),
\r
607 kFRG_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 4),
\r
608 kNONE_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 7),
\r
610 kFRO12M_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 0),
\r
611 kFRO_HF_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 1),
\r
612 kAUDIO_PLL_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 2),
\r
613 kMCLK_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 3),
\r
614 kFRG_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 4),
\r
615 kNONE_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 7),
\r
617 kMAIN_CLK_to_FLEXCOMM10 = MUX_A(CM_FXCOMCLKSEL10, 0),
\r
618 kSYS_PLL_to_FLEXCOMM10 = MUX_A(CM_FXCOMCLKSEL10, 1),
\r
619 kUSB_PLL_to_FLEXCOMM10 = MUX_A(CM_FXCOMCLKSEL10, 2),
\r
620 kFRO_HF_to_FLEXCOMM10 = MUX_A(CM_FXCOMCLKSEL10, 3),
\r
621 kAUDIO_PLL_to_FLEXCOMM10 = MUX_A(CM_FXCOMCLKSEL10, 4),
\r
622 kNONE_to_FLEXCOMM10 = MUX_A(CM_FXCOMCLKSEL10, 7),
\r
624 kFRO_HF_to_MCLK = MUX_A(CM_MCLKCLKSEL, 0),
\r
625 kAUDIO_PLL_to_MCLK = MUX_A(CM_MCLKCLKSEL, 1),
\r
626 kNONE_to_MCLK = MUX_A(CM_MCLKCLKSEL, 7),
\r
628 kMAIN_CLK_to_FRG = MUX_A(CM_FRGCLKSEL, 0),
\r
629 kSYS_PLL_to_FRG = MUX_A(CM_FRGCLKSEL, 1),
\r
630 kFRO12M_to_FRG = MUX_A(CM_FRGCLKSEL, 2),
\r
631 kFRO_HF_to_FRG = MUX_A(CM_FRGCLKSEL, 3),
\r
632 kNONE_to_FRG = MUX_A(CM_FRGCLKSEL, 7),
\r
634 kFRO12M_to_DMIC = MUX_A(CM_DMICCLKSEL, 0),
\r
635 kFRO_HF_DIV_to_DMIC = MUX_A(CM_DMICCLKSEL, 1),
\r
636 kAUDIO_PLL_to_DMIC = MUX_A(CM_DMICCLKSEL, 2),
\r
637 kMCLK_to_DMIC = MUX_A(CM_DMICCLKSEL, 3),
\r
638 kMAIN_CLK_to_DMIC = MUX_A(CM_DMICCLKSEL, 4),
\r
639 kWDT_OSC_to_DMIC = MUX_A(CM_DMICCLKSEL, 5),
\r
640 kNONE_to_DMIC = MUX_A(CM_DMICCLKSEL, 7),
\r
642 kMAIN_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 0),
\r
643 kSYS_PLL_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 1),
\r
644 kFRO_HF_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 2),
\r
645 kAUDIO_PLL_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 3),
\r
646 kNONE_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 7),
\r
648 kMAIN_CLK_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 0),
\r
649 kLCDCLKIN_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 1),
\r
650 kFRO_HF_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 2),
\r
651 kNONE_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 3),
\r
653 kMAIN_CLK_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 0),
\r
654 kSYS_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 1),
\r
655 kUSB_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 2),
\r
656 kFRO_HF_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 3),
\r
657 kAUDIO_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 4),
\r
658 kNONE_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 7),
\r
660 kMAIN_CLK_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 0),
\r
661 kFRO12M_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 1),
\r
662 kAUDIO_PLL_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 2),
\r
663 kI2C_CLK_FC6_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 3),
\r
664 kNONE_to_NONE = (int)0x80000000U,
\r
665 } clock_attach_id_t;
\r
667 /* Clock dividers */
\r
668 typedef enum _clock_div_name
\r
670 kCLOCK_DivSystickClk = 0,
\r
671 kCLOCK_DivArmTrClkDiv = 1,
\r
672 kCLOCK_DivCan0Clk = 2,
\r
673 kCLOCK_DivCan1Clk = 3,
\r
674 kCLOCK_DivSmartCard0Clk = 4,
\r
675 kCLOCK_DivSmartCard1Clk = 5,
\r
676 kCLOCK_DivAhbClk = 32,
\r
677 kCLOCK_DivClkOut = 33,
\r
678 kCLOCK_DivFrohfClk = 34,
\r
679 kCLOCK_DivSpifiClk = 36,
\r
680 kCLOCK_DivAdcAsyncClk = 37,
\r
681 kCLOCK_DivUsb0Clk = 38,
\r
682 kCLOCK_DivUsb1Clk = 39,
\r
683 kCLOCK_DivFrg = 40,
\r
684 kCLOCK_DivDmicClk = 42,
\r
685 kCLOCK_DivMClk = 43,
\r
686 kCLOCK_DivLcdClk = 44,
\r
687 kCLOCK_DivSctClk = 45,
\r
688 kCLOCK_DivEmcClk = 46,
\r
689 kCLOCK_DivSdioClk = 47
\r
690 } clock_div_name_t;
\r
692 /*******************************************************************************
\r
694 ******************************************************************************/
\r
696 #if defined(__cplusplus)
\r
698 #endif /* __cplusplus */
\r
700 static inline void CLOCK_EnableClock(clock_ip_name_t clk)
\r
702 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
\r
705 SYSCON->AHBCLKCTRLSET[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
\r
709 SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE(1);
\r
710 ASYNC_SYSCON->ASYNCAPBCLKCTRLSET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
\r
714 static inline void CLOCK_DisableClock(clock_ip_name_t clk)
\r
716 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
\r
719 SYSCON->AHBCLKCTRLCLR[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
\r
723 ASYNC_SYSCON->ASYNCAPBCLKCTRLCLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
\r
724 SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE(0);
\r
730 * Initialize the Core clock to given frequency (12, 48 or 96 MHz), this API is implememnt in ROM code.
\r
731 * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed
\r
732 * output is enabled.
\r
733 * Usage: CLOCK_SetupFROClocking(frequency), (frequency must be one of 12, 48 or 96 MHz)
\r
734 * Note: Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U) before calling this API since this API is
\r
735 * implemented in ROM code and the FROHF TRIM value is stored in OTP
\r
737 * @param froFreq target fro frequency.
\r
741 void CLOCK_SetupFROClocking(uint32_t froFreq);
\r
744 * @brief Configure the clock selection muxes.
\r
745 * @param connection : Clock to be configured.
\r
748 void CLOCK_AttachClk(clock_attach_id_t connection);
\r
750 * @brief Get the actual clock attach id.
\r
751 * This fuction uses the offset in input attach id, then it reads the actual source value in
\r
752 * the register and combine the offset to obtain an actual attach id.
\r
753 * @param attachId : Clock attach id to get.
\r
754 * @return Clock source value.
\r
756 clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId);
\r
758 * @brief Setup peripheral clock dividers.
\r
759 * @param div_name : Clock divider name
\r
760 * @param divided_by_value: Value to be divided
\r
761 * @param reset : Whether to reset the divider counter.
\r
764 void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset);
\r
766 /*! @brief Return Frequency of selected clock
\r
767 * @return Frequency of selected clock
\r
769 uint32_t CLOCK_GetFreq(clock_name_t clockName);
\r
770 /*! @brief Return Frequency of FRO 12MHz
\r
771 * @return Frequency of FRO 12MHz
\r
773 uint32_t CLOCK_GetFro12MFreq(void);
\r
774 /*! @brief Return Frequency of ClockOut
\r
775 * @return Frequency of ClockOut
\r
777 uint32_t CLOCK_GetClockOutClkFreq(void);
\r
778 /*! @brief Return Frequency of Spifi Clock
\r
779 * @return Frequency of Spifi.
\r
781 uint32_t CLOCK_GetSpifiClkFreq(void);
\r
782 /*! @brief Return Frequency of Adc Clock
\r
783 * @return Frequency of Adc Clock.
\r
785 uint32_t CLOCK_GetAdcClkFreq(void);
\r
786 /*! brief Return Frequency of MCAN Clock
\r
787 * param MCanSel : 0U: MCAN0; 1U: MCAN1
\r
788 * return Frequency of MCAN Clock
\r
790 uint32_t CLOCK_GetMCanClkFreq(uint32_t MCanSel);
\r
791 /*! @brief Return Frequency of Usb0 Clock
\r
792 * @return Frequency of Usb0 Clock.
\r
794 uint32_t CLOCK_GetUsb0ClkFreq(void);
\r
795 /*! @brief Return Frequency of Usb1 Clock
\r
796 * @return Frequency of Usb1 Clock.
\r
798 uint32_t CLOCK_GetUsb1ClkFreq(void);
\r
799 /*! @brief Return Frequency of MClk Clock
\r
800 * @return Frequency of MClk Clock.
\r
802 uint32_t CLOCK_GetMclkClkFreq(void);
\r
803 /*! @brief Return Frequency of SCTimer Clock
\r
804 * @return Frequency of SCTimer Clock.
\r
806 uint32_t CLOCK_GetSctClkFreq(void);
\r
807 /*! @brief Return Frequency of SDIO Clock
\r
808 * @return Frequency of SDIO Clock.
\r
810 uint32_t CLOCK_GetSdioClkFreq(void);
\r
811 /*! @brief Return Frequency of LCD Clock
\r
812 * @return Frequency of LCD Clock.
\r
814 uint32_t CLOCK_GetLcdClkFreq(void);
\r
815 /*! @brief Return Frequency of LCD CLKIN Clock
\r
816 * @return Frequency of LCD CLKIN Clock.
\r
818 uint32_t CLOCK_GetLcdClkIn(void);
\r
819 /*! @brief Return Frequency of External Clock
\r
820 * @return Frequency of External Clock. If no external clock is used returns 0.
\r
822 uint32_t CLOCK_GetExtClkFreq(void);
\r
823 /*! @brief Return Frequency of Watchdog Oscillator
\r
824 * @return Frequency of Watchdog Oscillator
\r
826 uint32_t CLOCK_GetWdtOscFreq(void);
\r
827 /*! @brief Return Frequency of High-Freq output of FRO
\r
828 * @return Frequency of High-Freq output of FRO
\r
830 uint32_t CLOCK_GetFroHfFreq(void);
\r
831 /*! @brief Return Frequency of frg
\r
832 * @return Frequency of FRG
\r
834 uint32_t CLOCK_GetFrgClkFreq(void);
\r
835 /*! @brief Return Frequency of dmic
\r
836 * @return Frequency of DMIC
\r
838 uint32_t CLOCK_GetDmicClkFreq(void);
\r
841 * @brief Set FRG Clk
\r
843 * 1: if set FRG CLK successfully.
\r
844 * 0: if set FRG CLK fail.
\r
846 uint32_t CLOCK_SetFRGClock(uint32_t freq);
\r
848 /*! @brief Return Frequency of PLL
\r
849 * @return Frequency of PLL
\r
851 uint32_t CLOCK_GetPllOutFreq(void);
\r
852 /*! @brief Return Frequency of USB PLL
\r
853 * @return Frequency of PLL
\r
855 uint32_t CLOCK_GetUsbPllOutFreq(void);
\r
856 /*! @brief Return Frequency of AUDIO PLL
\r
857 * @return Frequency of PLL
\r
859 uint32_t CLOCK_GetAudioPllOutFreq(void);
\r
860 /*! @brief Return Frequency of 32kHz osc
\r
861 * @return Frequency of 32kHz osc
\r
863 uint32_t CLOCK_GetOsc32KFreq(void);
\r
864 /*! @brief Return Frequency of Core System
\r
865 * @return Frequency of Core System
\r
867 uint32_t CLOCK_GetCoreSysClkFreq(void);
\r
868 /*! @brief Return Frequency of I2S MCLK Clock
\r
869 * @return Frequency of I2S MCLK Clock
\r
871 uint32_t CLOCK_GetI2SMClkFreq(void);
\r
872 /*! @brief Return Frequency of Flexcomm functional Clock
\r
873 * @return Frequency of Flexcomm functional Clock
\r
875 uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id);
\r
877 /*! @brief return FRG Clk
\r
878 * @return Frequency of FRG CLK.
\r
880 uint32_t CLOCK_GetFRGInputClock(void);
\r
881 /*! @brief Return Asynchronous APB Clock source
\r
882 * @return Asynchronous APB CLock source
\r
884 __STATIC_INLINE async_clock_src_t CLOCK_GetAsyncApbClkSrc(void)
\r
886 return (async_clock_src_t)(uint32_t)(ASYNC_SYSCON->ASYNCAPBCLKSELA & 0x3U);
\r
888 /*! @brief Return Frequency of Asynchronous APB Clock
\r
889 * @return Frequency of Asynchronous APB Clock Clock
\r
891 uint32_t CLOCK_GetAsyncApbClkFreq(void);
\r
892 /*! @brief Return EMC source
\r
893 * @return EMC source
\r
895 __STATIC_INLINE uint32_t CLOCK_GetEmcClkFreq(void)
\r
899 freqtmp = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U);
\r
900 return freqtmp / ((SYSCON->EMCCLKDIV & 0xffU) + 1U);
\r
902 /*! @brief Return Audio PLL input clock rate
\r
903 * @return Audio PLL input clock rate
\r
905 uint32_t CLOCK_GetAudioPLLInClockRate(void);
\r
906 /*! @brief Return System PLL input clock rate
\r
907 * @return System PLL input clock rate
\r
909 uint32_t CLOCK_GetSystemPLLInClockRate(void);
\r
911 /*! @brief Return System PLL output clock rate
\r
912 * @param recompute : Forces a PLL rate recomputation if true
\r
913 * @return System PLL output clock rate
\r
914 * @note The PLL rate is cached in the driver in a variable as
\r
915 * the rate computation function can take some time to perform. It
\r
916 * is recommended to use 'false' with the 'recompute' parameter.
\r
918 uint32_t CLOCK_GetSystemPLLOutClockRate(bool recompute);
\r
920 /*! @brief Return System AUDIO PLL output clock rate
\r
921 * @param recompute : Forces a AUDIO PLL rate recomputation if true
\r
922 * @return System AUDIO PLL output clock rate
\r
923 * @note The AUDIO PLL rate is cached in the driver in a variable as
\r
924 * the rate computation function can take some time to perform. It
\r
925 * is recommended to use 'false' with the 'recompute' parameter.
\r
927 uint32_t CLOCK_GetAudioPLLOutClockRate(bool recompute);
\r
929 /*! @brief Return System USB PLL output clock rate
\r
930 * @param recompute : Forces a USB PLL rate recomputation if true
\r
931 * @return System USB PLL output clock rate
\r
932 * @note The USB PLL rate is cached in the driver in a variable as
\r
933 * the rate computation function can take some time to perform. It
\r
934 * is recommended to use 'false' with the 'recompute' parameter.
\r
936 uint32_t CLOCK_GetUsbPLLOutClockRate(bool recompute);
\r
938 /*! @brief Enables and disables PLL bypass mode
\r
939 * @brief bypass : true to bypass PLL (PLL output = PLL input, false to disable bypass
\r
940 * @return System PLL output clock rate
\r
942 __STATIC_INLINE void CLOCK_SetBypassPLL(bool bypass)
\r
946 SYSCON->SYSPLLCTRL |= (1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT);
\r
950 SYSCON->SYSPLLCTRL &= ~(1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT);
\r
954 /*! @brief Check if PLL is locked or not
\r
955 * @return true if the PLL is locked, false if not locked
\r
957 __STATIC_INLINE bool CLOCK_IsSystemPLLLocked(void)
\r
959 return (bool)((SYSCON->SYSPLLSTAT & SYSCON_SYSPLLSTAT_LOCK_MASK) != 0U);
\r
962 /*! @brief Check if USB PLL is locked or not
\r
963 * @return true if the USB PLL is locked, false if not locked
\r
965 __STATIC_INLINE bool CLOCK_IsUsbPLLLocked(void)
\r
967 return (bool)((SYSCON->USBPLLSTAT & SYSCON_USBPLLSTAT_LOCK_MASK) != 0U);
\r
970 /*! @brief Check if AUDIO PLL is locked or not
\r
971 * @return true if the AUDIO PLL is locked, false if not locked
\r
973 __STATIC_INLINE bool CLOCK_IsAudioPLLLocked(void)
\r
975 return (bool)((SYSCON->AUDPLLSTAT & SYSCON_AUDPLLSTAT_LOCK_MASK) != 0U);
\r
978 /*! @brief Enables and disables SYS OSC
\r
979 * @brief enable : true to enable SYS OSC, false to disable SYS OSC
\r
981 __STATIC_INLINE void CLOCK_Enable_SysOsc(bool enable)
\r
985 SYSCON->PDRUNCFGCLR[0] |= SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK;
\r
986 SYSCON->PDRUNCFGCLR[1] |= SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK;
\r
991 SYSCON->PDRUNCFGSET[0] = SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK;
\r
992 SYSCON->PDRUNCFGSET[1] = SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK;
\r
996 /*! @brief Store the current PLL rate
\r
997 * @param rate: Current rate of the PLL
\r
1000 void CLOCK_SetStoredPLLClockRate(uint32_t rate);
\r
1002 /*! @brief Store the current AUDIO PLL rate
\r
1003 * @param rate: Current rate of the PLL
\r
1006 void CLOCK_SetStoredAudioPLLClockRate(uint32_t rate);
\r
1008 /*! @brief PLL configuration structure flags for 'flags' field
\r
1009 * These flags control how the PLL configuration function sets up the PLL setup structure.<br>
\r
1011 * When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the
\r
1012 * configuration structure must be assigned with the expected PLL frequency. If the
\r
1013 * PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration
\r
1014 * function and the driver will determine the PLL rate from the currently selected
\r
1015 * PLL source. This flag might be used to configure the PLL input clock more accurately
\r
1016 * when using the WDT oscillator or a more dyanmic CLKIN source.<br>
\r
1018 * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the
\r
1019 * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider
\r
1020 * are not used.<br>
\r
1022 #define PLL_CONFIGFLAG_USEINRATE (1U << 0U) /*!< Flag to use InputRate in PLL configuration structure for setup */
\r
1023 #define PLL_CONFIGFLAG_FORCENOFRACT \
\r
1024 (1U << 2U) /*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or \
\r
1027 /*! @brief PLL configuration structure
\r
1029 * This structure can be used to configure the settings for a PLL
\r
1030 * setup structure. Fill in the desired configuration for the PLL
\r
1031 * and call the PLL setup function to fill in a PLL setup structure.
\r
1033 typedef struct _pll_config
\r
1035 uint32_t desiredRate; /*!< Desired PLL rate in Hz */
\r
1036 uint32_t inputRate; /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */
\r
1037 uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */
\r
1040 /*! @brief PLL setup structure flags for 'flags' field
\r
1041 * These flags control how the PLL setup function sets up the PLL
\r
1043 #define PLL_SETUPFLAG_POWERUP (1U << 0U) /*!< Setup will power on the PLL after setup */
\r
1044 #define PLL_SETUPFLAG_WAITLOCK (1U << 1U) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */
\r
1045 #define PLL_SETUPFLAG_ADGVOLT (1U << 2U) /*!< Optimize system voltage for the new PLL rate */
\r
1047 /*! @brief PLL setup structure
\r
1048 * This structure can be used to pre-build a PLL setup configuration
\r
1049 * at run-time and quickly set the PLL to the configuration. It can be
\r
1050 * populated with the PLL setup function. If powering up or waiting
\r
1051 * for PLL lock, the PLL input clock source should be configured prior
\r
1054 typedef struct _pll_setup
\r
1056 uint32_t pllctrl; /*!< PLL control register SYSPLLCTRL */
\r
1057 uint32_t pllndec; /*!< PLL NDEC register SYSPLLNDEC */
\r
1058 uint32_t pllpdec; /*!< PLL PDEC register SYSPLLPDEC */
\r
1059 uint32_t pllmdec; /*!< PLL MDEC registers SYSPLLPDEC */
\r
1060 uint32_t pllRate; /*!< Acutal PLL rate */
\r
1061 uint32_t audpllfrac; /*!< only aduio PLL has this function*/
\r
1062 uint32_t flags; /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */
\r
1065 /*! @brief PLL status definitions
\r
1067 typedef enum _pll_error
\r
1069 kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */
\r
1070 kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */
\r
1071 kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */
\r
1072 kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */
\r
1073 kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */
\r
1074 kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Requested output rate isn't possible */
\r
1075 kStatus_PLL_CCOTooLow = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Requested CCO rate isn't possible */
\r
1076 kStatus_PLL_CCOTooHigh = MAKE_STATUS(kStatusGroup_Generic, 7) /*!< Requested CCO rate isn't possible */
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1079 /*! @brief USB clock source definition. */
\r
1080 typedef enum _clock_usb_src
\r
1082 kCLOCK_UsbSrcFro = (uint32_t)kCLOCK_FroHf, /*!< Use FRO 96 or 48 MHz. */
\r
1083 kCLOCK_UsbSrcSystemPll = (uint32_t)kCLOCK_PllOut, /*!< Use System PLL output. */
\r
1084 kCLOCK_UsbSrcMainClock = (uint32_t)kCLOCK_CoreSysClk, /*!< Use Main clock. */
\r
1085 kCLOCK_UsbSrcUsbPll = (uint32_t)kCLOCK_UsbPll, /*!< Use USB PLL clock. */
\r
1087 kCLOCK_UsbSrcNone = SYSCON_USB0CLKSEL_SEL(
\r
1088 7U) /*!< Use None, this may be selected in order to reduce power when no output is needed.. */
\r
1089 } clock_usb_src_t;
\r
1091 /*! @brief USB PDEL Divider. */
\r
1092 typedef enum _usb_pll_psel
\r
1094 pSel_Divide_1 = 0U,
\r
1100 /*! @brief PLL setup structure
\r
1101 * This structure can be used to pre-build a USB PLL setup configuration
\r
1102 * at run-time and quickly set the usb PLL to the configuration. It can be
\r
1103 * populated with the USB PLL setup function. If powering up or waiting
\r
1104 * for USB PLL lock, the PLL input clock source should be configured prior
\r
1105 * to USB PLL setup.
\r
1107 typedef struct _usb_pll_setup
\r
1109 uint8_t msel; /*!< USB PLL control register msel:1U-256U */
\r
1110 uint8_t psel; /*!< USB PLL control register psel:only support inter 1U 2U 4U 8U */
\r
1111 uint8_t nsel; /*!< USB PLL control register nsel:only suppoet inter 1U 2U 3U 4U */
\r
1112 bool direct; /*!< USB PLL CCO output control */
\r
1113 bool bypass; /*!< USB PLL inout clock bypass control */
\r
1114 bool fbsel; /*!< USB PLL ineter mode and non-integer mode control*/
\r
1115 uint32_t inputRate; /*!< USB PLL input rate */
\r
1116 } usb_pll_setup_t;
\r
1118 /*! @brief Return System PLL output clock rate from setup structure
\r
1119 * @param pSetup : Pointer to a PLL setup structure
\r
1120 * @return System PLL output clock rate the setup structure will generate
\r
1122 uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup);
\r
1124 /*! @brief Return System AUDIO PLL output clock rate from setup structure
\r
1125 * @param pSetup : Pointer to a PLL setup structure
\r
1126 * @return System PLL output clock rate the setup structure will generate
\r
1128 uint32_t CLOCK_GetAudioPLLOutFromSetup(pll_setup_t *pSetup);
\r
1130 /*! @brief Return System AUDIO PLL output clock rate from audio fractioanl setup structure
\r
1131 * @param pSetup : Pointer to a PLL setup structure
\r
1132 * @return System PLL output clock rate the setup structure will generate
\r
1134 uint32_t CLOCK_GetAudioPLLOutFromFractSetup(pll_setup_t *pSetup);
\r
1136 /*! @brief Return System USB PLL output clock rate from setup structure
\r
1137 * @param pSetup : Pointer to a PLL setup structure
\r
1138 * @return System PLL output clock rate the setup structure will generate
\r
1140 uint32_t CLOCK_GetUsbPLLOutFromSetup(const usb_pll_setup_t *pSetup);
\r
1142 /*! @brief Set PLL output based on the passed PLL setup data
\r
1143 * @param pControl : Pointer to populated PLL control structure to generate setup with
\r
1144 * @param pSetup : Pointer to PLL setup structure to be filled
\r
1145 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
\r
1146 * @note Actual frequency for setup may vary from the desired frequency based on the
\r
1147 * accuracy of input clocks, rounding, non-fractional PLL mode, etc.
\r
1149 pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup);
\r
1151 /*! @brief Set AUDIO PLL output based on the passed AUDIO PLL setup data
\r
1152 * @param pControl : Pointer to populated PLL control structure to generate setup with
\r
1153 * @param pSetup : Pointer to PLL setup structure to be filled
\r
1154 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
\r
1155 * @note Actual frequency for setup may vary from the desired frequency based on the
\r
1156 * accuracy of input clocks, rounding, non-fractional PLL mode, etc.
\r
1158 pll_error_t CLOCK_SetupAudioPLLData(pll_config_t *pControl, pll_setup_t *pSetup);
\r
1160 /*! @brief Set PLL output from PLL setup structure (precise frequency)
\r
1161 * @param pSetup : Pointer to populated PLL setup structure
\r
1162 * @param flagcfg : Flag configuration for PLL config structure
\r
1163 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
\r
1164 * @note This function will power off the PLL, setup the PLL with the
\r
1165 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
\r
1166 * and adjust system voltages to the new PLL rate. The function will not
\r
1167 * alter any source clocks (ie, main systen clock) that may use the PLL,
\r
1168 * so these should be setup prior to and after exiting the function.
\r
1170 pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg);
\r
1172 /*! @brief Set AUDIO PLL output from AUDIOPLL setup structure (precise frequency)
\r
1173 * @param pSetup : Pointer to populated PLL setup structure
\r
1174 * @param flagcfg : Flag configuration for PLL config structure
\r
1175 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
\r
1176 * @note This function will power off the PLL, setup the PLL with the
\r
1177 * new setup data, and then optionally powerup the AUDIO PLL, wait for PLL lock,
\r
1178 * and adjust system voltages to the new AUDIOPLL rate. The function will not
\r
1179 * alter any source clocks (ie, main systen clock) that may use the AUDIO PLL,
\r
1180 * so these should be setup prior to and after exiting the function.
\r
1182 pll_error_t CLOCK_SetupAudioPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg);
\r
1184 /*! @brief Set AUDIO PLL output from AUDIOPLL setup structure using the Audio Fractional divider register(precise
\r
1186 * @param pSetup : Pointer to populated PLL setup structure
\r
1187 * @param flagcfg : Flag configuration for PLL config structure
\r
1188 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
\r
1189 * @note This function will power off the PLL, setup the PLL with the
\r
1190 * new setup data, and then optionally powerup the AUDIO PLL, wait for PLL lock,
\r
1191 * and adjust system voltages to the new AUDIOPLL rate. The function will not
\r
1192 * alter any source clocks (ie, main systen clock) that may use the AUDIO PLL,
\r
1193 * so these should be setup prior to and after exiting the function.
\r
1195 pll_error_t CLOCK_SetupAudioPLLPrecFract(pll_setup_t *pSetup, uint32_t flagcfg);
\r
1198 * @brief Set PLL output from PLL setup structure (precise frequency)
\r
1199 * @param pSetup : Pointer to populated PLL setup structure
\r
1200 * @return kStatus_PLL_Success on success, or PLL setup error code
\r
1201 * @note This function will power off the PLL, setup the PLL with the
\r
1202 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
\r
1203 * and adjust system voltages to the new PLL rate. The function will not
\r
1204 * alter any source clocks (ie, main systen clock) that may use the PLL,
\r
1205 * so these should be setup prior to and after exiting the function.
\r
1207 pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup);
\r
1210 * @brief Set Audio PLL output from Audio PLL setup structure (precise frequency)
\r
1211 * @param pSetup : Pointer to populated PLL setup structure
\r
1212 * @return kStatus_PLL_Success on success, or Audio PLL setup error code
\r
1213 * @note This function will power off the PLL, setup the Audio PLL with the
\r
1214 * new setup data, and then optionally powerup the PLL, wait for Audio PLL lock,
\r
1215 * and adjust system voltages to the new PLL rate. The function will not
\r
1216 * alter any source clocks (ie, main systen clock) that may use the Audio PLL,
\r
1217 * so these should be setup prior to and after exiting the function.
\r
1219 pll_error_t CLOCK_SetAudioPLLFreq(const pll_setup_t *pSetup);
\r
1222 * @brief Set USB PLL output from USB PLL setup structure (precise frequency)
\r
1223 * @param pSetup : Pointer to populated USB PLL setup structure
\r
1224 * @return kStatus_PLL_Success on success, or USB PLL setup error code
\r
1225 * @note This function will power off the USB PLL, setup the PLL with the
\r
1226 * new setup data, and then optionally powerup the USB PLL, wait for USB PLL lock,
\r
1227 * and adjust system voltages to the new USB PLL rate. The function will not
\r
1228 * alter any source clocks (ie, usb pll clock) that may use the USB PLL,
\r
1229 * so these should be setup prior to and after exiting the function.
\r
1231 pll_error_t CLOCK_SetUsbPLLFreq(const usb_pll_setup_t *pSetup);
\r
1233 /*! @brief Set PLL output based on the multiplier and input frequency
\r
1234 * @param multiply_by : multiplier
\r
1235 * @param input_freq : Clock input frequency of the PLL
\r
1237 * @note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this
\r
1238 * function does not disable or enable PLL power, wait for PLL lock,
\r
1239 * or adjust system voltages. These must be done in the application.
\r
1240 * The function will not alter any source clocks (ie, main systen clock)
\r
1241 * that may use the PLL, so these should be setup prior to and after
\r
1242 * exiting the function.
\r
1244 void CLOCK_SetupSystemPLLMult(uint32_t multiply_by, uint32_t input_freq);
\r
1246 /*! @brief Disable USB clock.
\r
1248 * Disable USB clock.
\r
1250 static inline void CLOCK_DisableUsbDevicefs0Clock(clock_ip_name_t clk)
\r
1252 CLOCK_DisableClock(clk);
\r
1255 /*! @brief Enable USB Device FS clock.
\r
1256 * @param src : clock source
\r
1257 * @param freq: clock frequency
\r
1258 * Enable USB Device Full Speed clock.
\r
1260 bool CLOCK_EnableUsbfs0DeviceClock(clock_usb_src_t src, uint32_t freq);
\r
1262 /*! @brief Enable USB HOST FS clock.
\r
1263 * @param src : clock source
\r
1264 * @param freq: clock frequency
\r
1265 * Enable USB HOST Full Speed clock.
\r
1267 bool CLOCK_EnableUsbfs0HostClock(clock_usb_src_t src, uint32_t freq);
\r
1269 /*! @brief Set the current Usb PLL Rate
\r
1271 void CLOCK_SetStoredUsbPLLClockRate(uint32_t rate);
\r
1273 /*! @brief Enable USB Device HS clock.
\r
1274 * @param src : clock source
\r
1275 * @param freq: clock frequency
\r
1276 * Enable USB Device High Speed clock.
\r
1278 bool CLOCK_EnableUsbhs0DeviceClock(clock_usb_src_t src, uint32_t freq);
\r
1280 /*! @brief Enable USB HOST HS clock.
\r
1281 * @param src : clock source
\r
1282 * @param freq: clock frequency
\r
1283 * Enable USB HOST High Speed clock.
\r
1285 bool CLOCK_EnableUsbhs0HostClock(clock_usb_src_t src, uint32_t freq);
\r
1287 #if defined(__cplusplus)
\r
1289 #endif /* __cplusplus */
\r
1293 #endif /* _FSL_CLOCK_H_ */
\r
projects / freertos / blob