2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
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3 * Copyright 2016, NXP
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4 * All rights reserved.
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7 * SPDX-License-Identifier: BSD-3-Clause
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9 #ifndef _FSL_POWER_H_
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10 #define _FSL_POWER_H_
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12 #include "fsl_common.h"
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14 /*! @addtogroup power */
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19 /*******************************************************************************
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21 ******************************************************************************/
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23 /*! @name Driver version */
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25 /*! @brief power driver version 2.0.0. */
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26 #define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
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29 #define MAKE_PD_BITS(reg, slot) (((reg) << 8) | (slot))
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30 #define PDRCFG0 0x0U
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31 #define PDRCFG1 0x1U
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33 typedef enum pd_bits
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35 kPDRUNCFG_LP_REG = MAKE_PD_BITS(PDRCFG0, 2U),
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36 kPDRUNCFG_PD_FRO_EN = MAKE_PD_BITS(PDRCFG0, 4U),
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37 kPDRUNCFG_PD_TS = MAKE_PD_BITS(PDRCFG0, 6U),
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38 kPDRUNCFG_PD_BOD_RESET = MAKE_PD_BITS(PDRCFG0, 7U),
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39 kPDRUNCFG_PD_BOD_INTR = MAKE_PD_BITS(PDRCFG0, 8U),
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40 kPDRUNCFG_PD_VD2_ANA = MAKE_PD_BITS(PDRCFG0, 9U),
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41 kPDRUNCFG_PD_ADC0 = MAKE_PD_BITS(PDRCFG0, 10U),
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42 kPDRUNCFG_PD_RAM0 = MAKE_PD_BITS(PDRCFG0, 13U),
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43 kPDRUNCFG_PD_RAM1 = MAKE_PD_BITS(PDRCFG0, 14U),
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44 kPDRUNCFG_PD_RAM2 = MAKE_PD_BITS(PDRCFG0, 15U),
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45 kPDRUNCFG_PD_RAM3 = MAKE_PD_BITS(PDRCFG0, 16U),
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46 kPDRUNCFG_PD_ROM = MAKE_PD_BITS(PDRCFG0, 17U),
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47 kPDRUNCFG_PD_VDDA = MAKE_PD_BITS(PDRCFG0, 19U),
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48 kPDRUNCFG_PD_WDT_OSC = MAKE_PD_BITS(PDRCFG0, 20U),
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49 kPDRUNCFG_PD_USB0_PHY = MAKE_PD_BITS(PDRCFG0, 21U),
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50 kPDRUNCFG_PD_SYS_PLL0 = MAKE_PD_BITS(PDRCFG0, 22U),
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51 kPDRUNCFG_PD_VREFP = MAKE_PD_BITS(PDRCFG0, 23U),
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52 kPDRUNCFG_PD_FLASH_BG = MAKE_PD_BITS(PDRCFG0, 25U),
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53 kPDRUNCFG_PD_VD3 = MAKE_PD_BITS(PDRCFG0, 26U),
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54 kPDRUNCFG_PD_VD4 = MAKE_PD_BITS(PDRCFG0, 27U),
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55 kPDRUNCFG_PD_VD5 = MAKE_PD_BITS(PDRCFG0, 28U),
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56 kPDRUNCFG_PD_VD6 = MAKE_PD_BITS(PDRCFG0, 29U),
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57 kPDRUNCFG_REQ_DELAY = MAKE_PD_BITS(PDRCFG0, 30U),
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58 kPDRUNCFG_FORCE_RBB = MAKE_PD_BITS(PDRCFG0, 31U),
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60 kPDRUNCFG_PD_USB1_PHY = MAKE_PD_BITS(PDRCFG1, 0U),
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61 kPDRUNCFG_PD_USB_PLL = MAKE_PD_BITS(PDRCFG1, 1U),
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62 kPDRUNCFG_PD_AUDIO_PLL = MAKE_PD_BITS(PDRCFG1, 2U),
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63 kPDRUNCFG_PD_SYS_OSC = MAKE_PD_BITS(PDRCFG1, 3U),
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64 kPDRUNCFG_PD_EEPROM = MAKE_PD_BITS(PDRCFG1, 5U),
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65 kPDRUNCFG_PD_rng = MAKE_PD_BITS(PDRCFG1, 6U),
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68 This enum member has no practical meaning,it is used to avoid MISRA issue,
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69 user should not trying to use it.
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71 kPDRUNCFG_ForceUnsigned = (int)0x80000000U,
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74 /* Power mode configuration API parameter */
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75 typedef enum _power_mode_config
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78 kPmu_Deep_Sleep = 1U,
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79 kPmu_Deep_PowerDown = 2U,
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82 /*******************************************************************************
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84 ******************************************************************************/
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91 * @name Power Configuration
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96 * @brief API to enable PDRUNCFG bit in the Syscon. Note that enabling the bit powers down the peripheral
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98 * @param en peripheral for which to enable the PDRUNCFG bit
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101 static inline void POWER_EnablePD(pd_bit_t en)
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104 SYSCON->PDRUNCFGSET[((uint32_t)en >> 8UL)] = (1UL << ((uint32_t)en & 0xffU));
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108 * @brief API to disable PDRUNCFG bit in the Syscon. Note that disabling the bit powers up the peripheral
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110 * @param en peripheral for which to disable the PDRUNCFG bit
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113 static inline void POWER_DisablePD(pd_bit_t en)
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116 SYSCON->PDRUNCFGCLR[((uint32_t)en >> 8UL)] = (1UL << ((uint32_t)en & 0xffU));
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120 * @brief API to enable deep sleep bit in the ARM Core.
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125 static inline void POWER_EnableDeepSleep(void)
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127 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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131 * @brief API to disable deep sleep bit in the ARM Core.
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136 static inline void POWER_DisableDeepSleep(void)
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138 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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142 * @brief Power Library API to reload OTP.
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143 * This API must be called if VD6 is power down
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144 * and power back again since FROHF TRIM value
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145 * is store in OTP. If not, when calling FROHF settng
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146 * API in clock driver then the FROHF clock out put
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147 * will be inaccurate.
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150 void POWER_OtpReload(void);
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153 * @brief Power Library API to power the PLLs.
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158 void POWER_SetPLL(void);
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161 * @brief Power Library API to power the USB PHY.
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166 void POWER_SetUsbPhy(void);
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169 * @brief Power Library API to enter different power mode.
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171 * @param exclude_from_pd Bit mask of the PDRUNCFG0(low 32bits) and PDRUNCFG1(high 32bits) that needs to be powered on
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172 * during power mode selected.
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175 void POWER_EnterPowerMode(power_mode_cfg_t mode, uint64_t exclude_from_pd);
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178 * @brief Power Library API to enter sleep mode.
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182 void POWER_EnterSleep(void);
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185 * @brief Power Library API to enter deep sleep mode.
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187 * @param exclude_from_pd Bit mask of the PDRUNCFG0(low 32bits) and PDRUNCFG1(high 32bits) bits that needs to be
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188 * powered on during deep sleep
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191 void POWER_EnterDeepSleep(uint64_t exclude_from_pd);
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194 * @brief Power Library API to enter deep power down mode.
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196 * @param exclude_from_pd Bit mask of the PDRUNCFG0(low 32bits) and PDRUNCFG1(high 32bits) that needs to be powered on
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198 * down mode, but this is has no effect as the voltages are cut off.
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202 void POWER_EnterDeepPowerDown(uint64_t exclude_from_pd);
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205 * @brief Power Library API to choose normal regulation and set the voltage for the desired operating frequency.
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207 * @param freq - The desired frequency at which the part would like to operate,
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208 * note that the voltage and flash wait states should be set before changing frequency
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211 void POWER_SetVoltageForFreq(uint32_t freq);
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214 * @brief Power Library API to return the library version.
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217 * @return version number of the power library
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219 uint32_t POWER_GetLibVersion(void);
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225 #endif /* _FSL_POWER_H_ */
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