1 /**************************************************************************//**
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2 * @file cmsis_armcc.h
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3 * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
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5 * @date 14. December 2018
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6 ******************************************************************************/
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8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
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10 * SPDX-License-Identifier: Apache-2.0
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12 * Licensed under the Apache License, Version 2.0 (the License); you may
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13 * not use this file except in compliance with the License.
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14 * You may obtain a copy of the License at
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16 * www.apache.org/licenses/LICENSE-2.0
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18 * Unless required by applicable law or agreed to in writing, software
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19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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21 * See the License for the specific language governing permissions and
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22 * limitations under the License.
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25 #ifndef __CMSIS_ARMCC_H
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26 #define __CMSIS_ARMCC_H
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29 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
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30 #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
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33 /* CMSIS compiler control architecture macros */
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34 #if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
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35 (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
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36 #define __ARM_ARCH_6M__ 1
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39 #if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
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40 #define __ARM_ARCH_7M__ 1
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43 #if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
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44 #define __ARM_ARCH_7EM__ 1
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47 /* __ARM_ARCH_8M_BASE__ not applicable */
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48 /* __ARM_ARCH_8M_MAIN__ not applicable */
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50 /* CMSIS compiler control DSP macros */
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51 #if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
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52 #define __ARM_FEATURE_DSP 1
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55 /* CMSIS compiler specific defines */
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60 #define __INLINE __inline
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62 #ifndef __STATIC_INLINE
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63 #define __STATIC_INLINE static __inline
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65 #ifndef __STATIC_FORCEINLINE
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66 #define __STATIC_FORCEINLINE static __forceinline
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69 #define __NO_RETURN __declspec(noreturn)
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72 #define __USED __attribute__((used))
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75 #define __WEAK __attribute__((weak))
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78 #define __PACKED __attribute__((packed))
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80 #ifndef __PACKED_STRUCT
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81 #define __PACKED_STRUCT __packed struct
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83 #ifndef __PACKED_UNION
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84 #define __PACKED_UNION __packed union
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86 #ifndef __UNALIGNED_UINT32 /* deprecated */
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87 #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
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89 #ifndef __UNALIGNED_UINT16_WRITE
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90 #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
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92 #ifndef __UNALIGNED_UINT16_READ
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93 #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
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95 #ifndef __UNALIGNED_UINT32_WRITE
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96 #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
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98 #ifndef __UNALIGNED_UINT32_READ
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99 #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
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102 #define __ALIGNED(x) __attribute__((aligned(x)))
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105 #define __RESTRICT __restrict
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108 /* ########################### Core Function Access ########################### */
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109 /** \ingroup CMSIS_Core_FunctionInterface
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110 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
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115 \brief Enable IRQ Interrupts
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116 \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
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117 Can only be executed in Privileged modes.
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119 /* intrinsic void __enable_irq(); */
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123 \brief Disable IRQ Interrupts
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124 \details Disables IRQ interrupts by setting the I-bit in the CPSR.
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125 Can only be executed in Privileged modes.
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127 /* intrinsic void __disable_irq(); */
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130 \brief Get Control Register
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131 \details Returns the content of the Control Register.
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132 \return Control Register value
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134 __STATIC_INLINE uint32_t __get_CONTROL(void)
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136 register uint32_t __regControl __ASM("control");
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137 return(__regControl);
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142 \brief Set Control Register
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143 \details Writes the given value to the Control Register.
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144 \param [in] control Control Register value to set
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146 __STATIC_INLINE void __set_CONTROL(uint32_t control)
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148 register uint32_t __regControl __ASM("control");
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149 __regControl = control;
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154 \brief Get IPSR Register
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155 \details Returns the content of the IPSR Register.
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156 \return IPSR Register value
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158 __STATIC_INLINE uint32_t __get_IPSR(void)
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160 register uint32_t __regIPSR __ASM("ipsr");
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166 \brief Get APSR Register
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167 \details Returns the content of the APSR Register.
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168 \return APSR Register value
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170 __STATIC_INLINE uint32_t __get_APSR(void)
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172 register uint32_t __regAPSR __ASM("apsr");
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178 \brief Get xPSR Register
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179 \details Returns the content of the xPSR Register.
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180 \return xPSR Register value
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182 __STATIC_INLINE uint32_t __get_xPSR(void)
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184 register uint32_t __regXPSR __ASM("xpsr");
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190 \brief Get Process Stack Pointer
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191 \details Returns the current value of the Process Stack Pointer (PSP).
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192 \return PSP Register value
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194 __STATIC_INLINE uint32_t __get_PSP(void)
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196 register uint32_t __regProcessStackPointer __ASM("psp");
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197 return(__regProcessStackPointer);
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202 \brief Set Process Stack Pointer
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203 \details Assigns the given value to the Process Stack Pointer (PSP).
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204 \param [in] topOfProcStack Process Stack Pointer value to set
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206 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
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208 register uint32_t __regProcessStackPointer __ASM("psp");
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209 __regProcessStackPointer = topOfProcStack;
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214 \brief Get Main Stack Pointer
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215 \details Returns the current value of the Main Stack Pointer (MSP).
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216 \return MSP Register value
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218 __STATIC_INLINE uint32_t __get_MSP(void)
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220 register uint32_t __regMainStackPointer __ASM("msp");
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221 return(__regMainStackPointer);
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226 \brief Set Main Stack Pointer
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227 \details Assigns the given value to the Main Stack Pointer (MSP).
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228 \param [in] topOfMainStack Main Stack Pointer value to set
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230 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
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232 register uint32_t __regMainStackPointer __ASM("msp");
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233 __regMainStackPointer = topOfMainStack;
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238 \brief Get Priority Mask
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239 \details Returns the current state of the priority mask bit from the Priority Mask Register.
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240 \return Priority Mask value
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242 __STATIC_INLINE uint32_t __get_PRIMASK(void)
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244 register uint32_t __regPriMask __ASM("primask");
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245 return(__regPriMask);
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250 \brief Set Priority Mask
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251 \details Assigns the given value to the Priority Mask Register.
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252 \param [in] priMask Priority Mask
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254 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
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256 register uint32_t __regPriMask __ASM("primask");
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257 __regPriMask = (priMask);
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261 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
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262 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
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266 \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
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267 Can only be executed in Privileged modes.
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269 #define __enable_fault_irq __enable_fiq
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274 \details Disables FIQ interrupts by setting the F-bit in the CPSR.
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275 Can only be executed in Privileged modes.
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277 #define __disable_fault_irq __disable_fiq
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281 \brief Get Base Priority
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282 \details Returns the current value of the Base Priority register.
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283 \return Base Priority register value
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285 __STATIC_INLINE uint32_t __get_BASEPRI(void)
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287 register uint32_t __regBasePri __ASM("basepri");
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288 return(__regBasePri);
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293 \brief Set Base Priority
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294 \details Assigns the given value to the Base Priority register.
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295 \param [in] basePri Base Priority value to set
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297 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
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299 register uint32_t __regBasePri __ASM("basepri");
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300 __regBasePri = (basePri & 0xFFU);
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305 \brief Set Base Priority with condition
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306 \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
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307 or the new value increases the BASEPRI priority level.
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308 \param [in] basePri Base Priority value to set
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310 __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
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312 register uint32_t __regBasePriMax __ASM("basepri_max");
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313 __regBasePriMax = (basePri & 0xFFU);
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318 \brief Get Fault Mask
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319 \details Returns the current value of the Fault Mask register.
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320 \return Fault Mask register value
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322 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
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324 register uint32_t __regFaultMask __ASM("faultmask");
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325 return(__regFaultMask);
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330 \brief Set Fault Mask
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331 \details Assigns the given value to the Fault Mask register.
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332 \param [in] faultMask Fault Mask value to set
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334 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
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336 register uint32_t __regFaultMask __ASM("faultmask");
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337 __regFaultMask = (faultMask & (uint32_t)1U);
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340 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
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341 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
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346 \details Returns the current value of the Floating Point Status/Control register.
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347 \return Floating Point Status/Control register value
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349 __STATIC_INLINE uint32_t __get_FPSCR(void)
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351 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
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352 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
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353 register uint32_t __regfpscr __ASM("fpscr");
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354 return(__regfpscr);
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363 \details Assigns the given value to the Floating Point Status/Control register.
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364 \param [in] fpscr Floating Point Status/Control value to set
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366 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
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368 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
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369 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
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370 register uint32_t __regfpscr __ASM("fpscr");
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371 __regfpscr = (fpscr);
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378 /*@} end of CMSIS_Core_RegAccFunctions */
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381 /* ########################## Core Instruction Access ######################### */
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382 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
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383 Access to dedicated instructions
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388 \brief No Operation
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389 \details No Operation does nothing. This instruction can be used for code alignment purposes.
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391 #define __NOP __nop
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395 \brief Wait For Interrupt
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396 \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
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398 #define __WFI __wfi
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402 \brief Wait For Event
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403 \details Wait For Event is a hint instruction that permits the processor to enter
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404 a low-power state until one of a number of events occurs.
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406 #define __WFE __wfe
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411 \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
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413 #define __SEV __sev
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417 \brief Instruction Synchronization Barrier
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418 \details Instruction Synchronization Barrier flushes the pipeline in the processor,
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419 so that all instructions following the ISB are fetched from cache or memory,
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420 after the instruction has been completed.
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422 #define __ISB() do {\
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423 __schedule_barrier();\
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425 __schedule_barrier();\
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429 \brief Data Synchronization Barrier
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430 \details Acts as a special kind of Data Memory Barrier.
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431 It completes when all explicit memory accesses before this instruction complete.
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433 #define __DSB() do {\
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434 __schedule_barrier();\
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436 __schedule_barrier();\
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440 \brief Data Memory Barrier
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441 \details Ensures the apparent order of the explicit memory operations before
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442 and after the instruction, without ensuring their completion.
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444 #define __DMB() do {\
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445 __schedule_barrier();\
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447 __schedule_barrier();\
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452 \brief Reverse byte order (32 bit)
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453 \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
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454 \param [in] value Value to reverse
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455 \return Reversed value
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457 #define __REV __rev
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461 \brief Reverse byte order (16 bit)
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462 \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
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463 \param [in] value Value to reverse
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464 \return Reversed value
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466 #ifndef __NO_EMBEDDED_ASM
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467 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
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476 \brief Reverse byte order (16 bit)
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477 \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
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478 \param [in] value Value to reverse
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479 \return Reversed value
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481 #ifndef __NO_EMBEDDED_ASM
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482 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
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491 \brief Rotate Right in unsigned value (32 bit)
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492 \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
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493 \param [in] op1 Value to rotate
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494 \param [in] op2 Number of Bits to rotate
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495 \return Rotated value
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497 #define __ROR __ror
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502 \details Causes the processor to enter Debug state.
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503 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
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504 \param [in] value is ignored by the processor.
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505 If required, a debugger can use it to store additional information about the breakpoint.
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507 #define __BKPT(value) __breakpoint(value)
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511 \brief Reverse bit order of value
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512 \details Reverses the bit order of the given value.
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513 \param [in] value Value to reverse
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514 \return Reversed value
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516 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
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517 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
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518 #define __RBIT __rbit
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520 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
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523 uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
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525 result = value; /* r will be reversed bits of v; first get LSB of v */
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526 for (value >>= 1U; value != 0U; value >>= 1U)
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529 result |= value & 1U;
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532 result <<= s; /* shift when v's highest bits are zero */
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539 \brief Count leading zeros
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540 \details Counts the number of leading zeros of a data value.
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541 \param [in] value Value to count the leading zeros
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542 \return number of leading zeros in value
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544 #define __CLZ __clz
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547 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
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548 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
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551 \brief LDR Exclusive (8 bit)
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552 \details Executes a exclusive LDR instruction for 8 bit value.
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553 \param [in] ptr Pointer to data
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554 \return value of type uint8_t at (*ptr)
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556 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
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557 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
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559 #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
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564 \brief LDR Exclusive (16 bit)
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565 \details Executes a exclusive LDR instruction for 16 bit values.
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566 \param [in] ptr Pointer to data
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567 \return value of type uint16_t at (*ptr)
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569 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
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570 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
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572 #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
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577 \brief LDR Exclusive (32 bit)
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578 \details Executes a exclusive LDR instruction for 32 bit values.
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579 \param [in] ptr Pointer to data
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580 \return value of type uint32_t at (*ptr)
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582 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
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583 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
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585 #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
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590 \brief STR Exclusive (8 bit)
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591 \details Executes a exclusive STR instruction for 8 bit values.
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592 \param [in] value Value to store
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593 \param [in] ptr Pointer to location
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594 \return 0 Function succeeded
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595 \return 1 Function failed
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597 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
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598 #define __STREXB(value, ptr) __strex(value, ptr)
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600 #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
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605 \brief STR Exclusive (16 bit)
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606 \details Executes a exclusive STR instruction for 16 bit values.
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607 \param [in] value Value to store
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608 \param [in] ptr Pointer to location
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609 \return 0 Function succeeded
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610 \return 1 Function failed
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612 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
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613 #define __STREXH(value, ptr) __strex(value, ptr)
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615 #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
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620 \brief STR Exclusive (32 bit)
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621 \details Executes a exclusive STR instruction for 32 bit values.
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622 \param [in] value Value to store
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623 \param [in] ptr Pointer to location
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624 \return 0 Function succeeded
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625 \return 1 Function failed
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627 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
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628 #define __STREXW(value, ptr) __strex(value, ptr)
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630 #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
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635 \brief Remove the exclusive lock
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636 \details Removes the exclusive lock which is created by LDREX.
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638 #define __CLREX __clrex
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642 \brief Signed Saturate
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643 \details Saturates a signed value.
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644 \param [in] value Value to be saturated
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645 \param [in] sat Bit position to saturate to (1..32)
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646 \return Saturated value
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648 #define __SSAT __ssat
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652 \brief Unsigned Saturate
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653 \details Saturates an unsigned value.
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654 \param [in] value Value to be saturated
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655 \param [in] sat Bit position to saturate to (0..31)
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656 \return Saturated value
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658 #define __USAT __usat
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662 \brief Rotate Right with Extend (32 bit)
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663 \details Moves each bit of a bitstring right by one bit.
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664 The carry input is shifted in at the left end of the bitstring.
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665 \param [in] value Value to rotate
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666 \return Rotated value
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668 #ifndef __NO_EMBEDDED_ASM
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669 __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
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678 \brief LDRT Unprivileged (8 bit)
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679 \details Executes a Unprivileged LDRT instruction for 8 bit value.
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680 \param [in] ptr Pointer to data
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681 \return value of type uint8_t at (*ptr)
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683 #define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
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687 \brief LDRT Unprivileged (16 bit)
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688 \details Executes a Unprivileged LDRT instruction for 16 bit values.
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689 \param [in] ptr Pointer to data
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690 \return value of type uint16_t at (*ptr)
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692 #define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
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696 \brief LDRT Unprivileged (32 bit)
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697 \details Executes a Unprivileged LDRT instruction for 32 bit values.
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698 \param [in] ptr Pointer to data
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699 \return value of type uint32_t at (*ptr)
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701 #define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
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705 \brief STRT Unprivileged (8 bit)
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706 \details Executes a Unprivileged STRT instruction for 8 bit values.
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707 \param [in] value Value to store
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708 \param [in] ptr Pointer to location
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710 #define __STRBT(value, ptr) __strt(value, ptr)
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714 \brief STRT Unprivileged (16 bit)
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715 \details Executes a Unprivileged STRT instruction for 16 bit values.
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716 \param [in] value Value to store
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717 \param [in] ptr Pointer to location
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719 #define __STRHT(value, ptr) __strt(value, ptr)
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723 \brief STRT Unprivileged (32 bit)
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724 \details Executes a Unprivileged STRT instruction for 32 bit values.
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725 \param [in] value Value to store
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726 \param [in] ptr Pointer to location
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728 #define __STRT(value, ptr) __strt(value, ptr)
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730 #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
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731 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
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734 \brief Signed Saturate
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735 \details Saturates a signed value.
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736 \param [in] value Value to be saturated
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737 \param [in] sat Bit position to saturate to (1..32)
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738 \return Saturated value
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740 __attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
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742 if ((sat >= 1U) && (sat <= 32U))
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744 const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
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745 const int32_t min = -1 - max ;
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750 else if (val < min)
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759 \brief Unsigned Saturate
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760 \details Saturates an unsigned value.
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761 \param [in] value Value to be saturated
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762 \param [in] sat Bit position to saturate to (0..31)
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763 \return Saturated value
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765 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
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769 const uint32_t max = ((1U << sat) - 1U);
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770 if (val > (int32_t)max)
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779 return (uint32_t)val;
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782 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
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783 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
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785 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
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788 /* ################### Compiler specific Intrinsics ########################### */
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789 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
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790 Access to dedicated SIMD instructions
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794 #if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
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796 #define __SADD8 __sadd8
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797 #define __QADD8 __qadd8
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798 #define __SHADD8 __shadd8
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799 #define __UADD8 __uadd8
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800 #define __UQADD8 __uqadd8
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801 #define __UHADD8 __uhadd8
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802 #define __SSUB8 __ssub8
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803 #define __QSUB8 __qsub8
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804 #define __SHSUB8 __shsub8
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805 #define __USUB8 __usub8
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806 #define __UQSUB8 __uqsub8
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807 #define __UHSUB8 __uhsub8
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808 #define __SADD16 __sadd16
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809 #define __QADD16 __qadd16
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810 #define __SHADD16 __shadd16
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811 #define __UADD16 __uadd16
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812 #define __UQADD16 __uqadd16
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813 #define __UHADD16 __uhadd16
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814 #define __SSUB16 __ssub16
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815 #define __QSUB16 __qsub16
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816 #define __SHSUB16 __shsub16
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817 #define __USUB16 __usub16
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818 #define __UQSUB16 __uqsub16
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819 #define __UHSUB16 __uhsub16
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820 #define __SASX __sasx
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821 #define __QASX __qasx
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822 #define __SHASX __shasx
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823 #define __UASX __uasx
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824 #define __UQASX __uqasx
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825 #define __UHASX __uhasx
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826 #define __SSAX __ssax
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827 #define __QSAX __qsax
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828 #define __SHSAX __shsax
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829 #define __USAX __usax
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830 #define __UQSAX __uqsax
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831 #define __UHSAX __uhsax
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832 #define __USAD8 __usad8
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833 #define __USADA8 __usada8
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834 #define __SSAT16 __ssat16
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835 #define __USAT16 __usat16
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836 #define __UXTB16 __uxtb16
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837 #define __UXTAB16 __uxtab16
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838 #define __SXTB16 __sxtb16
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839 #define __SXTAB16 __sxtab16
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840 #define __SMUAD __smuad
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841 #define __SMUADX __smuadx
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842 #define __SMLAD __smlad
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843 #define __SMLADX __smladx
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844 #define __SMLALD __smlald
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845 #define __SMLALDX __smlaldx
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846 #define __SMUSD __smusd
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847 #define __SMUSDX __smusdx
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848 #define __SMLSD __smlsd
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849 #define __SMLSDX __smlsdx
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850 #define __SMLSLD __smlsld
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851 #define __SMLSLDX __smlsldx
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852 #define __SEL __sel
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853 #define __QADD __qadd
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854 #define __QSUB __qsub
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856 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
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857 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
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859 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
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860 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
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862 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
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863 ((int64_t)(ARG3) << 32U) ) >> 32U))
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865 #endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
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866 /*@} end of group CMSIS_SIMD_intrinsics */
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869 #endif /* __CMSIS_ARMCC_H */
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