1 /**************************************************************************//**
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2 * @file cmsis_armclang.h
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3 * @brief CMSIS compiler armclang (Arm Compiler 6) header file
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5 * @date 14. March 2019
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6 ******************************************************************************/
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8 * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
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10 * SPDX-License-Identifier: Apache-2.0
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12 * Licensed under the Apache License, Version 2.0 (the License); you may
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13 * not use this file except in compliance with the License.
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14 * You may obtain a copy of the License at
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16 * www.apache.org/licenses/LICENSE-2.0
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18 * Unless required by applicable law or agreed to in writing, software
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19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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21 * See the License for the specific language governing permissions and
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22 * limitations under the License.
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25 /*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
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27 #ifndef __CMSIS_ARMCLANG_H
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28 #define __CMSIS_ARMCLANG_H
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30 #pragma clang system_header /* treat file as system include file */
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32 #ifndef __ARM_COMPAT_H
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33 #include <arm_compat.h> /* Compatibility header for Arm Compiler 5 intrinsics */
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36 /* CMSIS compiler specific defines */
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41 #define __INLINE __inline
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43 #ifndef __STATIC_INLINE
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44 #define __STATIC_INLINE static __inline
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46 #ifndef __STATIC_FORCEINLINE
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47 #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
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50 #define __NO_RETURN __attribute__((__noreturn__))
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53 #define __USED __attribute__((used))
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56 #define __WEAK __attribute__((weak))
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59 #define __PACKED __attribute__((packed, aligned(1)))
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61 #ifndef __PACKED_STRUCT
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62 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
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64 #ifndef __PACKED_UNION
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65 #define __PACKED_UNION union __attribute__((packed, aligned(1)))
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67 #ifndef __UNALIGNED_UINT32 /* deprecated */
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68 #pragma clang diagnostic push
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69 #pragma clang diagnostic ignored "-Wpacked"
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70 /*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
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71 struct __attribute__((packed)) T_UINT32 { uint32_t v; };
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72 #pragma clang diagnostic pop
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73 #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
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75 #ifndef __UNALIGNED_UINT16_WRITE
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76 #pragma clang diagnostic push
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77 #pragma clang diagnostic ignored "-Wpacked"
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78 /*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
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79 __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
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80 #pragma clang diagnostic pop
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81 #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
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83 #ifndef __UNALIGNED_UINT16_READ
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84 #pragma clang diagnostic push
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85 #pragma clang diagnostic ignored "-Wpacked"
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86 /*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
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87 __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
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88 #pragma clang diagnostic pop
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89 #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
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91 #ifndef __UNALIGNED_UINT32_WRITE
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92 #pragma clang diagnostic push
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93 #pragma clang diagnostic ignored "-Wpacked"
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94 /*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
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95 __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
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96 #pragma clang diagnostic pop
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97 #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
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99 #ifndef __UNALIGNED_UINT32_READ
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100 #pragma clang diagnostic push
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101 #pragma clang diagnostic ignored "-Wpacked"
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102 /*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
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103 __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
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104 #pragma clang diagnostic pop
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105 #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
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108 #define __ALIGNED(x) __attribute__((aligned(x)))
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111 #define __RESTRICT __restrict
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115 /* ########################### Core Function Access ########################### */
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116 /** \ingroup CMSIS_Core_FunctionInterface
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117 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
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122 \brief Enable IRQ Interrupts
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123 \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
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124 Can only be executed in Privileged modes.
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126 /* intrinsic void __enable_irq(); see arm_compat.h */
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130 \brief Disable IRQ Interrupts
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131 \details Disables IRQ interrupts by setting the I-bit in the CPSR.
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132 Can only be executed in Privileged modes.
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134 /* intrinsic void __disable_irq(); see arm_compat.h */
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138 \brief Get Control Register
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139 \details Returns the content of the Control Register.
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140 \return Control Register value
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142 __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
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146 __ASM volatile ("MRS %0, control" : "=r" (result) );
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151 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
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153 \brief Get Control Register (non-secure)
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154 \details Returns the content of the non-secure Control Register when in secure mode.
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155 \return non-secure Control Register value
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157 __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
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161 __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
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168 \brief Set Control Register
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169 \details Writes the given value to the Control Register.
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170 \param [in] control Control Register value to set
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172 __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
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174 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
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178 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
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180 \brief Set Control Register (non-secure)
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181 \details Writes the given value to the non-secure Control Register when in secure state.
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182 \param [in] control Control Register value to set
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184 __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
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186 __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
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192 \brief Get IPSR Register
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193 \details Returns the content of the IPSR Register.
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194 \return IPSR Register value
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196 __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
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200 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
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206 \brief Get APSR Register
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207 \details Returns the content of the APSR Register.
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208 \return APSR Register value
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210 __STATIC_FORCEINLINE uint32_t __get_APSR(void)
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214 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
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220 \brief Get xPSR Register
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221 \details Returns the content of the xPSR Register.
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222 \return xPSR Register value
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224 __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
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228 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
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234 \brief Get Process Stack Pointer
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235 \details Returns the current value of the Process Stack Pointer (PSP).
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236 \return PSP Register value
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238 __STATIC_FORCEINLINE uint32_t __get_PSP(void)
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242 __ASM volatile ("MRS %0, psp" : "=r" (result) );
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247 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
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249 \brief Get Process Stack Pointer (non-secure)
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250 \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
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251 \return PSP Register value
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253 __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
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257 __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
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264 \brief Set Process Stack Pointer
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265 \details Assigns the given value to the Process Stack Pointer (PSP).
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266 \param [in] topOfProcStack Process Stack Pointer value to set
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268 __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
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270 __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
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274 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
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276 \brief Set Process Stack Pointer (non-secure)
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277 \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
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278 \param [in] topOfProcStack Process Stack Pointer value to set
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280 __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
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282 __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
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288 \brief Get Main Stack Pointer
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289 \details Returns the current value of the Main Stack Pointer (MSP).
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290 \return MSP Register value
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292 __STATIC_FORCEINLINE uint32_t __get_MSP(void)
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296 __ASM volatile ("MRS %0, msp" : "=r" (result) );
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301 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
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303 \brief Get Main Stack Pointer (non-secure)
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304 \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
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305 \return MSP Register value
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307 __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
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311 __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
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318 \brief Set Main Stack Pointer
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319 \details Assigns the given value to the Main Stack Pointer (MSP).
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320 \param [in] topOfMainStack Main Stack Pointer value to set
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322 __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
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324 __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
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328 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
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330 \brief Set Main Stack Pointer (non-secure)
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331 \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
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332 \param [in] topOfMainStack Main Stack Pointer value to set
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334 __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
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336 __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
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341 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
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343 \brief Get Stack Pointer (non-secure)
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344 \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
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345 \return SP Register value
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347 __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
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351 __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
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357 \brief Set Stack Pointer (non-secure)
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358 \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
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359 \param [in] topOfStack Stack Pointer value to set
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361 __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
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363 __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
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369 \brief Get Priority Mask
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370 \details Returns the current state of the priority mask bit from the Priority Mask Register.
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371 \return Priority Mask value
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373 __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
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377 __ASM volatile ("MRS %0, primask" : "=r" (result) );
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382 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
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384 \brief Get Priority Mask (non-secure)
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385 \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
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386 \return Priority Mask value
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388 __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
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392 __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
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399 \brief Set Priority Mask
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400 \details Assigns the given value to the Priority Mask Register.
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401 \param [in] priMask Priority Mask
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403 __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
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405 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
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409 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
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411 \brief Set Priority Mask (non-secure)
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412 \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
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413 \param [in] priMask Priority Mask
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415 __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
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417 __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
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422 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
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423 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
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424 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
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427 \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
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428 Can only be executed in Privileged modes.
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430 #define __enable_fault_irq __enable_fiq /* see arm_compat.h */
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435 \details Disables FIQ interrupts by setting the F-bit in the CPSR.
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436 Can only be executed in Privileged modes.
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438 #define __disable_fault_irq __disable_fiq /* see arm_compat.h */
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442 \brief Get Base Priority
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443 \details Returns the current value of the Base Priority register.
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444 \return Base Priority register value
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446 __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
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450 __ASM volatile ("MRS %0, basepri" : "=r" (result) );
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455 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
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457 \brief Get Base Priority (non-secure)
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458 \details Returns the current value of the non-secure Base Priority register when in secure state.
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459 \return Base Priority register value
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461 __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
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465 __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
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472 \brief Set Base Priority
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473 \details Assigns the given value to the Base Priority register.
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474 \param [in] basePri Base Priority value to set
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476 __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
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478 __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
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482 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
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484 \brief Set Base Priority (non-secure)
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485 \details Assigns the given value to the non-secure Base Priority register when in secure state.
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486 \param [in] basePri Base Priority value to set
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488 __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
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490 __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
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496 \brief Set Base Priority with condition
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497 \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
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498 or the new value increases the BASEPRI priority level.
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499 \param [in] basePri Base Priority value to set
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501 __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
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503 __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
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508 \brief Get Fault Mask
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509 \details Returns the current value of the Fault Mask register.
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510 \return Fault Mask register value
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512 __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
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516 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
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521 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
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523 \brief Get Fault Mask (non-secure)
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524 \details Returns the current value of the non-secure Fault Mask register when in secure state.
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525 \return Fault Mask register value
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527 __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
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531 __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
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538 \brief Set Fault Mask
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539 \details Assigns the given value to the Fault Mask register.
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540 \param [in] faultMask Fault Mask value to set
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542 __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
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544 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
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548 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
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550 \brief Set Fault Mask (non-secure)
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551 \details Assigns the given value to the non-secure Fault Mask register when in secure state.
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552 \param [in] faultMask Fault Mask value to set
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554 __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
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556 __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
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560 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
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561 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
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562 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
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565 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
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566 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
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569 \brief Get Process Stack Pointer Limit
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570 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
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571 Stack Pointer Limit register hence zero is returned always in non-secure
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574 \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
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575 \return PSPLIM Register value
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577 __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
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579 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
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580 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
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581 // without main extensions, the non-secure PSPLIM is RAZ/WI
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585 __ASM volatile ("MRS %0, psplim" : "=r" (result) );
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590 #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
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592 \brief Get Process Stack Pointer Limit (non-secure)
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593 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
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594 Stack Pointer Limit register hence zero is returned always in non-secure
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597 \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
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598 \return PSPLIM Register value
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600 __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
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602 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
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603 // without main extensions, the non-secure PSPLIM is RAZ/WI
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607 __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
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615 \brief Set Process Stack Pointer Limit
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616 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
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617 Stack Pointer Limit register hence the write is silently ignored in non-secure
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620 \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
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621 \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
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623 __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
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625 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
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626 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
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627 // without main extensions, the non-secure PSPLIM is RAZ/WI
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628 (void)ProcStackPtrLimit;
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630 __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
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635 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
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637 \brief Set Process Stack Pointer (non-secure)
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638 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
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639 Stack Pointer Limit register hence the write is silently ignored in non-secure
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642 \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
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643 \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
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645 __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
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647 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
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648 // without main extensions, the non-secure PSPLIM is RAZ/WI
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649 (void)ProcStackPtrLimit;
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651 __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
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658 \brief Get Main Stack Pointer Limit
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659 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
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660 Stack Pointer Limit register hence zero is returned always.
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662 \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
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663 \return MSPLIM Register value
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665 __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
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667 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
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668 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
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669 // without main extensions, the non-secure MSPLIM is RAZ/WI
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673 __ASM volatile ("MRS %0, msplim" : "=r" (result) );
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679 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
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681 \brief Get Main Stack Pointer Limit (non-secure)
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682 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
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683 Stack Pointer Limit register hence zero is returned always.
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685 \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
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686 \return MSPLIM Register value
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688 __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
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690 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
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691 // without main extensions, the non-secure MSPLIM is RAZ/WI
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695 __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
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703 \brief Set Main Stack Pointer Limit
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704 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
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705 Stack Pointer Limit register hence the write is silently ignored.
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707 \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
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708 \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
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710 __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
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712 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
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713 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
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714 // without main extensions, the non-secure MSPLIM is RAZ/WI
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715 (void)MainStackPtrLimit;
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717 __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
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722 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
\r
724 \brief Set Main Stack Pointer Limit (non-secure)
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725 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
\r
726 Stack Pointer Limit register hence the write is silently ignored.
\r
728 \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
\r
729 \param [in] MainStackPtrLimit Main Stack Pointer value to set
\r
731 __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
\r
733 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
\r
734 // without main extensions, the non-secure MSPLIM is RAZ/WI
\r
735 (void)MainStackPtrLimit;
\r
737 __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
\r
742 #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
\r
743 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
\r
747 \details Returns the current value of the Floating Point Status/Control register.
\r
748 \return Floating Point Status/Control register value
\r
750 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
\r
751 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
\r
752 #define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr
\r
754 #define __get_FPSCR() ((uint32_t)0U)
\r
759 \details Assigns the given value to the Floating Point Status/Control register.
\r
760 \param [in] fpscr Floating Point Status/Control value to set
\r
762 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
\r
763 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
\r
764 #define __set_FPSCR __builtin_arm_set_fpscr
\r
766 #define __set_FPSCR(x) ((void)(x))
\r
770 /*@} end of CMSIS_Core_RegAccFunctions */
\r
773 /* ########################## Core Instruction Access ######################### */
\r
774 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
\r
775 Access to dedicated instructions
\r
779 /* Define macros for porting to both thumb1 and thumb2.
\r
780 * For thumb1, use low register (r0-r7), specified by constraint "l"
\r
781 * Otherwise, use general registers, specified by constraint "r" */
\r
782 #if defined (__thumb__) && !defined (__thumb2__)
\r
783 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
\r
784 #define __CMSIS_GCC_RW_REG(r) "+l" (r)
\r
785 #define __CMSIS_GCC_USE_REG(r) "l" (r)
\r
787 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
\r
788 #define __CMSIS_GCC_RW_REG(r) "+r" (r)
\r
789 #define __CMSIS_GCC_USE_REG(r) "r" (r)
\r
793 \brief No Operation
\r
794 \details No Operation does nothing. This instruction can be used for code alignment purposes.
\r
796 #define __NOP __builtin_arm_nop
\r
799 \brief Wait For Interrupt
\r
800 \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
\r
802 #define __WFI __builtin_arm_wfi
\r
806 \brief Wait For Event
\r
807 \details Wait For Event is a hint instruction that permits the processor to enter
\r
808 a low-power state until one of a number of events occurs.
\r
810 #define __WFE __builtin_arm_wfe
\r
815 \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
\r
817 #define __SEV __builtin_arm_sev
\r
821 \brief Instruction Synchronization Barrier
\r
822 \details Instruction Synchronization Barrier flushes the pipeline in the processor,
\r
823 so that all instructions following the ISB are fetched from cache or memory,
\r
824 after the instruction has been completed.
\r
826 #define __ISB() __builtin_arm_isb(0xF)
\r
829 \brief Data Synchronization Barrier
\r
830 \details Acts as a special kind of Data Memory Barrier.
\r
831 It completes when all explicit memory accesses before this instruction complete.
\r
833 #define __DSB() __builtin_arm_dsb(0xF)
\r
837 \brief Data Memory Barrier
\r
838 \details Ensures the apparent order of the explicit memory operations before
\r
839 and after the instruction, without ensuring their completion.
\r
841 #define __DMB() __builtin_arm_dmb(0xF)
\r
845 \brief Reverse byte order (32 bit)
\r
846 \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
\r
847 \param [in] value Value to reverse
\r
848 \return Reversed value
\r
850 #define __REV(value) __builtin_bswap32(value)
\r
854 \brief Reverse byte order (16 bit)
\r
855 \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
\r
856 \param [in] value Value to reverse
\r
857 \return Reversed value
\r
859 #define __REV16(value) __ROR(__REV(value), 16)
\r
863 \brief Reverse byte order (16 bit)
\r
864 \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
\r
865 \param [in] value Value to reverse
\r
866 \return Reversed value
\r
868 #define __REVSH(value) (int16_t)__builtin_bswap16(value)
\r
872 \brief Rotate Right in unsigned value (32 bit)
\r
873 \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\r
874 \param [in] op1 Value to rotate
\r
875 \param [in] op2 Number of Bits to rotate
\r
876 \return Rotated value
\r
878 __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
\r
885 return (op1 >> op2) | (op1 << (32U - op2));
\r
891 \details Causes the processor to enter Debug state.
\r
892 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\r
893 \param [in] value is ignored by the processor.
\r
894 If required, a debugger can use it to store additional information about the breakpoint.
\r
896 #define __BKPT(value) __ASM volatile ("bkpt "#value)
\r
900 \brief Reverse bit order of value
\r
901 \details Reverses the bit order of the given value.
\r
902 \param [in] value Value to reverse
\r
903 \return Reversed value
\r
905 #define __RBIT __builtin_arm_rbit
\r
908 \brief Count leading zeros
\r
909 \details Counts the number of leading zeros of a data value.
\r
910 \param [in] value Value to count the leading zeros
\r
911 \return number of leading zeros in value
\r
913 __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
\r
915 /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
\r
916 __builtin_clz(0) is undefined behaviour, so handle this case specially.
\r
917 This guarantees ARM-compatible results if happening to compile on a non-ARM
\r
918 target, and ensures the compiler doesn't decide to activate any
\r
919 optimisations using the logic "value was passed to __builtin_clz, so it
\r
921 ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
\r
922 single CLZ instruction.
\r
928 return __builtin_clz(value);
\r
932 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
\r
933 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
\r
934 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
\r
935 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
\r
937 \brief LDR Exclusive (8 bit)
\r
938 \details Executes a exclusive LDR instruction for 8 bit value.
\r
939 \param [in] ptr Pointer to data
\r
940 \return value of type uint8_t at (*ptr)
\r
942 #define __LDREXB (uint8_t)__builtin_arm_ldrex
\r
946 \brief LDR Exclusive (16 bit)
\r
947 \details Executes a exclusive LDR instruction for 16 bit values.
\r
948 \param [in] ptr Pointer to data
\r
949 \return value of type uint16_t at (*ptr)
\r
951 #define __LDREXH (uint16_t)__builtin_arm_ldrex
\r
955 \brief LDR Exclusive (32 bit)
\r
956 \details Executes a exclusive LDR instruction for 32 bit values.
\r
957 \param [in] ptr Pointer to data
\r
958 \return value of type uint32_t at (*ptr)
\r
960 #define __LDREXW (uint32_t)__builtin_arm_ldrex
\r
964 \brief STR Exclusive (8 bit)
\r
965 \details Executes a exclusive STR instruction for 8 bit values.
\r
966 \param [in] value Value to store
\r
967 \param [in] ptr Pointer to location
\r
968 \return 0 Function succeeded
\r
969 \return 1 Function failed
\r
971 #define __STREXB (uint32_t)__builtin_arm_strex
\r
975 \brief STR Exclusive (16 bit)
\r
976 \details Executes a exclusive STR instruction for 16 bit values.
\r
977 \param [in] value Value to store
\r
978 \param [in] ptr Pointer to location
\r
979 \return 0 Function succeeded
\r
980 \return 1 Function failed
\r
982 #define __STREXH (uint32_t)__builtin_arm_strex
\r
986 \brief STR Exclusive (32 bit)
\r
987 \details Executes a exclusive STR instruction for 32 bit values.
\r
988 \param [in] value Value to store
\r
989 \param [in] ptr Pointer to location
\r
990 \return 0 Function succeeded
\r
991 \return 1 Function failed
\r
993 #define __STREXW (uint32_t)__builtin_arm_strex
\r
997 \brief Remove the exclusive lock
\r
998 \details Removes the exclusive lock which is created by LDREX.
\r
1000 #define __CLREX __builtin_arm_clrex
\r
1002 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
\r
1003 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
\r
1004 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
\r
1005 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
\r
1008 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
\r
1009 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
\r
1010 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
\r
1013 \brief Signed Saturate
\r
1014 \details Saturates a signed value.
\r
1015 \param [in] value Value to be saturated
\r
1016 \param [in] sat Bit position to saturate to (1..32)
\r
1017 \return Saturated value
\r
1019 #define __SSAT __builtin_arm_ssat
\r
1023 \brief Unsigned Saturate
\r
1024 \details Saturates an unsigned value.
\r
1025 \param [in] value Value to be saturated
\r
1026 \param [in] sat Bit position to saturate to (0..31)
\r
1027 \return Saturated value
\r
1029 #define __USAT __builtin_arm_usat
\r
1033 \brief Rotate Right with Extend (32 bit)
\r
1034 \details Moves each bit of a bitstring right by one bit.
\r
1035 The carry input is shifted in at the left end of the bitstring.
\r
1036 \param [in] value Value to rotate
\r
1037 \return Rotated value
\r
1039 __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
\r
1043 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
\r
1049 \brief LDRT Unprivileged (8 bit)
\r
1050 \details Executes a Unprivileged LDRT instruction for 8 bit value.
\r
1051 \param [in] ptr Pointer to data
\r
1052 \return value of type uint8_t at (*ptr)
\r
1054 __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
\r
1058 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
\r
1059 return ((uint8_t) result); /* Add explicit type cast here */
\r
1064 \brief LDRT Unprivileged (16 bit)
\r
1065 \details Executes a Unprivileged LDRT instruction for 16 bit values.
\r
1066 \param [in] ptr Pointer to data
\r
1067 \return value of type uint16_t at (*ptr)
\r
1069 __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
\r
1073 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
\r
1074 return ((uint16_t) result); /* Add explicit type cast here */
\r
1079 \brief LDRT Unprivileged (32 bit)
\r
1080 \details Executes a Unprivileged LDRT instruction for 32 bit values.
\r
1081 \param [in] ptr Pointer to data
\r
1082 \return value of type uint32_t at (*ptr)
\r
1084 __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
\r
1088 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
\r
1094 \brief STRT Unprivileged (8 bit)
\r
1095 \details Executes a Unprivileged STRT instruction for 8 bit values.
\r
1096 \param [in] value Value to store
\r
1097 \param [in] ptr Pointer to location
\r
1099 __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
\r
1101 __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
\r
1106 \brief STRT Unprivileged (16 bit)
\r
1107 \details Executes a Unprivileged STRT instruction for 16 bit values.
\r
1108 \param [in] value Value to store
\r
1109 \param [in] ptr Pointer to location
\r
1111 __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
\r
1113 __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
\r
1118 \brief STRT Unprivileged (32 bit)
\r
1119 \details Executes a Unprivileged STRT instruction for 32 bit values.
\r
1120 \param [in] value Value to store
\r
1121 \param [in] ptr Pointer to location
\r
1123 __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
\r
1125 __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
\r
1128 #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
\r
1129 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
\r
1130 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
\r
1133 \brief Signed Saturate
\r
1134 \details Saturates a signed value.
\r
1135 \param [in] value Value to be saturated
\r
1136 \param [in] sat Bit position to saturate to (1..32)
\r
1137 \return Saturated value
\r
1139 __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
\r
1141 if ((sat >= 1U) && (sat <= 32U))
\r
1143 const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
\r
1144 const int32_t min = -1 - max ;
\r
1149 else if (val < min)
\r
1158 \brief Unsigned Saturate
\r
1159 \details Saturates an unsigned value.
\r
1160 \param [in] value Value to be saturated
\r
1161 \param [in] sat Bit position to saturate to (0..31)
\r
1162 \return Saturated value
\r
1164 __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
\r
1168 const uint32_t max = ((1U << sat) - 1U);
\r
1169 if (val > (int32_t)max)
\r
1178 return (uint32_t)val;
\r
1181 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
\r
1182 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
\r
1183 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
\r
1186 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
\r
1187 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
\r
1189 \brief Load-Acquire (8 bit)
\r
1190 \details Executes a LDAB instruction for 8 bit value.
\r
1191 \param [in] ptr Pointer to data
\r
1192 \return value of type uint8_t at (*ptr)
\r
1194 __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
\r
1198 __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
\r
1199 return ((uint8_t) result);
\r
1204 \brief Load-Acquire (16 bit)
\r
1205 \details Executes a LDAH instruction for 16 bit values.
\r
1206 \param [in] ptr Pointer to data
\r
1207 \return value of type uint16_t at (*ptr)
\r
1209 __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
\r
1213 __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
\r
1214 return ((uint16_t) result);
\r
1219 \brief Load-Acquire (32 bit)
\r
1220 \details Executes a LDA instruction for 32 bit values.
\r
1221 \param [in] ptr Pointer to data
\r
1222 \return value of type uint32_t at (*ptr)
\r
1224 __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
\r
1228 __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
\r
1234 \brief Store-Release (8 bit)
\r
1235 \details Executes a STLB instruction for 8 bit values.
\r
1236 \param [in] value Value to store
\r
1237 \param [in] ptr Pointer to location
\r
1239 __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
\r
1241 __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
\r
1246 \brief Store-Release (16 bit)
\r
1247 \details Executes a STLH instruction for 16 bit values.
\r
1248 \param [in] value Value to store
\r
1249 \param [in] ptr Pointer to location
\r
1251 __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
\r
1253 __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
\r
1258 \brief Store-Release (32 bit)
\r
1259 \details Executes a STL instruction for 32 bit values.
\r
1260 \param [in] value Value to store
\r
1261 \param [in] ptr Pointer to location
\r
1263 __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
\r
1265 __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
\r
1270 \brief Load-Acquire Exclusive (8 bit)
\r
1271 \details Executes a LDAB exclusive instruction for 8 bit value.
\r
1272 \param [in] ptr Pointer to data
\r
1273 \return value of type uint8_t at (*ptr)
\r
1275 #define __LDAEXB (uint8_t)__builtin_arm_ldaex
\r
1279 \brief Load-Acquire Exclusive (16 bit)
\r
1280 \details Executes a LDAH exclusive instruction for 16 bit values.
\r
1281 \param [in] ptr Pointer to data
\r
1282 \return value of type uint16_t at (*ptr)
\r
1284 #define __LDAEXH (uint16_t)__builtin_arm_ldaex
\r
1288 \brief Load-Acquire Exclusive (32 bit)
\r
1289 \details Executes a LDA exclusive instruction for 32 bit values.
\r
1290 \param [in] ptr Pointer to data
\r
1291 \return value of type uint32_t at (*ptr)
\r
1293 #define __LDAEX (uint32_t)__builtin_arm_ldaex
\r
1297 \brief Store-Release Exclusive (8 bit)
\r
1298 \details Executes a STLB exclusive instruction for 8 bit values.
\r
1299 \param [in] value Value to store
\r
1300 \param [in] ptr Pointer to location
\r
1301 \return 0 Function succeeded
\r
1302 \return 1 Function failed
\r
1304 #define __STLEXB (uint32_t)__builtin_arm_stlex
\r
1308 \brief Store-Release Exclusive (16 bit)
\r
1309 \details Executes a STLH exclusive instruction for 16 bit values.
\r
1310 \param [in] value Value to store
\r
1311 \param [in] ptr Pointer to location
\r
1312 \return 0 Function succeeded
\r
1313 \return 1 Function failed
\r
1315 #define __STLEXH (uint32_t)__builtin_arm_stlex
\r
1319 \brief Store-Release Exclusive (32 bit)
\r
1320 \details Executes a STL exclusive instruction for 32 bit values.
\r
1321 \param [in] value Value to store
\r
1322 \param [in] ptr Pointer to location
\r
1323 \return 0 Function succeeded
\r
1324 \return 1 Function failed
\r
1326 #define __STLEX (uint32_t)__builtin_arm_stlex
\r
1328 #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
\r
1329 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
\r
1331 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
\r
1334 /* ################### Compiler specific Intrinsics ########################### */
\r
1335 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
\r
1336 Access to dedicated SIMD instructions
\r
1340 #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
\r
1342 #define __SADD8 __builtin_arm_sadd8
\r
1343 #define __QADD8 __builtin_arm_qadd8
\r
1344 #define __SHADD8 __builtin_arm_shadd8
\r
1345 #define __UADD8 __builtin_arm_uadd8
\r
1346 #define __UQADD8 __builtin_arm_uqadd8
\r
1347 #define __UHADD8 __builtin_arm_uhadd8
\r
1348 #define __SSUB8 __builtin_arm_ssub8
\r
1349 #define __QSUB8 __builtin_arm_qsub8
\r
1350 #define __SHSUB8 __builtin_arm_shsub8
\r
1351 #define __USUB8 __builtin_arm_usub8
\r
1352 #define __UQSUB8 __builtin_arm_uqsub8
\r
1353 #define __UHSUB8 __builtin_arm_uhsub8
\r
1354 #define __SADD16 __builtin_arm_sadd16
\r
1355 #define __QADD16 __builtin_arm_qadd16
\r
1356 #define __SHADD16 __builtin_arm_shadd16
\r
1357 #define __UADD16 __builtin_arm_uadd16
\r
1358 #define __UQADD16 __builtin_arm_uqadd16
\r
1359 #define __UHADD16 __builtin_arm_uhadd16
\r
1360 #define __SSUB16 __builtin_arm_ssub16
\r
1361 #define __QSUB16 __builtin_arm_qsub16
\r
1362 #define __SHSUB16 __builtin_arm_shsub16
\r
1363 #define __USUB16 __builtin_arm_usub16
\r
1364 #define __UQSUB16 __builtin_arm_uqsub16
\r
1365 #define __UHSUB16 __builtin_arm_uhsub16
\r
1366 #define __SASX __builtin_arm_sasx
\r
1367 #define __QASX __builtin_arm_qasx
\r
1368 #define __SHASX __builtin_arm_shasx
\r
1369 #define __UASX __builtin_arm_uasx
\r
1370 #define __UQASX __builtin_arm_uqasx
\r
1371 #define __UHASX __builtin_arm_uhasx
\r
1372 #define __SSAX __builtin_arm_ssax
\r
1373 #define __QSAX __builtin_arm_qsax
\r
1374 #define __SHSAX __builtin_arm_shsax
\r
1375 #define __USAX __builtin_arm_usax
\r
1376 #define __UQSAX __builtin_arm_uqsax
\r
1377 #define __UHSAX __builtin_arm_uhsax
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1378 #define __USAD8 __builtin_arm_usad8
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1379 #define __USADA8 __builtin_arm_usada8
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1380 #define __SSAT16 __builtin_arm_ssat16
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1381 #define __USAT16 __builtin_arm_usat16
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1382 #define __UXTB16 __builtin_arm_uxtb16
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1383 #define __UXTAB16 __builtin_arm_uxtab16
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1384 #define __SXTB16 __builtin_arm_sxtb16
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1385 #define __SXTAB16 __builtin_arm_sxtab16
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1386 #define __SMUAD __builtin_arm_smuad
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1387 #define __SMUADX __builtin_arm_smuadx
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1388 #define __SMLAD __builtin_arm_smlad
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1389 #define __SMLADX __builtin_arm_smladx
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1390 #define __SMLALD __builtin_arm_smlald
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1391 #define __SMLALDX __builtin_arm_smlaldx
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1392 #define __SMUSD __builtin_arm_smusd
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1393 #define __SMUSDX __builtin_arm_smusdx
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1394 #define __SMLSD __builtin_arm_smlsd
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1395 #define __SMLSDX __builtin_arm_smlsdx
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1396 #define __SMLSLD __builtin_arm_smlsld
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1397 #define __SMLSLDX __builtin_arm_smlsldx
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1398 #define __SEL __builtin_arm_sel
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1399 #define __QADD __builtin_arm_qadd
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1400 #define __QSUB __builtin_arm_qsub
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1402 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
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1403 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
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1405 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
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1406 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
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1408 __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
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1412 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
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1416 #endif /* (__ARM_FEATURE_DSP == 1) */
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1417 /*@} end of group CMSIS_SIMD_intrinsics */
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1420 #endif /* __CMSIS_ARMCLANG_H */
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