1 /**************************************************************************//**
2 * @file cmsis_armclang_ltm.h
3 * @brief CMSIS compiler armclang (Arm Compiler 6) header file
6 ******************************************************************************/
8 * Copyright (c) 2018-2019 Arm Limited. All rights reserved.
10 * SPDX-License-Identifier: Apache-2.0
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
16 * www.apache.org/licenses/LICENSE-2.0
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
25 /*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
27 #ifndef __CMSIS_ARMCLANG_H
28 #define __CMSIS_ARMCLANG_H
30 #pragma clang system_header /* treat file as system include file */
32 #ifndef __ARM_COMPAT_H
33 #include <arm_compat.h> /* Compatibility header for Arm Compiler 5 intrinsics */
36 /* CMSIS compiler specific defines */
41 #define __INLINE __inline
43 #ifndef __STATIC_INLINE
44 #define __STATIC_INLINE static __inline
46 #ifndef __STATIC_FORCEINLINE
47 #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
50 #define __NO_RETURN __attribute__((__noreturn__))
53 #define __USED __attribute__((used))
56 #define __WEAK __attribute__((weak))
59 #define __PACKED __attribute__((packed, aligned(1)))
61 #ifndef __PACKED_STRUCT
62 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
64 #ifndef __PACKED_UNION
65 #define __PACKED_UNION union __attribute__((packed, aligned(1)))
67 #ifndef __UNALIGNED_UINT32 /* deprecated */
68 #pragma clang diagnostic push
69 #pragma clang diagnostic ignored "-Wpacked"
70 /*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
71 struct __attribute__((packed)) T_UINT32 { uint32_t v; };
72 #pragma clang diagnostic pop
73 #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
75 #ifndef __UNALIGNED_UINT16_WRITE
76 #pragma clang diagnostic push
77 #pragma clang diagnostic ignored "-Wpacked"
78 /*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
79 __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
80 #pragma clang diagnostic pop
81 #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
83 #ifndef __UNALIGNED_UINT16_READ
84 #pragma clang diagnostic push
85 #pragma clang diagnostic ignored "-Wpacked"
86 /*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
87 __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
88 #pragma clang diagnostic pop
89 #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
91 #ifndef __UNALIGNED_UINT32_WRITE
92 #pragma clang diagnostic push
93 #pragma clang diagnostic ignored "-Wpacked"
94 /*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
95 __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
96 #pragma clang diagnostic pop
97 #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
99 #ifndef __UNALIGNED_UINT32_READ
100 #pragma clang diagnostic push
101 #pragma clang diagnostic ignored "-Wpacked"
102 /*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
103 __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
104 #pragma clang diagnostic pop
105 #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
108 #define __ALIGNED(x) __attribute__((aligned(x)))
111 #define __RESTRICT __restrict
115 /* ########################### Core Function Access ########################### */
116 /** \ingroup CMSIS_Core_FunctionInterface
117 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
122 \brief Enable IRQ Interrupts
123 \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
124 Can only be executed in Privileged modes.
126 /* intrinsic void __enable_irq(); see arm_compat.h */
130 \brief Disable IRQ Interrupts
131 \details Disables IRQ interrupts by setting the I-bit in the CPSR.
132 Can only be executed in Privileged modes.
134 /* intrinsic void __disable_irq(); see arm_compat.h */
138 \brief Get Control Register
139 \details Returns the content of the Control Register.
140 \return Control Register value
142 __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
146 __ASM volatile ("MRS %0, control" : "=r" (result) );
151 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
153 \brief Get Control Register (non-secure)
154 \details Returns the content of the non-secure Control Register when in secure mode.
155 \return non-secure Control Register value
157 __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
161 __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
168 \brief Set Control Register
169 \details Writes the given value to the Control Register.
170 \param [in] control Control Register value to set
172 __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
174 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
178 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
180 \brief Set Control Register (non-secure)
181 \details Writes the given value to the non-secure Control Register when in secure state.
182 \param [in] control Control Register value to set
184 __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
186 __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
192 \brief Get IPSR Register
193 \details Returns the content of the IPSR Register.
194 \return IPSR Register value
196 __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
200 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
206 \brief Get APSR Register
207 \details Returns the content of the APSR Register.
208 \return APSR Register value
210 __STATIC_FORCEINLINE uint32_t __get_APSR(void)
214 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
220 \brief Get xPSR Register
221 \details Returns the content of the xPSR Register.
222 \return xPSR Register value
224 __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
228 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
234 \brief Get Process Stack Pointer
235 \details Returns the current value of the Process Stack Pointer (PSP).
236 \return PSP Register value
238 __STATIC_FORCEINLINE uint32_t __get_PSP(void)
242 __ASM volatile ("MRS %0, psp" : "=r" (result) );
247 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
249 \brief Get Process Stack Pointer (non-secure)
250 \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
251 \return PSP Register value
253 __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
257 __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
264 \brief Set Process Stack Pointer
265 \details Assigns the given value to the Process Stack Pointer (PSP).
266 \param [in] topOfProcStack Process Stack Pointer value to set
268 __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
270 __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
274 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
276 \brief Set Process Stack Pointer (non-secure)
277 \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
278 \param [in] topOfProcStack Process Stack Pointer value to set
280 __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
282 __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
288 \brief Get Main Stack Pointer
289 \details Returns the current value of the Main Stack Pointer (MSP).
290 \return MSP Register value
292 __STATIC_FORCEINLINE uint32_t __get_MSP(void)
296 __ASM volatile ("MRS %0, msp" : "=r" (result) );
301 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
303 \brief Get Main Stack Pointer (non-secure)
304 \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
305 \return MSP Register value
307 __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
311 __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
318 \brief Set Main Stack Pointer
319 \details Assigns the given value to the Main Stack Pointer (MSP).
320 \param [in] topOfMainStack Main Stack Pointer value to set
322 __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
324 __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
328 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
330 \brief Set Main Stack Pointer (non-secure)
331 \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
332 \param [in] topOfMainStack Main Stack Pointer value to set
334 __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
336 __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
341 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
343 \brief Get Stack Pointer (non-secure)
344 \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
345 \return SP Register value
347 __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
351 __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
357 \brief Set Stack Pointer (non-secure)
358 \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
359 \param [in] topOfStack Stack Pointer value to set
361 __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
363 __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
369 \brief Get Priority Mask
370 \details Returns the current state of the priority mask bit from the Priority Mask Register.
371 \return Priority Mask value
373 __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
377 __ASM volatile ("MRS %0, primask" : "=r" (result) );
382 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
384 \brief Get Priority Mask (non-secure)
385 \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
386 \return Priority Mask value
388 __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
392 __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
399 \brief Set Priority Mask
400 \details Assigns the given value to the Priority Mask Register.
401 \param [in] priMask Priority Mask
403 __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
405 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
409 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
411 \brief Set Priority Mask (non-secure)
412 \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
413 \param [in] priMask Priority Mask
415 __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
417 __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
422 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
423 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
424 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
427 \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
428 Can only be executed in Privileged modes.
430 #define __enable_fault_irq __enable_fiq /* see arm_compat.h */
435 \details Disables FIQ interrupts by setting the F-bit in the CPSR.
436 Can only be executed in Privileged modes.
438 #define __disable_fault_irq __disable_fiq /* see arm_compat.h */
442 \brief Get Base Priority
443 \details Returns the current value of the Base Priority register.
444 \return Base Priority register value
446 __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
450 __ASM volatile ("MRS %0, basepri" : "=r" (result) );
455 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
457 \brief Get Base Priority (non-secure)
458 \details Returns the current value of the non-secure Base Priority register when in secure state.
459 \return Base Priority register value
461 __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
465 __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
472 \brief Set Base Priority
473 \details Assigns the given value to the Base Priority register.
474 \param [in] basePri Base Priority value to set
476 __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
478 __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
482 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
484 \brief Set Base Priority (non-secure)
485 \details Assigns the given value to the non-secure Base Priority register when in secure state.
486 \param [in] basePri Base Priority value to set
488 __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
490 __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
496 \brief Set Base Priority with condition
497 \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
498 or the new value increases the BASEPRI priority level.
499 \param [in] basePri Base Priority value to set
501 __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
503 __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
508 \brief Get Fault Mask
509 \details Returns the current value of the Fault Mask register.
510 \return Fault Mask register value
512 __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
516 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
521 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
523 \brief Get Fault Mask (non-secure)
524 \details Returns the current value of the non-secure Fault Mask register when in secure state.
525 \return Fault Mask register value
527 __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
531 __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
538 \brief Set Fault Mask
539 \details Assigns the given value to the Fault Mask register.
540 \param [in] faultMask Fault Mask value to set
542 __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
544 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
548 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
550 \brief Set Fault Mask (non-secure)
551 \details Assigns the given value to the non-secure Fault Mask register when in secure state.
552 \param [in] faultMask Fault Mask value to set
554 __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
556 __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
560 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
561 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
562 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
565 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
566 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
569 \brief Get Process Stack Pointer Limit
570 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
571 Stack Pointer Limit register hence zero is returned always in non-secure
574 \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
575 \return PSPLIM Register value
577 __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
579 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
580 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
581 // without main extensions, the non-secure PSPLIM is RAZ/WI
585 __ASM volatile ("MRS %0, psplim" : "=r" (result) );
590 #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
592 \brief Get Process Stack Pointer Limit (non-secure)
593 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
594 Stack Pointer Limit register hence zero is returned always in non-secure
597 \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
598 \return PSPLIM Register value
600 __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
602 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
603 // without main extensions, the non-secure PSPLIM is RAZ/WI
607 __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
615 \brief Set Process Stack Pointer Limit
616 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
617 Stack Pointer Limit register hence the write is silently ignored in non-secure
620 \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
621 \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
623 __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
625 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
626 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
627 // without main extensions, the non-secure PSPLIM is RAZ/WI
628 (void)ProcStackPtrLimit;
630 __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
635 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
637 \brief Set Process Stack Pointer (non-secure)
638 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
639 Stack Pointer Limit register hence the write is silently ignored in non-secure
642 \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
643 \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
645 __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
647 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
648 // without main extensions, the non-secure PSPLIM is RAZ/WI
649 (void)ProcStackPtrLimit;
651 __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
658 \brief Get Main Stack Pointer Limit
659 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
660 Stack Pointer Limit register hence zero is returned always.
662 \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
663 \return MSPLIM Register value
665 __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
667 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
668 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
669 // without main extensions, the non-secure MSPLIM is RAZ/WI
673 __ASM volatile ("MRS %0, msplim" : "=r" (result) );
679 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
681 \brief Get Main Stack Pointer Limit (non-secure)
682 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
683 Stack Pointer Limit register hence zero is returned always.
685 \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
686 \return MSPLIM Register value
688 __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
690 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
691 // without main extensions, the non-secure MSPLIM is RAZ/WI
695 __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
703 \brief Set Main Stack Pointer Limit
704 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
705 Stack Pointer Limit register hence the write is silently ignored.
707 \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
708 \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
710 __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
712 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
713 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
714 // without main extensions, the non-secure MSPLIM is RAZ/WI
715 (void)MainStackPtrLimit;
717 __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
722 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
724 \brief Set Main Stack Pointer Limit (non-secure)
725 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
726 Stack Pointer Limit register hence the write is silently ignored.
728 \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
729 \param [in] MainStackPtrLimit Main Stack Pointer value to set
731 __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
733 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
734 // without main extensions, the non-secure MSPLIM is RAZ/WI
735 (void)MainStackPtrLimit;
737 __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
742 #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
743 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
747 \details Returns the current value of the Floating Point Status/Control register.
748 \return Floating Point Status/Control register value
750 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
751 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
752 #define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr
754 #define __get_FPSCR() ((uint32_t)0U)
759 \details Assigns the given value to the Floating Point Status/Control register.
760 \param [in] fpscr Floating Point Status/Control value to set
762 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
763 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
764 #define __set_FPSCR __builtin_arm_set_fpscr
766 #define __set_FPSCR(x) ((void)(x))
770 /*@} end of CMSIS_Core_RegAccFunctions */
773 /* ########################## Core Instruction Access ######################### */
774 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
775 Access to dedicated instructions
779 /* Define macros for porting to both thumb1 and thumb2.
780 * For thumb1, use low register (r0-r7), specified by constraint "l"
781 * Otherwise, use general registers, specified by constraint "r" */
782 #if defined (__thumb__) && !defined (__thumb2__)
783 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
784 #define __CMSIS_GCC_USE_REG(r) "l" (r)
786 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
787 #define __CMSIS_GCC_USE_REG(r) "r" (r)
792 \details No Operation does nothing. This instruction can be used for code alignment purposes.
794 #define __NOP __builtin_arm_nop
797 \brief Wait For Interrupt
798 \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
800 #define __WFI __builtin_arm_wfi
804 \brief Wait For Event
805 \details Wait For Event is a hint instruction that permits the processor to enter
806 a low-power state until one of a number of events occurs.
808 #define __WFE __builtin_arm_wfe
813 \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
815 #define __SEV __builtin_arm_sev
819 \brief Instruction Synchronization Barrier
820 \details Instruction Synchronization Barrier flushes the pipeline in the processor,
821 so that all instructions following the ISB are fetched from cache or memory,
822 after the instruction has been completed.
824 #define __ISB() __builtin_arm_isb(0xF)
827 \brief Data Synchronization Barrier
828 \details Acts as a special kind of Data Memory Barrier.
829 It completes when all explicit memory accesses before this instruction complete.
831 #define __DSB() __builtin_arm_dsb(0xF)
835 \brief Data Memory Barrier
836 \details Ensures the apparent order of the explicit memory operations before
837 and after the instruction, without ensuring their completion.
839 #define __DMB() __builtin_arm_dmb(0xF)
843 \brief Reverse byte order (32 bit)
844 \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
845 \param [in] value Value to reverse
846 \return Reversed value
848 #define __REV(value) __builtin_bswap32(value)
852 \brief Reverse byte order (16 bit)
853 \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
854 \param [in] value Value to reverse
855 \return Reversed value
857 #define __REV16(value) __ROR(__REV(value), 16)
861 \brief Reverse byte order (16 bit)
862 \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
863 \param [in] value Value to reverse
864 \return Reversed value
866 #define __REVSH(value) (int16_t)__builtin_bswap16(value)
870 \brief Rotate Right in unsigned value (32 bit)
871 \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
872 \param [in] op1 Value to rotate
873 \param [in] op2 Number of Bits to rotate
874 \return Rotated value
876 __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
883 return (op1 >> op2) | (op1 << (32U - op2));
889 \details Causes the processor to enter Debug state.
890 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
891 \param [in] value is ignored by the processor.
892 If required, a debugger can use it to store additional information about the breakpoint.
894 #define __BKPT(value) __ASM volatile ("bkpt "#value)
898 \brief Reverse bit order of value
899 \details Reverses the bit order of the given value.
900 \param [in] value Value to reverse
901 \return Reversed value
903 #define __RBIT __builtin_arm_rbit
906 \brief Count leading zeros
907 \details Counts the number of leading zeros of a data value.
908 \param [in] value Value to count the leading zeros
909 \return number of leading zeros in value
911 __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
913 /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
914 __builtin_clz(0) is undefined behaviour, so handle this case specially.
915 This guarantees ARM-compatible results if happening to compile on a non-ARM
916 target, and ensures the compiler doesn't decide to activate any
917 optimisations using the logic "value was passed to __builtin_clz, so it
919 ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
920 single CLZ instruction.
926 return __builtin_clz(value);
930 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
931 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
932 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
933 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
935 \brief LDR Exclusive (8 bit)
936 \details Executes a exclusive LDR instruction for 8 bit value.
937 \param [in] ptr Pointer to data
938 \return value of type uint8_t at (*ptr)
940 #define __LDREXB (uint8_t)__builtin_arm_ldrex
944 \brief LDR Exclusive (16 bit)
945 \details Executes a exclusive LDR instruction for 16 bit values.
946 \param [in] ptr Pointer to data
947 \return value of type uint16_t at (*ptr)
949 #define __LDREXH (uint16_t)__builtin_arm_ldrex
953 \brief LDR Exclusive (32 bit)
954 \details Executes a exclusive LDR instruction for 32 bit values.
955 \param [in] ptr Pointer to data
956 \return value of type uint32_t at (*ptr)
958 #define __LDREXW (uint32_t)__builtin_arm_ldrex
962 \brief STR Exclusive (8 bit)
963 \details Executes a exclusive STR instruction for 8 bit values.
964 \param [in] value Value to store
965 \param [in] ptr Pointer to location
966 \return 0 Function succeeded
967 \return 1 Function failed
969 #define __STREXB (uint32_t)__builtin_arm_strex
973 \brief STR Exclusive (16 bit)
974 \details Executes a exclusive STR instruction for 16 bit values.
975 \param [in] value Value to store
976 \param [in] ptr Pointer to location
977 \return 0 Function succeeded
978 \return 1 Function failed
980 #define __STREXH (uint32_t)__builtin_arm_strex
984 \brief STR Exclusive (32 bit)
985 \details Executes a exclusive STR instruction for 32 bit values.
986 \param [in] value Value to store
987 \param [in] ptr Pointer to location
988 \return 0 Function succeeded
989 \return 1 Function failed
991 #define __STREXW (uint32_t)__builtin_arm_strex
995 \brief Remove the exclusive lock
996 \details Removes the exclusive lock which is created by LDREX.
998 #define __CLREX __builtin_arm_clrex
1000 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
1001 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
1002 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1003 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
1006 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
1007 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
1008 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
1011 \brief Signed Saturate
1012 \details Saturates a signed value.
1013 \param [in] value Value to be saturated
1014 \param [in] sat Bit position to saturate to (1..32)
1015 \return Saturated value
1017 #define __SSAT __builtin_arm_ssat
1021 \brief Unsigned Saturate
1022 \details Saturates an unsigned value.
1023 \param [in] value Value to be saturated
1024 \param [in] sat Bit position to saturate to (0..31)
1025 \return Saturated value
1027 #define __USAT __builtin_arm_usat
1031 \brief Rotate Right with Extend (32 bit)
1032 \details Moves each bit of a bitstring right by one bit.
1033 The carry input is shifted in at the left end of the bitstring.
1034 \param [in] value Value to rotate
1035 \return Rotated value
1037 __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
1041 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
1047 \brief LDRT Unprivileged (8 bit)
1048 \details Executes a Unprivileged LDRT instruction for 8 bit value.
1049 \param [in] ptr Pointer to data
1050 \return value of type uint8_t at (*ptr)
1052 __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
1056 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
1057 return ((uint8_t) result); /* Add explicit type cast here */
1062 \brief LDRT Unprivileged (16 bit)
1063 \details Executes a Unprivileged LDRT instruction for 16 bit values.
1064 \param [in] ptr Pointer to data
1065 \return value of type uint16_t at (*ptr)
1067 __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
1071 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
1072 return ((uint16_t) result); /* Add explicit type cast here */
1077 \brief LDRT Unprivileged (32 bit)
1078 \details Executes a Unprivileged LDRT instruction for 32 bit values.
1079 \param [in] ptr Pointer to data
1080 \return value of type uint32_t at (*ptr)
1082 __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
1086 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
1092 \brief STRT Unprivileged (8 bit)
1093 \details Executes a Unprivileged STRT instruction for 8 bit values.
1094 \param [in] value Value to store
1095 \param [in] ptr Pointer to location
1097 __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
1099 __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
1104 \brief STRT Unprivileged (16 bit)
1105 \details Executes a Unprivileged STRT instruction for 16 bit values.
1106 \param [in] value Value to store
1107 \param [in] ptr Pointer to location
1109 __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
1111 __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
1116 \brief STRT Unprivileged (32 bit)
1117 \details Executes a Unprivileged STRT instruction for 32 bit values.
1118 \param [in] value Value to store
1119 \param [in] ptr Pointer to location
1121 __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
1123 __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
1126 #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
1127 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
1128 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
1131 \brief Signed Saturate
1132 \details Saturates a signed value.
1133 \param [in] value Value to be saturated
1134 \param [in] sat Bit position to saturate to (1..32)
1135 \return Saturated value
1137 __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
1139 if ((sat >= 1U) && (sat <= 32U))
1141 const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
1142 const int32_t min = -1 - max ;
1156 \brief Unsigned Saturate
1157 \details Saturates an unsigned value.
1158 \param [in] value Value to be saturated
1159 \param [in] sat Bit position to saturate to (0..31)
1160 \return Saturated value
1162 __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
1166 const uint32_t max = ((1U << sat) - 1U);
1167 if (val > (int32_t)max)
1176 return (uint32_t)val;
1179 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
1180 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
1181 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
1184 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1185 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
1187 \brief Load-Acquire (8 bit)
1188 \details Executes a LDAB instruction for 8 bit value.
1189 \param [in] ptr Pointer to data
1190 \return value of type uint8_t at (*ptr)
1192 __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
1196 __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
1197 return ((uint8_t) result);
1202 \brief Load-Acquire (16 bit)
1203 \details Executes a LDAH instruction for 16 bit values.
1204 \param [in] ptr Pointer to data
1205 \return value of type uint16_t at (*ptr)
1207 __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
1211 __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
1212 return ((uint16_t) result);
1217 \brief Load-Acquire (32 bit)
1218 \details Executes a LDA instruction for 32 bit values.
1219 \param [in] ptr Pointer to data
1220 \return value of type uint32_t at (*ptr)
1222 __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
1226 __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
1232 \brief Store-Release (8 bit)
1233 \details Executes a STLB instruction for 8 bit values.
1234 \param [in] value Value to store
1235 \param [in] ptr Pointer to location
1237 __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
1239 __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
1244 \brief Store-Release (16 bit)
1245 \details Executes a STLH instruction for 16 bit values.
1246 \param [in] value Value to store
1247 \param [in] ptr Pointer to location
1249 __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
1251 __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
1256 \brief Store-Release (32 bit)
1257 \details Executes a STL instruction for 32 bit values.
1258 \param [in] value Value to store
1259 \param [in] ptr Pointer to location
1261 __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
1263 __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
1268 \brief Load-Acquire Exclusive (8 bit)
1269 \details Executes a LDAB exclusive instruction for 8 bit value.
1270 \param [in] ptr Pointer to data
1271 \return value of type uint8_t at (*ptr)
1273 #define __LDAEXB (uint8_t)__builtin_arm_ldaex
1277 \brief Load-Acquire Exclusive (16 bit)
1278 \details Executes a LDAH exclusive instruction for 16 bit values.
1279 \param [in] ptr Pointer to data
1280 \return value of type uint16_t at (*ptr)
1282 #define __LDAEXH (uint16_t)__builtin_arm_ldaex
1286 \brief Load-Acquire Exclusive (32 bit)
1287 \details Executes a LDA exclusive instruction for 32 bit values.
1288 \param [in] ptr Pointer to data
1289 \return value of type uint32_t at (*ptr)
1291 #define __LDAEX (uint32_t)__builtin_arm_ldaex
1295 \brief Store-Release Exclusive (8 bit)
1296 \details Executes a STLB exclusive instruction for 8 bit values.
1297 \param [in] value Value to store
1298 \param [in] ptr Pointer to location
1299 \return 0 Function succeeded
1300 \return 1 Function failed
1302 #define __STLEXB (uint32_t)__builtin_arm_stlex
1306 \brief Store-Release Exclusive (16 bit)
1307 \details Executes a STLH exclusive instruction for 16 bit values.
1308 \param [in] value Value to store
1309 \param [in] ptr Pointer to location
1310 \return 0 Function succeeded
1311 \return 1 Function failed
1313 #define __STLEXH (uint32_t)__builtin_arm_stlex
1317 \brief Store-Release Exclusive (32 bit)
1318 \details Executes a STL exclusive instruction for 32 bit values.
1319 \param [in] value Value to store
1320 \param [in] ptr Pointer to location
1321 \return 0 Function succeeded
1322 \return 1 Function failed
1324 #define __STLEX (uint32_t)__builtin_arm_stlex
1326 #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1327 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
1329 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
1332 /* ################### Compiler specific Intrinsics ########################### */
1333 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
1334 Access to dedicated SIMD instructions
1338 #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
1340 __STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
1344 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1348 __STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
1352 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1356 __STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
1360 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1364 __STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
1368 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1372 __STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
1376 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1380 __STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
1384 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1389 __STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
1393 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1397 __STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
1401 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1405 __STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
1409 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1413 __STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
1417 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1421 __STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
1425 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1429 __STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
1433 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1438 __STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
1442 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1446 __STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
1450 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1454 __STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
1458 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1462 __STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
1466 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1470 __STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
1474 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1478 __STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
1482 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1486 __STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
1490 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1494 __STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
1498 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1502 __STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
1506 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1510 __STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
1514 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1518 __STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
1522 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1526 __STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
1530 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1534 __STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
1538 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1542 __STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
1546 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1550 __STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
1554 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1558 __STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
1562 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1566 __STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
1570 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1574 __STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
1578 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1582 __STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
1586 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1590 __STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
1594 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1598 __STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
1602 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1606 __STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
1610 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1614 __STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
1618 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1622 __STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
1626 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1630 __STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
1634 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1638 __STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
1642 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
1646 #define __SSAT16(ARG1,ARG2) \
1648 int32_t __RES, __ARG1 = (ARG1); \
1649 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
1653 #define __USAT16(ARG1,ARG2) \
1655 uint32_t __RES, __ARG1 = (ARG1); \
1656 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
1660 __STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
1664 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
1668 __STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
1672 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1676 __STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
1680 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
1684 __STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
1688 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1692 __STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
1696 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1700 __STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
1704 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1708 __STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
1712 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
1716 __STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
1720 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
1724 __STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
1732 #ifndef __ARMEB__ /* Little endian */
1733 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
1734 #else /* Big endian */
1735 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
1741 __STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
1749 #ifndef __ARMEB__ /* Little endian */
1750 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
1751 #else /* Big endian */
1752 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
1758 __STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
1762 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1766 __STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
1770 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1774 __STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
1778 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
1782 __STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
1786 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
1790 __STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
1798 #ifndef __ARMEB__ /* Little endian */
1799 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
1800 #else /* Big endian */
1801 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
1807 __STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
1815 #ifndef __ARMEB__ /* Little endian */
1816 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
1817 #else /* Big endian */
1818 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
1824 __STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
1828 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1832 __STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
1836 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1840 __STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
1844 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1848 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
1849 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
1851 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
1852 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
1854 __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
1858 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
1862 #endif /* (__ARM_FEATURE_DSP == 1) */
1863 /*@} end of group CMSIS_SIMD_intrinsics */
1866 #endif /* __CMSIS_ARMCLANG_H */