1 /**************************************************************************//**
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2 * @file core_armv8mbl.h
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3 * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File
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5 * @date 10. January 2018
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6 ******************************************************************************/
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8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
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10 * SPDX-License-Identifier: Apache-2.0
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12 * Licensed under the Apache License, Version 2.0 (the License); you may
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13 * not use this file except in compliance with the License.
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14 * You may obtain a copy of the License at
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16 * www.apache.org/licenses/LICENSE-2.0
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18 * Unless required by applicable law or agreed to in writing, software
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19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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21 * See the License for the specific language governing permissions and
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22 * limitations under the License.
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25 #if defined ( __ICCARM__ )
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26 #pragma system_include /* treat file as system include file for MISRA check */
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27 #elif defined (__clang__)
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28 #pragma clang system_header /* treat file as system include file */
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31 #ifndef __CORE_ARMV8MBL_H_GENERIC
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32 #define __CORE_ARMV8MBL_H_GENERIC
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41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
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42 CMSIS violates the following MISRA-C:2004 rules:
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44 \li Required Rule 8.5, object/function definition in header file.<br>
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45 Function definitions in header files are used to allow 'inlining'.
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47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
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48 Unions are used for effective representation of core registers.
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50 \li Advisory Rule 19.7, Function-like macro defined.<br>
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51 Function-like macros are used to allow more efficient code.
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55 /*******************************************************************************
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57 ******************************************************************************/
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59 \ingroup Cortex_ARMv8MBL
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63 #include "cmsis_version.h"
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65 /* CMSIS definitions */
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66 #define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
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67 #define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
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68 #define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
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69 __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
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71 #define __CORTEX_M ( 2U) /*!< Cortex-M Core */
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73 /** __FPU_USED indicates whether an FPU is used or not.
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74 This core does not support an FPU at all
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76 #define __FPU_USED 0U
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78 #if defined ( __CC_ARM )
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79 #if defined __TARGET_FPU_VFP
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80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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83 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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84 #if defined __ARM_PCS_VFP
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85 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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88 #elif defined ( __GNUC__ )
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89 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
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90 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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93 #elif defined ( __ICCARM__ )
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94 #if defined __ARMVFP__
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95 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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98 #elif defined ( __TI_ARM__ )
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99 #if defined __TI_VFP_SUPPORT__
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100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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103 #elif defined ( __TASKING__ )
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104 #if defined __FPU_VFP__
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105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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108 #elif defined ( __CSMC__ )
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109 #if ( __CSMC__ & 0x400U)
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110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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115 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
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122 #endif /* __CORE_ARMV8MBL_H_GENERIC */
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124 #ifndef __CMSIS_GENERIC
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126 #ifndef __CORE_ARMV8MBL_H_DEPENDANT
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127 #define __CORE_ARMV8MBL_H_DEPENDANT
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133 /* check device defines and use defaults */
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134 #if defined __CHECK_DEVICE_DEFINES
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135 #ifndef __ARMv8MBL_REV
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136 #define __ARMv8MBL_REV 0x0000U
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137 #warning "__ARMv8MBL_REV not defined in device header file; using default!"
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140 #ifndef __FPU_PRESENT
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141 #define __FPU_PRESENT 0U
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142 #warning "__FPU_PRESENT not defined in device header file; using default!"
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145 #ifndef __MPU_PRESENT
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146 #define __MPU_PRESENT 0U
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147 #warning "__MPU_PRESENT not defined in device header file; using default!"
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150 #ifndef __SAUREGION_PRESENT
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151 #define __SAUREGION_PRESENT 0U
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152 #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
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155 #ifndef __VTOR_PRESENT
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156 #define __VTOR_PRESENT 0U
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157 #warning "__VTOR_PRESENT not defined in device header file; using default!"
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160 #ifndef __NVIC_PRIO_BITS
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161 #define __NVIC_PRIO_BITS 2U
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162 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
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165 #ifndef __Vendor_SysTickConfig
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166 #define __Vendor_SysTickConfig 0U
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167 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
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170 #ifndef __ETM_PRESENT
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171 #define __ETM_PRESENT 0U
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172 #warning "__ETM_PRESENT not defined in device header file; using default!"
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175 #ifndef __MTB_PRESENT
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176 #define __MTB_PRESENT 0U
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177 #warning "__MTB_PRESENT not defined in device header file; using default!"
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182 /* IO definitions (access restrictions to peripheral registers) */
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184 \defgroup CMSIS_glob_defs CMSIS Global Defines
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186 <strong>IO Type Qualifiers</strong> are used
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187 \li to specify the access to peripheral variables.
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188 \li for automatic generation of peripheral register debug information.
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191 #define __I volatile /*!< Defines 'read only' permissions */
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193 #define __I volatile const /*!< Defines 'read only' permissions */
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195 #define __O volatile /*!< Defines 'write only' permissions */
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196 #define __IO volatile /*!< Defines 'read / write' permissions */
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198 /* following defines should be used for structure members */
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199 #define __IM volatile const /*! Defines 'read only' structure member permissions */
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200 #define __OM volatile /*! Defines 'write only' structure member permissions */
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201 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
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203 /*@} end of group ARMv8MBL */
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207 /*******************************************************************************
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208 * Register Abstraction
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209 Core Register contain:
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211 - Core NVIC Register
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212 - Core SCB Register
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213 - Core SysTick Register
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214 - Core Debug Register
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215 - Core MPU Register
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216 - Core SAU Register
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217 ******************************************************************************/
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219 \defgroup CMSIS_core_register Defines and Type Definitions
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220 \brief Type definitions and defines for Cortex-M processor based devices.
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224 \ingroup CMSIS_core_register
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225 \defgroup CMSIS_CORE Status and Control Registers
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226 \brief Core Register type definitions.
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231 \brief Union type to access the Application Program Status Register (APSR).
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237 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
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238 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
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239 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
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240 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
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241 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
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242 } b; /*!< Structure used for bit access */
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243 uint32_t w; /*!< Type used for word access */
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246 /* APSR Register Definitions */
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247 #define APSR_N_Pos 31U /*!< APSR: N Position */
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248 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
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250 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
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251 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
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253 #define APSR_C_Pos 29U /*!< APSR: C Position */
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254 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
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256 #define APSR_V_Pos 28U /*!< APSR: V Position */
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257 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
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261 \brief Union type to access the Interrupt Program Status Register (IPSR).
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267 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
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268 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
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269 } b; /*!< Structure used for bit access */
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270 uint32_t w; /*!< Type used for word access */
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273 /* IPSR Register Definitions */
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274 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
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275 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
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279 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
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285 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
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286 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
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287 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
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288 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
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289 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
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290 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
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291 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
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292 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
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293 } b; /*!< Structure used for bit access */
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294 uint32_t w; /*!< Type used for word access */
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297 /* xPSR Register Definitions */
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298 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
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299 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
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301 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
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302 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
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304 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
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305 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
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307 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
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308 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
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310 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
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311 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
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313 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
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314 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
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318 \brief Union type to access the Control Registers (CONTROL).
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324 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
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325 uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
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326 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
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327 } b; /*!< Structure used for bit access */
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328 uint32_t w; /*!< Type used for word access */
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331 /* CONTROL Register Definitions */
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332 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
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333 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
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335 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
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336 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
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338 /*@} end of group CMSIS_CORE */
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342 \ingroup CMSIS_core_register
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343 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
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344 \brief Type definitions for the NVIC Registers
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349 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
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353 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
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354 uint32_t RESERVED0[16U];
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355 __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
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356 uint32_t RSERVED1[16U];
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357 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
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358 uint32_t RESERVED2[16U];
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359 __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
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360 uint32_t RESERVED3[16U];
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361 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
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362 uint32_t RESERVED4[16U];
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363 __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
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364 uint32_t RESERVED5[16U];
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365 __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
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368 /*@} end of group CMSIS_NVIC */
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372 \ingroup CMSIS_core_register
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373 \defgroup CMSIS_SCB System Control Block (SCB)
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374 \brief Type definitions for the System Control Block Registers
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379 \brief Structure type to access the System Control Block (SCB).
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383 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
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384 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
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385 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
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386 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
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388 uint32_t RESERVED0;
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390 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
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391 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
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392 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
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393 uint32_t RESERVED1;
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394 __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
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395 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
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398 /* SCB CPUID Register Definitions */
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399 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
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400 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
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402 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
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403 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
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405 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
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406 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
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408 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
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409 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
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411 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
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412 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
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414 /* SCB Interrupt Control State Register Definitions */
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415 #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
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416 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
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418 #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
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419 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
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421 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
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422 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
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424 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
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425 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
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427 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
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428 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
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430 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
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431 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
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433 #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
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434 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
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436 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
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437 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
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439 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
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440 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
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442 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
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443 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
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445 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
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446 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
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448 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
\r
449 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
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451 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
\r
452 /* SCB Vector Table Offset Register Definitions */
\r
453 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
\r
454 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
\r
457 /* SCB Application Interrupt and Reset Control Register Definitions */
\r
458 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
\r
459 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
\r
461 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
\r
462 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
\r
464 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
\r
465 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
\r
467 #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
\r
468 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
\r
470 #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
\r
471 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
\r
473 #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
\r
474 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
\r
476 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
\r
477 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
\r
479 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
\r
480 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
\r
482 /* SCB System Control Register Definitions */
\r
483 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
\r
484 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
\r
486 #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
\r
487 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
\r
489 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
\r
490 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
\r
492 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
\r
493 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
\r
495 /* SCB Configuration Control Register Definitions */
\r
496 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
\r
497 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
\r
499 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
\r
500 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
\r
502 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
\r
503 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
\r
505 #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
\r
506 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
\r
508 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
\r
509 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
\r
511 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
\r
512 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
\r
514 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
\r
515 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
\r
517 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
\r
518 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
\r
520 /* SCB System Handler Control and State Register Definitions */
\r
521 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
\r
522 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
\r
524 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
\r
525 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
\r
527 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
\r
528 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
\r
530 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
\r
531 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
\r
533 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
\r
534 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
\r
536 #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
\r
537 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
\r
539 #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
\r
540 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
\r
542 /*@} end of group CMSIS_SCB */
\r
546 \ingroup CMSIS_core_register
\r
547 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
\r
548 \brief Type definitions for the System Timer Registers.
\r
553 \brief Structure type to access the System Timer (SysTick).
\r
557 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
\r
558 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
\r
559 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
\r
560 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
\r
563 /* SysTick Control / Status Register Definitions */
\r
564 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
\r
565 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
\r
567 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
\r
568 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
\r
570 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
\r
571 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
\r
573 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
\r
574 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
\r
576 /* SysTick Reload Register Definitions */
\r
577 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
\r
578 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
\r
580 /* SysTick Current Register Definitions */
\r
581 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
\r
582 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
\r
584 /* SysTick Calibration Register Definitions */
\r
585 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
\r
586 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
\r
588 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
\r
589 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
\r
591 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
\r
592 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
\r
594 /*@} end of group CMSIS_SysTick */
\r
598 \ingroup CMSIS_core_register
\r
599 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
\r
600 \brief Type definitions for the Data Watchpoint and Trace (DWT)
\r
605 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
\r
609 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
\r
610 uint32_t RESERVED0[6U];
\r
611 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
\r
612 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
\r
613 uint32_t RESERVED1[1U];
\r
614 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
\r
615 uint32_t RESERVED2[1U];
\r
616 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
\r
617 uint32_t RESERVED3[1U];
\r
618 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
\r
619 uint32_t RESERVED4[1U];
\r
620 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
\r
621 uint32_t RESERVED5[1U];
\r
622 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
\r
623 uint32_t RESERVED6[1U];
\r
624 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
\r
625 uint32_t RESERVED7[1U];
\r
626 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
\r
627 uint32_t RESERVED8[1U];
\r
628 __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
\r
629 uint32_t RESERVED9[1U];
\r
630 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
\r
631 uint32_t RESERVED10[1U];
\r
632 __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
\r
633 uint32_t RESERVED11[1U];
\r
634 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
\r
635 uint32_t RESERVED12[1U];
\r
636 __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
\r
637 uint32_t RESERVED13[1U];
\r
638 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
\r
639 uint32_t RESERVED14[1U];
\r
640 __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
\r
641 uint32_t RESERVED15[1U];
\r
642 __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
\r
643 uint32_t RESERVED16[1U];
\r
644 __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
\r
645 uint32_t RESERVED17[1U];
\r
646 __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
\r
647 uint32_t RESERVED18[1U];
\r
648 __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
\r
649 uint32_t RESERVED19[1U];
\r
650 __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
\r
651 uint32_t RESERVED20[1U];
\r
652 __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
\r
653 uint32_t RESERVED21[1U];
\r
654 __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
\r
655 uint32_t RESERVED22[1U];
\r
656 __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
\r
657 uint32_t RESERVED23[1U];
\r
658 __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
\r
659 uint32_t RESERVED24[1U];
\r
660 __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
\r
661 uint32_t RESERVED25[1U];
\r
662 __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
\r
663 uint32_t RESERVED26[1U];
\r
664 __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
\r
665 uint32_t RESERVED27[1U];
\r
666 __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
\r
667 uint32_t RESERVED28[1U];
\r
668 __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
\r
669 uint32_t RESERVED29[1U];
\r
670 __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
\r
671 uint32_t RESERVED30[1U];
\r
672 __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
\r
673 uint32_t RESERVED31[1U];
\r
674 __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
\r
677 /* DWT Control Register Definitions */
\r
678 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
\r
679 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
\r
681 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
\r
682 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
\r
684 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
\r
685 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
\r
687 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
\r
688 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
\r
690 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
\r
691 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
\r
693 /* DWT Comparator Function Register Definitions */
\r
694 #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
\r
695 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
\r
697 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
\r
698 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
\r
700 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
\r
701 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
\r
703 #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
\r
704 #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
\r
706 #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
\r
707 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
\r
709 /*@}*/ /* end of group CMSIS_DWT */
\r
713 \ingroup CMSIS_core_register
\r
714 \defgroup CMSIS_TPI Trace Port Interface (TPI)
\r
715 \brief Type definitions for the Trace Port Interface (TPI)
\r
720 \brief Structure type to access the Trace Port Interface Register (TPI).
\r
724 __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
\r
725 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
\r
726 uint32_t RESERVED0[2U];
\r
727 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
\r
728 uint32_t RESERVED1[55U];
\r
729 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
\r
730 uint32_t RESERVED2[131U];
\r
731 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
\r
732 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
\r
733 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
\r
734 uint32_t RESERVED3[759U];
\r
735 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
\r
736 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
\r
737 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
\r
738 uint32_t RESERVED4[1U];
\r
739 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
\r
740 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
\r
741 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
\r
742 uint32_t RESERVED5[39U];
\r
743 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
\r
744 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
\r
745 uint32_t RESERVED7[8U];
\r
746 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
\r
747 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
\r
750 /* TPI Asynchronous Clock Prescaler Register Definitions */
\r
751 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
\r
752 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
\r
754 /* TPI Selected Pin Protocol Register Definitions */
\r
755 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
\r
756 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
\r
758 /* TPI Formatter and Flush Status Register Definitions */
\r
759 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
\r
760 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
\r
762 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
\r
763 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
\r
765 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
\r
766 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
\r
768 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
\r
769 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
\r
771 /* TPI Formatter and Flush Control Register Definitions */
\r
772 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
\r
773 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
\r
775 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
\r
776 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
\r
778 /* TPI TRIGGER Register Definitions */
\r
779 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
\r
780 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
\r
782 /* TPI Integration ETM Data Register Definitions (FIFO0) */
\r
783 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
\r
784 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
\r
786 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
\r
787 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
\r
789 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
\r
790 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
\r
792 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
\r
793 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
\r
795 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
\r
796 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
\r
798 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
\r
799 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
\r
801 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
\r
802 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
\r
804 /* TPI ITATBCTR2 Register Definitions */
\r
805 #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
\r
806 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
\r
808 /* TPI Integration ITM Data Register Definitions (FIFO1) */
\r
809 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
\r
810 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
\r
812 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
\r
813 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
\r
815 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
\r
816 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
\r
818 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
\r
819 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
\r
821 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
\r
822 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
\r
824 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
\r
825 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
\r
827 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
\r
828 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
\r
830 /* TPI ITATBCTR0 Register Definitions */
\r
831 #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
\r
832 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
\r
834 /* TPI Integration Mode Control Register Definitions */
\r
835 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
\r
836 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
\r
838 /* TPI DEVID Register Definitions */
\r
839 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
\r
840 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
\r
842 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
\r
843 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
\r
845 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
\r
846 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
\r
848 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
\r
849 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
\r
851 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
\r
852 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
\r
854 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
\r
855 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
\r
857 /* TPI DEVTYPE Register Definitions */
\r
858 #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
\r
859 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
\r
861 #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
\r
862 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
\r
864 /*@}*/ /* end of group CMSIS_TPI */
\r
867 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
\r
869 \ingroup CMSIS_core_register
\r
870 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
\r
871 \brief Type definitions for the Memory Protection Unit (MPU)
\r
876 \brief Structure type to access the Memory Protection Unit (MPU).
\r
880 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
\r
881 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
\r
882 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
\r
883 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
\r
884 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
\r
885 uint32_t RESERVED0[7U];
\r
887 __IOM uint32_t MAIR[2];
\r
889 __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
\r
890 __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
\r
895 #define MPU_TYPE_RALIASES 1U
\r
897 /* MPU Type Register Definitions */
\r
898 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
\r
899 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
\r
901 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
\r
902 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
\r
904 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
\r
905 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
\r
907 /* MPU Control Register Definitions */
\r
908 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
\r
909 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
\r
911 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
\r
912 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
\r
914 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
\r
915 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
\r
917 /* MPU Region Number Register Definitions */
\r
918 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
\r
919 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
\r
921 /* MPU Region Base Address Register Definitions */
\r
922 #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
\r
923 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
\r
925 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
\r
926 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
\r
928 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
\r
929 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
\r
931 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
\r
932 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
\r
934 /* MPU Region Limit Address Register Definitions */
\r
935 #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
\r
936 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
\r
938 #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
\r
939 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
\r
941 #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
\r
942 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
\r
944 /* MPU Memory Attribute Indirection Register 0 Definitions */
\r
945 #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
\r
946 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
\r
948 #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
\r
949 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
\r
951 #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
\r
952 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
\r
954 #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
\r
955 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
\r
957 /* MPU Memory Attribute Indirection Register 1 Definitions */
\r
958 #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
\r
959 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
\r
961 #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
\r
962 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
\r
964 #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
\r
965 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
\r
967 #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
\r
968 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
\r
970 /*@} end of group CMSIS_MPU */
\r
974 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
\r
976 \ingroup CMSIS_core_register
\r
977 \defgroup CMSIS_SAU Security Attribution Unit (SAU)
\r
978 \brief Type definitions for the Security Attribution Unit (SAU)
\r
983 \brief Structure type to access the Security Attribution Unit (SAU).
\r
987 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
\r
988 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
\r
989 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
\r
990 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
\r
991 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
\r
992 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
\r
996 /* SAU Control Register Definitions */
\r
997 #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
\r
998 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
\r
1000 #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
\r
1001 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
\r
1003 /* SAU Type Register Definitions */
\r
1004 #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
\r
1005 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
\r
1007 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
\r
1008 /* SAU Region Number Register Definitions */
\r
1009 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
\r
1010 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
\r
1012 /* SAU Region Base Address Register Definitions */
\r
1013 #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
\r
1014 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
\r
1016 /* SAU Region Limit Address Register Definitions */
\r
1017 #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
\r
1018 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
\r
1020 #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
\r
1021 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
\r
1023 #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
\r
1024 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
\r
1026 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
\r
1028 /*@} end of group CMSIS_SAU */
\r
1029 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
\r
1033 \ingroup CMSIS_core_register
\r
1034 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\r
1035 \brief Type definitions for the Core Debug Registers
\r
1040 \brief Structure type to access the Core Debug Register (CoreDebug).
\r
1044 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
\r
1045 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
\r
1046 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
\r
1047 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
\r
1048 uint32_t RESERVED4[1U];
\r
1049 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
\r
1050 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
\r
1053 /* Debug Halting Control and Status Register Definitions */
\r
1054 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
\r
1055 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
\r
1057 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
\r
1058 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
\r
1060 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
\r
1061 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
\r
1063 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
\r
1064 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
\r
1066 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
\r
1067 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
\r
1069 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
\r
1070 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
\r
1072 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
\r
1073 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
\r
1075 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
\r
1076 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
\r
1078 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
\r
1079 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
\r
1081 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
\r
1082 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
\r
1084 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
\r
1085 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
\r
1087 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
\r
1088 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
\r
1090 /* Debug Core Register Selector Register Definitions */
\r
1091 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
\r
1092 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
\r
1094 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
\r
1095 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
\r
1097 /* Debug Exception and Monitor Control Register */
\r
1098 #define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */
\r
1099 #define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */
\r
1101 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
\r
1102 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
\r
1104 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
\r
1105 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
\r
1107 /* Debug Authentication Control Register Definitions */
\r
1108 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
\r
1109 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
\r
1111 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
\r
1112 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
\r
1114 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
\r
1115 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
\r
1117 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
\r
1118 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
\r
1120 /* Debug Security Control and Status Register Definitions */
\r
1121 #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
\r
1122 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
\r
1124 #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
\r
1125 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
\r
1127 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
\r
1128 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
\r
1130 /*@} end of group CMSIS_CoreDebug */
\r
1134 \ingroup CMSIS_core_register
\r
1135 \defgroup CMSIS_core_bitfield Core register bit field macros
\r
1136 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
\r
1141 \brief Mask and shift a bit field value for use in a register bit range.
\r
1142 \param[in] field Name of the register bit field.
\r
1143 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\r
1144 \return Masked and shifted value.
\r
1146 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
\r
1149 \brief Mask and shift a register value to extract a bit filed value.
\r
1150 \param[in] field Name of the register bit field.
\r
1151 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\r
1152 \return Masked and shifted bit field value.
\r
1154 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
\r
1156 /*@} end of group CMSIS_core_bitfield */
\r
1160 \ingroup CMSIS_core_register
\r
1161 \defgroup CMSIS_core_base Core Definitions
\r
1162 \brief Definitions for base addresses, unions, and structures.
\r
1166 /* Memory mapping of Core Hardware */
\r
1167 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
\r
1168 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
\r
1169 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
\r
1170 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
\r
1171 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
\r
1172 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
\r
1173 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
\r
1176 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
\r
1177 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
\r
1178 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
\r
1179 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
\r
1180 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
\r
1181 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
\r
1183 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
\r
1184 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
\r
1185 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
\r
1188 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
\r
1189 #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
\r
1190 #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
\r
1193 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
\r
1194 #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
\r
1195 #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
\r
1196 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
\r
1197 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
\r
1198 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
\r
1200 #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
\r
1201 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
\r
1202 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
\r
1203 #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
\r
1205 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
\r
1206 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
\r
1207 #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
\r
1210 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
\r
1215 /*******************************************************************************
\r
1216 * Hardware Abstraction Layer
\r
1217 Core Function Interface contains:
\r
1218 - Core NVIC Functions
\r
1219 - Core SysTick Functions
\r
1220 - Core Register Access Functions
\r
1221 ******************************************************************************/
\r
1223 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
\r
1228 /* ########################## NVIC functions #################################### */
\r
1230 \ingroup CMSIS_Core_FunctionInterface
\r
1231 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
\r
1232 \brief Functions that manage interrupts and exceptions via the NVIC.
\r
1236 #ifdef CMSIS_NVIC_VIRTUAL
\r
1237 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
\r
1238 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
\r
1240 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
\r
1242 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Armv8-M Baseline */
\r
1243 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Armv8-M Baseline */
\r
1244 #define NVIC_EnableIRQ __NVIC_EnableIRQ
\r
1245 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
\r
1246 #define NVIC_DisableIRQ __NVIC_DisableIRQ
\r
1247 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
\r
1248 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
\r
1249 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
\r
1250 #define NVIC_GetActive __NVIC_GetActive
\r
1251 #define NVIC_SetPriority __NVIC_SetPriority
\r
1252 #define NVIC_GetPriority __NVIC_GetPriority
\r
1253 #define NVIC_SystemReset __NVIC_SystemReset
\r
1254 #endif /* CMSIS_NVIC_VIRTUAL */
\r
1256 #ifdef CMSIS_VECTAB_VIRTUAL
\r
1257 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
\r
1258 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
\r
1260 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
\r
1262 #define NVIC_SetVector __NVIC_SetVector
\r
1263 #define NVIC_GetVector __NVIC_GetVector
\r
1264 #endif /* (CMSIS_VECTAB_VIRTUAL) */
\r
1266 #define NVIC_USER_IRQ_OFFSET 16
\r
1269 /* Interrupt Priorities are WORD accessible only under Armv6-M */
\r
1270 /* The following MACROS handle generation of the register offset and byte masks */
\r
1271 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
\r
1272 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
\r
1273 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
\r
1277 \brief Enable Interrupt
\r
1278 \details Enables a device specific interrupt in the NVIC interrupt controller.
\r
1279 \param [in] IRQn Device specific interrupt number.
\r
1280 \note IRQn must not be negative.
\r
1282 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
\r
1284 if ((int32_t)(IRQn) >= 0)
\r
1286 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
\r
1292 \brief Get Interrupt Enable status
\r
1293 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\r
1294 \param [in] IRQn Device specific interrupt number.
\r
1295 \return 0 Interrupt is not enabled.
\r
1296 \return 1 Interrupt is enabled.
\r
1297 \note IRQn must not be negative.
\r
1299 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
\r
1301 if ((int32_t)(IRQn) >= 0)
\r
1303 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
\r
1313 \brief Disable Interrupt
\r
1314 \details Disables a device specific interrupt in the NVIC interrupt controller.
\r
1315 \param [in] IRQn Device specific interrupt number.
\r
1316 \note IRQn must not be negative.
\r
1318 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
\r
1320 if ((int32_t)(IRQn) >= 0)
\r
1322 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
\r
1330 \brief Get Pending Interrupt
\r
1331 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\r
1332 \param [in] IRQn Device specific interrupt number.
\r
1333 \return 0 Interrupt status is not pending.
\r
1334 \return 1 Interrupt status is pending.
\r
1335 \note IRQn must not be negative.
\r
1337 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
\r
1339 if ((int32_t)(IRQn) >= 0)
\r
1341 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
\r
1351 \brief Set Pending Interrupt
\r
1352 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\r
1353 \param [in] IRQn Device specific interrupt number.
\r
1354 \note IRQn must not be negative.
\r
1356 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
\r
1358 if ((int32_t)(IRQn) >= 0)
\r
1360 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
\r
1366 \brief Clear Pending Interrupt
\r
1367 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\r
1368 \param [in] IRQn Device specific interrupt number.
\r
1369 \note IRQn must not be negative.
\r
1371 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
\r
1373 if ((int32_t)(IRQn) >= 0)
\r
1375 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
\r
1381 \brief Get Active Interrupt
\r
1382 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
\r
1383 \param [in] IRQn Device specific interrupt number.
\r
1384 \return 0 Interrupt status is not active.
\r
1385 \return 1 Interrupt status is active.
\r
1386 \note IRQn must not be negative.
\r
1388 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
\r
1390 if ((int32_t)(IRQn) >= 0)
\r
1392 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
\r
1401 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
\r
1403 \brief Get Interrupt Target State
\r
1404 \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
\r
1405 \param [in] IRQn Device specific interrupt number.
\r
1406 \return 0 if interrupt is assigned to Secure
\r
1407 \return 1 if interrupt is assigned to Non Secure
\r
1408 \note IRQn must not be negative.
\r
1410 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
\r
1412 if ((int32_t)(IRQn) >= 0)
\r
1414 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
\r
1424 \brief Set Interrupt Target State
\r
1425 \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
\r
1426 \param [in] IRQn Device specific interrupt number.
\r
1427 \return 0 if interrupt is assigned to Secure
\r
1428 1 if interrupt is assigned to Non Secure
\r
1429 \note IRQn must not be negative.
\r
1431 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
\r
1433 if ((int32_t)(IRQn) >= 0)
\r
1435 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
\r
1436 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
\r
1446 \brief Clear Interrupt Target State
\r
1447 \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
\r
1448 \param [in] IRQn Device specific interrupt number.
\r
1449 \return 0 if interrupt is assigned to Secure
\r
1450 1 if interrupt is assigned to Non Secure
\r
1451 \note IRQn must not be negative.
\r
1453 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
\r
1455 if ((int32_t)(IRQn) >= 0)
\r
1457 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
\r
1458 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
\r
1465 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
\r
1469 \brief Set Interrupt Priority
\r
1470 \details Sets the priority of a device specific interrupt or a processor exception.
\r
1471 The interrupt number can be positive to specify a device specific interrupt,
\r
1472 or negative to specify a processor exception.
\r
1473 \param [in] IRQn Interrupt number.
\r
1474 \param [in] priority Priority to set.
\r
1475 \note The priority cannot be set for every processor exception.
\r
1477 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
\r
1479 if ((int32_t)(IRQn) >= 0)
\r
1481 NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
\r
1482 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
\r
1486 SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
\r
1487 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
\r
1493 \brief Get Interrupt Priority
\r
1494 \details Reads the priority of a device specific interrupt or a processor exception.
\r
1495 The interrupt number can be positive to specify a device specific interrupt,
\r
1496 or negative to specify a processor exception.
\r
1497 \param [in] IRQn Interrupt number.
\r
1498 \return Interrupt Priority.
\r
1499 Value is aligned automatically to the implemented priority bits of the microcontroller.
\r
1501 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
\r
1504 if ((int32_t)(IRQn) >= 0)
\r
1506 return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
\r
1510 return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
\r
1516 \brief Set Interrupt Vector
\r
1517 \details Sets an interrupt vector in SRAM based interrupt vector table.
\r
1518 The interrupt number can be positive to specify a device specific interrupt,
\r
1519 or negative to specify a processor exception.
\r
1520 VTOR must been relocated to SRAM before.
\r
1521 If VTOR is not present address 0 must be mapped to SRAM.
\r
1522 \param [in] IRQn Interrupt number
\r
1523 \param [in] vector Address of interrupt handler function
\r
1525 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
\r
1527 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
\r
1528 uint32_t *vectors = (uint32_t *)SCB->VTOR;
\r
1530 uint32_t *vectors = (uint32_t *)0x0U;
\r
1532 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
\r
1537 \brief Get Interrupt Vector
\r
1538 \details Reads an interrupt vector from interrupt vector table.
\r
1539 The interrupt number can be positive to specify a device specific interrupt,
\r
1540 or negative to specify a processor exception.
\r
1541 \param [in] IRQn Interrupt number.
\r
1542 \return Address of interrupt handler function
\r
1544 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
\r
1546 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
\r
1547 uint32_t *vectors = (uint32_t *)SCB->VTOR;
\r
1549 uint32_t *vectors = (uint32_t *)0x0U;
\r
1551 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
\r
1556 \brief System Reset
\r
1557 \details Initiates a system reset request to reset the MCU.
\r
1559 __STATIC_INLINE void __NVIC_SystemReset(void)
\r
1561 __DSB(); /* Ensure all outstanding memory accesses included
\r
1562 buffered write are completed before reset */
\r
1563 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
\r
1564 SCB_AIRCR_SYSRESETREQ_Msk);
\r
1565 __DSB(); /* Ensure completion of memory access */
\r
1567 for(;;) /* wait until reset */
\r
1573 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
\r
1575 \brief Enable Interrupt (non-secure)
\r
1576 \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
\r
1577 \param [in] IRQn Device specific interrupt number.
\r
1578 \note IRQn must not be negative.
\r
1580 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
\r
1582 if ((int32_t)(IRQn) >= 0)
\r
1584 NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
\r
1590 \brief Get Interrupt Enable status (non-secure)
\r
1591 \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
\r
1592 \param [in] IRQn Device specific interrupt number.
\r
1593 \return 0 Interrupt is not enabled.
\r
1594 \return 1 Interrupt is enabled.
\r
1595 \note IRQn must not be negative.
\r
1597 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
\r
1599 if ((int32_t)(IRQn) >= 0)
\r
1601 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
\r
1611 \brief Disable Interrupt (non-secure)
\r
1612 \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
\r
1613 \param [in] IRQn Device specific interrupt number.
\r
1614 \note IRQn must not be negative.
\r
1616 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
\r
1618 if ((int32_t)(IRQn) >= 0)
\r
1620 NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
\r
1626 \brief Get Pending Interrupt (non-secure)
\r
1627 \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
\r
1628 \param [in] IRQn Device specific interrupt number.
\r
1629 \return 0 Interrupt status is not pending.
\r
1630 \return 1 Interrupt status is pending.
\r
1631 \note IRQn must not be negative.
\r
1633 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
\r
1635 if ((int32_t)(IRQn) >= 0)
\r
1637 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
\r
1647 \brief Set Pending Interrupt (non-secure)
\r
1648 \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
\r
1649 \param [in] IRQn Device specific interrupt number.
\r
1650 \note IRQn must not be negative.
\r
1652 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
\r
1654 if ((int32_t)(IRQn) >= 0)
\r
1656 NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
\r
1662 \brief Clear Pending Interrupt (non-secure)
\r
1663 \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
\r
1664 \param [in] IRQn Device specific interrupt number.
\r
1665 \note IRQn must not be negative.
\r
1667 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
\r
1669 if ((int32_t)(IRQn) >= 0)
\r
1671 NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
\r
1677 \brief Get Active Interrupt (non-secure)
\r
1678 \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
\r
1679 \param [in] IRQn Device specific interrupt number.
\r
1680 \return 0 Interrupt status is not active.
\r
1681 \return 1 Interrupt status is active.
\r
1682 \note IRQn must not be negative.
\r
1684 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
\r
1686 if ((int32_t)(IRQn) >= 0)
\r
1688 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
\r
1698 \brief Set Interrupt Priority (non-secure)
\r
1699 \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
\r
1700 The interrupt number can be positive to specify a device specific interrupt,
\r
1701 or negative to specify a processor exception.
\r
1702 \param [in] IRQn Interrupt number.
\r
1703 \param [in] priority Priority to set.
\r
1704 \note The priority cannot be set for every non-secure processor exception.
\r
1706 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
\r
1708 if ((int32_t)(IRQn) >= 0)
\r
1710 NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
\r
1711 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
\r
1715 SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
\r
1716 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
\r
1722 \brief Get Interrupt Priority (non-secure)
\r
1723 \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
\r
1724 The interrupt number can be positive to specify a device specific interrupt,
\r
1725 or negative to specify a processor exception.
\r
1726 \param [in] IRQn Interrupt number.
\r
1727 \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
\r
1729 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
\r
1732 if ((int32_t)(IRQn) >= 0)
\r
1734 return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
\r
1738 return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
\r
1741 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
\r
1743 /*@} end of CMSIS_Core_NVICFunctions */
\r
1745 /* ########################## MPU functions #################################### */
\r
1747 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
\r
1749 #include "mpu_armv8.h"
\r
1753 /* ########################## FPU functions #################################### */
\r
1755 \ingroup CMSIS_Core_FunctionInterface
\r
1756 \defgroup CMSIS_Core_FpuFunctions FPU Functions
\r
1757 \brief Function that provides FPU type.
\r
1762 \brief get FPU type
\r
1763 \details returns the FPU type
\r
1766 - \b 1: Single precision FPU
\r
1767 - \b 2: Double + Single precision FPU
\r
1769 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
\r
1771 return 0U; /* No FPU */
\r
1775 /*@} end of CMSIS_Core_FpuFunctions */
\r
1779 /* ########################## SAU functions #################################### */
\r
1781 \ingroup CMSIS_Core_FunctionInterface
\r
1782 \defgroup CMSIS_Core_SAUFunctions SAU Functions
\r
1783 \brief Functions that configure the SAU.
\r
1787 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
\r
1791 \details Enables the Security Attribution Unit (SAU).
\r
1793 __STATIC_INLINE void TZ_SAU_Enable(void)
\r
1795 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
\r
1801 \brief Disable SAU
\r
1802 \details Disables the Security Attribution Unit (SAU).
\r
1804 __STATIC_INLINE void TZ_SAU_Disable(void)
\r
1806 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
\r
1809 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
\r
1811 /*@} end of CMSIS_Core_SAUFunctions */
\r
1816 /* ################################## SysTick function ############################################ */
\r
1818 \ingroup CMSIS_Core_FunctionInterface
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1819 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
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1820 \brief Functions that configure the System.
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1824 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
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1827 \brief System Tick Configuration
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1828 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
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1829 Counter is in free running mode to generate periodic interrupts.
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1830 \param [in] ticks Number of ticks between two interrupts.
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1831 \return 0 Function succeeded.
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1832 \return 1 Function failed.
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1833 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
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1834 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
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1835 must contain a vendor-specific implementation of this function.
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1837 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
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1839 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
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1841 return (1UL); /* Reload value impossible */
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1844 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
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1845 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
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1846 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
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1847 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
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1848 SysTick_CTRL_TICKINT_Msk |
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1849 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
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1850 return (0UL); /* Function successful */
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1853 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
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1855 \brief System Tick Configuration (non-secure)
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1856 \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
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1857 Counter is in free running mode to generate periodic interrupts.
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1858 \param [in] ticks Number of ticks between two interrupts.
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1859 \return 0 Function succeeded.
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1860 \return 1 Function failed.
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1861 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
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1862 function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
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1863 must contain a vendor-specific implementation of this function.
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1866 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
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1868 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
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1870 return (1UL); /* Reload value impossible */
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1873 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
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1874 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
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1875 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
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1876 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
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1877 SysTick_CTRL_TICKINT_Msk |
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1878 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
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1879 return (0UL); /* Function successful */
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1881 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
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1885 /*@} end of CMSIS_Core_SysTickFunctions */
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1890 #ifdef __cplusplus
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1894 #endif /* __CORE_ARMV8MBL_H_DEPENDANT */
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1896 #endif /* __CMSIS_GENERIC */
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