1 /******************************************************************************
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3 * @brief CMSIS MPU API for Armv7-M MPU
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5 * @date 10. January 2018
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6 ******************************************************************************/
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8 * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
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10 * SPDX-License-Identifier: Apache-2.0
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12 * Licensed under the Apache License, Version 2.0 (the License); you may
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13 * not use this file except in compliance with the License.
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14 * You may obtain a copy of the License at
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16 * www.apache.org/licenses/LICENSE-2.0
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18 * Unless required by applicable law or agreed to in writing, software
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19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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21 * See the License for the specific language governing permissions and
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22 * limitations under the License.
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25 #if defined ( __ICCARM__ )
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26 #pragma system_include /* treat file as system include file for MISRA check */
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27 #elif defined (__clang__)
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28 #pragma clang system_header /* treat file as system include file */
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31 #ifndef ARM_MPU_ARMV7_H
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32 #define ARM_MPU_ARMV7_H
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34 #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U)
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35 #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U)
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36 #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U)
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37 #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U)
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38 #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U)
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39 #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
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40 #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
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41 #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
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42 #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
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43 #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
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44 #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
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45 #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
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46 #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
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47 #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
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48 #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
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49 #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
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50 #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
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51 #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
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52 #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
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53 #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
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54 #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
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55 #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
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56 #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
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57 #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
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58 #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
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59 #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
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60 #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
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61 #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
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63 #define ARM_MPU_AP_NONE 0U
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64 #define ARM_MPU_AP_PRIV 1U
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65 #define ARM_MPU_AP_URO 2U
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66 #define ARM_MPU_AP_FULL 3U
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67 #define ARM_MPU_AP_PRO 5U
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68 #define ARM_MPU_AP_RO 6U
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70 /** MPU Region Base Address Register Value
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72 * \param Region The region to be configured, number 0 to 15.
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73 * \param BaseAddress The base address for the region.
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75 #define ARM_MPU_RBAR(Region, BaseAddress) \
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76 (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
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77 ((Region) & MPU_RBAR_REGION_Msk) | \
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78 (MPU_RBAR_VALID_Msk))
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81 * MPU Region Attribute and Size Register Value
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83 * \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
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84 * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
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85 * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
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86 * \param IsShareable Region is shareable between multiple bus masters.
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87 * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
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88 * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
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89 * \param SubRegionDisable Sub-region disable field.
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90 * \param Size Region size of the region to be configured, for example 4K, 8K.
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92 #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
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93 ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
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94 (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
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95 (((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
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96 (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
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97 (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
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98 (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) | \
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99 (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
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100 (((Size ) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
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101 (MPU_RASR_ENABLE_Msk))
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105 * Struct for a single MPU Region
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108 uint32_t RBAR; //!< The region base address register value (RBAR)
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109 uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
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110 } ARM_MPU_Region_t;
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112 /** Enable the MPU.
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113 * \param MPU_Control Default access permissions for unconfigured regions.
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115 __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
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119 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
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120 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
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121 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
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125 /** Disable the MPU.
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127 __STATIC_INLINE void ARM_MPU_Disable(void)
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131 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
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132 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
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134 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
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137 /** Clear and disable the given MPU region.
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138 * \param rnr Region number to be cleared.
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140 __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
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146 /** Configure an MPU region.
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147 * \param rbar Value for RBAR register.
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148 * \param rsar Value for RSAR register.
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150 __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
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156 /** Configure the given MPU region.
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157 * \param rnr Region number to be configured.
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158 * \param rbar Value for RBAR register.
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159 * \param rsar Value for RSAR register.
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161 __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
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168 /** Memcopy with strictly ordered memory access, e.g. for register targets.
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169 * \param dst Destination data is copied to.
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170 * \param src Source data is copied from.
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171 * \param len Amount of data words to be copied.
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173 __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
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176 for (i = 0U; i < len; ++i)
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182 /** Load the given number of MPU regions from a table.
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183 * \param table Pointer to the MPU configuration table.
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184 * \param cnt Amount of regions to be configured.
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186 __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
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188 const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
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189 while (cnt > MPU_TYPE_RALIASES) {
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190 orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
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191 table += MPU_TYPE_RALIASES;
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192 cnt -= MPU_TYPE_RALIASES;
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194 orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
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