2 * Copyright 2017-2019 NXP
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3 * All rights reserved.
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5 * SPDX-License-Identifier: BSD-3-Clause
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7 /***********************************************************************************************************************
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8 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
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9 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
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10 **********************************************************************************************************************/
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12 * How to set up clock using clock driver functions:
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14 * 1. Setup clock sources.
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16 * 2. Set up wait states of the flash.
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18 * 3. Set up all dividers.
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20 * 4. Set up all selectors to provide selected clocks.
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23 /* clang-format off */
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24 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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26 product: Clocks v7.0
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28 package_id: LPC55S69JBD100
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30 processor_version: 0.7.2
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31 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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32 /* clang-format on */
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34 #include "fsl_power.h"
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35 #include "fsl_clock.h"
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36 #include "clock_config.h"
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38 /*******************************************************************************
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40 ******************************************************************************/
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42 /*******************************************************************************
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44 ******************************************************************************/
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45 /* System clock frequency. */
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46 extern uint32_t SystemCoreClock;
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48 /*******************************************************************************
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49 ************************ BOARD_InitBootClocks function ************************
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50 ******************************************************************************/
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51 void BOARD_InitBootClocks(void)
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53 BOARD_BootClockPLL150M();
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56 /*******************************************************************************
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57 ******************** Configuration BOARD_BootClockFRO12M **********************
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58 ******************************************************************************/
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59 /* clang-format off */
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60 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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62 name: BOARD_BootClockFRO12M
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64 - {id: System_clock.outFreq, value: 12 MHz}
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66 - {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
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68 - {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
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69 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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70 /* clang-format on */
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72 /*******************************************************************************
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73 * Variables for BOARD_BootClockFRO12M configuration
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74 ******************************************************************************/
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75 /*******************************************************************************
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76 * Code for BOARD_BootClockFRO12M configuration
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77 ******************************************************************************/
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78 void BOARD_BootClockFRO12M(void)
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80 #ifndef SDK_SECONDARY_CORE
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81 /*!< Set up the clock sources */
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82 /*!< Configure FRO192M */
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83 POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
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84 CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
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85 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
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87 CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */
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89 POWER_SetVoltageForFreq(
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90 12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
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91 CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */
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93 /*!< Set up dividers */
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94 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
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96 /*!< Set up clock selectors - Attach clocks to the peripheries */
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97 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */
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99 /*< Set SystemCoreClock variable. */
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100 SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
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104 /*******************************************************************************
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105 ******************* Configuration BOARD_BootClockFROHF96M *********************
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106 ******************************************************************************/
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107 /* clang-format off */
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108 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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110 name: BOARD_BootClockFROHF96M
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112 - {id: System_clock.outFreq, value: 96 MHz}
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114 - {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
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115 - {id: SYSCON.MAINCLKSELA.sel, value: ANACTRL.fro_hf_clk}
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117 - {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
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118 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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119 /* clang-format on */
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121 /*******************************************************************************
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122 * Variables for BOARD_BootClockFROHF96M configuration
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123 ******************************************************************************/
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124 /*******************************************************************************
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125 * Code for BOARD_BootClockFROHF96M configuration
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126 ******************************************************************************/
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127 void BOARD_BootClockFROHF96M(void)
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129 #ifndef SDK_SECONDARY_CORE
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130 /*!< Set up the clock sources */
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131 /*!< Configure FRO192M */
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132 POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
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133 CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
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134 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
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136 CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */
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138 POWER_SetVoltageForFreq(
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139 96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
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140 CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */
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142 /*!< Set up dividers */
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143 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
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145 /*!< Set up clock selectors - Attach clocks to the peripheries */
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146 CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
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148 /*< Set SystemCoreClock variable. */
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149 SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK;
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153 /*******************************************************************************
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154 ******************** Configuration BOARD_BootClockPLL100M *********************
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155 ******************************************************************************/
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156 /* clang-format off */
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157 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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159 name: BOARD_BootClockPLL100M
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161 - {id: System_clock.outFreq, value: 100 MHz}
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163 - {id: PLL0_Mode, value: Normal}
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164 - {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
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165 - {id: ENABLE_CLKIN_ENA, value: Enabled}
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166 - {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
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167 - {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
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168 - {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
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169 - {id: SYSCON.PLL0M_MULT.scale, value: '100', locked: true}
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170 - {id: SYSCON.PLL0N_DIV.scale, value: '4', locked: true}
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171 - {id: SYSCON.PLL0_PDEC.scale, value: '4', locked: true}
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173 - {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
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174 - {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
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175 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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176 /* clang-format on */
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178 /*******************************************************************************
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179 * Variables for BOARD_BootClockPLL100M configuration
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180 ******************************************************************************/
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181 /*******************************************************************************
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182 * Code for BOARD_BootClockPLL100M configuration
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183 ******************************************************************************/
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184 void BOARD_BootClockPLL100M(void)
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186 #ifndef SDK_SECONDARY_CORE
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187 /*!< Set up the clock sources */
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188 /*!< Configure FRO192M */
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189 POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
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190 CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
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191 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
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193 CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */
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195 /*!< Configure XTAL32M */
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196 POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */
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197 POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */
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198 CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */
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199 SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */
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200 ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */
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202 POWER_SetVoltageForFreq(
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203 100000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
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204 CLOCK_SetFLASHAccessCyclesForFreq(100000000U); /*!< Set FLASH wait states for core */
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207 CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */
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208 POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */
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209 POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
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210 const pll_setup_t pll0Setup = {
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211 .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(26U),
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212 .pllndec = SYSCON_PLL0NDEC_NDIV(4U),
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213 .pllpdec = SYSCON_PLL0PDEC_PDIV(2U),
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214 .pllsscg = {0x0U, (SYSCON_PLL0SSCG1_MDIV_EXT(100U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
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215 .pllRate = 100000000U,
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216 .flags = PLL_SETUPFLAG_WAITLOCK};
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217 CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */
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219 /*!< Set up dividers */
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220 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
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222 /*!< Set up clock selectors - Attach clocks to the peripheries */
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223 CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */
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225 /*< Set SystemCoreClock variable. */
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226 SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;
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230 /*******************************************************************************
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231 ******************** Configuration BOARD_BootClockPLL150M *********************
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232 ******************************************************************************/
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233 /* clang-format off */
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234 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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236 name: BOARD_BootClockPLL150M
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237 called_from_default_init: true
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239 - {id: System_clock.outFreq, value: 150 MHz}
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241 - {id: PLL0_Mode, value: Normal}
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242 - {id: ENABLE_CLKIN_ENA, value: Enabled}
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243 - {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
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244 - {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
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245 - {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
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246 - {id: SYSCON.PLL0M_MULT.scale, value: '150', locked: true}
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247 - {id: SYSCON.PLL0N_DIV.scale, value: '8', locked: true}
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248 - {id: SYSCON.PLL0_PDEC.scale, value: '2', locked: true}
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250 - {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
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251 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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252 /* clang-format on */
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254 /*******************************************************************************
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255 * Variables for BOARD_BootClockPLL150M configuration
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256 ******************************************************************************/
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257 /*******************************************************************************
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258 * Code for BOARD_BootClockPLL150M configuration
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259 ******************************************************************************/
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260 void BOARD_BootClockPLL150M(void)
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262 #ifndef SDK_SECONDARY_CORE
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263 /*!< Set up the clock sources */
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264 /*!< Configure FRO192M */
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265 POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
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266 CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
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267 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
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269 /*!< Configure XTAL32M */
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270 POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */
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271 POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */
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272 CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */
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273 SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */
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274 ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */
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276 POWER_SetVoltageForFreq(
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277 150000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
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278 CLOCK_SetFLASHAccessCyclesForFreq(150000000U); /*!< Set FLASH wait states for core */
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281 CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */
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282 POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */
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283 POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
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284 const pll_setup_t pll0Setup = {
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285 .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(31U),
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286 .pllndec = SYSCON_PLL0NDEC_NDIV(8U),
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287 .pllpdec = SYSCON_PLL0PDEC_PDIV(1U),
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288 .pllsscg = {0x0U, (SYSCON_PLL0SSCG1_MDIV_EXT(150U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
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289 .pllRate = 150000000U,
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290 .flags = PLL_SETUPFLAG_WAITLOCK};
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291 CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */
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293 /*!< Set up dividers */
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294 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
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296 /*!< Set up clock selectors - Attach clocks to the peripheries */
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297 CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */
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299 /*< Set SystemCoreClock variable. */
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300 SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK;
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