2 * Copyright 2017-2018 NXP
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3 * All rights reserved.
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5 * SPDX-License-Identifier: BSD-3-Clause
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8 /***********************************************************************************************************************
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9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
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10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
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11 **********************************************************************************************************************/
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13 * How to set up clock using clock driver functions:
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15 * 1. Setup clock sources.
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17 * 2. Set up wait states of the flash.
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19 * 3. Set up all dividers.
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21 * 4. Set up all selectors to provide selected clocks.
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24 /* clang-format off */
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25 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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27 product: Clocks v5.0
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29 package_id: LPC55S69JBD100
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31 processor_version: 0.0.6
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32 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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33 /* clang-format on */
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35 #include "fsl_power.h"
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36 #include "fsl_clock.h"
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37 #include "clock_config.h"
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39 /*******************************************************************************
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41 ******************************************************************************/
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43 /*******************************************************************************
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45 ******************************************************************************/
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46 /* System clock frequency. */
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47 extern uint32_t SystemCoreClock;
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49 /*******************************************************************************
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50 ************************ BOARD_InitBootClocks function ************************
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51 ******************************************************************************/
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52 void BOARD_InitBootClocks(void)
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54 BOARD_BootClockFROHF96M();
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57 /*******************************************************************************
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58 ******************** Configuration BOARD_BootClockFRO12M **********************
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59 ******************************************************************************/
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60 /* clang-format off */
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61 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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63 name: BOARD_BootClockFRO12M
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65 - {id: System_clock.outFreq, value: 12 MHz}
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67 - {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
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69 - {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
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70 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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71 /* clang-format on */
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73 /*******************************************************************************
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74 * Variables for BOARD_BootClockFRO12M configuration
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75 ******************************************************************************/
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76 /*******************************************************************************
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77 * Code for BOARD_BootClockFRO12M configuration
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78 ******************************************************************************/
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79 void BOARD_BootClockFRO12M(void)
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81 #ifndef SDK_SECONDARY_CORE
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82 /*!< Set up the clock sources */
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83 /*!< Configure FRO192M */
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84 POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
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85 CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
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86 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
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88 CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */
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90 POWER_SetVoltageForFreq(12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
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91 CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */
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93 /*!< Set up dividers */
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94 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
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96 /*!< Set up clock selectors - Attach clocks to the peripheries */
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97 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */
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99 /*< Set SystemCoreClock variable. */
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100 SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
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104 /*******************************************************************************
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105 ******************* Configuration BOARD_BootClockFROHF96M *********************
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106 ******************************************************************************/
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107 /* clang-format off */
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108 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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110 name: BOARD_BootClockFROHF96M
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111 called_from_default_init: true
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113 - {id: System_clock.outFreq, value: 96 MHz}
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115 - {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
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116 - {id: SYSCON.MAINCLKSELA.sel, value: ANACTRL.fro_hf_clk}
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118 - {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
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119 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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120 /* clang-format on */
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122 /*******************************************************************************
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123 * Variables for BOARD_BootClockFROHF96M configuration
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124 ******************************************************************************/
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125 /*******************************************************************************
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126 * Code for BOARD_BootClockFROHF96M configuration
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127 ******************************************************************************/
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128 void BOARD_BootClockFROHF96M(void)
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130 #ifndef SDK_SECONDARY_CORE
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131 /*!< Set up the clock sources */
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132 /*!< Configure FRO192M */
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133 POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
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134 CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
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135 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
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137 CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */
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139 POWER_SetVoltageForFreq(96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
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140 CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */
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142 /*!< Set up dividers */
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143 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
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145 /*!< Set up clock selectors - Attach clocks to the peripheries */
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146 CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
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148 /*< Set SystemCoreClock variable. */
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149 SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK;
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153 /*******************************************************************************
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154 ******************** Configuration BOARD_BootClockPLL100M *********************
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155 ******************************************************************************/
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156 /* clang-format off */
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157 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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159 name: BOARD_BootClockPLL100M
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161 - {id: System_clock.outFreq, value: 100 MHz}
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163 - {id: PLL0_Mode, value: Normal}
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164 - {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
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165 - {id: ENABLE_CLKIN_ENA, value: Enabled}
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166 - {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
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167 - {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
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168 - {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
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169 - {id: SYSCON.PLL0M_MULT.scale, value: '100', locked: true}
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170 - {id: SYSCON.PLL0N_DIV.scale, value: '4', locked: true}
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171 - {id: SYSCON.PLL0_PDEC.scale, value: '4', locked: true}
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173 - {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
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174 - {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
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175 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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176 /* clang-format on */
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178 /*******************************************************************************
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179 * Variables for BOARD_BootClockPLL100M configuration
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180 ******************************************************************************/
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181 /*******************************************************************************
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182 * Code for BOARD_BootClockPLL100M configuration
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183 ******************************************************************************/
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184 void BOARD_BootClockPLL100M(void)
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186 #ifndef SDK_SECONDARY_CORE
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187 /*!< Set up the clock sources */
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188 /*!< Configure FRO192M */
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189 POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
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190 CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
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191 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
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193 CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */
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195 POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */
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196 POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */
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197 CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */
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198 SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */
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199 ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */
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201 POWER_SetVoltageForFreq(100000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
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202 CLOCK_SetFLASHAccessCyclesForFreq(100000000U); /*!< Set FLASH wait states for core */
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205 CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */
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206 POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */
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207 POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
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208 const pll_setup_t pll0Setup = {
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209 .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(54U) | SYSCON_PLL0CTRL_SELP(26U),
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210 .pllndec = SYSCON_PLL0NDEC_NDIV(4U),
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211 .pllpdec = SYSCON_PLL0PDEC_PDIV(2U),
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212 .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(100U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
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213 .pllRate = 100000000U,
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214 .flags = PLL_SETUPFLAG_WAITLOCK
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216 CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */
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218 /*!< Set up dividers */
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219 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
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221 /*!< Set up clock selectors - Attach clocks to the peripheries */
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222 CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */
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224 /*< Set SystemCoreClock variable. */
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225 SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;
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