2 * Copyright 2017-2019 NXP
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3 * All rights reserved.
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5 * SPDX-License-Identifier: BSD-3-Clause
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8 /***********************************************************************************************************************
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9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
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10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
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11 **********************************************************************************************************************/
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13 /* clang-format off */
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15 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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19 package_id: LPC55S69JBD100
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21 processor_version: 0.0.0
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22 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
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24 /* clang-format on */
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26 #include "fsl_common.h"
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27 #include "fsl_iocon.h"
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28 #include "pin_mux.h"
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30 /* FUNCTION ************************************************************************************************************
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32 * Function Name : BOARD_InitBootPins
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33 * Description : Calls initialization functions.
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35 * END ****************************************************************************************************************/
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36 void BOARD_InitBootPins(void)
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41 /* clang-format off */
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43 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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45 - options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
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47 - {pin_num: '92', peripheral: FLEXCOMM0, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_29/FC0_RXD_SDA_MOSI_DATA/SD1_D2/CTIMER2_MAT3/SCT0_OUT8/CMP0_OUT/PLU_OUT2/SECURE_GPIO0_29,
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48 mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled}
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49 - {pin_num: '94', peripheral: FLEXCOMM0, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_30/FC0_TXD_SCL_MISO_WS/SD1_D3/CTIMER0_MAT0/SCT0_OUT9/SECURE_GPIO0_30, mode: inactive,
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50 slew_rate: standard, invert: disabled, open_drain: disabled}
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51 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
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53 /* clang-format on */
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55 /* FUNCTION ************************************************************************************************************
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57 * Function Name : BOARD_InitPins
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58 * Description : Configures pin routing and optionally pin electrical features.
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60 * END ****************************************************************************************************************/
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61 /* Function assigned for the Cortex-M33 (Core #0) */
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62 void BOARD_InitPins(void)
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64 /* Enables the clock for the I/O controller.: Enable Clock. */
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65 CLOCK_EnableClock(kCLOCK_Iocon);
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67 const uint32_t port0_pin29_config = (/* Pin is configured as FC0_RXD_SDA_MOSI_DATA */
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69 /* No addition pin function */
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70 IOCON_PIO_MODE_INACT |
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71 /* Standard mode, output slew rate control is enabled */
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72 IOCON_PIO_SLEW_STANDARD |
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73 /* Input function is not inverted */
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75 /* Enables digital function */
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76 IOCON_PIO_DIGITAL_EN |
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77 /* Open drain is disabled */
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78 IOCON_PIO_OPENDRAIN_DI);
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79 /* PORT0 PIN29 (coords: 92) is configured as FC0_RXD_SDA_MOSI_DATA */
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80 IOCON_PinMuxSet(IOCON, 0U, 29U, port0_pin29_config);
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82 const uint32_t port0_pin30_config = (/* Pin is configured as FC0_TXD_SCL_MISO_WS */
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84 /* No addition pin function */
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85 IOCON_PIO_MODE_INACT |
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86 /* Standard mode, output slew rate control is enabled */
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87 IOCON_PIO_SLEW_STANDARD |
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88 /* Input function is not inverted */
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90 /* Enables digital function */
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91 IOCON_PIO_DIGITAL_EN |
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92 /* Open drain is disabled */
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93 IOCON_PIO_OPENDRAIN_DI);
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94 /* PORT0 PIN30 (coords: 94) is configured as FC0_TXD_SCL_MISO_WS */
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95 IOCON_PinMuxSet(IOCON, 0U, 30U, port0_pin30_config);
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97 /***********************************************************************************************************************
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99 **********************************************************************************************************************/
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