2 ** ###################################################################
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3 ** Version: rev. 1.1, 2019-05-16
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7 ** Chip specific module features.
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9 ** Copyright 2016 Freescale Semiconductor, Inc.
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10 ** Copyright 2016-2019 NXP
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11 ** All rights reserved.
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13 ** SPDX-License-Identifier: BSD-3-Clause
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15 ** http: www.nxp.com
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16 ** mail: support@nxp.com
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19 ** - rev. 1.0 (2018-08-22)
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20 ** Initial version based on v0.2UM
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21 ** - rev. 1.1 (2019-05-16)
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22 ** Initial A1 version based on v1.3UM
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24 ** ###################################################################
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27 #ifndef _LPC55S69_cm33_core0_FEATURES_H_
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28 #define _LPC55S69_cm33_core0_FEATURES_H_
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30 /* SOC module features */
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32 /* @brief CASPER availability on the SoC. */
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33 #define FSL_FEATURE_SOC_CASPER_COUNT (1)
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34 /* @brief CRC availability on the SoC. */
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35 #define FSL_FEATURE_SOC_CRC_COUNT (1)
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36 /* @brief CTIMER availability on the SoC. */
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37 #define FSL_FEATURE_SOC_CTIMER_COUNT (5)
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38 /* @brief DMA availability on the SoC. */
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39 #define FSL_FEATURE_SOC_DMA_COUNT (2)
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40 /* @brief FLASH availability on the SoC. */
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41 #define FSL_FEATURE_SOC_FLASH_COUNT (1)
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42 /* @brief FLEXCOMM availability on the SoC. */
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43 #define FSL_FEATURE_SOC_FLEXCOMM_COUNT (9)
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44 /* @brief GINT availability on the SoC. */
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45 #define FSL_FEATURE_SOC_GINT_COUNT (2)
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46 /* @brief GPIO availability on the SoC. */
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47 #define FSL_FEATURE_SOC_GPIO_COUNT (1)
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48 /* @brief SECGPIO availability on the SoC. */
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49 #define FSL_FEATURE_SOC_SECGPIO_COUNT (1)
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50 /* @brief HASHCRYPT availability on the SoC. */
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51 #define FSL_FEATURE_SOC_HASHCRYPT_COUNT (1)
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52 /* @brief I2C availability on the SoC. */
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53 #define FSL_FEATURE_SOC_I2C_COUNT (8)
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54 /* @brief I2S availability on the SoC. */
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55 #define FSL_FEATURE_SOC_I2S_COUNT (8)
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56 /* @brief INPUTMUX availability on the SoC. */
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57 #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)
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58 /* @brief IOCON availability on the SoC. */
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59 #define FSL_FEATURE_SOC_IOCON_COUNT (1)
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60 /* @brief LPADC availability on the SoC. */
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61 #define FSL_FEATURE_SOC_LPADC_COUNT (1)
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62 /* @brief MAILBOX availability on the SoC. */
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63 #define FSL_FEATURE_SOC_MAILBOX_COUNT (1)
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64 /* @brief MRT availability on the SoC. */
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65 #define FSL_FEATURE_SOC_MRT_COUNT (1)
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66 /* @brief OSTIMER availability on the SoC. */
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67 #define FSL_FEATURE_SOC_OSTIMER_COUNT (1)
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68 /* @brief PINT availability on the SoC. */
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69 #define FSL_FEATURE_SOC_PINT_COUNT (1)
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70 /* @brief SECPINT availability on the SoC. */
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71 #define FSL_FEATURE_SOC_SECPINT_COUNT (1)
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72 /* @brief PMC availability on the SoC. */
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73 #define FSL_FEATURE_SOC_PMC_COUNT (1)
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74 /* @brief POWERQUAD availability on the SoC. */
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75 #define FSL_FEATURE_SOC_POWERQUAD_COUNT (1)
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76 /* @brief PUF availability on the SoC. */
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77 #define FSL_FEATURE_SOC_PUF_COUNT (1)
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78 /* @brief RNG1 availability on the SoC. */
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79 #define FSL_FEATURE_SOC_LPC_RNG1_COUNT (1)
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80 /* @brief RTC availability on the SoC. */
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81 #define FSL_FEATURE_SOC_RTC_COUNT (1)
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82 /* @brief SCT availability on the SoC. */
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83 #define FSL_FEATURE_SOC_SCT_COUNT (1)
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84 /* @brief SDIF availability on the SoC. */
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85 #define FSL_FEATURE_SOC_SDIF_COUNT (1)
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86 /* @brief SPI availability on the SoC. */
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87 #define FSL_FEATURE_SOC_SPI_COUNT (9)
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88 /* @brief SYSCON availability on the SoC. */
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89 #define FSL_FEATURE_SOC_SYSCON_COUNT (1)
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90 /* @brief SYSCTL1 availability on the SoC. */
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91 #define FSL_FEATURE_SOC_SYSCTL1_COUNT (1)
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92 /* @brief USART availability on the SoC. */
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93 #define FSL_FEATURE_SOC_USART_COUNT (8)
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94 /* @brief USB availability on the SoC. */
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95 #define FSL_FEATURE_SOC_USB_COUNT (1)
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96 /* @brief USBFSH availability on the SoC. */
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97 #define FSL_FEATURE_SOC_USBFSH_COUNT (1)
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98 /* @brief USBHSD availability on the SoC. */
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99 #define FSL_FEATURE_SOC_USBHSD_COUNT (1)
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100 /* @brief USBHSH availability on the SoC. */
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101 #define FSL_FEATURE_SOC_USBHSH_COUNT (1)
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102 /* @brief USBPHY availability on the SoC. */
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103 #define FSL_FEATURE_SOC_USBPHY_COUNT (1)
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104 /* @brief UTICK availability on the SoC. */
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105 #define FSL_FEATURE_SOC_UTICK_COUNT (1)
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106 /* @brief WWDT availability on the SoC. */
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107 #define FSL_FEATURE_SOC_WWDT_COUNT (1)
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109 /* LPADC module features */
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111 /* @brief FIFO availability on the SoC. */
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112 #define FSL_FEATURE_LPADC_FIFO_COUNT (2)
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113 /* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */
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114 #define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1)
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115 /* @brief Has differential mode (bitfield CMDLn[DIFF]). */
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116 #define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0)
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117 /* @brief Has channel scale (bitfield CMDLn[CSCALE]). */
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118 #define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0)
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119 /* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */
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120 #define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1)
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121 /* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */
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122 #define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1)
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123 /* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */
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124 #define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1)
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125 /* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */
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126 #define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1)
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127 /* @brief Has offset calibration (bitfield CTRL[CALOFS]). */
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128 #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1)
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129 /* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */
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130 #define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1)
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131 /* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */
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132 #define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1)
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133 /* @brief Has internal clock (bitfield CFG[ADCKEN]). */
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134 #define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0)
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135 /* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */
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136 #define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0)
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137 /* @brief Has calibration (bitfield CFG[CALOFS]). */
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138 #define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0)
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139 /* @brief Has offset trim (register OFSTRIM). */
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140 #define FSL_FEATURE_LPADC_HAS_OFSTRIM (1)
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141 /* @brief Has internal temperature sensor. */
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142 #define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1)
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143 /* @brief Temperature sensor parameter A (slope). */
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144 #define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (744.6f)
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145 /* @brief Temperature sensor parameter B (offset). */
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146 #define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (313.7f)
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147 /* @brief Temperature sensor parameter Alpha. */
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148 #define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (11.5f)
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150 /* CASPER module features */
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152 /* @brief Base address of the CASPER dedicated RAM */
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153 #define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x04000000)
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154 /* @brief Interleaving of the CASPER dedicated RAM */
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155 #define FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED (1)
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156 /* @brief CASPER dedicated RAM offset */
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157 #define FSL_FEATURE_CASPER_RAM_OFFSET (0xE)
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159 /* DMA module features */
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161 /* @brief Number of channels */
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162 #define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (23)
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163 /* @brief Align size of DMA descriptor */
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164 #define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512)
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165 /* @brief DMA head link descriptor table align size */
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166 #define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U)
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168 /* FLEXCOMM module features */
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170 /* @brief FLEXCOMM0 USART INDEX 0 */
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171 #define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0)
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172 /* @brief FLEXCOMM0 SPI INDEX 0 */
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173 #define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0)
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174 /* @brief FLEXCOMM0 I2C INDEX 0 */
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175 #define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0)
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176 /* @brief FLEXCOMM0 I2S INDEX 0 */
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177 #define FSL_FEATURE_FLEXCOMM0_I2S_INDEX (0)
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178 /* @brief FLEXCOMM1 USART INDEX 1 */
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179 #define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1)
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180 /* @brief FLEXCOMM1 SPI INDEX 1 */
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181 #define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1)
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182 /* @brief FLEXCOMM1 I2C INDEX 1 */
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183 #define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1)
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184 /* @brief FLEXCOMM1 I2S INDEX 1 */
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185 #define FSL_FEATURE_FLEXCOMM1_I2S_INDEX (1)
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186 /* @brief FLEXCOMM2 USART INDEX 2 */
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187 #define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2)
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188 /* @brief FLEXCOMM2 SPI INDEX 2 */
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189 #define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2)
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190 /* @brief FLEXCOMM2 I2C INDEX 2 */
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191 #define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2)
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192 /* @brief FLEXCOMM2 I2S INDEX 2 */
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193 #define FSL_FEATURE_FLEXCOMM2_I2S_INDEX (2)
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194 /* @brief FLEXCOMM3 USART INDEX 3 */
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195 #define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3)
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196 /* @brief FLEXCOMM3 SPI INDEX 3 */
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197 #define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3)
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198 /* @brief FLEXCOMM3 I2C INDEX 3 */
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199 #define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3)
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200 /* @brief FLEXCOMM3 I2S INDEX 3 */
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201 #define FSL_FEATURE_FLEXCOMM3_I2S_INDEX (3)
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202 /* @brief FLEXCOMM4 USART INDEX 4 */
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203 #define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4)
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204 /* @brief FLEXCOMM4 SPI INDEX 4 */
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205 #define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4)
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206 /* @brief FLEXCOMM4 I2C INDEX 4 */
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207 #define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4)
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208 /* @brief FLEXCOMM4 I2S INDEX 4 */
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209 #define FSL_FEATURE_FLEXCOMM4_I2S_INDEX (4)
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210 /* @brief FLEXCOMM5 USART INDEX 5 */
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211 #define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5)
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212 /* @brief FLEXCOMM5 SPI INDEX 5 */
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213 #define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5)
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214 /* @brief FLEXCOMM5 I2C INDEX 5 */
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215 #define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5)
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216 /* @brief FLEXCOMM5 I2S INDEX 5 */
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217 #define FSL_FEATURE_FLEXCOMM5_I2S_INDEX (5)
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218 /* @brief FLEXCOMM6 USART INDEX 6 */
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219 #define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6)
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220 /* @brief FLEXCOMM6 SPI INDEX 6 */
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221 #define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6)
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222 /* @brief FLEXCOMM6 I2C INDEX 6 */
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223 #define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6)
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224 /* @brief FLEXCOMM6 I2S INDEX 6 */
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225 #define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (6)
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226 /* @brief FLEXCOMM7 USART INDEX 7 */
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227 #define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7)
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228 /* @brief FLEXCOMM7 SPI INDEX 7 */
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229 #define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7)
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230 /* @brief FLEXCOMM7 I2C INDEX 7 */
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231 #define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7)
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232 /* @brief FLEXCOMM7 I2S INDEX 7 */
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233 #define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (7)
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234 /* @brief FLEXCOMM8 SPI(HS_SPI) INDEX 8 */
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235 #define FSL_FEATURE_FLEXCOMM8_SPI_INDEX (8)
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236 /* @brief I2S has DMIC interconnection */
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237 #define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) (0)
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239 /* HASHCRYPT module features */
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241 /* @brief the address of alias offset */
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242 #define FSL_FEATURE_HASHCRYPT_ALIAS_OFFSET (0x00000000)
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244 /* I2S module features */
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246 /* @brief I2S support dual channel transfer. */
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247 #define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (0)
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248 /* @brief I2S has DMIC interconnection. */
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249 #define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (0)
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251 /* IOCON module features */
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253 /* @brief Func bit field width */
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254 #define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4)
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256 /* MAILBOX module features */
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258 /* @brief Mailbox side for current core */
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259 #define FSL_FEATURE_MAILBOX_SIDE_A (1)
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261 /* MRT module features */
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263 /* @brief number of channels. */
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264 #define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4)
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266 /* PINT module features */
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268 /* @brief Number of connected outputs */
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269 #define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8)
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271 /* PLU module features */
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273 /* @brief Has WAKEINT_CTRL register. */
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274 #define FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG (1)
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276 /* POWERLIB module features */
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278 /* @brief Powerlib API is different with other LPC series devices. */
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279 #define FSL_FEATURE_POWERLIB_EXTEND (1)
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281 /* POWERQUAD module features */
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283 /* @brief Sine and Cossine fix errata */
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284 #define FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA (1)
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286 /* PUF module features */
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288 /* @brief Number of PUF key slots available on device. */
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289 #define FSL_FEATURE_PUF_HAS_KEYSLOTS (4)
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290 /* @brief the shift status value */
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291 #define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (1)
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293 /* SCT module features */
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295 /* @brief Number of events */
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296 #define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16)
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297 /* @brief Number of states */
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298 #define FSL_FEATURE_SCT_NUMBER_OF_STATES (32)
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299 /* @brief Number of match capture */
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300 #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16)
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301 /* @brief Number of outputs */
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302 #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10)
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304 /* SDIF module features */
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306 /* @brief FIFO depth, every location is a WORD */
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307 #define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64)
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308 /* @brief Max DMA buffer size */
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309 #define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096)
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310 /* @brief Max source clock in HZ */
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311 #define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000)
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312 /* @brief support 2 cards */
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313 #define FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD (1)
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315 /* SECPINT module features */
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317 /* @brief Number of connected outputs */
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318 #define FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS (2)
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320 /* SYSCON module features */
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322 /* @brief Pointer to ROM IAP entry functions */
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323 #define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205)
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324 /* @brief Flash page size in bytes */
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325 #define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (512)
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326 /* @brief Flash sector size in bytes */
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327 #define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768)
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328 /* @brief Flash size in bytes */
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329 #define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (622592)
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330 /* @brief Has Power Down mode */
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331 #define FSL_FEATURE_SYSCON_HAS_POWERDOWN_MODE (1)
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332 /* @brief CCM_ANALOG availability on the SoC. */
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333 #define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1)
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334 /* @brief Starter register discontinuous. */
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335 #define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1)
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337 /* USB module features */
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339 /* @brief Size of the USB dedicated RAM */
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340 #define FSL_FEATURE_USB_USB_RAM (0x00004000)
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341 /* @brief Base address of the USB dedicated RAM */
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342 #define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x40100000)
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343 /* @brief USB version */
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344 #define FSL_FEATURE_USB_VERSION (200)
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345 /* @brief Number of the endpoint in USB FS */
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346 #define FSL_FEATURE_USB_EP_NUM (5)
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348 /* USBFSH module features */
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350 /* @brief Size of the USB dedicated RAM */
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351 #define FSL_FEATURE_USBFSH_USB_RAM (0x00004000)
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352 /* @brief Base address of the USB dedicated RAM */
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353 #define FSL_FEATURE_USBFSH_USB_RAM_BASE_ADDRESS (0x40100000)
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354 /* @brief USBFSH version */
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355 #define FSL_FEATURE_USBFSH_VERSION (200)
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357 /* USBHSD module features */
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359 /* @brief Size of the USB dedicated RAM */
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360 #define FSL_FEATURE_USBHSD_USB_RAM (0x00004000)
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361 /* @brief Base address of the USB dedicated RAM */
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362 #define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40100000)
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363 /* @brief USBHSD version */
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364 #define FSL_FEATURE_USBHSD_VERSION (300)
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365 /* @brief Number of the endpoint in USB HS */
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366 #define FSL_FEATURE_USBHSD_EP_NUM (6)
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368 /* USBHSH module features */
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370 /* @brief Size of the USB dedicated RAM */
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371 #define FSL_FEATURE_USBHSH_USB_RAM (0x00004000)
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372 /* @brief Base address of the USB dedicated RAM */
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373 #define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000)
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374 /* @brief USBHSH version */
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375 #define FSL_FEATURE_USBHSH_VERSION (300)
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377 /* UTICK module features */
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379 /* @brief UTICK does not support PD configure. */
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380 #define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1)
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382 /* WWDT module features */
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384 /* @brief WWDT does not support oscillator lock. */
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385 #define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1)
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386 /* @brief WWDT does not support power down configure */
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387 #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1)
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389 #endif /* _LPC55S69_cm33_core0_FEATURES_H_ */
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