git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/device/fsl_device_registers.h

   1 /*\r
   2  * Copyright 2014-2016 Freescale Semiconductor, Inc.\r
   3  * Copyright 2016-2019 NXP\r
   4  * All rights reserved.\r
   5  *\r
   6  * SPDX-License-Identifier: BSD-3-Clause\r
   7  *\r
   8  */\r
   9 \r
  10 #ifndef __FSL_DEVICE_REGISTERS_H__\r
  11 #define __FSL_DEVICE_REGISTERS_H__\r
  12 \r
  13 /*\r
  14  * Include the cpu specific register header files.\r
  15  *\r
  16  * The CPU macro should be declared in the project or makefile.\r
  17  */\r
  18 #if (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || \\r
  19      defined(CPU_LPC55S69JEV98_cm33_core0))\r
  20 \r
  21 #define LPC55S69_cm33_core0_SERIES\r
  22 \r
  23 /* CMSIS-style register definitions */\r
  24 #include "LPC55S69_cm33_core0.h"\r
  25 /* CPU specific feature definitions */\r
  26 #include "LPC55S69_cm33_core0_features.h"\r
  27 \r
  28 #elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || \\r
  29        defined(CPU_LPC55S69JEV98_cm33_core1))\r
  30 \r
  31 #define LPC55S69_cm33_core1_SERIES\r
  32 \r
  33 /* CMSIS-style register definitions */\r
  34 #include "LPC55S69_cm33_core1.h"\r
  35 /* CPU specific feature definitions */\r
  36 #include "LPC55S69_cm33_core1_features.h"\r
  37 \r
  38 #else\r
  39 #error "No valid CPU defined!"\r
  40 #endif\r
  41 \r
  42 #endif /* __FSL_DEVICE_REGISTERS_H__ */\r
  43 \r
  44 /*******************************************************************************\r
  45  * EOF\r
  46  ******************************************************************************/\r