2 ** ###################################################################
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3 ** Processors: LPC55S69JBD100_cm33_core0
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4 ** LPC55S69JBD64_cm33_core0
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5 ** LPC55S69JEV98_cm33_core0
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7 ** Compilers: GNU C Compiler
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8 ** IAR ANSI C/C++ Compiler for ARM
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9 ** Keil ARM C/C++ Compiler
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10 ** MCUXpresso Compiler
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12 ** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019
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13 ** Version: rev. 1.1, 2019-05-16
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17 ** Provides a system configuration function and a global variable that
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18 ** contains the system frequency. It configures the device and initializes
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19 ** the oscillator (PLL) that is part of the microcontroller device.
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21 ** Copyright 2016 Freescale Semiconductor, Inc.
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22 ** Copyright 2016-2019 NXP
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23 ** All rights reserved.
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25 ** SPDX-License-Identifier: BSD-3-Clause
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27 ** http: www.nxp.com
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28 ** mail: support@nxp.com
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31 ** - rev. 1.0 (2018-08-22)
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32 ** Initial version based on v0.2UM
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33 ** - rev. 1.1 (2019-05-16)
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34 ** Initial A1 version based on v1.3UM
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36 ** ###################################################################
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40 * @file LPC55S69_cm33_core0
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43 * @brief Device specific configuration file for LPC55S69_cm33_core0
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44 * (implementation file)
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46 * Provides a system configuration function and a global variable that contains
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47 * the system frequency. It configures the device and initializes the oscillator
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48 * (PLL) that is part of the microcontroller device.
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52 #include "fsl_device_registers.h"
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54 /* PLL0 SSCG control1 */
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55 #define PLL_SSCG_MD_FRACT_P 0U
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56 #define PLL_SSCG_MD_INT_P 25U
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57 #define PLL_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL_SSCG_MD_FRACT_P)
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58 #define PLL_SSCG_MD_INT_M ((uint64_t)0xFFUL << PLL_SSCG_MD_INT_P)
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60 /* Get predivider (N) from PLL0 NDEC setting */
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61 static uint32_t findPll0PreDiv(void)
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63 uint32_t preDiv = 1;
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65 /* Direct input is not used? */
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66 if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) == 0)
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68 preDiv = SYSCON->PLL0NDEC & SYSCON_PLL0NDEC_NDIV_MASK;
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77 /* Get postdivider (P) from PLL0 PDEC setting */
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78 static uint32_t findPll0PostDiv(void)
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80 uint32_t postDiv = 1;
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82 if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) == 0)
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84 if (SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK)
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86 postDiv = SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK;
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90 postDiv = 2 * (SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK);
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100 /* Get multiplier (M) from PLL0 SSCG and SEL_EXT settings */
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101 static float findPll0MMult(void)
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105 uint32_t mMult_int;
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107 if (SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK)
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109 mMult = (SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) >> SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT;
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114 ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MD_MBS_MASK) << 7U) | ((SYSCON->PLL0SSCG0) >> PLL_SSCG_MD_INT_P);
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115 mMult_fract = ((float)((SYSCON->PLL0SSCG0) & PLL_SSCG_MD_FRACT_M) / (1 << PLL_SSCG_MD_INT_P));
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116 mMult = (float)mMult_int + mMult_fract;
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125 /* Get predivider (N) from PLL1 NDEC setting */
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126 static uint32_t findPll1PreDiv(void)
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128 uint32_t preDiv = 1;
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130 /* Direct input is not used? */
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131 if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) == 0)
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133 preDiv = SYSCON->PLL1NDEC & SYSCON_PLL1NDEC_NDIV_MASK;
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142 /* Get postdivider (P) from PLL1 PDEC setting */
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143 static uint32_t findPll1PostDiv(void)
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145 uint32_t postDiv = 1;
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147 if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK) == 0)
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149 if (SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK)
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151 postDiv = SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK;
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155 postDiv = 2 * (SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK);
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165 /* Get multiplier (M) from PLL1 MDEC settings */
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166 static uint32_t findPll1MMult(void)
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168 uint32_t mMult = 1;
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170 mMult = SYSCON->PLL1MDEC & SYSCON_PLL1MDEC_MDIV_MASK;
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179 /* Get FRO 12M Clk */
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180 /*! brief Return Frequency of FRO 12MHz
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181 * return Frequency of FRO 12MHz
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183 static uint32_t CLOCK_GetFro12MFreq(void)
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185 return (ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) ? 12000000U : 0U;
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188 /* Get FRO 1M Clk */
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189 /*! brief Return Frequency of FRO 1MHz
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190 * return Frequency of FRO 1MHz
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192 static uint32_t CLOCK_GetFro1MFreq(void)
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194 return (SYSCON->CLOCK_CTRL & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) ? 1000000U : 0U;
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197 /* Get EXT OSC Clk */
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198 /*! brief Return Frequency of External Clock
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199 * return Frequency of External Clock. If no external clock is used returns 0.
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201 static uint32_t CLOCK_GetExtClkFreq(void)
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203 return (ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) ? CLK_CLK_IN : 0U;
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206 /* Get HF FRO Clk */
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207 /*! brief Return Frequency of High-Freq output of FRO
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208 * return Frequency of High-Freq output of FRO
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210 static uint32_t CLOCK_GetFroHfFreq(void)
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212 return (ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) ? 96000000U : 0U;
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215 /* Get RTC OSC Clk */
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216 /*! brief Return Frequency of 32kHz osc
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217 * return Frequency of 32kHz osc
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219 static uint32_t CLOCK_GetOsc32KFreq(void)
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221 return ((!(PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)) && (!(PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK))) ?
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223 ((!(PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)) && (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK)) ?
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228 /* ----------------------------------------------------------------------------
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230 ---------------------------------------------------------------------------- */
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232 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
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234 /* ----------------------------------------------------------------------------
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236 ---------------------------------------------------------------------------- */
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238 __attribute__((weak)) void SystemInit(void)
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240 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
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241 SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access in Secure mode */
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242 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
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243 SCB_NS->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access in Normal mode */
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244 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
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245 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
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247 SCB->CPACR |= ((3UL << 0 * 2) | (3UL << 1 * 2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */
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248 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
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249 SCB_NS->CPACR |= ((3UL << 0 * 2) | (3UL << 1 * 2)); /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */
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250 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
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252 SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */
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254 #if defined(__MCUXPRESSO)
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255 extern void (*const g_pfnVectors[])(void);
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256 SCB->VTOR = (uint32_t)&g_pfnVectors;
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258 extern void *__Vectors;
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259 SCB->VTOR = (uint32_t)&__Vectors;
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261 SYSCON->TRACECLKDIV = 0;
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262 /* Optionally enable RAM banks that may be off by default at reset */
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263 #if !defined(DONT_ENABLE_DISABLED_RAMBANKS)
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264 SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK | SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK |
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265 SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK | SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK;
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270 /* ----------------------------------------------------------------------------
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271 -- SystemCoreClockUpdate()
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272 ---------------------------------------------------------------------------- */
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274 void SystemCoreClockUpdate(void)
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276 uint32_t clkRate = 0;
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277 uint32_t prediv, postdiv;
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279 uint64_t workRate1;
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281 switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK)
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283 case 0x00: /* MAINCLKSELA clock (main_clk_a)*/
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284 switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK)
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286 case 0x00: /* FRO 12 MHz (fro_12m) */
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287 clkRate = CLOCK_GetFro12MFreq();
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289 case 0x01: /* CLKIN (clk_in) */
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290 clkRate = CLOCK_GetExtClkFreq();
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292 case 0x02: /* Fro 1MHz (fro_1m) */
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293 clkRate = CLOCK_GetFro1MFreq();
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295 default: /* = 0x03 = FRO 96 MHz (fro_hf) */
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296 clkRate = CLOCK_GetFroHfFreq();
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300 case 0x01: /* PLL0 clock (pll0_clk)*/
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301 switch (SYSCON->PLL0CLKSEL & SYSCON_PLL0CLKSEL_SEL_MASK)
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303 case 0x00: /* FRO 12 MHz (fro_12m) */
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304 clkRate = CLOCK_GetFro12MFreq();
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306 case 0x01: /* CLKIN (clk_in) */
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307 clkRate = CLOCK_GetExtClkFreq();
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309 case 0x02: /* Fro 1MHz (fro_1m) */
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310 clkRate = CLOCK_GetFro1MFreq();
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312 case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
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313 clkRate = CLOCK_GetOsc32KFreq();
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318 if (((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPLL_MASK) == 0) &&
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319 (SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_CLKEN_MASK) &&
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320 ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_MASK) == 0) &&
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321 ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) == 0))
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323 prediv = findPll0PreDiv();
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324 postdiv = findPll0PostDiv();
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325 /* Adjust input clock */
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326 clkRate = clkRate / prediv;
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327 /* MDEC used for rate */
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328 workRate = (float)clkRate * (float)findPll0MMult();
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329 clkRate = (uint32_t)(workRate / ((float)postdiv));
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332 case 0x02: /* PLL1 clock (pll1_clk)*/
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333 switch (SYSCON->PLL1CLKSEL & SYSCON_PLL1CLKSEL_SEL_MASK)
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335 case 0x00: /* FRO 12 MHz (fro_12m) */
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336 clkRate = CLOCK_GetFro12MFreq();
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338 case 0x01: /* CLKIN (clk_in) */
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339 clkRate = CLOCK_GetExtClkFreq();
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341 case 0x02: /* Fro 1MHz (fro_1m) */
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342 clkRate = CLOCK_GetFro1MFreq();
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344 case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
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345 clkRate = CLOCK_GetOsc32KFreq();
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350 if (((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPLL_MASK) == 0) &&
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351 (SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_CLKEN_MASK) &&
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352 ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL1_MASK) == 0))
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354 /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */
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355 prediv = findPll1PreDiv();
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356 postdiv = findPll1PostDiv();
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357 /* Adjust input clock */
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358 clkRate = clkRate / prediv;
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360 /* MDEC used for rate */
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361 workRate1 = (uint64_t)clkRate * (uint64_t)findPll1MMult();
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362 clkRate = workRate1 / ((uint64_t)postdiv);
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365 case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
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366 clkRate = CLOCK_GetOsc32KFreq();
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371 SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFF) + 1);
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374 /* ----------------------------------------------------------------------------
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375 -- SystemInitHook()
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376 ---------------------------------------------------------------------------- */
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378 __attribute__((weak)) void SystemInitHook(void)
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380 /* Void implementation of the weak function. */
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