2 * Copyright (c) 2017 - 2018 , NXP
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3 * All rights reserved.
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5 * SPDX-License-Identifier: BSD-3-Clause
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8 #include "fsl_common.h"
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9 #include "fsl_clock.h"
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10 #include "fsl_power.h"
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11 /*******************************************************************************
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13 ******************************************************************************/
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14 /* Component ID definition, used by tools. */
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15 #ifndef FSL_COMPONENT_ID
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16 #define FSL_COMPONENT_ID "platform.drivers.clock"
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18 #define NVALMAX (0x100U)
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19 #define PVALMAX (0x20U)
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20 #define MVALMAX (0x10000U)
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22 #define PLL_MAX_N_DIV 0x100U
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24 /*--------------------------------------------------------------------------
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25 !!! If required these #defines can be moved to chip library file
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26 ----------------------------------------------------------------------------*/
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28 #define PLL_SSCG1_MDEC_VAL_P (10U) /* MDEC is in bits 16 downto 0 */
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29 #define PLL_SSCG1_MDEC_VAL_M (0x3FFFC00ULL << PLL_SSCG1_MDEC_VAL_P) /* NDEC is in bits 9 downto 0 */
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30 #define PLL_NDEC_VAL_P (0U) /* NDEC is in bits 9:0 */
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31 #define PLL_NDEC_VAL_M (0xFFUL << PLL_NDEC_VAL_P)
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32 #define PLL_PDEC_VAL_P (0U) /*!< PDEC is in bits 6:0 */
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33 #define PLL_PDEC_VAL_M (0x1FUL << PLL_PDEC_VAL_P)
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35 #define PLL_MIN_CCO_FREQ_MHZ (275000000U)
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36 #define PLL_MAX_CCO_FREQ_MHZ (550000000U)
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37 #define PLL_LOWER_IN_LIMIT (2000U) /*!< Minimum PLL input rate */
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38 #define PLL_HIGHER_IN_LIMIT (150000000U) /*!< Maximum PLL input rate */
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39 #define PLL_MIN_IN_SSMODE (3000000U)
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40 #define PLL_MAX_IN_SSMODE (100000000U) /*!< Not find the value in UM, Just use the maximum frequency which device support */
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43 #define PLL_NDEC_VAL_SET(value) (((unsigned long)(value) << PLL_NDEC_VAL_P) & PLL_NDEC_VAL_M)
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45 #define PLL_PDEC_VAL_SET(value) (((unsigned long)(value) << PLL_PDEC_VAL_P) & PLL_PDEC_VAL_M)
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47 #define PLL_SSCG1_MDEC_VAL_SET(value) (((unsigned long)(value) << PLL_SSCG1_MDEC_VAL_P) & PLL_SSCG1_MDEC_VAL_M)
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49 /* PLL0 SSCG control1 */
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50 #define PLL0_SSCG_MD_FRACT_P 0U
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51 #define PLL0_SSCG_MD_INT_P 25U
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52 #define PLL0_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL0_SSCG_MD_FRACT_P)
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53 #define PLL0_SSCG_MD_INT_M ((uint64_t)0xFFUL << PLL0_SSCG_MD_INT_P)
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55 #define PLL0_SSCG_MD_FRACT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_FRACT_P) & PLL0_SSCG_MD_FRACT_M)
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56 #define PLL0_SSCG_MD_INT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_INT_P) & PLL0_SSCG_MD_INT_M)
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58 /* Saved value of PLL output rate, computed whenever needed to save run-time
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59 computation on each call to retrive the PLL rate. */
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60 static uint32_t s_Pll0_Freq;
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61 static uint32_t s_Pll1_Freq;
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63 /** External clock rate on the CLKIN pin in Hz. If not used,
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64 set this to 0. Otherwise, set it to the exact rate in Hz this pin is
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66 static uint32_t s_Ext_Clk_Freq = 16000000U;
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67 static uint32_t s_I2S_Mclk_Freq = 0U;
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69 /*******************************************************************************
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71 ******************************************************************************/
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73 /*******************************************************************************
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75 ******************************************************************************/
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76 /* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */
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77 static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR);
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78 /* Get predivider (N) from PLL0 NDEC setting */
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79 static uint32_t findPll0PreDiv(void);
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80 /* Get predivider (N) from PLL1 NDEC setting */
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81 static uint32_t findPll1PreDiv(void);
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82 /* Get postdivider (P) from PLL0 PDEC setting */
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83 static uint32_t findPll0PostDiv(void);
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84 /* Get multiplier (M) from PLL0 MDEC and SSCG settings */
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85 static float findPll0MMult(void);
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86 /* Get the greatest common divisor */
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87 static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n);
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88 /* Set PLL output based on desired output rate */
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89 static pll_error_t CLOCK_GetPll0Config(
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90 uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS);
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91 /* Update local PLL rate variable */
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92 static void CLOCK_GetPLL0OutFromSetupUpdate(pll_setup_t *pSetup);
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94 /*******************************************************************************
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96 ******************************************************************************/
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98 /* Clock Selection for IP */
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100 * brief Configure the clock selection muxes.
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101 * param connection : Clock to be configured.
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104 void CLOCK_AttachClk(clock_attach_id_t connection)
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110 volatile uint32_t *pClkSel;
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112 pClkSel = &(SYSCON->SYSTICKCLKSELX[0]);
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114 if (connection != kNONE_to_NONE)
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116 for (i = 0U; i < 2U; i++)
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118 if (connection == 0U)
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122 item = (uint16_t)GET_ID_ITEM(connection);
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125 mux = GET_ID_ITEM_MUX(item);
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126 sel = GET_ID_ITEM_SEL(item);
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127 if (mux == CM_RTCOSC32KCLKSEL)
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129 PMC->RTCOSC32K |= sel;
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133 pClkSel[mux] = sel;
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136 connection = GET_ID_NEXT_ITEM(connection); /* pick up next descriptor */
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141 /* Return the actual clock attach id */
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143 * brief Get the actual clock attach id.
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144 * This fuction uses the offset in input attach id, then it reads the actual source value in
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145 * the register and combine the offset to obtain an actual attach id.
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146 * param attachId : Clock attach id to get.
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147 * return Clock source value.
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149 clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId)
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154 uint32_t actualAttachId = 0U;
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155 uint32_t selector = GET_ID_SELECTOR(attachId);
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156 volatile uint32_t *pClkSel;
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158 pClkSel = &(SYSCON->SYSTICKCLKSELX[0]);
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160 if (attachId == kNONE_to_NONE)
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162 return kNONE_to_NONE;
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165 for (i = 0U; i < 2U; i++)
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167 mux = GET_ID_ITEM_MUX(attachId);
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170 if (mux == CM_RTCOSC32KCLKSEL)
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172 actualSel = PMC->RTCOSC32K;
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176 actualSel = pClkSel[mux];
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179 /* Consider the combination of two registers */
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180 actualAttachId |= CLK_ATTACH_ID(mux, actualSel, i);
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182 attachId = GET_ID_NEXT_ITEM(attachId); /*!< pick up next descriptor */
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185 actualAttachId |= selector;
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187 return (clock_attach_id_t)actualAttachId;
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190 /* Set IP Clock Divider */
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192 * brief Setup peripheral clock dividers.
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193 * param div_name : Clock divider name
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194 * param divided_by_value: Value to be divided
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195 * param reset : Whether to reset the divider counter.
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198 void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset)
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200 volatile uint32_t *pClkDiv;
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202 pClkDiv = &(SYSCON->SYSTICKCLKDIV0);
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205 pClkDiv[div_name] = 1U << 29U;
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207 if (divided_by_value == 0U) /*!< halt */
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209 pClkDiv[div_name] = 1U << 30U;
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213 pClkDiv[div_name] = (divided_by_value - 1U);
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217 /* Set RTC 1KHz Clock Divider */
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219 * brief Setup rtc 1khz clock divider.
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220 * param divided_by_value: Value to be divided
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223 void CLOCK_SetRtc1khzClkDiv(uint32_t divided_by_value)
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225 PMC->RTCOSC32K |= (((divided_by_value - 28U) << PMC_RTCOSC32K_CLK1KHZDIV_SHIFT) | PMC_RTCOSC32K_CLK1KHZDIV_MASK);
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228 /* Set RTC 1KHz Clock Divider */
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230 * brief Setup rtc 1hz clock divider.
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231 * param divided_by_value: Value to be divided
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234 void CLOCK_SetRtc1hzClkDiv(uint32_t divided_by_value)
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236 if (divided_by_value == 0U) /*!< halt */
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238 PMC->RTCOSC32K |= (1U << PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT);
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243 (((divided_by_value - 31744U) << PMC_RTCOSC32K_CLK1HZDIV_SHIFT) | PMC_RTCOSC32K_CLK1HZDIV_MASK);
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247 /* Set FRO Clocking */
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249 * brief Initialize the Core clock to given frequency (12, 48 or 96 MHz).
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250 * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is
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252 * param iFreq : Desired frequency (must be one of #CLK_FRO_12MHZ or #CLK_FRO_48MHZ or #CLK_FRO_96MHZ)
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253 * return returns success or fail status.
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255 status_t CLOCK_SetupFROClocking(uint32_t iFreq)
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257 if ((iFreq != 12000000U) && (iFreq != 48000000U) && (iFreq != 96000000U))
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259 return kStatus_Fail;
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261 /* Enable Analog Control module */
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262 SYSCON->PRESETCTRLCLR[2] = (1U << SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT);
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263 SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK;
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264 /* Power up the FRO192M */
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265 POWER_DisablePD(kPDRUNCFG_PD_FRO192M);
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267 if (iFreq == 96000000U)
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269 ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_96MHZCLK(1);
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271 else if (iFreq == 48000000U)
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273 ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_48MHZCLK(1);
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277 ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_12MHZCLK(1);
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282 /* Set the FLASH wait states for the passed frequency */
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284 * brief Set the flash wait states for the input freuqency.
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285 * param iFreq : Input frequency
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288 void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq)
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290 uint32_t num_wait_states;
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291 float f_num_wait_states = 0.00000009 * ((float)iFreq);
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292 /* Rational : timing is closed at 100MHz+10% tolerance, hence the ¡®9¡¯ in the formula above */
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293 num_wait_states = (uint32_t)f_num_wait_states;
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296 * It is guaranteed by design that "num_wait_states = 8"
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297 * will fit all frequencies (below and including) 100 MHz.
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299 if (num_wait_states >= 9)
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301 num_wait_states = 8;
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304 /* Don't alter other bits */
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305 SYSCON->FMCCR = (SYSCON->FMCCR & ~SYSCON_FMCCR_FMCTIM_MASK) |
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306 ((num_wait_states << SYSCON_FMCCR_FMCTIM_SHIFT) & SYSCON_FMCCR_FMCTIM_MASK);
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309 /* Set EXT OSC Clk */
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311 * brief Initialize the external osc clock to given frequency.
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312 * param iFreq : Desired frequency (must be equal to exact rate in Hz)
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313 * return returns success or fail status.
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315 status_t CLOCK_SetupExtClocking(uint32_t iFreq)
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317 if (iFreq >= 32000000U)
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319 return kStatus_Fail;
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321 /* Turn on power for crystal 32 MHz */
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322 POWER_DisablePD(kPDRUNCFG_PD_XTAL32M);
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323 POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M);
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324 /* Enable clock_in clock for clock module. */
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325 SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK;
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327 s_Ext_Clk_Freq = iFreq;
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331 /* Set I2S MCLK Clk */
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333 * brief Initialize the I2S MCLK clock to given frequency.
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334 * param iFreq : Desired frequency (must be equal to exact rate in Hz)
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335 * return returns success or fail status.
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337 status_t CLOCK_SetupI2SMClkClocking(uint32_t iFreq)
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339 s_I2S_Mclk_Freq = iFreq;
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343 /* Get CLOCK OUT Clk */
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344 /*! brief Return Frequency of ClockOut
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345 * return Frequency of ClockOut
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347 uint32_t CLOCK_GetClockOutClkFreq(void)
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349 uint32_t freq = 0U;
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351 switch (SYSCON->CLKOUTSEL)
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354 freq = CLOCK_GetCoreSysClkFreq();
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358 freq = CLOCK_GetPll0OutFreq();
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362 freq = CLOCK_GetExtClkFreq();
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366 freq = CLOCK_GetFroHfFreq();
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370 freq = CLOCK_GetFro1MFreq();
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374 freq = CLOCK_GetPll1OutFreq();
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378 freq = CLOCK_GetOsc32KFreq();
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388 return freq / ((SYSCON->CLKOUTDIV & 0xffU) + 1U);
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392 /*! brief Return Frequency of Adc Clock
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393 * return Frequency of Adc.
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395 uint32_t CLOCK_GetAdcClkFreq(void)
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397 uint32_t freq = 0U;
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399 switch (SYSCON->ADCCLKSEL)
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402 freq = CLOCK_GetCoreSysClkFreq();
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405 freq = CLOCK_GetPll0OutFreq();
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408 freq = CLOCK_GetFroHfFreq();
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418 return freq / ((SYSCON->ADCCLKDIV & SYSCON_ADCCLKDIV_DIV_MASK) + 1U);
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422 /*! brief Return Frequency of Usb0 Clock
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423 * return Frequency of Usb0 Clock.
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425 uint32_t CLOCK_GetUsb0ClkFreq(void)
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427 uint32_t freq = 0U;
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429 switch (SYSCON->USB0CLKSEL)
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432 freq = CLOCK_GetCoreSysClkFreq();
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435 freq = CLOCK_GetPll0OutFreq();
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438 freq = CLOCK_GetFroHfFreq();
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441 freq = CLOCK_GetPll1OutFreq();
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451 return freq / ((SYSCON->USB0CLKDIV & 0xffU) + 1U);
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455 /*! brief Return Frequency of Usb1 Clock
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456 * return Frequency of Usb1 Clock.
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458 uint32_t CLOCK_GetUsb1ClkFreq(void)
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460 return (ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK) ? s_Ext_Clk_Freq : 0U;
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464 /*! brief Return Frequency of MClk Clock
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465 * return Frequency of MClk Clock.
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467 uint32_t CLOCK_GetMclkClkFreq(void)
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469 uint32_t freq = 0U;
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471 switch (SYSCON->MCLKCLKSEL)
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474 freq = CLOCK_GetFroHfFreq();
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477 freq = CLOCK_GetPll0OutFreq();
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487 return freq / ((SYSCON->MCLKDIV & 0xffU) + 1U);
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490 /* Get SCTIMER Clk */
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491 /*! brief Return Frequency of SCTimer Clock
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492 * return Frequency of SCTimer Clock.
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494 uint32_t CLOCK_GetSctClkFreq(void)
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496 uint32_t freq = 0U;
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498 switch (SYSCON->SCTCLKSEL)
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501 freq = CLOCK_GetCoreSysClkFreq();
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504 freq = CLOCK_GetPll0OutFreq();
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507 freq = CLOCK_GetExtClkFreq();
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510 freq = CLOCK_GetFroHfFreq();
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513 freq = CLOCK_GetI2SMClkFreq();
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523 return freq / ((SYSCON->SCTCLKDIV & 0xffU) + 1U);
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527 /*! brief Return Frequency of SDIO Clock
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528 * return Frequency of SDIO Clock.
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530 uint32_t CLOCK_GetSdioClkFreq(void)
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532 uint32_t freq = 0U;
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534 switch (SYSCON->SDIOCLKSEL)
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537 freq = CLOCK_GetCoreSysClkFreq();
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540 freq = CLOCK_GetPll0OutFreq();
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543 freq = CLOCK_GetFroHfFreq();
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546 freq = CLOCK_GetPll1OutFreq();
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555 return freq / ((SYSCON->SDIOCLKDIV & 0xffU) + 1U);
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558 /* Get FRO 12M Clk */
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559 /*! brief Return Frequency of FRO 12MHz
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560 * return Frequency of FRO 12MHz
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562 uint32_t CLOCK_GetFro12MFreq(void)
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564 return (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO192M_MASK) ?
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566 (ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) ? 12000000U : 0U;
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569 /* Get FRO 1M Clk */
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570 /*! brief Return Frequency of FRO 1MHz
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571 * return Frequency of FRO 1MHz
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573 uint32_t CLOCK_GetFro1MFreq(void)
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575 return (SYSCON->CLOCK_CTRL & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) ? 1000000U : 0U;
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578 /* Get EXT OSC Clk */
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579 /*! brief Return Frequency of External Clock
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580 * return Frequency of External Clock. If no external clock is used returns 0.
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582 uint32_t CLOCK_GetExtClkFreq(void)
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584 return (ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) ? s_Ext_Clk_Freq : 0U;
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587 /* Get WATCH DOG Clk */
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588 /*! brief Return Frequency of Watchdog
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589 * return Frequency of Watchdog
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591 uint32_t CLOCK_GetWdtClkFreq(void)
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593 return CLOCK_GetFro1MFreq() / ((SYSCON->WDTCLKDIV & SYSCON_WDTCLKDIV_DIV_MASK) + 1U);
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596 /* Get HF FRO Clk */
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597 /*! brief Return Frequency of High-Freq output of FRO
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598 * return Frequency of High-Freq output of FRO
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600 uint32_t CLOCK_GetFroHfFreq(void)
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602 return (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO192M_MASK) ?
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604 (ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) ? 96000000U : 0U;
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607 /* Get SYSTEM PLL Clk */
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608 /*! brief Return Frequency of PLL
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609 * return Frequency of PLL
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611 uint32_t CLOCK_GetPll0OutFreq(void)
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613 return s_Pll0_Freq;
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616 /* Get USB PLL Clk */
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617 /*! brief Return Frequency of USB PLL
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618 * return Frequency of PLL
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620 uint32_t CLOCK_GetPll1OutFreq(void)
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622 return s_Pll1_Freq;
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625 /* Get RTC OSC Clk */
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626 /*! brief Return Frequency of 32kHz osc
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627 * return Frequency of 32kHz osc
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629 uint32_t CLOCK_GetOsc32KFreq(void)
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631 return ((~(PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)) && (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL(0))) ?
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633 ((~(PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)) && (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL(1))) ?
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639 /*! brief Return Frequency of Core System
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640 * return Frequency of Core System
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642 uint32_t CLOCK_GetCoreSysClkFreq(void)
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644 uint32_t freq = 0U;
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646 switch (SYSCON->MAINCLKSELB)
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649 if (SYSCON->MAINCLKSELA == 0U)
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651 freq = CLOCK_GetFro12MFreq();
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653 else if (SYSCON->MAINCLKSELA == 1U)
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655 freq = CLOCK_GetExtClkFreq();
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657 else if (SYSCON->MAINCLKSELA == 2U)
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659 freq = CLOCK_GetFro1MFreq();
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661 else if (SYSCON->MAINCLKSELA == 3U)
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663 freq = CLOCK_GetFroHfFreq();
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670 freq = CLOCK_GetPll0OutFreq();
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673 freq = CLOCK_GetPll1OutFreq();
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677 freq = CLOCK_GetOsc32KFreq();
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687 /* Get I2S MCLK Clk */
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688 /*! brief Return Frequency of I2S MCLK Clock
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689 * return Frequency of I2S MCLK Clock
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691 uint32_t CLOCK_GetI2SMClkFreq(void)
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693 return s_I2S_Mclk_Freq;
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696 /* Get FLEXCOMM input clock */
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697 /*! brief Return Frequency of flexcomm input clock
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698 * param id : flexcomm instance id
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699 * return Frequency value
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701 uint32_t CLOCK_GetFlexCommInputClock(uint32_t id)
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703 uint32_t freq = 0U;
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705 switch (SYSCON->FCCLKSELX[id])
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708 freq = CLOCK_GetCoreSysClkFreq();
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711 freq = CLOCK_GetPll0OutFreq() / ((SYSCON->PLL0CLKDIV & 0xffU) + 1U);
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714 freq = CLOCK_GetFro12MFreq();
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717 freq = CLOCK_GetFroHfFreq() / ((SYSCON->FROHFDIV & 0xffU) + 1U);
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720 freq = CLOCK_GetFro1MFreq();
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723 freq = CLOCK_GetI2SMClkFreq();
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726 freq = CLOCK_GetOsc32KFreq();
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739 /* Get FLEXCOMM Clk */
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740 uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id)
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742 uint32_t freq = 0U;
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744 freq = CLOCK_GetFlexCommInputClock(id);
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746 (SYSCON->FLEXFRGXCTRL[id] & SYSCON_FLEXFRG0CTRL_MULT_MASK) /
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747 ((SYSCON->FLEXFRGXCTRL[id] & SYSCON_FLEXFRG0CTRL_DIV_MASK) + 1U));
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750 /* Get HS_LPSI Clk */
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751 uint32_t CLOCK_GetHsLspiClkFreq(void)
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753 uint32_t freq = 0U;
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755 switch (SYSCON->HSLSPICLKSEL)
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758 freq = CLOCK_GetCoreSysClkFreq();
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761 freq = CLOCK_GetPll0OutFreq() / ((SYSCON->PLL0CLKDIV & 0xffU) + 1U);
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764 freq = CLOCK_GetFro12MFreq();
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767 freq = CLOCK_GetFroHfFreq() / ((SYSCON->FROHFDIV & 0xffU) + 1U);
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770 freq = CLOCK_GetFro1MFreq();
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773 freq = CLOCK_GetOsc32KFreq();
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786 /* Get CTimer Clk */
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787 /*! brief Return Frequency of CTimer functional Clock
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788 * return Frequency of CTimer functional Clock
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790 uint32_t CLOCK_GetCTimerClkFreq(uint32_t id)
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792 uint32_t freq = 0U;
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794 switch (SYSCON->CTIMERCLKSELX[id])
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797 freq = CLOCK_GetCoreSysClkFreq();
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800 freq = CLOCK_GetPll0OutFreq();
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803 freq = CLOCK_GetFroHfFreq();
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806 freq = CLOCK_GetFro1MFreq();
\r
809 freq = CLOCK_GetI2SMClkFreq();
\r
812 freq = CLOCK_GetOsc32KFreq();
\r
825 /* Get Systick Clk */
\r
826 /*! brief Return Frequency of SystickClock
\r
827 * return Frequency of Systick Clock
\r
829 uint32_t CLOCK_GetSystickClkFreq(uint32_t id)
\r
831 volatile uint32_t *pSystickClkDiv;
\r
832 pSystickClkDiv = &(SYSCON->SYSTICKCLKDIV0);
\r
833 uint32_t freq = 0U;
\r
835 switch (SYSCON->SYSTICKCLKSELX[id])
\r
838 freq = CLOCK_GetCoreSysClkFreq() / ((pSystickClkDiv[id] & 0xffU) + 1U);
\r
841 freq = CLOCK_GetFro1MFreq();
\r
844 freq = CLOCK_GetOsc32KFreq();
\r
857 /* Set FlexComm Clock */
\r
859 * brief Set the flexcomm output frequency.
\r
860 * param id : flexcomm instance id
\r
861 * freq : output frequency
\r
862 * return 0 : the frequency range is out of range.
\r
863 * 1 : switch successfully.
\r
865 uint32_t CLOCK_SetFlexCommClock(uint32_t id, uint32_t freq)
\r
867 uint32_t input = CLOCK_GetFlexCommClkFreq(id);
\r
870 if ((freq > 48000000) || (freq > input) || (input / freq >= 2))
\r
872 /* FRG output frequency should be less than equal to 48MHz */
\r
877 mul = ((uint64_t)(input - freq) * 256) / ((uint64_t)freq);
\r
878 SYSCON->FLEXFRGXCTRL[id] = (mul << 8U) | 0xFFU;
\r
884 /*! brief Return Frequency of selected clock
\r
885 * return Frequency of selected clock
\r
887 uint32_t CLOCK_GetFreq(clock_name_t clockName)
\r
892 case kCLOCK_CoreSysClk:
\r
893 freq = CLOCK_GetCoreSysClkFreq();
\r
895 case kCLOCK_BusClk:
\r
896 freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U);
\r
898 case kCLOCK_ClockOut:
\r
899 freq = CLOCK_GetClockOutClkFreq();
\r
902 freq = CLOCK_GetAdcClkFreq();
\r
905 freq = CLOCK_GetUsb0ClkFreq();
\r
908 freq = CLOCK_GetUsb1ClkFreq();
\r
910 case kCLOCK_Pll1Out:
\r
911 freq = CLOCK_GetPll1OutFreq();
\r
914 freq = CLOCK_GetMclkClkFreq();
\r
917 freq = CLOCK_GetFroHfFreq();
\r
919 case kCLOCK_Fro12M:
\r
920 freq = CLOCK_GetFro12MFreq();
\r
922 case kCLOCK_ExtClk:
\r
923 freq = CLOCK_GetExtClkFreq();
\r
925 case kCLOCK_Pll0Out:
\r
926 freq = CLOCK_GetPll0OutFreq();
\r
928 case kCLOCK_WdtClk:
\r
929 freq = CLOCK_GetWdtClkFreq();
\r
932 freq = CLOCK_GetSctClkFreq();
\r
935 freq = CLOCK_GetSdioClkFreq();
\r
937 case kCLOCK_FlexI2S:
\r
938 freq = CLOCK_GetI2SMClkFreq();
\r
940 case kCLOCK_Flexcomm0:
\r
941 freq = CLOCK_GetFlexCommClkFreq(0U);
\r
943 case kCLOCK_Flexcomm1:
\r
944 freq = CLOCK_GetFlexCommClkFreq(1U);
\r
946 case kCLOCK_Flexcomm2:
\r
947 freq = CLOCK_GetFlexCommClkFreq(2U);
\r
949 case kCLOCK_Flexcomm3:
\r
950 freq = CLOCK_GetFlexCommClkFreq(3U);
\r
952 case kCLOCK_Flexcomm4:
\r
953 freq = CLOCK_GetFlexCommClkFreq(4U);
\r
955 case kCLOCK_Flexcomm5:
\r
956 freq = CLOCK_GetFlexCommClkFreq(5U);
\r
958 case kCLOCK_Flexcomm6:
\r
959 freq = CLOCK_GetFlexCommClkFreq(6U);
\r
961 case kCLOCK_Flexcomm7:
\r
962 freq = CLOCK_GetFlexCommClkFreq(7U);
\r
964 case kCLOCK_HsLspi:
\r
965 freq = CLOCK_GetHsLspiClkFreq();
\r
967 case kCLOCK_CTmier0:
\r
968 freq = CLOCK_GetCTimerClkFreq(0U);
\r
970 case kCLOCK_CTmier1:
\r
971 freq = CLOCK_GetCTimerClkFreq(1U);
\r
973 case kCLOCK_CTmier2:
\r
974 freq = CLOCK_GetCTimerClkFreq(2U);
\r
976 case kCLOCK_CTmier3:
\r
977 freq = CLOCK_GetCTimerClkFreq(3U);
\r
979 case kCLOCK_CTmier4:
\r
980 freq = CLOCK_GetCTimerClkFreq(4U);
\r
982 case kCLOCK_Systick0:
\r
983 freq = CLOCK_GetSystickClkFreq(0U);
\r
985 case kCLOCK_Systick1:
\r
986 freq = CLOCK_GetSystickClkFreq(1U);
\r
995 /* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */
\r
996 static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR)
\r
998 uint32_t seli, selp;
\r
999 /* bandwidth: compute selP from Multiplier */
\r
1000 if (SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK)
\r
1002 selp = (M >> 2U) + 1U;
\r
1013 else if (M >= 16384)
\r
1017 else if (M >= 4096)
\r
1021 else if (M >= 1002)
\r
1025 else if (M >= 120)
\r
1027 seli = 4 * ((1024/(M/2 + 9)) + 1);
\r
1031 seli = 4 * (M/8 + 1);
\r
1050 /* Get predivider (N) from PLL0 NDEC setting */
\r
1051 static uint32_t findPll0PreDiv(void)
\r
1053 uint32_t preDiv = 1;
\r
1055 /* Direct input is not used? */
\r
1056 if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) == 0)
\r
1058 preDiv = SYSCON->PLL0NDEC & SYSCON_PLL0NDEC_NDIV_MASK;
\r
1067 /* Get predivider (N) from PLL1 NDEC setting */
\r
1068 static uint32_t findPll1PreDiv(void)
\r
1070 uint32_t preDiv = 1;
\r
1072 /* Direct input is not used? */
\r
1073 if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) == 0)
\r
1075 preDiv = SYSCON->PLL1NDEC & SYSCON_PLL1NDEC_NDIV_MASK;
\r
1084 /* Get postdivider (P) from PLL0 PDEC setting */
\r
1085 static uint32_t findPll0PostDiv(void)
\r
1087 uint32_t postDiv = 1;
\r
1089 if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) == 0)
\r
1091 if (SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK)
\r
1093 postDiv = SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK;
\r
1097 postDiv = 2 * (SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK);
\r
1107 /* Get multiplier (M) from PLL0 SSCG and SEL_EXT settings */
\r
1108 static float findPll0MMult(void)
\r
1111 float mMult_fract;
\r
1112 uint32_t mMult_int;
\r
1114 if (SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK)
\r
1116 mMult = (SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) >> SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT;
\r
1120 mMult_int = ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MD_MBS_MASK) << 7U) | ((SYSCON->PLL0SSCG0) >> PLL0_SSCG_MD_INT_P);
\r
1121 mMult_fract = ((float)((SYSCON->PLL0SSCG0) & PLL0_SSCG_MD_FRACT_M)/(1 << PLL0_SSCG_MD_INT_P));
\r
1122 mMult = (float)mMult_int + mMult_fract;
\r
1132 /* Find greatest common divisor between m and n */
\r
1133 static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n)
\r
1148 * Set PLL0 output based on desired output rate.
\r
1149 * In this function, the it calculates the PLL0 setting for output frequency from input clock
\r
1150 * frequency. The calculation would cost a few time. So it is not recommaned to use it frequently.
\r
1151 * the "pllctrl", "pllndec", "pllpdec", "pllmdec" would updated in this function.
\r
1153 static pll_error_t CLOCK_GetPll0ConfigInternal(
\r
1154 uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS)
\r
1156 uint32_t nDivOutHz, fccoHz;
\r
1157 uint32_t pllPreDivider, pllMultiplier, pllPostDivider;
\r
1158 uint32_t pllDirectInput, pllDirectOutput;
\r
1159 uint32_t pllSelP, pllSelI, pllSelR, uplimoff;
\r
1161 /* Baseline parameters (no input or output dividers) */
\r
1162 pllPreDivider = 1U; /* 1 implies pre-divider will be disabled */
\r
1163 pllPostDivider = 1U; /* 1 implies post-divider will be disabled */
\r
1164 pllDirectOutput = 1U;
\r
1166 /* Verify output rate parameter */
\r
1167 if (foutHz > PLL_MAX_CCO_FREQ_MHZ)
\r
1169 /* Maximum PLL output with post divider=1 cannot go above this frequency */
\r
1170 return kStatus_PLL_OutputTooHigh;
\r
1172 if (foutHz < (PLL_MIN_CCO_FREQ_MHZ / (PVALMAX << 1U)))
\r
1174 /* Minmum PLL output with maximum post divider cannot go below this frequency */
\r
1175 return kStatus_PLL_OutputTooLow;
\r
1178 /* If using SS mode, input clock needs to be between 3MHz and 20MHz */
\r
1181 /* Verify input rate parameter */
\r
1182 if (finHz < PLL_MIN_IN_SSMODE)
\r
1184 /* Input clock into the PLL cannot be lower than this */
\r
1185 return kStatus_PLL_InputTooLow;
\r
1187 /* PLL input in SS mode must be under 20MHz */
\r
1188 if (finHz > (PLL_MAX_IN_SSMODE * NVALMAX))
\r
1190 return kStatus_PLL_InputTooHigh;
\r
1195 /* Verify input rate parameter */
\r
1196 if (finHz < PLL_LOWER_IN_LIMIT)
\r
1198 /* Input clock into the PLL cannot be lower than this */
\r
1199 return kStatus_PLL_InputTooLow;
\r
1201 if (finHz > PLL_HIGHER_IN_LIMIT)
\r
1203 /* Input clock into the PLL cannot be higher than this */
\r
1204 return kStatus_PLL_InputTooHigh;
\r
1208 /* Find the optimal CCO frequency for the output and input that
\r
1209 will keep it inside the PLL CCO range. This may require
\r
1210 tweaking the post-divider for the PLL. */
\r
1212 while (fccoHz < PLL_MIN_CCO_FREQ_MHZ)
\r
1214 /* CCO output is less than minimum CCO range, so the CCO output
\r
1215 needs to be bumped up and the post-divider is used to bring
\r
1216 the PLL output back down. */
\r
1218 if (pllPostDivider > PVALMAX)
\r
1220 return kStatus_PLL_OutsideIntLimit;
\r
1223 /* Target CCO goes up, PLL output goes down */
\r
1224 /* divide-by-2 divider in the post-divider is always work*/
\r
1225 fccoHz = foutHz * (pllPostDivider * 2U);
\r
1226 pllDirectOutput = 0U;
\r
1229 /* Determine if a pre-divider is needed to get the best frequency */
\r
1230 if ((finHz > PLL_LOWER_IN_LIMIT) && (fccoHz >= finHz) && (useSS == false))
\r
1232 uint32_t a = FindGreatestCommonDivisor(fccoHz, finHz);
\r
1234 if (a > PLL_LOWER_IN_LIMIT)
\r
1237 if ((a != 0U) && (a < PLL_MAX_N_DIV))
\r
1239 pllPreDivider = a;
\r
1244 /* Bypass pre-divider hardware if pre-divider is 1 */
\r
1245 if (pllPreDivider > 1U)
\r
1247 pllDirectInput = 0U;
\r
1251 pllDirectInput = 1U;
\r
1254 /* Determine PLL multipler */
\r
1255 nDivOutHz = (finHz / pllPreDivider);
\r
1256 pllMultiplier = (fccoHz / nDivOutHz);
\r
1258 /* Find optimal values for filter */
\r
1259 if (useSS == false)
\r
1261 /* Will bumping up M by 1 get us closer to the desired CCO frequency? */
\r
1262 if ((nDivOutHz * ((pllMultiplier * 2U) + 1U)) < (fccoHz * 2U))
\r
1267 /* Setup filtering */
\r
1268 pllFindSel(pllMultiplier, &pllSelP, &pllSelI, &pllSelR);
\r
1271 /* Get encoded value for M (mult) and use manual filter, disable SS mode */
\r
1272 pSetup->pllsscg[1] = (PLL_SSCG1_MDEC_VAL_SET(pllMultiplier)) | (1U << SYSCON_PLL0SSCG1_SEL_EXT_SHIFT);
\r
1278 /* Filtering will be handled by SSC */
\r
1279 pllSelR = pllSelI = pllSelP = 0U;
\r
1282 /* The PLL multiplier will get very close and slightly under the
\r
1283 desired target frequency. A small fractional component can be
\r
1284 added to fine tune the frequency upwards to the target. */
\r
1285 fc = ((uint64_t)(fccoHz % nDivOutHz) << 25U) / nDivOutHz;
\r
1287 /* Set multiplier */
\r
1288 pSetup->pllsscg[0] = (uint32_t)(PLL0_SSCG_MD_INT_SET(pllMultiplier) | PLL0_SSCG_MD_FRACT_SET((uint32_t)fc));
\r
1289 pSetup->pllsscg[1] = PLL0_SSCG_MD_INT_SET(pllMultiplier) >> 32U;
\r
1292 /* Get encoded values for N (prediv) and P (postdiv) */
\r
1293 pSetup->pllndec = PLL_NDEC_VAL_SET(pllPreDivider);
\r
1294 pSetup->pllpdec = PLL_PDEC_VAL_SET(pllPostDivider);
\r
1297 pSetup->pllctrl = (pllSelR << SYSCON_PLL0CTRL_SELR_SHIFT) | /* Filter coefficient */
\r
1298 (pllSelI << SYSCON_PLL0CTRL_SELI_SHIFT) | /* Filter coefficient */
\r
1299 (pllSelP << SYSCON_PLL0CTRL_SELP_SHIFT) | /* Filter coefficient */
\r
1300 (0 << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT) | /* PLL bypass mode disabled */
\r
1301 (uplimoff << SYSCON_PLL0CTRL_LIMUPOFF_SHIFT) | /* SS/fractional mode disabled */
\r
1302 (pllDirectInput << SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT) | /* Bypass pre-divider? */
\r
1303 (pllDirectOutput << SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT) | /* Bypass post-divider? */
\r
1304 (1 << SYSCON_PLL0CTRL_CLKEN_SHIFT); /* Ensure the PLL clock output */
\r
1306 return kStatus_PLL_Success;
\r
1309 #if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT)
\r
1310 /* Alloct the static buffer for cache. */
\r
1311 static pll_setup_t s_PllSetupCacheStruct[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT];
\r
1312 static uint32_t s_FinHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0};
\r
1313 static uint32_t s_FoutHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0};
\r
1314 static bool s_UseSSCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {false};
\r
1315 static uint32_t s_PllSetupCacheIdx = 0U;
\r
1316 #endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */
\r
1319 * Calculate the PLL setting values from input clock freq to output freq.
\r
1321 static pll_error_t CLOCK_GetPll0Config(
\r
1322 uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS)
\r
1324 pll_error_t retErr;
\r
1325 #if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT)
\r
1328 for (i = 0U; i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; i++)
\r
1330 if ((finHz == s_FinHzCache[i]) && (foutHz == s_FoutHzCache[i]) && (useSS == s_UseSSCache[i]))
\r
1332 /* Hit the target in cache buffer. */
\r
1333 pSetup->pllctrl = s_PllSetupCacheStruct[i].pllctrl;
\r
1334 pSetup->pllndec = s_PllSetupCacheStruct[i].pllndec;
\r
1335 pSetup->pllpdec = s_PllSetupCacheStruct[i].pllpdec;
\r
1336 pSetup->pllsscg[0] = s_PllSetupCacheStruct[i].pllsscg[0];
\r
1337 pSetup->pllsscg[1] = s_PllSetupCacheStruct[i].pllsscg[1];
\r
1338 retErr = kStatus_PLL_Success;
\r
1343 if (i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT)
\r
1347 #endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */
\r
1349 retErr = CLOCK_GetPll0ConfigInternal(finHz, foutHz, pSetup, useSS);
\r
1351 #if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT)
\r
1352 /* Cache the most recent calulation result into buffer. */
\r
1353 s_FinHzCache[s_PllSetupCacheIdx] = finHz;
\r
1354 s_FoutHzCache[s_PllSetupCacheIdx] = foutHz;
\r
1355 s_UseSSCache[s_PllSetupCacheIdx] = useSS;
\r
1357 s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllctrl = pSetup->pllctrl;
\r
1358 s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllndec = pSetup->pllndec;
\r
1359 s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllpdec = pSetup->pllpdec;
\r
1360 s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllsscg[0] = pSetup->pllsscg[0];
\r
1361 s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllsscg[1] = pSetup->pllsscg[1];
\r
1362 /* Update the index for next available buffer. */
\r
1363 s_PllSetupCacheIdx = (s_PllSetupCacheIdx + 1U) % CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT;
\r
1364 #endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */
\r
1369 /* Update local PLL rate variable */
\r
1370 static void CLOCK_GetPLL0OutFromSetupUpdate(pll_setup_t *pSetup)
\r
1372 s_Pll0_Freq = CLOCK_GetPLL0OutFromSetup(pSetup);
\r
1375 /* Return System PLL input clock rate */
\r
1376 /*! brief Return PLL0 input clock rate
\r
1377 * return PLL0 input clock rate
\r
1379 uint32_t CLOCK_GetPLL0InClockRate(void)
\r
1381 uint32_t clkRate = 0U;
\r
1383 switch ((SYSCON->PLL0CLKSEL & SYSCON_PLL0CLKSEL_SEL_MASK))
\r
1386 clkRate = CLK_FRO_12MHZ;
\r
1390 clkRate = CLOCK_GetExtClkFreq();
\r
1394 clkRate = CLOCK_GetFro1MFreq();
\r
1398 clkRate = CLOCK_GetOsc32KFreq();
\r
1409 /* Return PLL1 input clock rate */
\r
1410 uint32_t CLOCK_GetPLL1InClockRate(void)
\r
1412 uint32_t clkRate = 0U;
\r
1414 switch ((SYSCON->PLL1CLKSEL & SYSCON_PLL1CLKSEL_SEL_MASK))
\r
1417 clkRate = CLK_FRO_12MHZ;
\r
1421 clkRate = CLOCK_GetExtClkFreq();
\r
1425 clkRate = CLOCK_GetFro1MFreq();
\r
1429 clkRate = CLOCK_GetOsc32KFreq();
\r
1440 /* Return PLL0 output clock rate from setup structure */
\r
1441 /*! brief Return PLL0 output clock rate from setup structure
\r
1442 * param pSetup : Pointer to a PLL setup structure
\r
1443 * return PLL0 output clock rate the setup structure will generate
\r
1445 uint32_t CLOCK_GetPLL0OutFromSetup(pll_setup_t *pSetup)
\r
1447 uint32_t clkRate = 0;
\r
1448 uint32_t prediv, postdiv;
\r
1449 float workRate = 0;
\r
1451 /* Get the input clock frequency of PLL. */
\r
1452 clkRate = CLOCK_GetPLL0InClockRate();
\r
1454 if (((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPLL_MASK) == 0) && (SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_CLKEN_MASK) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_MASK) == 0) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) == 0))
\r
1456 prediv = findPll0PreDiv();
\r
1457 postdiv = findPll0PostDiv();
\r
1458 /* Adjust input clock */
\r
1459 clkRate = clkRate / prediv;
\r
1460 /* MDEC used for rate */
\r
1461 workRate = (float)clkRate * (float)findPll0MMult();
\r
1462 clkRate = (uint32_t)(workRate / ((float)postdiv));
\r
1465 return (uint32_t)workRate;
\r
1468 /* Set the current PLL0 Rate */
\r
1469 /*! brief Store the current PLL rate
\r
1470 * param rate: Current rate of the PLL
\r
1473 void CLOCK_SetStoredPLL0ClockRate(uint32_t rate)
\r
1475 s_Pll0_Freq = rate;
\r
1478 /* Return PLL0 output clock rate */
\r
1479 /*! brief Return PLL0 output clock rate
\r
1480 * param recompute : Forces a PLL rate recomputation if true
\r
1481 * return PLL0 output clock rate
\r
1482 * note The PLL rate is cached in the driver in a variable as
\r
1483 * the rate computation function can take some time to perform. It
\r
1484 * is recommended to use 'false' with the 'recompute' parameter.
\r
1486 uint32_t CLOCK_GetPLL0OutClockRate(bool recompute)
\r
1488 pll_setup_t Setup;
\r
1491 if ((recompute) || (s_Pll0_Freq == 0U))
\r
1493 Setup.pllctrl = SYSCON->PLL0CTRL;
\r
1494 Setup.pllndec = SYSCON->PLL0NDEC;
\r
1495 Setup.pllpdec = SYSCON->PLL0PDEC;
\r
1496 Setup.pllsscg[0] = SYSCON->PLL0SSCG0;
\r
1497 Setup.pllsscg[1] = SYSCON->PLL0SSCG1;
\r
1499 CLOCK_GetPLL0OutFromSetupUpdate(&Setup);
\r
1502 rate = s_Pll0_Freq;
\r
1507 /* Set PLL0 output based on the passed PLL setup data */
\r
1508 /*! brief Set PLL output based on the passed PLL setup data
\r
1509 * param pControl : Pointer to populated PLL control structure to generate setup with
\r
1510 * param pSetup : Pointer to PLL setup structure to be filled
\r
1511 * return PLL_ERROR_SUCCESS on success, or PLL setup error code
\r
1512 * note Actual frequency for setup may vary from the desired frequency based on the
\r
1513 * accuracy of input clocks, rounding, non-fractional PLL mode, etc.
\r
1515 pll_error_t CLOCK_SetupPLL0Data(pll_config_t *pControl, pll_setup_t *pSetup)
\r
1518 bool useSS = (bool)((pControl->flags & PLL_CONFIGFLAG_FORCENOFRACT) == 0U);
\r
1520 pll_error_t pllError;
\r
1522 /* Determine input rate for the PLL */
\r
1523 if ((pControl->flags & PLL_CONFIGFLAG_USEINRATE) != 0U)
\r
1525 inRate = pControl->inputRate;
\r
1529 inRate = CLOCK_GetPLL0InClockRate();
\r
1532 /* PLL flag options */
\r
1533 pllError = CLOCK_GetPll0Config(inRate, pControl->desiredRate, pSetup, useSS);
\r
1534 if ((useSS) && (pllError == kStatus_PLL_Success))
\r
1536 /* If using SS mode, then some tweaks are made to the generated setup */
\r
1537 pSetup->pllsscg[1] |= (uint32_t)pControl->ss_mf | (uint32_t)pControl->ss_mr | (uint32_t)pControl->ss_mc;
\r
1538 if (pControl->mfDither)
\r
1540 pSetup->pllsscg[1] |= (1U << SYSCON_PLL0SSCG1_DITHER_SHIFT);
\r
1547 /* Set PLL0 output from PLL setup structure */
\r
1548 /*! brief Set PLL output from PLL setup structure (precise frequency)
\r
1549 * param pSetup : Pointer to populated PLL setup structure
\r
1550 * param flagcfg : Flag configuration for PLL config structure
\r
1551 * return PLL_ERROR_SUCCESS on success, or PLL setup error code
\r
1552 * note This function will power off the PLL, setup the PLL with the
\r
1553 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
\r
1554 * and adjust system voltages to the new PLL rate. The function will not
\r
1555 * alter any source clocks (ie, main systen clock) that may use the PLL,
\r
1556 * so these should be setup prior to and after exiting the function.
\r
1558 pll_error_t CLOCK_SetupPLL0Prec(pll_setup_t *pSetup, uint32_t flagcfg)
\r
1560 uint32_t inRate, clkRate, prediv;
\r
1562 /* Power off PLL during setup changes */
\r
1563 POWER_EnablePD(kPDRUNCFG_PD_PLL0);
\r
1564 POWER_EnablePD(kPDRUNCFG_PD_PLL0_SSCG);
\r
1566 pSetup->flags = flagcfg;
\r
1568 /* Write PLL setup data */
\r
1569 SYSCON->PLL0CTRL = pSetup->pllctrl;
\r
1570 SYSCON->PLL0NDEC = pSetup->pllndec;
\r
1571 SYSCON->PLL0NDEC = pSetup->pllndec | (1U << SYSCON_PLL0NDEC_NREQ_SHIFT); /* latch */
\r
1572 SYSCON->PLL0PDEC = pSetup->pllpdec;
\r
1573 SYSCON->PLL0PDEC = pSetup->pllpdec | (1U << SYSCON_PLL0PDEC_PREQ_SHIFT); /* latch */
\r
1574 SYSCON->PLL0SSCG0 = pSetup->pllsscg[0];
\r
1575 SYSCON->PLL0SSCG1 = pSetup->pllsscg[1];
\r
1576 SYSCON->PLL0SSCG1 =
\r
1577 pSetup->pllsscg[1] | (1U << SYSCON_PLL0SSCG1_MREQ_SHIFT) | (1U << SYSCON_PLL0SSCG1_MD_REQ_SHIFT); /* latch */
\r
1579 POWER_DisablePD(kPDRUNCFG_PD_PLL0);
\r
1580 POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
\r
1582 if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U)
\r
1584 inRate = CLOCK_GetPLL0InClockRate();
\r
1585 prediv = findPll0PreDiv();
\r
1586 /* Adjust input clock */
\r
1587 clkRate = inRate / prediv;
\r
1588 /* The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */
\r
1589 if ((clkRate >= 100000) && (clkRate <= 20000000))
\r
1591 while (CLOCK_IsPLL0Locked() == false)
\r
1597 /* Update current programmed PLL rate var */
\r
1598 CLOCK_GetPLL0OutFromSetupUpdate(pSetup);
\r
1600 /* System voltage adjustment, occurs prior to setting main system clock */
\r
1601 if ((pSetup->flags & PLL_SETUPFLAG_ADGVOLT) != 0U)
\r
1603 POWER_SetVoltageForFreq(s_Pll0_Freq);
\r
1606 return kStatus_PLL_Success;
\r
1609 /* Setup PLL Frequency from pre-calculated value */
\r
1611 * brief Set PLL0 output from PLL setup structure (precise frequency)
\r
1612 * param pSetup : Pointer to populated PLL setup structure
\r
1613 * return kStatus_PLL_Success on success, or PLL setup error code
\r
1614 * note This function will power off the PLL, setup the PLL with the
\r
1615 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
\r
1616 * and adjust system voltages to the new PLL rate. The function will not
\r
1617 * alter any source clocks (ie, main systen clock) that may use the PLL,
\r
1618 * so these should be setup prior to and after exiting the function.
\r
1620 pll_error_t CLOCK_SetPLL0Freq(const pll_setup_t *pSetup)
\r
1622 uint32_t inRate, clkRate, prediv;
\r
1623 /* Power off PLL during setup changes */
\r
1624 POWER_EnablePD(kPDRUNCFG_PD_PLL0);
\r
1625 POWER_EnablePD(kPDRUNCFG_PD_PLL0_SSCG);
\r
1627 /* Write PLL setup data */
\r
1628 SYSCON->PLL0CTRL = pSetup->pllctrl;
\r
1629 SYSCON->PLL0NDEC = pSetup->pllndec;
\r
1630 SYSCON->PLL0NDEC = pSetup->pllndec | (1U << SYSCON_PLL0NDEC_NREQ_SHIFT); /* latch */
\r
1631 SYSCON->PLL0PDEC = pSetup->pllpdec;
\r
1632 SYSCON->PLL0PDEC = pSetup->pllpdec | (1U << SYSCON_PLL0PDEC_PREQ_SHIFT); /* latch */
\r
1633 SYSCON->PLL0SSCG0 = pSetup->pllsscg[0];
\r
1634 SYSCON->PLL0SSCG1 = pSetup->pllsscg[1];
\r
1635 SYSCON->PLL0SSCG1 =
\r
1636 pSetup->pllsscg[1] | (1U << SYSCON_PLL0SSCG1_MD_REQ_SHIFT) | (1U << SYSCON_PLL0SSCG1_MREQ_SHIFT); /* latch */
\r
1638 POWER_DisablePD(kPDRUNCFG_PD_PLL0);
\r
1639 POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
\r
1641 if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U)
\r
1643 inRate = CLOCK_GetPLL0InClockRate();
\r
1644 prediv = findPll0PreDiv();
\r
1645 /* Adjust input clock */
\r
1646 clkRate = inRate / prediv;
\r
1647 /* The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */
\r
1648 if ((clkRate >= 100000) && (clkRate <= 20000000))
\r
1650 while (CLOCK_IsPLL0Locked() == false)
\r
1656 /* Update current programmed PLL rate var */
\r
1657 s_Pll0_Freq = pSetup->pllRate;
\r
1659 return kStatus_PLL_Success;
\r
1662 /* Setup PLL1 Frequency from pre-calculated value */
\r
1664 * brief Set PLL1 output from PLL setup structure (precise frequency)
\r
1665 * param pSetup : Pointer to populated PLL setup structure
\r
1666 * return kStatus_PLL_Success on success, or PLL setup error code
\r
1667 * note This function will power off the PLL, setup the PLL with the
\r
1668 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
\r
1669 * and adjust system voltages to the new PLL rate. The function will not
\r
1670 * alter any source clocks (ie, main systen clock) that may use the PLL,
\r
1671 * so these should be setup prior to and after exiting the function.
\r
1673 pll_error_t CLOCK_SetPLL1Freq(const pll_setup_t *pSetup)
\r
1675 uint32_t inRate, clkRate, prediv;
\r
1676 /* Power off PLL during setup changes */
\r
1677 POWER_EnablePD(kPDRUNCFG_PD_PLL1);
\r
1679 /* Write PLL setup data */
\r
1680 SYSCON->PLL1CTRL = pSetup->pllctrl;
\r
1681 SYSCON->PLL1NDEC = pSetup->pllndec;
\r
1682 SYSCON->PLL1NDEC = pSetup->pllndec | (1U << SYSCON_PLL1NDEC_NREQ_SHIFT); /* latch */
\r
1683 SYSCON->PLL1PDEC = pSetup->pllpdec;
\r
1684 SYSCON->PLL1PDEC = pSetup->pllpdec | (1U << SYSCON_PLL1PDEC_PREQ_SHIFT); /* latch */
\r
1685 SYSCON->PLL1MDEC = pSetup->pllmdec;
\r
1686 SYSCON->PLL1MDEC = pSetup->pllmdec | (1U << SYSCON_PLL1MDEC_MREQ_SHIFT); /* latch */
\r
1688 POWER_DisablePD(kPDRUNCFG_PD_PLL1);
\r
1690 if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U)
\r
1692 inRate = CLOCK_GetPLL1InClockRate();
\r
1693 prediv = findPll1PreDiv();
\r
1694 /* Adjust input clock */
\r
1695 clkRate = inRate / prediv;
\r
1696 /* The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */
\r
1697 if ((clkRate >= 100000) && (clkRate <= 20000000))
\r
1699 while (CLOCK_IsPLL1Locked() == false)
\r
1705 /* Update current programmed PLL rate var */
\r
1706 s_Pll0_Freq = pSetup->pllRate;
\r
1708 return kStatus_PLL_Success;
\r
1711 /* Set PLL0 clock based on the input frequency and multiplier */
\r
1712 /*! brief Set PLL0 output based on the multiplier and input frequency
\r
1713 * param multiply_by : multiplier
\r
1714 * param input_freq : Clock input frequency of the PLL
\r
1716 * note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this
\r
1717 * function does not disable or enable PLL power, wait for PLL lock,
\r
1718 * or adjust system voltages. These must be done in the application.
\r
1719 * The function will not alter any source clocks (ie, main systen clock)
\r
1720 * that may use the PLL, so these should be setup prior to and after
\r
1721 * exiting the function.
\r
1723 void CLOCK_SetupPLL0Mult(uint32_t multiply_by, uint32_t input_freq)
\r
1725 uint32_t cco_freq = input_freq * multiply_by;
\r
1726 uint32_t pdec = 1U;
\r
1730 uint32_t mdec, ndec;
\r
1732 while (cco_freq < 275000000U)
\r
1734 multiply_by <<= 1U; /* double value in each iteration */
\r
1735 pdec <<= 1U; /* correspondingly double pdec to cancel effect of double msel */
\r
1736 cco_freq = input_freq * multiply_by;
\r
1741 if (multiply_by >= 32768)
\r
1745 else if (multiply_by >= 16384)
\r
1749 else if (multiply_by >= 4096)
\r
1753 else if (multiply_by >= 1002)
\r
1757 else if (multiply_by >= 120)
\r
1759 seli = 4 * ((1024/(multiply_by/2 + 9)) + 1);
\r
1763 seli = 4 * (multiply_by/8 + 1);
\r
1770 selp = (multiply_by >> 2U) + 1U;
\r
1777 pdec = pdec / 2U; /* Account for minus 1 encoding */
\r
1778 /* Translate P value */
\r
1781 mdec = PLL_SSCG1_MDEC_VAL_SET(multiply_by);
\r
1782 ndec = 0x1U; /* pre divide by 1 (hardcoded) */
\r
1784 SYSCON->PLL0CTRL = SYSCON_PLL0CTRL_CLKEN_MASK |SYSCON_PLL0CTRL_BYPASSPOSTDIV(0) | SYSCON_PLL0CTRL_BYPASSPOSTDIV2(0) |
\r
1785 (selr << SYSCON_PLL0CTRL_SELR_SHIFT) | (seli << SYSCON_PLL0CTRL_SELI_SHIFT) |
\r
1786 (selp << SYSCON_PLL0CTRL_SELP_SHIFT);
\r
1787 SYSCON->PLL0PDEC = pdec | (1U << SYSCON_PLL0PDEC_PREQ_SHIFT); /* set Pdec value and assert preq */
\r
1788 SYSCON->PLL0NDEC = ndec | (1U << SYSCON_PLL0NDEC_NREQ_SHIFT); /* set Pdec value and assert preq */
\r
1789 SYSCON->PLL0SSCG1 = mdec | (1U << SYSCON_PLL0SSCG1_MREQ_SHIFT); /* select non sscg MDEC value, assert mreq and select mdec value */
\r
1792 /* Enable USB DEVICE FULL SPEED clock */
\r
1793 /*! brief Enable USB Device FS clock.
\r
1794 * param src : clock source
\r
1795 * param freq: clock frequency
\r
1796 * Enable USB Device Full Speed clock.
\r
1798 bool CLOCK_EnableUsbfs0DeviceClock(clock_usbfs_src_t src, uint32_t freq)
\r
1802 CLOCK_DisableClock(kCLOCK_Usbd0);
\r
1804 if (kCLOCK_UsbfsSrcFro == src)
\r
1809 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */
\r
1816 /* Turn ON FRO HF */
\r
1817 POWER_DisablePD(kPDRUNCFG_PD_FRO192M);
\r
1818 /* Enable FRO 96MHz output */
\r
1819 ANACTRL->FRO192M_CTRL = ANACTRL->FRO192M_CTRL | ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK;
\r
1820 /* Select FRO 96 or 48 MHz */
\r
1821 CLOCK_AttachClk(kFRO_HF_to_USB0_CLK);
\r
1825 /*Set the USB PLL as the Usb0 CLK*/
\r
1826 POWER_DisablePD(kPDRUNCFG_PD_PLL1);
\r
1827 POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /*!< Ensure XTAL32K is on */
\r
1828 POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /*!< Ensure XTAL32K is on */
\r
1829 SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /*!< Ensure CLK_IN is on */
\r
1830 ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;
\r
1832 CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL0 clock source selector to XTAL16M */
\r
1834 const pll_setup_t pll1Setup = {
\r
1835 .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(16U) | SYSCON_PLL1CTRL_SELP(7U),
\r
1836 .pllndec = SYSCON_PLL1NDEC_NDIV(1U),
\r
1837 .pllpdec = SYSCON_PLL1PDEC_PDIV(4U),
\r
1838 .pllmdec = SYSCON_PLL1MDEC_MDIV(24U),
\r
1839 .pllRate = 48000000U,
\r
1840 .flags = PLL_SETUPFLAG_WAITLOCK,
\r
1843 CLOCK_SetPLL1Freq(&pll1Setup); /*!< Configure PLL1 to the desired values */
\r
1845 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false);
\r
1846 CLOCK_AttachClk(kPLL1_to_USB0_CLK);
\r
1847 uint32_t delay = 100000;
\r
1853 CLOCK_EnableClock(kCLOCK_Usbd0);
\r
1854 CLOCK_EnableClock(kCLOCK_UsbRam1);
\r
1859 /* Enable USB HOST FULL SPEED clock */
\r
1860 /*! brief Enable USB HOST FS clock.
\r
1861 * param src : clock source
\r
1862 * param freq: clock frequency
\r
1863 * Enable USB HOST Full Speed clock.
\r
1865 bool CLOCK_EnableUsbfs0HostClock(clock_usbfs_src_t src, uint32_t freq)
\r
1869 CLOCK_DisableClock(kCLOCK_Usbhmr0);
\r
1870 CLOCK_DisableClock(kCLOCK_Usbhsl0);
\r
1872 if (kCLOCK_UsbfsSrcFro == src)
\r
1877 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */
\r
1884 /* Turn ON FRO HF */
\r
1885 POWER_DisablePD(kPDRUNCFG_PD_FRO192M);
\r
1886 /* Enable FRO 96MHz output */
\r
1887 ANACTRL->FRO192M_CTRL = ANACTRL->FRO192M_CTRL | ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK;
\r
1888 /* Select FRO 96 MHz */
\r
1889 CLOCK_AttachClk(kFRO_HF_to_USB0_CLK);
\r
1893 /*Set the USB PLL as the Usb0 CLK*/
\r
1894 POWER_DisablePD(kPDRUNCFG_PD_PLL1);
\r
1895 POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /*!< Ensure XTAL32K is on */
\r
1896 POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /*!< Ensure XTAL32K is on */
\r
1897 SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /*!< Ensure CLK_IN is on */
\r
1898 ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;
\r
1900 CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL0 clock source selector to XTAL16M */
\r
1902 const pll_setup_t pll1Setup = {
\r
1903 .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(16U) | SYSCON_PLL1CTRL_SELP(7U),
\r
1904 .pllndec = SYSCON_PLL1NDEC_NDIV(1U),
\r
1905 .pllpdec = SYSCON_PLL1PDEC_PDIV(4U),
\r
1906 .pllmdec = SYSCON_PLL1MDEC_MDIV(24U),
\r
1907 .pllRate = 48000000U,
\r
1908 .flags = PLL_SETUPFLAG_WAITLOCK,
\r
1911 CLOCK_SetPLL1Freq(&pll1Setup); /*!< Configure PLL1 to the desired values */
\r
1913 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false);
\r
1914 CLOCK_AttachClk(kPLL1_to_USB0_CLK);
\r
1915 uint32_t delay = 100000;
\r
1921 CLOCK_EnableClock(kCLOCK_Usbhmr0);
\r
1922 CLOCK_EnableClock(kCLOCK_Usbhsl0);
\r
1923 CLOCK_EnableClock(kCLOCK_UsbRam1);
\r
1928 /* Enable USB PHY clock */
\r
1929 bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq)
\r
1931 volatile uint32_t i;
\r
1933 POWER_DisablePD(kPDRUNCFG_PD_XTAL32M);
\r
1934 POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M);
\r
1935 POWER_DisablePD(kPDRUNCFG_PD_FRO32K); /*!< Ensure FRO32k is on */
\r
1936 POWER_DisablePD(kPDRUNCFG_PD_XTAL32K); /*!< Ensure xtal32k is on */
\r
1937 POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY); /*!< Ensure xtal32k is on */
\r
1938 POWER_DisablePD(kPDRUNCFG_PD_LDOUSBHS); /*!< Ensure xtal32k is on */
\r
1940 /* wait to make sure PHY power is fully up */
\r
1947 SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_ANALOG_CTRL(1);
\r
1948 SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_PHY(1);
\r
1950 USBPHY->CTRL_CLR = USBPHY_CTRL_SFTRST_MASK;
\r
1951 USBPHY->PLL_SIC = (USBPHY->PLL_SIC & ~USBPHY_PLL_SIC_PLL_DIV_SEL(0x7)) | USBPHY_PLL_SIC_PLL_DIV_SEL(0x06);
\r
1952 USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK;
\r
1953 USBPHY->PLL_SIC_CLR = USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK;
\r
1954 USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_POWER_MASK;
\r
1955 USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK;
\r
1956 USBPHY->PLL_SIC_SET =
\r
1957 USBPHY_PLL_SIC_SET_MISC2_CONTROL0_MASK; /* enables auto power down of PHY PLL during suspend */
\r
1959 USBPHY->CTRL_CLR = USBPHY_CTRL_CLR_CLKGATE_MASK;
\r
1960 USBPHY->PWD_SET = 0x0;
\r
1965 /* Enable USB DEVICE HIGH SPEED clock */
\r
1966 bool CLOCK_EnableUsbhs0DeviceClock(clock_usbhs_src_t src, uint32_t freq)
\r
1968 SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_RAM(1);
\r
1969 SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_DEV(1);
\r
1971 /* 16 MHz will be driven by the tb on the xtal1 pin of XTAL32M */
\r
1972 SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clock_in clock for clock module. */
\r
1973 ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT(1);
\r
1977 /* Enable USB HOST HIGH SPEED clock */
\r
1978 bool CLOCK_EnableUsbhs0HostClock(clock_usbhs_src_t src, uint32_t freq)
\r
1980 SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_RAM(1);
\r
1981 SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_HOST(1);
\r
1983 /* 16 MHz will be driven by the tb on the xtal1 pin of XTAL32M */
\r
1984 SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clock_in clock for clock module. */
\r
1985 ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT(1);
\r
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