2 * Copyright (c) 2017 - 2018 , NXP
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3 * All rights reserved.
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5 * SPDX-License-Identifier: BSD-3-Clause
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8 #ifndef _FSL_CLOCK_H_
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9 #define _FSL_CLOCK_H_
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11 #include "fsl_device_registers.h"
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13 #include <stdbool.h>
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16 /*! @addtogroup clock */
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21 /*******************************************************************************
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23 *****************************************************************************/
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25 /*! @name Driver version */
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27 /*! @brief CLOCK driver version 2.0.3. */
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28 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 0, 3))
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31 /*! @brief Configure whether driver controls clock
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33 * When set to 0, peripheral drivers will enable clock in initialize function
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34 * and disable clock in de-initialize function. When set to 1, peripheral
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35 * driver will not control the clock, application could control the clock out of
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38 * @note All drivers share this feature switcher. If it is set to 1, application
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39 * should handle clock enable and disable for all drivers.
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41 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
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42 #define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
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46 * @brief User-defined the size of cache for CLOCK_PllGetConfig() function.
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48 * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function
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49 * would cache the recent calulation and accelerate the execution to get the
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52 #ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT
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53 #define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U
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56 /*! @brief Clock ip name array for ROM. */
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57 #define ROM_CLOCKS \
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61 /*! @brief Clock ip name array for SRAM. */
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62 #define SRAM_CLOCKS \
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64 kCLOCK_Sram1, kCLOCK_Sram2, kCLOCK_Sram3, kCLOCK_Sram4 \
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66 /*! @brief Clock ip name array for FLASH. */
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67 #define FLASH_CLOCKS \
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71 /*! @brief Clock ip name array for FMC. */
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72 #define FMC_CLOCKS \
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76 /*! @brief Clock ip name array for INPUTMUX. */
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77 #define INPUTMUX_CLOCKS \
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79 kCLOCK_InputMux0, kCLOCK_InputMux1 \
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81 /*! @brief Clock ip name array for IOCON. */
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82 #define IOCON_CLOCKS \
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86 /*! @brief Clock ip name array for GPIO. */
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87 #define GPIO_CLOCKS \
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89 kCLOCK_Gpio0, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 \
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91 /*! @brief Clock ip name array for PINT. */
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92 #define PINT_CLOCKS \
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96 /*! @brief Clock ip name array for GINT. */
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97 #define GINT_CLOCKS \
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99 kCLOCK_Gint, kCLOCK_Gint \
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101 /*! @brief Clock ip name array for DMA. */
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102 #define DMA_CLOCKS \
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104 kCLOCK_Dma0, kCLOCK_Dma1 \
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106 /*! @brief Clock ip name array for CRC. */
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107 #define CRC_CLOCKS \
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111 /*! @brief Clock ip name array for WWDT. */
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112 #define WWDT_CLOCKS \
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116 /*! @brief Clock ip name array for RTC. */
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117 #define RTC_CLOCKS \
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121 /*! @brief Clock ip name array for Mailbox. */
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122 #define MAILBOX_CLOCKS \
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126 /*! @brief Clock ip name array for LPADC. */
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127 #define LPADC_CLOCKS \
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131 /*! @brief Clock ip name array for MRT. */
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132 #define MRT_CLOCKS \
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136 /*! @brief Clock ip name array for OSTIMER. */
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137 #define OSTIMER_CLOCKS \
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141 /*! @brief Clock ip name array for SCT0. */
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142 #define SCT_CLOCKS \
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146 /*! @brief Clock ip name array for SCTIPU. */
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147 #define SCTIPU_CLOCKS \
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151 /*! @brief Clock ip name array for UTICK. */
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152 #define UTICK_CLOCKS \
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156 /*! @brief Clock ip name array for FLEXCOMM. */
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157 #define FLEXCOMM_CLOCKS \
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159 kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, kCLOCK_FlexComm4, kCLOCK_FlexComm5, \
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160 kCLOCK_FlexComm6, kCLOCK_FlexComm7, kCLOCK_Hs_Lspi \
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162 /*! @brief Clock ip name array for LPUART. */
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163 #define LPUART_CLOCKS \
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165 kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \
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166 kCLOCK_MinUart6, kCLOCK_MinUart7 \
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169 /*! @brief Clock ip name array for BI2C. */
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170 #define BI2C_CLOCKS \
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172 kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, kCLOCK_BI2c7 \
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174 /*! @brief Clock ip name array for LSPI. */
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175 #define LPSPI_CLOCKS \
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177 kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, kCLOCK_LSpi7 \
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179 /*! @brief Clock ip name array for FLEXI2S. */
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180 #define FLEXI2S_CLOCKS \
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182 kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \
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183 kCLOCK_FlexI2s6, kCLOCK_FlexI2s7 \
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185 /*! @brief Clock ip name array for USBTYPC. */
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186 #define USBTYPC_CLOCKS \
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190 /*! @brief Clock ip name array for CTIMER. */
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191 #define CTIMER_CLOCKS \
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193 kCLOCK_Timer0, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 \
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195 /*! @brief Clock ip name array for PVT */
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196 #define PVT_CLOCKS \
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200 /*! @brief Clock ip name array for EZHA */
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201 #define EZHA_CLOCKS \
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205 /*! @brief Clock ip name array for EZHB */
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206 #define EZHB_CLOCKS \
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210 /*! @brief Clock ip name array for COMP */
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211 #define COMP_CLOCKS \
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215 /*! @brief Clock ip name array for SDIO. */
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216 #define SDIO_CLOCKS \
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220 /*! @brief Clock ip name array for USB1CLK. */
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221 #define USB1CLK_CLOCKS \
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225 /*! @brief Clock ip name array for FREQME. */
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226 #define FREQME_CLOCKS \
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230 /*! @brief Clock ip name array for USBRAM. */
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231 #define USBRAM_CLOCKS \
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235 /*! @brief Clock ip name array for OTP. */
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236 #define OTP_CLOCKS \
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240 /*! @brief Clock ip name array for RNG. */
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241 #define RNG_CLOCKS \
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245 /*! @brief Clock ip name array for USBHMR0. */
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246 #define USBHMR0_CLOCKS \
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250 /*! @brief Clock ip name array for USBHSL0. */
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251 #define USBHSL0_CLOCKS \
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255 /*! @brief Clock ip name array for HashCrypt. */
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256 #define HASHCRYPT_CLOCKS \
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260 /*! @brief Clock ip name array for PowerQuad. */
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261 #define POWERQUAD_CLOCKS \
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265 /*! @brief Clock ip name array for PLULUT. */
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266 #define PLULUT_CLOCKS \
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270 /*! @brief Clock ip name array for PUF. */
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271 #define PUF_CLOCKS \
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275 /*! @brief Clock ip name array for CASPER. */
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276 #define CASPER_CLOCKS \
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280 /*! @brief Clock ip name array for ANALOGCTRL. */
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281 #define ANALOGCTRL_CLOCKS \
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283 kCLOCK_AnalogCtrl \
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285 /*! @brief Clock ip name array for HS_LSPI. */
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286 #define HS_LSPI_CLOCKS \
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290 /*! @brief Clock ip name array for GPIO_SEC. */
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291 #define GPIO_SEC_CLOCKS \
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295 /*! @brief Clock ip name array for GPIO_SEC_INT. */
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296 #define GPIO_SEC_INT_CLOCKS \
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298 kCLOCK_Gpio_Sec_Int \
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300 /*! @brief Clock ip name array for USBD. */
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301 #define USBD_CLOCKS \
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303 kCLOCK_Usbd0, kCLOCK_Usbh1, kCLOCK_Usbd1 \
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305 /*! @brief Clock ip name array for USBH. */
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306 #define USBH_CLOCKS \
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310 #define PLU_CLOCKS \
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314 #define SYSCTL_CLOCKS \
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318 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
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319 /*------------------------------------------------------------------------------
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320 clock_ip_name_t definition:
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321 ------------------------------------------------------------------------------*/
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323 #define CLK_GATE_REG_OFFSET_SHIFT 8U
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324 #define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U
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325 #define CLK_GATE_BIT_SHIFT_SHIFT 0U
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326 #define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU
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328 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \
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329 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
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330 (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
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332 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
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333 #define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
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335 #define AHB_CLK_CTRL0 0
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336 #define AHB_CLK_CTRL1 1
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337 #define AHB_CLK_CTRL2 2
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339 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
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340 typedef enum _clock_ip_name
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342 kCLOCK_IpInvalid = 0U,
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343 kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1),
\r
344 kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3),
\r
345 kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4),
\r
346 kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5),
\r
347 kCLOCK_Sram4 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 6),
\r
348 kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7),
\r
349 kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8),
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350 kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11),
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351 kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13),
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352 kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14),
\r
353 kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15),
\r
354 kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16),
\r
355 kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17),
\r
356 kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18),
\r
357 kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19),
\r
358 kCLOCK_Dma0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20),
\r
359 kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21),
\r
360 kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22),
\r
361 kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23),
\r
362 kCLOCK_Mailbox = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 26),
\r
363 kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27),
\r
364 kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0),
\r
365 kCLOCK_OsTimer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1),
\r
366 kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2),
\r
367 kCLOCK_Sctipu = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 6),
\r
368 kCLOCK_Utick0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10),
\r
369 kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
\r
370 kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
\r
371 kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
\r
372 kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
\r
373 kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
\r
374 kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
\r
375 kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
\r
376 kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
\r
377 kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
\r
378 kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
\r
379 kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
\r
380 kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
\r
381 kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
\r
382 kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
\r
383 kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
\r
384 kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
\r
385 kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
\r
386 kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
\r
387 kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
\r
388 kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
\r
389 kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
\r
390 kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
\r
391 kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
\r
392 kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
\r
393 kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
\r
394 kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
\r
395 kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
\r
396 kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
\r
397 kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
\r
398 kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
\r
399 kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
\r
400 kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
\r
401 kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
\r
402 kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
\r
403 kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
\r
404 kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
\r
405 kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
\r
406 kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
\r
407 kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
\r
408 kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
\r
409 kCLOCK_UsbTypc = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 20),
\r
410 kCLOCK_Timer2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22),
\r
411 kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25),
\r
412 kCLOCK_Timer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26),
\r
413 kCLOCK_Timer1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27),
\r
414 kCLOCK_Pvt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 28),
\r
415 kCLOCK_Ezha = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 30),
\r
416 kCLOCK_Ezhb = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31),
\r
417 kCLOCK_Dma1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 1),
\r
418 kCLOCK_Comp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2),
\r
419 kCLOCK_Sdio = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 3),
\r
420 kCLOCK_Usbh1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 4),
\r
421 kCLOCK_Usbd1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 5),
\r
422 kCLOCK_UsbRam1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 6),
\r
423 kCLOCK_Usb1Clk = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 7),
\r
424 kCLOCK_Freqme = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 8),
\r
425 kCLOCK_Gpio4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 9),
\r
426 kCLOCK_Gpio5 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 10),
\r
427 kCLOCK_Otp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 12),
\r
428 kCLOCK_Rng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13),
\r
429 kCLOCK_InputMux1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
\r
430 kCLOCK_Sysctl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
\r
431 kCLOCK_Usbhmr0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16),
\r
432 kCLOCK_Usbhsl0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17),
\r
433 kCLOCK_HashCrypt = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18),
\r
434 kCLOCK_PowerQuad = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 19),
\r
435 kCLOCK_PluLut = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 20),
\r
436 kCLOCK_Timer3 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 21),
\r
437 kCLOCK_Timer4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 22),
\r
438 kCLOCK_Puf = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 23),
\r
439 kCLOCK_Casper = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 24),
\r
440 kCLOCK_AnalogCtrl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 27),
\r
441 kCLOCK_Hs_Lspi = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 28),
\r
442 kCLOCK_Gpio_Sec = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 29),
\r
443 kCLOCK_Gpio_sec_Int = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 30)
\r
446 /*! @brief Peripherals clock source definition. */
\r
447 #define BUS_CLK kCLOCK_BusClk
\r
449 #define I2C0_CLK_SRC BUS_CLK
\r
451 /*! @brief Clock name used to get clock frequency. */
\r
452 typedef enum _clock_name
\r
454 kCLOCK_CoreSysClk, /*!< Core/system clock (aka MAIN_CLK) */
\r
455 kCLOCK_BusClk, /*!< Bus clock (AHB clock) */
\r
456 kCLOCK_ClockOut, /*!< CLOCKOUT */
\r
457 kCLOCK_FroHf, /*!< FRO48/96 */
\r
458 kCLOCK_Adc, /*!< ADC */
\r
459 kCLOCK_Usb0, /*!< USB0 */
\r
460 kCLOCK_Usb1, /*!< USB1 */
\r
461 kCLOCK_Pll1Out, /*!< PLL1 Output */
\r
462 kCLOCK_Mclk, /*!< MCLK */
\r
463 kCLOCK_Sct, /*!< SCT */
\r
464 kCLOCK_SDio, /*!< SDIO */
\r
465 kCLOCK_Fro12M, /*!< FRO12M */
\r
466 kCLOCK_ExtClk, /*!< External Clock */
\r
467 kCLOCK_Pll0Out, /*!< PLL0 Output */
\r
468 kCLOCK_WdtClk, /*!< Watchdog clock */
\r
469 kCLOCK_FlexI2S, /*!< FlexI2S clock */
\r
470 kCLOCK_Flexcomm0, /*!< Flexcomm0Clock */
\r
471 kCLOCK_Flexcomm1, /*!< Flexcomm1Clock */
\r
472 kCLOCK_Flexcomm2, /*!< Flexcomm2Clock */
\r
473 kCLOCK_Flexcomm3, /*!< Flexcomm3Clock */
\r
474 kCLOCK_Flexcomm4, /*!< Flexcomm4Clock */
\r
475 kCLOCK_Flexcomm5, /*!< Flexcomm5Clock */
\r
476 kCLOCK_Flexcomm6, /*!< Flexcomm6Clock */
\r
477 kCLOCK_Flexcomm7, /*!< Flexcomm7Clock */
\r
478 kCLOCK_HsLspi, /*!< HS LPSPI Clock */
\r
479 kCLOCK_CTmier0, /*!< CTmier0Clock */
\r
480 kCLOCK_CTmier1, /*!< CTmier1Clock */
\r
481 kCLOCK_CTmier2, /*!< CTmier2Clock */
\r
482 kCLOCK_CTmier3, /*!< CTmier3Clock */
\r
483 kCLOCK_CTmier4, /*!< CTmier4Clock */
\r
484 kCLOCK_Systick0, /*!< System Tick 0 Clock */
\r
485 kCLOCK_Systick1, /*!< System Tick 1 Clock */
\r
489 /*! @brief Clock Mux Switches
\r
490 * The encoding is as follows each connection identified is 32bits wide while 24bits are valuable
\r
491 * starting from LSB upwards
\r
493 * [4 bits for choice, 0 means invalid choice] [8 bits mux ID]*
\r
497 #define CLK_ATTACH_ID(mux, sel, pos) (((mux << 0U) | ((sel + 1) & 0xFU) << 8U) << (pos * 12U))
\r
498 #define MUX_A(mux, sel) CLK_ATTACH_ID(mux, sel, 0U)
\r
499 #define MUX_B(mux, sel, selector) (CLK_ATTACH_ID(mux, sel, 1U) | (selector << 24U))
\r
501 #define GET_ID_ITEM(connection) ((connection)&0xFFFU)
\r
502 #define GET_ID_NEXT_ITEM(connection) ((connection) >> 12U)
\r
503 #define GET_ID_ITEM_MUX(connection) ((connection)&0xFFU)
\r
504 #define GET_ID_ITEM_SEL(connection) ((((connection)&0xF00U) >> 8U) - 1U)
\r
505 #define GET_ID_SELECTOR(connection) ((connection)&0xF000000U)
\r
507 #define CM_SYSTICKCLKSEL0 0
\r
508 #define CM_SYSTICKCLKSEL1 1
\r
509 #define CM_TRACECLKSEL 2
\r
510 #define CM_CTIMERCLKSEL0 3
\r
511 #define CM_CTIMERCLKSEL1 4
\r
512 #define CM_CTIMERCLKSEL2 5
\r
513 #define CM_CTIMERCLKSEL3 6
\r
514 #define CM_CTIMERCLKSEL4 7
\r
515 #define CM_MAINCLKSELA 8
\r
516 #define CM_MAINCLKSELB 9
\r
517 #define CM_CLKOUTCLKSEL 10
\r
518 #define CM_PLL0CLKSEL 12
\r
519 #define CM_PLL1CLKSEL 13
\r
520 #define CM_ADCASYNCCLKSEL 17
\r
521 #define CM_USB0CLKSEL 18
\r
522 #define CM_FXCOMCLKSEL0 20
\r
523 #define CM_FXCOMCLKSEL1 21
\r
524 #define CM_FXCOMCLKSEL2 22
\r
525 #define CM_FXCOMCLKSEL3 23
\r
526 #define CM_FXCOMCLKSEL4 24
\r
527 #define CM_FXCOMCLKSEL5 25
\r
528 #define CM_FXCOMCLKSEL6 26
\r
529 #define CM_FXCOMCLKSEL7 27
\r
530 #define CM_HSLSPICLKSEL 28
\r
531 #define CM_MCLKCLKSEL 32
\r
532 #define CM_SCTCLKSEL 36
\r
533 #define CM_SDIOCLKSEL 38
\r
535 #define CM_RTCOSC32KCLKSEL 63
\r
537 typedef enum _clock_attach_id
\r
540 kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0, 0),
\r
541 kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0, 0),
\r
542 kFRO1M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0, 0),
\r
543 kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0, 0),
\r
544 kPLL0_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 1, 0),
\r
545 kPLL1_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 2, 0),
\r
546 kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 3, 0),
\r
548 kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 0),
\r
549 kPLL0_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 1),
\r
550 kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 2),
\r
551 kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 3),
\r
552 kFRO1M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 4),
\r
553 kPLL1_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 5),
\r
554 kOSC32K_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 6),
\r
555 kNONE_to_SYS_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 7),
\r
557 kFRO12M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 0),
\r
558 kEXT_CLK_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 1),
\r
559 kFRO1M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 2),
\r
560 kOSC32K_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 3),
\r
561 kNONE_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 7),
\r
563 kMAIN_CLK_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0),
\r
564 kPLL0_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1),
\r
565 kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2),
\r
566 kFRO1M_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 3), /* Need confirm */
\r
567 kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7),
\r
569 kMAIN_CLK_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 0),
\r
570 kPLL0_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 1),
\r
571 kFRO_HF_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 3),
\r
572 kPLL1_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 5),
\r
573 kNONE_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 7),
\r
575 kMAIN_CLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0),
\r
576 kPLL0_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1),
\r
577 kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2),
\r
578 kFRO_HF_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3),
\r
579 kFRO1M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4),
\r
580 kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 5),
\r
581 kOSC32K_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 6),
\r
582 kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7),
\r
584 kMAIN_CLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0),
\r
585 kPLL0_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1),
\r
586 kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2),
\r
587 kFRO_HF_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3),
\r
588 kFRO1M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4),
\r
589 kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 5),
\r
590 kOSC32K_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 6),
\r
591 kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7),
\r
593 kMAIN_CLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0),
\r
594 kPLL0_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1),
\r
595 kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2),
\r
596 kFRO_HF_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3),
\r
597 kFRO1M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4),
\r
598 kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 5),
\r
599 kOSC32K_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 6),
\r
600 kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7),
\r
602 kMAIN_CLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0),
\r
603 kPLL0_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1),
\r
604 kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2),
\r
605 kFRO_HF_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3),
\r
606 kFRO1M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4),
\r
607 kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 5),
\r
608 kOSC32K_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 6),
\r
609 kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7),
\r
611 kMAIN_CLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0),
\r
612 kPLL0_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1),
\r
613 kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2),
\r
614 kFRO_HF_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3),
\r
615 kFRO1M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4),
\r
616 kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 5),
\r
617 kOSC32K_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 6),
\r
618 kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7),
\r
620 kMAIN_CLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0),
\r
621 kPLL0_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1),
\r
622 kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2),
\r
623 kFRO_HF_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3),
\r
624 kFRO1M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4),
\r
625 kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 5),
\r
626 kOSC32K_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 6),
\r
627 kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7),
\r
629 kMAIN_CLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0),
\r
630 kPLL0_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1),
\r
631 kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2),
\r
632 kFRO_HF_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3),
\r
633 kFRO1M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4),
\r
634 kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 5),
\r
635 kOSC32K_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 6),
\r
636 kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7),
\r
638 kMAIN_CLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0),
\r
639 kPLL0_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1),
\r
640 kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2),
\r
641 kFRO_HF_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3),
\r
642 kFRO1M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4),
\r
643 kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 5),
\r
644 kOSC32K_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 6),
\r
645 kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7),
\r
647 kMAIN_CLK_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 0),
\r
648 kPLL0_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 1),
\r
649 kFRO12M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 2),
\r
650 kFRO_HF_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 3),
\r
651 kFRO1M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 4),
\r
652 kOSC32K_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 6),
\r
653 kNONE_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 7),
\r
655 kFRO_HF_to_MCLK = MUX_A(CM_MCLKCLKSEL, 0),
\r
656 kPLL0_to_MCLK = MUX_A(CM_MCLKCLKSEL, 1),
\r
657 kFRO1M_to_MCLK = MUX_A(CM_MCLKCLKSEL, 2), /* Need confirm */
\r
658 kMAIN_CLK_to_MCLK = MUX_A(CM_MCLKCLKSEL, 3), /* Need confirm */
\r
659 kNONE_to_MCLK = MUX_A(CM_MCLKCLKSEL, 7),
\r
661 kMAIN_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 0),
\r
662 kPLL0_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 1),
\r
663 kEXT_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 2),
\r
664 kFRO_HF_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 3),
\r
665 kMCLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 5),
\r
666 kNONE_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 7),
\r
668 kMAIN_CLK_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 0),
\r
669 kPLL0_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 1),
\r
670 kFRO_HF_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 3),
\r
671 kPLL1_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 5),
\r
672 kNONE_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 7),
\r
674 kFRO32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 0),
\r
675 kXTAL32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 1),
\r
677 kTRACE_DIV_to_TRACE = MUX_A(CM_TRACECLKSEL, 0),
\r
678 kFRO1M_to_TRACE = MUX_A(CM_TRACECLKSEL, 1),
\r
679 kOSC32K_to_TRACE = MUX_A(CM_TRACECLKSEL, 2),
\r
680 kNONE_to_TRACE = MUX_A(CM_TRACECLKSEL, 7),
\r
682 kSYSTICK_DIV0_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 0),
\r
683 kFRO1M_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 1),
\r
684 kOSC32K_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 2),
\r
685 kNONE_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 7),
\r
687 kSYSTICK_DIV1_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 0),
\r
688 kFRO1M_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 1),
\r
689 kOSC32K_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 2),
\r
690 kNONE_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 7),
\r
692 kFRO12M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 0),
\r
693 kEXT_CLK_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 1),
\r
694 kFRO1M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 2),
\r
695 kOSC32K_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 3),
\r
696 kNONE_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 7),
\r
698 kMAIN_CLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 0),
\r
699 kPLL0_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 1),
\r
700 kFRO_HF_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 3),
\r
701 kFRO1M_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 4),
\r
702 kMCLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 5),
\r
703 kOSC32K_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 6),
\r
704 kNONE_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 7),
\r
706 kMAIN_CLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 0),
\r
707 kPLL0_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 1),
\r
708 kFRO_HF_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 3),
\r
709 kFRO1M_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 4),
\r
710 kMCLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 5),
\r
711 kOSC32K_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 6),
\r
712 kNONE_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 7),
\r
714 kMAIN_CLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 0),
\r
715 kPLL0_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 1),
\r
716 kFRO_HF_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 3),
\r
717 kFRO1M_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 4),
\r
718 kMCLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 5),
\r
719 kOSC32K_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 6),
\r
720 kNONE_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 7),
\r
722 kMAIN_CLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 0),
\r
723 kPLL0_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 1),
\r
724 kFRO_HF_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 3),
\r
725 kFRO1M_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 4),
\r
726 kMCLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 5),
\r
727 kOSC32K_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 6),
\r
728 kNONE_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 7),
\r
730 kMAIN_CLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 0),
\r
731 kPLL0_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 1),
\r
732 kFRO_HF_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 3),
\r
733 kFRO1M_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 4),
\r
734 kMCLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 5),
\r
735 kOSC32K_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 6),
\r
736 kNONE_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 7),
\r
737 kNONE_to_NONE = (int)0x80000000U,
\r
738 } clock_attach_id_t;
\r
740 /* Clock dividers */
\r
741 typedef enum _clock_div_name
\r
743 kCLOCK_DivSystickClk0 = 0,
\r
744 kCLOCK_DivSystickClk1 = 1,
\r
745 kCLOCK_DivArmTrClkDiv = 2,
\r
746 kCLOCK_DivFlexFrg0 = 8,
\r
747 kCLOCK_DivFlexFrg1 = 9,
\r
748 kCLOCK_DivFlexFrg2 = 10,
\r
749 kCLOCK_DivFlexFrg3 = 11,
\r
750 kCLOCK_DivFlexFrg4 = 12,
\r
751 kCLOCK_DivFlexFrg5 = 13,
\r
752 kCLOCK_DivFlexFrg6 = 14,
\r
753 kCLOCK_DivFlexFrg7 = 15,
\r
754 kCLOCK_DivAhbClk = 32,
\r
755 kCLOCK_DivClkOut = 33,
\r
756 kCLOCK_DivFrohfClk = 34,
\r
757 kCLOCK_DivWdtClk = 35,
\r
758 kCLOCK_DivAdcAsyncClk = 37,
\r
759 kCLOCK_DivUsb0Clk = 38,
\r
760 kCLOCK_DivMClk = 43,
\r
761 kCLOCK_DivSctClk = 45,
\r
762 kCLOCK_DivSdioClk = 47,
\r
763 kCLOCK_DivPll0Clk = 49
\r
764 } clock_div_name_t;
\r
766 /*******************************************************************************
\r
768 ******************************************************************************/
\r
770 #if defined(__cplusplus)
\r
772 #endif /* __cplusplus */
\r
775 * @brief Enable the clock for specific IP.
\r
776 * @param name : Clock to be enabled.
\r
779 static inline void CLOCK_EnableClock(clock_ip_name_t clk)
\r
781 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
\r
782 SYSCON->AHBCLKCTRLSET[index] = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
\r
785 * @brief Disable the clock for specific IP.
\r
786 * @param name : Clock to be Disabled.
\r
789 static inline void CLOCK_DisableClock(clock_ip_name_t clk)
\r
791 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
\r
792 SYSCON->AHBCLKCTRLCLR[index] = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
\r
795 * @brief Initialize the Core clock to given frequency (12, 48 or 96 MHz).
\r
796 * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is
\r
798 * @param iFreq : Desired frequency (must be one of #CLK_FRO_12MHZ or #CLK_FRO_48MHZ or #CLK_FRO_96MHZ)
\r
799 * @return returns success or fail status.
\r
801 status_t CLOCK_SetupFROClocking(uint32_t iFreq);
\r
803 * @brief Set the flash wait states for the input freuqency.
\r
804 * @param iFreq : Input frequency
\r
807 void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq);
\r
809 * @brief Initialize the external osc clock to given frequency.
\r
810 * @param iFreq : Desired frequency (must be equal to exact rate in Hz)
\r
811 * @return returns success or fail status.
\r
813 status_t CLOCK_SetupExtClocking(uint32_t iFreq);
\r
815 * @brief Initialize the I2S MCLK clock to given frequency.
\r
816 * @param iFreq : Desired frequency (must be equal to exact rate in Hz)
\r
817 * @return returns success or fail status.
\r
819 status_t CLOCK_SetupI2SMClkClocking(uint32_t iFreq);
\r
821 * @brief Configure the clock selection muxes.
\r
822 * @param connection : Clock to be configured.
\r
825 void CLOCK_AttachClk(clock_attach_id_t connection);
\r
827 * @brief Get the actual clock attach id.
\r
828 * This fuction uses the offset in input attach id, then it reads the actual source value in
\r
829 * the register and combine the offset to obtain an actual attach id.
\r
830 * @param attachId : Clock attach id to get.
\r
831 * @return Clock source value.
\r
833 clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId);
\r
835 * @brief Setup peripheral clock dividers.
\r
836 * @param div_name : Clock divider name
\r
837 * @param divided_by_value: Value to be divided
\r
838 * @param reset : Whether to reset the divider counter.
\r
841 void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset);
\r
843 * @brief Setup rtc 1khz clock divider.
\r
844 * @param divided_by_value: Value to be divided
\r
847 void CLOCK_SetRtc1khzClkDiv(uint32_t divided_by_value);
\r
849 * @brief Setup rtc 1hz clock divider.
\r
850 * @param divided_by_value: Value to be divided
\r
853 void CLOCK_SetRtc1hzClkDiv(uint32_t divided_by_value);
\r
856 * @brief Set the flexcomm output frequency.
\r
857 * @param id : flexcomm instance id
\r
858 * freq : output frequency
\r
859 * @return 0 : the frequency range is out of range.
\r
860 * 1 : switch successfully.
\r
862 uint32_t CLOCK_SetFlexCommClock(uint32_t id, uint32_t freq);
\r
864 /*! @brief Return Frequency of flexcomm input clock
\r
865 * @param id : flexcomm instance id
\r
866 * @return Frequency value
\r
868 uint32_t CLOCK_GetFlexCommInputClock(uint32_t id);
\r
870 /*! @brief Return Frequency of selected clock
\r
871 * @return Frequency of selected clock
\r
873 uint32_t CLOCK_GetFreq(clock_name_t clockName);
\r
874 /*! @brief Return Frequency of FRO 12MHz
\r
875 * @return Frequency of FRO 12MHz
\r
877 uint32_t CLOCK_GetFro12MFreq(void);
\r
878 /*! @brief Return Frequency of FRO 1MHz
\r
879 * @return Frequency of FRO 1MHz
\r
881 uint32_t CLOCK_GetFro1MFreq(void);
\r
882 /*! @brief Return Frequency of ClockOut
\r
883 * @return Frequency of ClockOut
\r
885 uint32_t CLOCK_GetClockOutClkFreq(void);
\r
886 /*! @brief Return Frequency of Adc Clock
\r
887 * @return Frequency of Adc.
\r
889 uint32_t CLOCK_GetAdcClkFreq(void);
\r
890 /*! @brief Return Frequency of Usb0 Clock
\r
891 * @return Frequency of Usb0 Clock.
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893 uint32_t CLOCK_GetUsb0ClkFreq(void);
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894 /*! @brief Return Frequency of Usb1 Clock
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895 * @return Frequency of Usb1 Clock.
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897 uint32_t CLOCK_GetUsb1ClkFreq(void);
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898 /*! @brief Return Frequency of MClk Clock
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899 * @return Frequency of MClk Clock.
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901 uint32_t CLOCK_GetMclkClkFreq(void);
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902 /*! @brief Return Frequency of SCTimer Clock
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903 * @return Frequency of SCTimer Clock.
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905 uint32_t CLOCK_GetSctClkFreq(void);
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906 /*! @brief Return Frequency of SDIO Clock
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907 * @return Frequency of SDIO Clock.
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909 uint32_t CLOCK_GetSdioClkFreq(void);
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910 /*! @brief Return Frequency of External Clock
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911 * @return Frequency of External Clock. If no external clock is used returns 0.
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913 uint32_t CLOCK_GetExtClkFreq(void);
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914 /*! @brief Return Frequency of Watchdog
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915 * @return Frequency of Watchdog
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917 uint32_t CLOCK_GetWdtClkFreq(void);
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918 /*! @brief Return Frequency of High-Freq output of FRO
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919 * @return Frequency of High-Freq output of FRO
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921 uint32_t CLOCK_GetFroHfFreq(void);
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922 /*! @brief Return Frequency of PLL
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923 * @return Frequency of PLL
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925 uint32_t CLOCK_GetPll0OutFreq(void);
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926 /*! @brief Return Frequency of USB PLL
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927 * @return Frequency of PLL
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929 uint32_t CLOCK_GetPll1OutFreq(void);
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930 /*! @brief Return Frequency of 32kHz osc
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931 * @return Frequency of 32kHz osc
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933 uint32_t CLOCK_GetOsc32KFreq(void);
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934 /*! @brief Return Frequency of Core System
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935 * @return Frequency of Core System
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937 uint32_t CLOCK_GetCoreSysClkFreq(void);
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938 /*! @brief Return Frequency of I2S MCLK Clock
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939 * @return Frequency of I2S MCLK Clock
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941 uint32_t CLOCK_GetI2SMClkFreq(void);
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942 /*! @brief Return Frequency of CTimer functional Clock
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943 * @return Frequency of CTimer functional Clock
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945 uint32_t CLOCK_GetCTimerClkFreq(uint32_t id);
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946 /*! @brief Return Frequency of SystickClock
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947 * @return Frequency of Systick Clock
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949 uint32_t CLOCK_GetSystickClkFreq(uint32_t id);
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951 /*! @brief Return PLL0 input clock rate
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952 * @return PLL0 input clock rate
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954 uint32_t CLOCK_GetPLL0InClockRate(void);
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956 /*! @brief Return PLL1 input clock rate
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957 * @return PLL1 input clock rate
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959 uint32_t CLOCK_GetPLL1InClockRate(void);
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961 /*! @brief Return PLL0 output clock rate
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962 * @param recompute : Forces a PLL rate recomputation if true
\r
963 * @return PLL0 output clock rate
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964 * @note The PLL rate is cached in the driver in a variable as
\r
965 * the rate computation function can take some time to perform. It
\r
966 * is recommended to use 'false' with the 'recompute' parameter.
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968 uint32_t CLOCK_GetPLL0OutClockRate(bool recompute);
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970 /*! @brief Return PLL1 output clock rate
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971 * @param recompute : Forces a PLL rate recomputation if true
\r
972 * @return PLL1 output clock rate
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973 * @note The PLL rate is cached in the driver in a variable as
\r
974 * the rate computation function can take some time to perform. It
\r
975 * is recommended to use 'false' with the 'recompute' parameter.
\r
977 uint32_t CLOCK_GetPLL1OutClockRate(bool recompute);
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979 /*! @brief Enables and disables PLL0 bypass mode
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980 * @brief bypass : true to bypass PLL0 (PLL0 output = PLL0 input, false to disable bypass
\r
981 * @return PLL0 output clock rate
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983 __STATIC_INLINE void CLOCK_SetBypassPLL0(bool bypass)
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987 SYSCON->PLL0CTRL |= (1UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT);
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991 SYSCON->PLL0CTRL &= ~(1UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT);
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995 /*! @brief Enables and disables PLL1 bypass mode
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996 * @brief bypass : true to bypass PLL1 (PLL1 output = PLL1 input, false to disable bypass
\r
997 * @return PLL1 output clock rate
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999 __STATIC_INLINE void CLOCK_SetBypassPLL1(bool bypass)
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1003 SYSCON->PLL1CTRL |= (1UL << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT);
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1007 SYSCON->PLL1CTRL &= ~(1UL << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT);
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1011 /*! @brief Check if PLL is locked or not
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1012 * @return true if the PLL is locked, false if not locked
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1014 __STATIC_INLINE bool CLOCK_IsPLL0Locked(void)
\r
1016 return (bool)((SYSCON->PLL0STAT & SYSCON_PLL0STAT_LOCK_MASK) != 0);
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1019 /*! @brief Check if PLL1 is locked or not
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1020 * @return true if the PLL1 is locked, false if not locked
\r
1022 __STATIC_INLINE bool CLOCK_IsPLL1Locked(void)
\r
1024 return (bool)((SYSCON->PLL1STAT & SYSCON_PLL1STAT_LOCK_MASK) != 0);
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1027 /*! @brief Store the current PLL0 rate
\r
1028 * @param rate: Current rate of the PLL0
\r
1031 void CLOCK_SetStoredPLL0ClockRate(uint32_t rate);
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1033 /*! @brief PLL configuration structure flags for 'flags' field
\r
1034 * These flags control how the PLL configuration function sets up the PLL setup structure.<br>
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1036 * When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the
\r
1037 * configuration structure must be assigned with the expected PLL frequency. If the
\r
1038 * PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration
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1039 * function and the driver will determine the PLL rate from the currently selected
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1040 * PLL source. This flag might be used to configure the PLL input clock more accurately
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1041 * when using the WDT oscillator or a more dyanmic CLKIN source.<br>
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1043 * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the
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1044 * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider
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1045 * are not used.<br>
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1047 #define PLL_CONFIGFLAG_USEINRATE (1 << 0) /*!< Flag to use InputRate in PLL configuration structure for setup */
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1048 #define PLL_CONFIGFLAG_FORCENOFRACT (1 << 2)
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1049 /*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS hardware */
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1051 /*! @brief PLL Spread Spectrum (SS) Programmable modulation frequency
\r
1052 * See (MF) field in the PLL0SSCG1 register in the UM.
\r
1054 typedef enum _ss_progmodfm
\r
1056 kSS_MF_512 = (0 << 20), /*!< Nss = 512 (fm ? 3.9 - 7.8 kHz) */
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1057 kSS_MF_384 = (1 << 20), /*!< Nss ?= 384 (fm ? 5.2 - 10.4 kHz) */
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1058 kSS_MF_256 = (2 << 20), /*!< Nss = 256 (fm ? 7.8 - 15.6 kHz) */
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1059 kSS_MF_128 = (3 << 20), /*!< Nss = 128 (fm ? 15.6 - 31.3 kHz) */
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1060 kSS_MF_64 = (4 << 20), /*!< Nss = 64 (fm ? 32.3 - 64.5 kHz) */
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1061 kSS_MF_32 = (5 << 20), /*!< Nss = 32 (fm ? 62.5- 125 kHz) */
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1062 kSS_MF_24 = (6 << 20), /*!< Nss ?= 24 (fm ? 83.3- 166.6 kHz) */
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1063 kSS_MF_16 = (7 << 20) /*!< Nss = 16 (fm ? 125- 250 kHz) */
\r
1066 /*! @brief PLL Spread Spectrum (SS) Programmable frequency modulation depth
\r
1067 * See (MR) field in the PLL0SSCG1 register in the UM.
\r
1069 typedef enum _ss_progmoddp
\r
1071 kSS_MR_K0 = (0 << 23), /*!< k = 0 (no spread spectrum) */
\r
1072 kSS_MR_K1 = (1 << 23), /*!< k = 1 */
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1073 kSS_MR_K1_5 = (2 << 23), /*!< k = 1.5 */
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1074 kSS_MR_K2 = (3 << 23), /*!< k = 2 */
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1075 kSS_MR_K3 = (4 << 23), /*!< k = 3 */
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1076 kSS_MR_K4 = (5 << 23), /*!< k = 4 */
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1077 kSS_MR_K6 = (6 << 23), /*!< k = 6 */
\r
1078 kSS_MR_K8 = (7 << 23) /*!< k = 8 */
\r
1081 /*! @brief PLL Spread Spectrum (SS) Modulation waveform control
\r
1082 * See (MC) field in the PLL0SSCG1 register in the UM.<br>
\r
1083 * Compensation for low pass filtering of the PLL to get a triangular
\r
1084 * modulation at the output of the PLL, giving a flat frequency spectrum.
\r
1086 typedef enum _ss_modwvctrl
\r
1088 kSS_MC_NOC = (0 << 26), /*!< no compensation */
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1089 kSS_MC_RECC = (2 << 26), /*!< recommended setting */
\r
1090 kSS_MC_MAXC = (3 << 26), /*!< max. compensation */
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1093 /*! @brief PLL configuration structure
\r
1095 * This structure can be used to configure the settings for a PLL
\r
1096 * setup structure. Fill in the desired configuration for the PLL
\r
1097 * and call the PLL setup function to fill in a PLL setup structure.
\r
1099 typedef struct _pll_config
\r
1101 uint32_t desiredRate; /*!< Desired PLL rate in Hz */
\r
1102 uint32_t inputRate; /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */
\r
1103 uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */
\r
1104 ss_progmodfm_t ss_mf; /*!< SS Programmable modulation frequency, only applicable when not using
\r
1105 PLL_CONFIGFLAG_FORCENOFRACT flag */
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1106 ss_progmoddp_t ss_mr; /*!< SS Programmable frequency modulation depth, only applicable when not using
\r
1107 PLL_CONFIGFLAG_FORCENOFRACT flag */
\r
1109 ss_mc; /*!< SS Modulation waveform control, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag */
\r
1110 bool mfDither; /*!< false for fixed modulation frequency or true for dithering, only applicable when not using
\r
1111 PLL_CONFIGFLAG_FORCENOFRACT flag */
\r
1115 /*! @brief PLL setup structure flags for 'flags' field
\r
1116 * These flags control how the PLL setup function sets up the PLL
\r
1118 #define PLL_SETUPFLAG_POWERUP (1 << 0) /*!< Setup will power on the PLL after setup */
\r
1119 #define PLL_SETUPFLAG_WAITLOCK (1 << 1) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */
\r
1120 #define PLL_SETUPFLAG_ADGVOLT (1 << 2) /*!< Optimize system voltage for the new PLL rate */
\r
1121 #define PLL_SETUPFLAG_USEFEEDBACKDIV2 (1 << 3) /*!< Use feedback divider by 2 in divider path */
\r
1123 /*! @brief PLL0 setup structure
\r
1124 * This structure can be used to pre-build a PLL setup configuration
\r
1125 * at run-time and quickly set the PLL to the configuration. It can be
\r
1126 * populated with the PLL setup function. If powering up or waiting
\r
1127 * for PLL lock, the PLL input clock source should be configured prior
\r
1130 typedef struct _pll_setup
\r
1132 uint32_t pllctrl; /*!< PLL control register PLL0CTRL */
\r
1133 uint32_t pllndec; /*!< PLL NDEC register PLL0NDEC */
\r
1134 uint32_t pllpdec; /*!< PLL PDEC register PLL0PDEC */
\r
1135 uint32_t pllmdec; /*!< PLL MDEC registers PLL0PDEC */
\r
1136 uint32_t pllsscg[2]; /*!< PLL SSCTL registers PLL0SSCG*/
\r
1137 uint32_t pllRate; /*!< Acutal PLL rate */
\r
1138 uint32_t flags; /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */
\r
1141 /*! @brief PLL status definitions
\r
1143 typedef enum _pll_error
\r
1145 kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */
\r
1146 kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */
\r
1147 kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */
\r
1148 kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */
\r
1149 kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */
\r
1150 kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Requested output rate isn't possible */
\r
1151 kStatus_PLL_CCOTooLow = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Requested CCO rate isn't possible */
\r
1152 kStatus_PLL_CCOTooHigh = MAKE_STATUS(kStatusGroup_Generic, 7) /*!< Requested CCO rate isn't possible */
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1155 /*! @brief USB FS clock source definition. */
\r
1156 typedef enum _clock_usbfs_src
\r
1158 kCLOCK_UsbfsSrcFro = (uint32_t)kCLOCK_FroHf, /*!< Use FRO 96 MHz. */
\r
1159 kCLOCK_UsbfsSrcPll0 = (uint32_t)kCLOCK_Pll0Out, /*!< Use PLL0 output. */
\r
1160 kCLOCK_UsbfsSrcMainClock = (uint32_t)kCLOCK_CoreSysClk, /*!< Use Main clock. */
\r
1161 kCLOCK_UsbfsSrcPll1 = (uint32_t)kCLOCK_Pll1Out, /*!< Use PLL1 clock. */
\r
1163 kCLOCK_UsbfsSrcNone =
\r
1164 SYSCON_USB0CLKSEL_SEL(7) /*!<this may be selected in order to reduce power when no output is needed. */
\r
1165 } clock_usbfs_src_t;
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1167 /*! @brief USBhs clock source definition. */
\r
1168 typedef enum _clock_usbhs_src
\r
1170 kCLOCK_UsbSrcUnused = 0xFFFFFFFFU, /*!< Used when the function does not
\r
1171 care the clock source. */
\r
1172 } clock_usbhs_src_t;
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1174 /*! @brief Source of the USB HS PHY. */
\r
1175 typedef enum _clock_usb_phy_src
\r
1177 kCLOCK_UsbPhySrcExt = 0U, /*!< Use external crystal. */
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1178 } clock_usb_phy_src_t;
\r
1180 /*! @brief Return PLL0 output clock rate from setup structure
\r
1181 * @param pSetup : Pointer to a PLL setup structure
\r
1182 * @return System PLL output clock rate the setup structure will generate
\r
1184 uint32_t CLOCK_GetPLL0OutFromSetup(pll_setup_t *pSetup);
\r
1186 /*! @brief Set PLL0 output based on the passed PLL setup data
\r
1187 * @param pControl : Pointer to populated PLL control structure to generate setup with
\r
1188 * @param pSetup : Pointer to PLL setup structure to be filled
\r
1189 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
\r
1190 * @note Actual frequency for setup may vary from the desired frequency based on the
\r
1191 * accuracy of input clocks, rounding, non-fractional PLL mode, etc.
\r
1193 pll_error_t CLOCK_SetupPLL0Data(pll_config_t *pControl, pll_setup_t *pSetup);
\r
1195 /*! @brief Set PLL output from PLL setup structure (precise frequency)
\r
1196 * @param pSetup : Pointer to populated PLL setup structure
\r
1197 * @param flagcfg : Flag configuration for PLL config structure
\r
1198 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
\r
1199 * @note This function will power off the PLL, setup the PLL with the
\r
1200 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
\r
1201 * and adjust system voltages to the new PLL rate. The function will not
\r
1202 * alter any source clocks (ie, main systen clock) that may use the PLL,
\r
1203 * so these should be setup prior to and after exiting the function.
\r
1205 pll_error_t CLOCK_SetupPLL0Prec(pll_setup_t *pSetup, uint32_t flagcfg);
\r
1208 * @brief Set PLL output from PLL setup structure (precise frequency)
\r
1209 * @param pSetup : Pointer to populated PLL setup structure
\r
1210 * @return kStatus_PLL_Success on success, or PLL setup error code
\r
1211 * @note This function will power off the PLL, setup the PLL with the
\r
1212 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
\r
1213 * and adjust system voltages to the new PLL rate. The function will not
\r
1214 * alter any source clocks (ie, main systen clock) that may use the PLL,
\r
1215 * so these should be setup prior to and after exiting the function.
\r
1217 pll_error_t CLOCK_SetPLL0Freq(const pll_setup_t *pSetup);
\r
1220 * @brief Set PLL output from PLL setup structure (precise frequency)
\r
1221 * @param pSetup : Pointer to populated PLL setup structure
\r
1222 * @return kStatus_PLL_Success on success, or PLL setup error code
\r
1223 * @note This function will power off the PLL, setup the PLL with the
\r
1224 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
\r
1225 * and adjust system voltages to the new PLL rate. The function will not
\r
1226 * alter any source clocks (ie, main systen clock) that may use the PLL,
\r
1227 * so these should be setup prior to and after exiting the function.
\r
1229 pll_error_t CLOCK_SetPLL1Freq(const pll_setup_t *pSetup);
\r
1231 /*! @brief Set PLL0 output based on the multiplier and input frequency
\r
1232 * @param multiply_by : multiplier
\r
1233 * @param input_freq : Clock input frequency of the PLL
\r
1235 * @note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this
\r
1236 * function does not disable or enable PLL power, wait for PLL lock,
\r
1237 * or adjust system voltages. These must be done in the application.
\r
1238 * The function will not alter any source clocks (ie, main systen clock)
\r
1239 * that may use the PLL, so these should be setup prior to and after
\r
1240 * exiting the function.
\r
1242 void CLOCK_SetupPLL0Mult(uint32_t multiply_by, uint32_t input_freq);
\r
1244 /*! @brief Disable USB clock.
\r
1246 * Disable USB clock.
\r
1248 static inline void CLOCK_DisableUsbDevicefs0Clock(clock_ip_name_t clk)
\r
1250 CLOCK_DisableClock(clk);
\r
1253 /*! @brief Enable USB Device FS clock.
\r
1254 * @param src : clock source
\r
1255 * @param freq: clock frequency
\r
1256 * Enable USB Device Full Speed clock.
\r
1258 bool CLOCK_EnableUsbfs0DeviceClock(clock_usbfs_src_t src, uint32_t freq);
\r
1260 /*! @brief Enable USB HOST FS clock.
\r
1261 * @param src : clock source
\r
1262 * @param freq: clock frequency
\r
1263 * Enable USB HOST Full Speed clock.
\r
1265 bool CLOCK_EnableUsbfs0HostClock(clock_usbfs_src_t src, uint32_t freq);
\r
1267 /*! @brief Enable USB phy clock.
\r
1268 * Enable USB phy clock.
\r
1270 bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq);
\r
1272 /*! @brief Enable USB Device HS clock.
\r
1273 * Enable USB Device High Speed clock.
\r
1275 bool CLOCK_EnableUsbhs0DeviceClock(clock_usbhs_src_t src, uint32_t freq);
\r
1277 /*! @brief Enable USB HOST HS clock.
\r
1278 * Enable USB HOST High Speed clock.
\r
1280 bool CLOCK_EnableUsbhs0HostClock(clock_usbhs_src_t src, uint32_t freq);
\r
1282 #if defined(__cplusplus)
\r
1284 #endif /* __cplusplus */
\r
1288 #endif /* _FSL_CLOCK_H_ */
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projects / freertos / blob