2 * Copyright 2017 - 2019 , NXP
\r
3 * All rights reserved.
\r
5 * SPDX-License-Identifier: BSD-3-Clause
\r
8 #ifndef _FSL_CLOCK_H_
\r
9 #define _FSL_CLOCK_H_
\r
11 #include "fsl_common.h"
\r
13 /*! @addtogroup clock */
\r
18 /*******************************************************************************
\r
20 *****************************************************************************/
\r
22 /*! @name Driver version */
\r
24 /*! @brief CLOCK driver version 2.3.1. */
\r
25 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 1))
\r
28 /*! @brief Configure whether driver controls clock
\r
30 * When set to 0, peripheral drivers will enable clock in initialize function
\r
31 * and disable clock in de-initialize function. When set to 1, peripheral
\r
32 * driver will not control the clock, application could control the clock out of
\r
35 * @note All drivers share this feature switcher. If it is set to 1, application
\r
36 * should handle clock enable and disable for all drivers.
\r
38 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
\r
39 #define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
\r
43 * @brief User-defined the size of cache for CLOCK_PllGetConfig() function.
\r
45 * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function
\r
46 * would cache the recent calulation and accelerate the execution to get the
\r
49 #ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT
\r
50 #define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U
\r
53 /* Definition for delay API in clock driver, users can redefine it to the real application. */
\r
54 #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
\r
55 #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (150000000UL)
\r
58 /*! @brief Clock ip name array for ROM. */
\r
59 #define ROM_CLOCKS \
\r
63 /*! @brief Clock ip name array for SRAM. */
\r
64 #define SRAM_CLOCKS \
\r
66 kCLOCK_Sram1, kCLOCK_Sram2, kCLOCK_Sram3, kCLOCK_Sram4 \
\r
68 /*! @brief Clock ip name array for FLASH. */
\r
69 #define FLASH_CLOCKS \
\r
73 /*! @brief Clock ip name array for FMC. */
\r
74 #define FMC_CLOCKS \
\r
78 /*! @brief Clock ip name array for INPUTMUX. */
\r
79 #define INPUTMUX_CLOCKS \
\r
83 /*! @brief Clock ip name array for IOCON. */
\r
84 #define IOCON_CLOCKS \
\r
88 /*! @brief Clock ip name array for GPIO. */
\r
89 #define GPIO_CLOCKS \
\r
91 kCLOCK_Gpio0, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3 \
\r
93 /*! @brief Clock ip name array for PINT. */
\r
94 #define PINT_CLOCKS \
\r
98 /*! @brief Clock ip name array for GINT. */
\r
99 #define GINT_CLOCKS \
\r
101 kCLOCK_Gint, kCLOCK_Gint \
\r
103 /*! @brief Clock ip name array for DMA. */
\r
104 #define DMA_CLOCKS \
\r
106 kCLOCK_Dma0, kCLOCK_Dma1 \
\r
108 /*! @brief Clock ip name array for CRC. */
\r
109 #define CRC_CLOCKS \
\r
113 /*! @brief Clock ip name array for WWDT. */
\r
114 #define WWDT_CLOCKS \
\r
118 /*! @brief Clock ip name array for RTC. */
\r
119 #define RTC_CLOCKS \
\r
123 /*! @brief Clock ip name array for Mailbox. */
\r
124 #define MAILBOX_CLOCKS \
\r
128 /*! @brief Clock ip name array for LPADC. */
\r
129 #define LPADC_CLOCKS \
\r
133 /*! @brief Clock ip name array for MRT. */
\r
134 #define MRT_CLOCKS \
\r
138 /*! @brief Clock ip name array for OSTIMER. */
\r
139 #define OSTIMER_CLOCKS \
\r
143 /*! @brief Clock ip name array for SCT0. */
\r
144 #define SCT_CLOCKS \
\r
148 /*! @brief Clock ip name array for UTICK. */
\r
149 #define UTICK_CLOCKS \
\r
153 /*! @brief Clock ip name array for FLEXCOMM. */
\r
154 #define FLEXCOMM_CLOCKS \
\r
156 kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, kCLOCK_FlexComm4, kCLOCK_FlexComm5, \
\r
157 kCLOCK_FlexComm6, kCLOCK_FlexComm7, kCLOCK_Hs_Lspi \
\r
159 /*! @brief Clock ip name array for LPUART. */
\r
160 #define LPUART_CLOCKS \
\r
162 kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \
\r
163 kCLOCK_MinUart6, kCLOCK_MinUart7 \
\r
166 /*! @brief Clock ip name array for BI2C. */
\r
167 #define BI2C_CLOCKS \
\r
169 kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, kCLOCK_BI2c7 \
\r
171 /*! @brief Clock ip name array for LSPI. */
\r
172 #define LPSPI_CLOCKS \
\r
174 kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, kCLOCK_LSpi7 \
\r
176 /*! @brief Clock ip name array for FLEXI2S. */
\r
177 #define FLEXI2S_CLOCKS \
\r
179 kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \
\r
180 kCLOCK_FlexI2s6, kCLOCK_FlexI2s7 \
\r
182 /*! @brief Clock ip name array for CTIMER. */
\r
183 #define CTIMER_CLOCKS \
\r
185 kCLOCK_Timer0, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 \
\r
187 /*! @brief Clock ip name array for COMP */
\r
188 #define COMP_CLOCKS \
\r
192 /*! @brief Clock ip name array for SDIO. */
\r
193 #define SDIO_CLOCKS \
\r
197 /*! @brief Clock ip name array for USB1CLK. */
\r
198 #define USB1CLK_CLOCKS \
\r
202 /*! @brief Clock ip name array for FREQME. */
\r
203 #define FREQME_CLOCKS \
\r
207 /*! @brief Clock ip name array for USBRAM. */
\r
208 #define USBRAM_CLOCKS \
\r
212 /*! @brief Clock ip name array for RNG. */
\r
213 #define RNG_CLOCKS \
\r
217 /*! @brief Clock ip name array for USBHMR0. */
\r
218 #define USBHMR0_CLOCKS \
\r
222 /*! @brief Clock ip name array for USBHSL0. */
\r
223 #define USBHSL0_CLOCKS \
\r
227 /*! @brief Clock ip name array for HashCrypt. */
\r
228 #define HASHCRYPT_CLOCKS \
\r
232 /*! @brief Clock ip name array for PowerQuad. */
\r
233 #define POWERQUAD_CLOCKS \
\r
237 /*! @brief Clock ip name array for PLULUT. */
\r
238 #define PLULUT_CLOCKS \
\r
242 /*! @brief Clock ip name array for PUF. */
\r
243 #define PUF_CLOCKS \
\r
247 /*! @brief Clock ip name array for CASPER. */
\r
248 #define CASPER_CLOCKS \
\r
252 /*! @brief Clock ip name array for ANALOGCTRL. */
\r
253 #define ANALOGCTRL_CLOCKS \
\r
255 kCLOCK_AnalogCtrl \
\r
257 /*! @brief Clock ip name array for HS_LSPI. */
\r
258 #define HS_LSPI_CLOCKS \
\r
262 /*! @brief Clock ip name array for GPIO_SEC. */
\r
263 #define GPIO_SEC_CLOCKS \
\r
267 /*! @brief Clock ip name array for GPIO_SEC_INT. */
\r
268 #define GPIO_SEC_INT_CLOCKS \
\r
270 kCLOCK_Gpio_Sec_Int \
\r
272 /*! @brief Clock ip name array for USBD. */
\r
273 #define USBD_CLOCKS \
\r
275 kCLOCK_Usbd0, kCLOCK_Usbh1, kCLOCK_Usbd1 \
\r
277 /*! @brief Clock ip name array for USBH. */
\r
278 #define USBH_CLOCKS \
\r
282 #define PLU_CLOCKS \
\r
286 #define SYSCTL_CLOCKS \
\r
290 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
\r
291 /*------------------------------------------------------------------------------
\r
292 clock_ip_name_t definition:
\r
293 ------------------------------------------------------------------------------*/
\r
295 #define CLK_GATE_REG_OFFSET_SHIFT 8U
\r
296 #define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U
\r
297 #define CLK_GATE_BIT_SHIFT_SHIFT 0U
\r
298 #define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU
\r
300 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \
\r
301 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
\r
302 (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
\r
304 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
\r
305 #define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
\r
307 #define AHB_CLK_CTRL0 0
\r
308 #define AHB_CLK_CTRL1 1
\r
309 #define AHB_CLK_CTRL2 2
\r
311 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
\r
312 typedef enum _clock_ip_name
\r
314 kCLOCK_IpInvalid = 0U,
\r
315 kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1),
\r
316 kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3),
\r
317 kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4),
\r
318 kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5),
\r
319 kCLOCK_Sram4 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 6),
\r
320 kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7),
\r
321 kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8),
\r
322 kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11),
\r
323 kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13),
\r
324 kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14),
\r
325 kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15),
\r
326 kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16),
\r
327 kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17),
\r
328 kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18),
\r
329 kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19),
\r
330 kCLOCK_Dma0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20),
\r
331 kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21),
\r
332 kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22),
\r
333 kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23),
\r
334 kCLOCK_Mailbox = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 26),
\r
335 kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27),
\r
336 kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0),
\r
337 kCLOCK_OsTimer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1),
\r
338 kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2),
\r
339 kCLOCK_Utick0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10),
\r
340 kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
\r
341 kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
\r
342 kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
\r
343 kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
\r
344 kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
\r
345 kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
\r
346 kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
\r
347 kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
\r
348 kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
\r
349 kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
\r
350 kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
\r
351 kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
\r
352 kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
\r
353 kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
\r
354 kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
\r
355 kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
\r
356 kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
\r
357 kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
\r
358 kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
\r
359 kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
\r
360 kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
\r
361 kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
\r
362 kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
\r
363 kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
\r
364 kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
\r
365 kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
\r
366 kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
\r
367 kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
\r
368 kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
\r
369 kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
\r
370 kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
\r
371 kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
\r
372 kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
\r
373 kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
\r
374 kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
\r
375 kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
\r
376 kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
\r
377 kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
\r
378 kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
\r
379 kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
\r
380 kCLOCK_Timer2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22),
\r
381 kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25),
\r
382 kCLOCK_Timer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26),
\r
383 kCLOCK_Timer1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27),
\r
384 kCLOCK_Pvt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 28),
\r
385 kCLOCK_Ezha = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 30),
\r
386 kCLOCK_Ezhb = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31),
\r
387 kCLOCK_Dma1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 1),
\r
388 kCLOCK_Comp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2),
\r
389 kCLOCK_Sdio = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 3),
\r
390 kCLOCK_Usbh1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 4),
\r
391 kCLOCK_Usbd1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 5),
\r
392 kCLOCK_UsbRam1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 6),
\r
393 kCLOCK_Usb1Clk = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 7),
\r
394 kCLOCK_Freqme = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 8),
\r
395 kCLOCK_Rng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13),
\r
396 kCLOCK_InputMux1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
\r
397 kCLOCK_Sysctl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
\r
398 kCLOCK_Usbhmr0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16),
\r
399 kCLOCK_Usbhsl0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17),
\r
400 kCLOCK_HashCrypt = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18),
\r
401 kCLOCK_PowerQuad = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 19),
\r
402 kCLOCK_PluLut = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 20),
\r
403 kCLOCK_Timer3 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 21),
\r
404 kCLOCK_Timer4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 22),
\r
405 kCLOCK_Puf = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 23),
\r
406 kCLOCK_Casper = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 24),
\r
407 kCLOCK_AnalogCtrl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 27),
\r
408 kCLOCK_Hs_Lspi = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 28),
\r
409 kCLOCK_Gpio_Sec = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 29),
\r
410 kCLOCK_Gpio_Sec_Int = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 30)
\r
413 /*! @brief Peripherals clock source definition. */
\r
414 #define BUS_CLK kCLOCK_BusClk
\r
416 #define I2C0_CLK_SRC BUS_CLK
\r
418 /*! @brief Clock name used to get clock frequency. */
\r
419 typedef enum _clock_name
\r
421 kCLOCK_CoreSysClk, /*!< Core/system clock (aka MAIN_CLK) */
\r
422 kCLOCK_BusClk, /*!< Bus clock (AHB clock) */
\r
423 kCLOCK_ClockOut, /*!< CLOCKOUT */
\r
424 kCLOCK_FroHf, /*!< FRO48/96 */
\r
425 kCLOCK_Pll1Out, /*!< PLL1 Output */
\r
426 kCLOCK_Mclk, /*!< MCLK */
\r
427 kCLOCK_Fro12M, /*!< FRO12M */
\r
428 kCLOCK_ExtClk, /*!< External Clock */
\r
429 kCLOCK_Pll0Out, /*!< PLL0 Output */
\r
430 kCLOCK_FlexI2S, /*!< FlexI2S clock */
\r
434 /*! @brief Clock Mux Switches
\r
435 * The encoding is as follows each connection identified is 32bits wide while 24bits are valuable
\r
436 * starting from LSB upwards
\r
438 * [4 bits for choice, 0 means invalid choice] [8 bits mux ID]*
\r
442 #define CLK_ATTACH_ID(mux, sel, pos) \
\r
443 ((((uint32_t)(mux) << 0U) | (((uint32_t)(sel) + 1U) & 0xFU) << 8U) << ((uint32_t)(pos)*12U))
\r
444 #define MUX_A(mux, sel) CLK_ATTACH_ID((mux), (sel), 0U)
\r
445 #define MUX_B(mux, sel, selector) (CLK_ATTACH_ID((mux), (sel), 1U) | ((selector) << 24U))
\r
447 #define GET_ID_ITEM(connection) ((connection)&0xFFFU)
\r
448 #define GET_ID_NEXT_ITEM(connection) ((connection) >> 12U)
\r
449 #define GET_ID_ITEM_MUX(connection) (((uint8_t)connection) & 0xFFU)
\r
450 #define GET_ID_ITEM_SEL(connection) ((uint8_t)((((uint32_t)(connection)&0xF00U) >> 8U) - 1U))
\r
451 #define GET_ID_SELECTOR(connection) ((connection)&0xF000000U)
\r
453 #define CM_SYSTICKCLKSEL0 0U
\r
454 #define CM_SYSTICKCLKSEL1 1U
\r
455 #define CM_TRACECLKSEL 2U
\r
456 #define CM_CTIMERCLKSEL0 3U
\r
457 #define CM_CTIMERCLKSEL1 4U
\r
458 #define CM_CTIMERCLKSEL2 5U
\r
459 #define CM_CTIMERCLKSEL3 6U
\r
460 #define CM_CTIMERCLKSEL4 7U
\r
461 #define CM_MAINCLKSELA 8U
\r
462 #define CM_MAINCLKSELB 9U
\r
463 #define CM_CLKOUTCLKSEL 10U
\r
464 #define CM_PLL0CLKSEL 12U
\r
465 #define CM_PLL1CLKSEL 13U
\r
466 #define CM_ADCASYNCCLKSEL 17U
\r
467 #define CM_USB0CLKSEL 18U
\r
468 #define CM_FXCOMCLKSEL0 20U
\r
469 #define CM_FXCOMCLKSEL1 21U
\r
470 #define CM_FXCOMCLKSEL2 22U
\r
471 #define CM_FXCOMCLKSEL3 23U
\r
472 #define CM_FXCOMCLKSEL4 24U
\r
473 #define CM_FXCOMCLKSEL5 25U
\r
474 #define CM_FXCOMCLKSEL6 26U
\r
475 #define CM_FXCOMCLKSEL7 27U
\r
476 #define CM_HSLSPICLKSEL 28U
\r
477 #define CM_MCLKCLKSEL 32U
\r
478 #define CM_SCTCLKSEL 36U
\r
479 #define CM_SDIOCLKSEL 38U
\r
481 #define CM_RTCOSC32KCLKSEL 63U
\r
483 typedef enum _clock_attach_id
\r
486 kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0, 0),
\r
487 kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0, 0),
\r
488 kFRO1M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0, 0),
\r
489 kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0, 0),
\r
490 kPLL0_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 1, 0),
\r
491 kPLL1_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 2, 0),
\r
492 kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 3, 0),
\r
494 kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 0),
\r
495 kPLL0_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 1),
\r
496 kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 2),
\r
497 kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 3),
\r
498 kFRO1M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 4),
\r
499 kPLL1_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 5),
\r
500 kOSC32K_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 6),
\r
501 kNONE_to_SYS_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 7),
\r
503 kFRO12M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 0),
\r
504 kEXT_CLK_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 1),
\r
505 kFRO1M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 2),
\r
506 kOSC32K_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 3),
\r
507 kNONE_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 7),
\r
509 kMAIN_CLK_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0),
\r
510 kPLL0_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1),
\r
511 kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2),
\r
512 kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7),
\r
514 kMAIN_CLK_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 0),
\r
515 kPLL0_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 1),
\r
516 kFRO_HF_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 3),
\r
517 kPLL1_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 5),
\r
518 kNONE_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 7),
\r
520 kMAIN_CLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0),
\r
521 kPLL0_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1),
\r
522 kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2),
\r
523 kFRO_HF_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3),
\r
524 kFRO1M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4),
\r
525 kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 5),
\r
526 kOSC32K_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 6),
\r
527 kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7),
\r
529 kMAIN_CLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0),
\r
530 kPLL0_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1),
\r
531 kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2),
\r
532 kFRO_HF_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3),
\r
533 kFRO1M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4),
\r
534 kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 5),
\r
535 kOSC32K_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 6),
\r
536 kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7),
\r
538 kMAIN_CLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0),
\r
539 kPLL0_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1),
\r
540 kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2),
\r
541 kFRO_HF_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3),
\r
542 kFRO1M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4),
\r
543 kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 5),
\r
544 kOSC32K_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 6),
\r
545 kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7),
\r
547 kMAIN_CLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0),
\r
548 kPLL0_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1),
\r
549 kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2),
\r
550 kFRO_HF_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3),
\r
551 kFRO1M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4),
\r
552 kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 5),
\r
553 kOSC32K_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 6),
\r
554 kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7),
\r
556 kMAIN_CLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0),
\r
557 kPLL0_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1),
\r
558 kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2),
\r
559 kFRO_HF_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3),
\r
560 kFRO1M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4),
\r
561 kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 5),
\r
562 kOSC32K_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 6),
\r
563 kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7),
\r
565 kMAIN_CLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0),
\r
566 kPLL0_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1),
\r
567 kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2),
\r
568 kFRO_HF_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3),
\r
569 kFRO1M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4),
\r
570 kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 5),
\r
571 kOSC32K_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 6),
\r
572 kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7),
\r
574 kMAIN_CLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0),
\r
575 kPLL0_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1),
\r
576 kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2),
\r
577 kFRO_HF_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3),
\r
578 kFRO1M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4),
\r
579 kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 5),
\r
580 kOSC32K_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 6),
\r
581 kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7),
\r
583 kMAIN_CLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0),
\r
584 kPLL0_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1),
\r
585 kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2),
\r
586 kFRO_HF_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3),
\r
587 kFRO1M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4),
\r
588 kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 5),
\r
589 kOSC32K_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 6),
\r
590 kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7),
\r
592 kMAIN_CLK_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 0),
\r
593 kPLL0_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 1),
\r
594 kFRO12M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 2),
\r
595 kFRO_HF_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 3),
\r
596 kFRO1M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 4),
\r
597 kOSC32K_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 6),
\r
598 kNONE_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 7),
\r
600 kFRO_HF_to_MCLK = MUX_A(CM_MCLKCLKSEL, 0),
\r
601 kPLL0_to_MCLK = MUX_A(CM_MCLKCLKSEL, 1),
\r
602 kNONE_to_MCLK = MUX_A(CM_MCLKCLKSEL, 7),
\r
604 kMAIN_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 0),
\r
605 kPLL0_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 1),
\r
606 kEXT_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 2),
\r
607 kFRO_HF_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 3),
\r
608 kMCLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 5),
\r
609 kNONE_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 7),
\r
611 kMAIN_CLK_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 0),
\r
612 kPLL0_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 1),
\r
613 kFRO_HF_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 3),
\r
614 kPLL1_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 5),
\r
615 kNONE_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 7),
\r
617 kFRO32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 0),
\r
618 kXTAL32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 1),
\r
620 kTRACE_DIV_to_TRACE = MUX_A(CM_TRACECLKSEL, 0),
\r
621 kFRO1M_to_TRACE = MUX_A(CM_TRACECLKSEL, 1),
\r
622 kOSC32K_to_TRACE = MUX_A(CM_TRACECLKSEL, 2),
\r
623 kNONE_to_TRACE = MUX_A(CM_TRACECLKSEL, 7),
\r
625 kSYSTICK_DIV0_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 0),
\r
626 kFRO1M_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 1),
\r
627 kOSC32K_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 2),
\r
628 kNONE_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 7),
\r
630 kSYSTICK_DIV1_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 0),
\r
631 kFRO1M_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 1),
\r
632 kOSC32K_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 2),
\r
633 kNONE_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 7),
\r
635 kFRO12M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 0),
\r
636 kEXT_CLK_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 1),
\r
637 kFRO1M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 2),
\r
638 kOSC32K_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 3),
\r
639 kNONE_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 7),
\r
641 kMAIN_CLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 0),
\r
642 kPLL0_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 1),
\r
643 kFRO_HF_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 3),
\r
644 kFRO1M_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 4),
\r
645 kMCLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 5),
\r
646 kOSC32K_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 6),
\r
647 kNONE_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 7),
\r
649 kMAIN_CLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 0),
\r
650 kPLL0_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 1),
\r
651 kFRO_HF_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 3),
\r
652 kFRO1M_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 4),
\r
653 kMCLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 5),
\r
654 kOSC32K_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 6),
\r
655 kNONE_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 7),
\r
657 kMAIN_CLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 0),
\r
658 kPLL0_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 1),
\r
659 kFRO_HF_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 3),
\r
660 kFRO1M_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 4),
\r
661 kMCLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 5),
\r
662 kOSC32K_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 6),
\r
663 kNONE_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 7),
\r
665 kMAIN_CLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 0),
\r
666 kPLL0_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 1),
\r
667 kFRO_HF_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 3),
\r
668 kFRO1M_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 4),
\r
669 kMCLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 5),
\r
670 kOSC32K_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 6),
\r
671 kNONE_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 7),
\r
673 kMAIN_CLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 0),
\r
674 kPLL0_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 1),
\r
675 kFRO_HF_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 3),
\r
676 kFRO1M_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 4),
\r
677 kMCLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 5),
\r
678 kOSC32K_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 6),
\r
679 kNONE_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 7),
\r
680 kNONE_to_NONE = (int)0x80000000U,
\r
681 } clock_attach_id_t;
\r
683 /* Clock dividers */
\r
684 typedef enum _clock_div_name
\r
686 kCLOCK_DivSystickClk0 = 0,
\r
687 kCLOCK_DivSystickClk1 = 1,
\r
688 kCLOCK_DivArmTrClkDiv = 2,
\r
689 kCLOCK_DivFlexFrg0 = 8,
\r
690 kCLOCK_DivFlexFrg1 = 9,
\r
691 kCLOCK_DivFlexFrg2 = 10,
\r
692 kCLOCK_DivFlexFrg3 = 11,
\r
693 kCLOCK_DivFlexFrg4 = 12,
\r
694 kCLOCK_DivFlexFrg5 = 13,
\r
695 kCLOCK_DivFlexFrg6 = 14,
\r
696 kCLOCK_DivFlexFrg7 = 15,
\r
697 kCLOCK_DivAhbClk = 32,
\r
698 kCLOCK_DivClkOut = 33,
\r
699 kCLOCK_DivFrohfClk = 34,
\r
700 kCLOCK_DivWdtClk = 35,
\r
701 kCLOCK_DivAdcAsyncClk = 37,
\r
702 kCLOCK_DivUsb0Clk = 38,
\r
703 kCLOCK_DivMClk = 43,
\r
704 kCLOCK_DivSctClk = 45,
\r
705 kCLOCK_DivSdioClk = 47,
\r
706 kCLOCK_DivPll0Clk = 49
\r
707 } clock_div_name_t;
\r
709 /*******************************************************************************
\r
711 ******************************************************************************/
\r
713 #if defined(__cplusplus)
\r
715 #endif /* __cplusplus */
\r
718 * @brief Enable the clock for specific IP.
\r
719 * @param name : Clock to be enabled.
\r
722 static inline void CLOCK_EnableClock(clock_ip_name_t clk)
\r
724 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
\r
725 SYSCON->AHBCLKCTRLSET[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
\r
728 * @brief Disable the clock for specific IP.
\r
729 * @param name : Clock to be Disabled.
\r
732 static inline void CLOCK_DisableClock(clock_ip_name_t clk)
\r
734 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
\r
735 SYSCON->AHBCLKCTRLCLR[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
\r
738 * @brief Initialize the Core clock to given frequency (12, 48 or 96 MHz).
\r
739 * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is
\r
741 * @param iFreq : Desired frequency (must be one of #CLK_FRO_12MHZ or #CLK_FRO_48MHZ or #CLK_FRO_96MHZ)
\r
742 * @return returns success or fail status.
\r
744 status_t CLOCK_SetupFROClocking(uint32_t iFreq);
\r
746 * @brief Set the flash wait states for the input freuqency.
\r
747 * @param iFreq : Input frequency
\r
750 void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq);
\r
752 * @brief Initialize the external osc clock to given frequency.
\r
753 * @param iFreq : Desired frequency (must be equal to exact rate in Hz)
\r
754 * @return returns success or fail status.
\r
756 status_t CLOCK_SetupExtClocking(uint32_t iFreq);
\r
758 * @brief Initialize the I2S MCLK clock to given frequency.
\r
759 * @param iFreq : Desired frequency (must be equal to exact rate in Hz)
\r
760 * @return returns success or fail status.
\r
762 status_t CLOCK_SetupI2SMClkClocking(uint32_t iFreq);
\r
764 * @brief Initialize the PLU CLKIN clock to given frequency.
\r
765 * @param iFreq : Desired frequency (must be equal to exact rate in Hz)
\r
766 * @return returns success or fail status.
\r
768 status_t CLOCK_SetupPLUClkInClocking(uint32_t iFreq);
\r
770 * @brief Configure the clock selection muxes.
\r
771 * @param connection : Clock to be configured.
\r
774 void CLOCK_AttachClk(clock_attach_id_t connection);
\r
776 * @brief Get the actual clock attach id.
\r
777 * This fuction uses the offset in input attach id, then it reads the actual source value in
\r
778 * the register and combine the offset to obtain an actual attach id.
\r
779 * @param attachId : Clock attach id to get.
\r
780 * @return Clock source value.
\r
782 clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId);
\r
784 * @brief Setup peripheral clock dividers.
\r
785 * @param div_name : Clock divider name
\r
786 * @param divided_by_value: Value to be divided
\r
787 * @param reset : Whether to reset the divider counter.
\r
790 void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset);
\r
792 * @brief Setup rtc 1khz clock divider.
\r
793 * @param divided_by_value: Value to be divided
\r
796 void CLOCK_SetRtc1khzClkDiv(uint32_t divided_by_value);
\r
798 * @brief Setup rtc 1hz clock divider.
\r
799 * @param divided_by_value: Value to be divided
\r
802 void CLOCK_SetRtc1hzClkDiv(uint32_t divided_by_value);
\r
805 * @brief Set the flexcomm output frequency.
\r
806 * @param id : flexcomm instance id
\r
807 * freq : output frequency
\r
808 * @return 0 : the frequency range is out of range.
\r
809 * 1 : switch successfully.
\r
811 uint32_t CLOCK_SetFlexCommClock(uint32_t id, uint32_t freq);
\r
813 /*! @brief Return Frequency of flexcomm input clock
\r
814 * @param id : flexcomm instance id
\r
815 * @return Frequency value
\r
817 uint32_t CLOCK_GetFlexCommInputClock(uint32_t id);
\r
819 /*! @brief Return Frequency of selected clock
\r
820 * @return Frequency of selected clock
\r
822 uint32_t CLOCK_GetFreq(clock_name_t clockName);
\r
823 /*! @brief Return Frequency of FRO 12MHz
\r
824 * @return Frequency of FRO 12MHz
\r
826 uint32_t CLOCK_GetFro12MFreq(void);
\r
827 /*! @brief Return Frequency of FRO 1MHz
\r
828 * @return Frequency of FRO 1MHz
\r
830 uint32_t CLOCK_GetFro1MFreq(void);
\r
831 /*! @brief Return Frequency of ClockOut
\r
832 * @return Frequency of ClockOut
\r
834 uint32_t CLOCK_GetClockOutClkFreq(void);
\r
835 /*! @brief Return Frequency of Adc Clock
\r
836 * @return Frequency of Adc.
\r
838 uint32_t CLOCK_GetAdcClkFreq(void);
\r
839 /*! @brief Return Frequency of Usb0 Clock
\r
840 * @return Frequency of Usb0 Clock.
\r
842 uint32_t CLOCK_GetUsb0ClkFreq(void);
\r
843 /*! @brief Return Frequency of Usb1 Clock
\r
844 * @return Frequency of Usb1 Clock.
\r
846 uint32_t CLOCK_GetUsb1ClkFreq(void);
\r
847 /*! @brief Return Frequency of MClk Clock
\r
848 * @return Frequency of MClk Clock.
\r
850 uint32_t CLOCK_GetMclkClkFreq(void);
\r
851 /*! @brief Return Frequency of SCTimer Clock
\r
852 * @return Frequency of SCTimer Clock.
\r
854 uint32_t CLOCK_GetSctClkFreq(void);
\r
855 /*! @brief Return Frequency of SDIO Clock
\r
856 * @return Frequency of SDIO Clock.
\r
858 uint32_t CLOCK_GetSdioClkFreq(void);
\r
859 /*! @brief Return Frequency of External Clock
\r
860 * @return Frequency of External Clock. If no external clock is used returns 0.
\r
862 uint32_t CLOCK_GetExtClkFreq(void);
\r
863 /*! @brief Return Frequency of Watchdog
\r
864 * @return Frequency of Watchdog
\r
866 uint32_t CLOCK_GetWdtClkFreq(void);
\r
867 /*! @brief Return Frequency of High-Freq output of FRO
\r
868 * @return Frequency of High-Freq output of FRO
\r
870 uint32_t CLOCK_GetFroHfFreq(void);
\r
871 /*! @brief Return Frequency of PLL
\r
872 * @return Frequency of PLL
\r
874 uint32_t CLOCK_GetPll0OutFreq(void);
\r
875 /*! @brief Return Frequency of USB PLL
\r
876 * @return Frequency of PLL
\r
878 uint32_t CLOCK_GetPll1OutFreq(void);
\r
879 /*! @brief Return Frequency of 32kHz osc
\r
880 * @return Frequency of 32kHz osc
\r
882 uint32_t CLOCK_GetOsc32KFreq(void);
\r
883 /*! @brief Return Frequency of Core System
\r
884 * @return Frequency of Core System
\r
886 uint32_t CLOCK_GetCoreSysClkFreq(void);
\r
887 /*! @brief Return Frequency of I2S MCLK Clock
\r
888 * @return Frequency of I2S MCLK Clock
\r
890 uint32_t CLOCK_GetI2SMClkFreq(void);
\r
891 /*! @brief Return Frequency of PLU CLKIN Clock
\r
892 * @return Frequency of PLU CLKIN Clock
\r
894 uint32_t CLOCK_GetPLUClkInFreq(void);
\r
895 /*! @brief Return Frequency of FlexComm Clock
\r
896 * @return Frequency of FlexComm Clock
\r
898 uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id);
\r
899 /*! @brief Return Frequency of High speed SPI Clock
\r
900 * @return Frequency of High speed SPI Clock
\r
902 uint32_t CLOCK_GetHsLspiClkFreq(void);
\r
903 /*! @brief Return Frequency of CTimer functional Clock
\r
904 * @return Frequency of CTimer functional Clock
\r
906 uint32_t CLOCK_GetCTimerClkFreq(uint32_t id);
\r
907 /*! @brief Return Frequency of SystickClock
\r
908 * @return Frequency of Systick Clock
\r
910 uint32_t CLOCK_GetSystickClkFreq(uint32_t id);
\r
912 /*! @brief Return PLL0 input clock rate
\r
913 * @return PLL0 input clock rate
\r
915 uint32_t CLOCK_GetPLL0InClockRate(void);
\r
917 /*! @brief Return PLL1 input clock rate
\r
918 * @return PLL1 input clock rate
\r
920 uint32_t CLOCK_GetPLL1InClockRate(void);
\r
922 /*! @brief Return PLL0 output clock rate
\r
923 * @param recompute : Forces a PLL rate recomputation if true
\r
924 * @return PLL0 output clock rate
\r
925 * @note The PLL rate is cached in the driver in a variable as
\r
926 * the rate computation function can take some time to perform. It
\r
927 * is recommended to use 'false' with the 'recompute' parameter.
\r
929 uint32_t CLOCK_GetPLL0OutClockRate(bool recompute);
\r
931 /*! @brief Enables and disables PLL0 bypass mode
\r
932 * @brief bypass : true to bypass PLL0 (PLL0 output = PLL0 input, false to disable bypass
\r
933 * @return PLL0 output clock rate
\r
935 __STATIC_INLINE void CLOCK_SetBypassPLL0(bool bypass)
\r
939 SYSCON->PLL0CTRL |= (1UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT);
\r
943 SYSCON->PLL0CTRL &= ~(1UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT);
\r
947 /*! @brief Enables and disables PLL1 bypass mode
\r
948 * @brief bypass : true to bypass PLL1 (PLL1 output = PLL1 input, false to disable bypass
\r
949 * @return PLL1 output clock rate
\r
951 __STATIC_INLINE void CLOCK_SetBypassPLL1(bool bypass)
\r
955 SYSCON->PLL1CTRL |= (1UL << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT);
\r
959 SYSCON->PLL1CTRL &= ~(1UL << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT);
\r
963 /*! @brief Check if PLL is locked or not
\r
964 * @return true if the PLL is locked, false if not locked
\r
966 __STATIC_INLINE bool CLOCK_IsPLL0Locked(void)
\r
968 return (bool)((SYSCON->PLL0STAT & SYSCON_PLL0STAT_LOCK_MASK) != 0UL);
\r
971 /*! @brief Check if PLL1 is locked or not
\r
972 * @return true if the PLL1 is locked, false if not locked
\r
974 __STATIC_INLINE bool CLOCK_IsPLL1Locked(void)
\r
976 return (bool)((SYSCON->PLL1STAT & SYSCON_PLL1STAT_LOCK_MASK) != 0UL);
\r
979 /*! @brief Store the current PLL0 rate
\r
980 * @param rate: Current rate of the PLL0
\r
983 void CLOCK_SetStoredPLL0ClockRate(uint32_t rate);
\r
985 /*! @brief PLL configuration structure flags for 'flags' field
\r
986 * These flags control how the PLL configuration function sets up the PLL setup structure.<br>
\r
988 * When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the
\r
989 * configuration structure must be assigned with the expected PLL frequency. If the
\r
990 * PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration
\r
991 * function and the driver will determine the PLL rate from the currently selected
\r
992 * PLL source. This flag might be used to configure the PLL input clock more accurately
\r
993 * when using the WDT oscillator or a more dyanmic CLKIN source.<br>
\r
995 * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the
\r
996 * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider
\r
997 * are not used.<br>
\r
999 #define PLL_CONFIGFLAG_USEINRATE (1U << 0U) /*!< Flag to use InputRate in PLL configuration structure for setup */
\r
1000 #define PLL_CONFIGFLAG_FORCENOFRACT (1U << 2U)
\r
1001 /*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS hardware */
\r
1003 /*! @brief PLL Spread Spectrum (SS) Programmable modulation frequency
\r
1004 * See (MF) field in the PLL0SSCG1 register in the UM.
\r
1006 typedef enum _ss_progmodfm
\r
1008 kSS_MF_512 = (0 << 20), /*!< Nss = 512 (fm ? 3.9 - 7.8 kHz) */
\r
1009 kSS_MF_384 = (1 << 20), /*!< Nss ?= 384 (fm ? 5.2 - 10.4 kHz) */
\r
1010 kSS_MF_256 = (2 << 20), /*!< Nss = 256 (fm ? 7.8 - 15.6 kHz) */
\r
1011 kSS_MF_128 = (3 << 20), /*!< Nss = 128 (fm ? 15.6 - 31.3 kHz) */
\r
1012 kSS_MF_64 = (4 << 20), /*!< Nss = 64 (fm ? 32.3 - 64.5 kHz) */
\r
1013 kSS_MF_32 = (5 << 20), /*!< Nss = 32 (fm ? 62.5- 125 kHz) */
\r
1014 kSS_MF_24 = (6 << 20), /*!< Nss ?= 24 (fm ? 83.3- 166.6 kHz) */
\r
1015 kSS_MF_16 = (7 << 20) /*!< Nss = 16 (fm ? 125- 250 kHz) */
\r
1018 /*! @brief PLL Spread Spectrum (SS) Programmable frequency modulation depth
\r
1019 * See (MR) field in the PLL0SSCG1 register in the UM.
\r
1021 typedef enum _ss_progmoddp
\r
1023 kSS_MR_K0 = (0 << 23), /*!< k = 0 (no spread spectrum) */
\r
1024 kSS_MR_K1 = (1 << 23), /*!< k = 1 */
\r
1025 kSS_MR_K1_5 = (2 << 23), /*!< k = 1.5 */
\r
1026 kSS_MR_K2 = (3 << 23), /*!< k = 2 */
\r
1027 kSS_MR_K3 = (4 << 23), /*!< k = 3 */
\r
1028 kSS_MR_K4 = (5 << 23), /*!< k = 4 */
\r
1029 kSS_MR_K6 = (6 << 23), /*!< k = 6 */
\r
1030 kSS_MR_K8 = (7 << 23) /*!< k = 8 */
\r
1033 /*! @brief PLL Spread Spectrum (SS) Modulation waveform control
\r
1034 * See (MC) field in the PLL0SSCG1 register in the UM.<br>
\r
1035 * Compensation for low pass filtering of the PLL to get a triangular
\r
1036 * modulation at the output of the PLL, giving a flat frequency spectrum.
\r
1038 typedef enum _ss_modwvctrl
\r
1040 kSS_MC_NOC = (0 << 26), /*!< no compensation */
\r
1041 kSS_MC_RECC = (2 << 26), /*!< recommended setting */
\r
1042 kSS_MC_MAXC = (3 << 26), /*!< max. compensation */
\r
1045 /*! @brief PLL configuration structure
\r
1047 * This structure can be used to configure the settings for a PLL
\r
1048 * setup structure. Fill in the desired configuration for the PLL
\r
1049 * and call the PLL setup function to fill in a PLL setup structure.
\r
1051 typedef struct _pll_config
\r
1053 uint32_t desiredRate; /*!< Desired PLL rate in Hz */
\r
1054 uint32_t inputRate; /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */
\r
1055 uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */
\r
1056 ss_progmodfm_t ss_mf; /*!< SS Programmable modulation frequency, only applicable when not using
\r
1057 PLL_CONFIGFLAG_FORCENOFRACT flag */
\r
1058 ss_progmoddp_t ss_mr; /*!< SS Programmable frequency modulation depth, only applicable when not using
\r
1059 PLL_CONFIGFLAG_FORCENOFRACT flag */
\r
1061 ss_mc; /*!< SS Modulation waveform control, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag */
\r
1062 bool mfDither; /*!< false for fixed modulation frequency or true for dithering, only applicable when not using
\r
1063 PLL_CONFIGFLAG_FORCENOFRACT flag */
\r
1067 /*! @brief PLL setup structure flags for 'flags' field
\r
1068 * These flags control how the PLL setup function sets up the PLL
\r
1070 #define PLL_SETUPFLAG_POWERUP (1U << 0U) /*!< Setup will power on the PLL after setup */
\r
1071 #define PLL_SETUPFLAG_WAITLOCK (1U << 1U) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */
\r
1072 #define PLL_SETUPFLAG_ADGVOLT (1U << 2U) /*!< Optimize system voltage for the new PLL rate */
\r
1073 #define PLL_SETUPFLAG_USEFEEDBACKDIV2 (1U << 3U) /*!< Use feedback divider by 2 in divider path */
\r
1075 /*! @brief PLL0 setup structure
\r
1076 * This structure can be used to pre-build a PLL setup configuration
\r
1077 * at run-time and quickly set the PLL to the configuration. It can be
\r
1078 * populated with the PLL setup function. If powering up or waiting
\r
1079 * for PLL lock, the PLL input clock source should be configured prior
\r
1082 typedef struct _pll_setup
\r
1084 uint32_t pllctrl; /*!< PLL control register PLL0CTRL */
\r
1085 uint32_t pllndec; /*!< PLL NDEC register PLL0NDEC */
\r
1086 uint32_t pllpdec; /*!< PLL PDEC register PLL0PDEC */
\r
1087 uint32_t pllmdec; /*!< PLL MDEC registers PLL0PDEC */
\r
1088 uint32_t pllsscg[2]; /*!< PLL SSCTL registers PLL0SSCG*/
\r
1089 uint32_t pllRate; /*!< Acutal PLL rate */
\r
1090 uint32_t flags; /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */
\r
1093 /*! @brief PLL status definitions
\r
1095 typedef enum _pll_error
\r
1097 kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */
\r
1098 kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */
\r
1099 kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */
\r
1100 kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */
\r
1101 kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */
\r
1102 kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Requested output rate isn't possible */
\r
1103 kStatus_PLL_CCOTooLow = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Requested CCO rate isn't possible */
\r
1104 kStatus_PLL_CCOTooHigh = MAKE_STATUS(kStatusGroup_Generic, 7) /*!< Requested CCO rate isn't possible */
\r
1107 /*! @brief USB FS clock source definition. */
\r
1108 typedef enum _clock_usbfs_src
\r
1110 kCLOCK_UsbfsSrcFro = (uint32_t)kCLOCK_FroHf, /*!< Use FRO 96 MHz. */
\r
1111 kCLOCK_UsbfsSrcPll0 = (uint32_t)kCLOCK_Pll0Out, /*!< Use PLL0 output. */
\r
1112 kCLOCK_UsbfsSrcMainClock = (uint32_t)kCLOCK_CoreSysClk, /*!< Use Main clock. */
\r
1113 kCLOCK_UsbfsSrcPll1 = (uint32_t)kCLOCK_Pll1Out, /*!< Use PLL1 clock. */
\r
1115 kCLOCK_UsbfsSrcNone =
\r
1116 SYSCON_USB0CLKSEL_SEL(7) /*!<this may be selected in order to reduce power when no output is needed. */
\r
1117 } clock_usbfs_src_t;
\r
1119 /*! @brief USBhs clock source definition. */
\r
1120 typedef enum _clock_usbhs_src
\r
1122 kCLOCK_UsbSrcUnused = 0xFFFFFFFFU, /*!< Used when the function does not
\r
1123 care the clock source. */
\r
1124 } clock_usbhs_src_t;
\r
1126 /*! @brief Source of the USB HS PHY. */
\r
1127 typedef enum _clock_usb_phy_src
\r
1129 kCLOCK_UsbPhySrcExt = 0U, /*!< Use external crystal. */
\r
1130 } clock_usb_phy_src_t;
\r
1132 /*! @brief Return PLL0 output clock rate from setup structure
\r
1133 * @param pSetup : Pointer to a PLL setup structure
\r
1134 * @return System PLL output clock rate the setup structure will generate
\r
1136 uint32_t CLOCK_GetPLL0OutFromSetup(pll_setup_t *pSetup);
\r
1138 /*! @brief Set PLL0 output based on the passed PLL setup data
\r
1139 * @param pControl : Pointer to populated PLL control structure to generate setup with
\r
1140 * @param pSetup : Pointer to PLL setup structure to be filled
\r
1141 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
\r
1142 * @note Actual frequency for setup may vary from the desired frequency based on the
\r
1143 * accuracy of input clocks, rounding, non-fractional PLL mode, etc.
\r
1145 pll_error_t CLOCK_SetupPLL0Data(pll_config_t *pControl, pll_setup_t *pSetup);
\r
1147 /*! @brief Set PLL output from PLL setup structure (precise frequency)
\r
1148 * @param pSetup : Pointer to populated PLL setup structure
\r
1149 * @param flagcfg : Flag configuration for PLL config structure
\r
1150 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
\r
1151 * @note This function will power off the PLL, setup the PLL with the
\r
1152 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
\r
1153 * and adjust system voltages to the new PLL rate. The function will not
\r
1154 * alter any source clocks (ie, main systen clock) that may use the PLL,
\r
1155 * so these should be setup prior to and after exiting the function.
\r
1157 pll_error_t CLOCK_SetupPLL0Prec(pll_setup_t *pSetup, uint32_t flagcfg);
\r
1160 * @brief Set PLL output from PLL setup structure (precise frequency)
\r
1161 * @param pSetup : Pointer to populated PLL setup structure
\r
1162 * @return kStatus_PLL_Success on success, or PLL setup error code
\r
1163 * @note This function will power off the PLL, setup the PLL with the
\r
1164 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
\r
1165 * and adjust system voltages to the new PLL rate. The function will not
\r
1166 * alter any source clocks (ie, main systen clock) that may use the PLL,
\r
1167 * so these should be setup prior to and after exiting the function.
\r
1169 pll_error_t CLOCK_SetPLL0Freq(const pll_setup_t *pSetup);
\r
1172 * @brief Set PLL output from PLL setup structure (precise frequency)
\r
1173 * @param pSetup : Pointer to populated PLL setup structure
\r
1174 * @return kStatus_PLL_Success on success, or PLL setup error code
\r
1175 * @note This function will power off the PLL, setup the PLL with the
\r
1176 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
\r
1177 * and adjust system voltages to the new PLL rate. The function will not
\r
1178 * alter any source clocks (ie, main systen clock) that may use the PLL,
\r
1179 * so these should be setup prior to and after exiting the function.
\r
1181 pll_error_t CLOCK_SetPLL1Freq(const pll_setup_t *pSetup);
\r
1183 /*! @brief Set PLL0 output based on the multiplier and input frequency
\r
1184 * @param multiply_by : multiplier
\r
1185 * @param input_freq : Clock input frequency of the PLL
\r
1187 * @note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this
\r
1188 * function does not disable or enable PLL power, wait for PLL lock,
\r
1189 * or adjust system voltages. These must be done in the application.
\r
1190 * The function will not alter any source clocks (ie, main systen clock)
\r
1191 * that may use the PLL, so these should be setup prior to and after
\r
1192 * exiting the function.
\r
1194 void CLOCK_SetupPLL0Mult(uint32_t multiply_by, uint32_t input_freq);
\r
1196 /*! @brief Disable USB clock.
\r
1198 * Disable USB clock.
\r
1200 static inline void CLOCK_DisableUsbDevicefs0Clock(clock_ip_name_t clk)
\r
1202 CLOCK_DisableClock(clk);
\r
1205 /*! @brief Enable USB Device FS clock.
\r
1206 * @param src : clock source
\r
1207 * @param freq: clock frequency
\r
1208 * Enable USB Device Full Speed clock.
\r
1210 bool CLOCK_EnableUsbfs0DeviceClock(clock_usbfs_src_t src, uint32_t freq);
\r
1212 /*! @brief Enable USB HOST FS clock.
\r
1213 * @param src : clock source
\r
1214 * @param freq: clock frequency
\r
1215 * Enable USB HOST Full Speed clock.
\r
1217 bool CLOCK_EnableUsbfs0HostClock(clock_usbfs_src_t src, uint32_t freq);
\r
1219 /*! @brief Enable USB phy clock.
\r
1220 * Enable USB phy clock.
\r
1222 bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq);
\r
1224 /*! @brief Enable USB Device HS clock.
\r
1225 * Enable USB Device High Speed clock.
\r
1227 bool CLOCK_EnableUsbhs0DeviceClock(clock_usbhs_src_t src, uint32_t freq);
\r
1229 /*! @brief Enable USB HOST HS clock.
\r
1230 * Enable USB HOST High Speed clock.
\r
1232 bool CLOCK_EnableUsbhs0HostClock(clock_usbhs_src_t src, uint32_t freq);
\r
1234 #if defined(__cplusplus)
\r
1236 #endif /* __cplusplus */
\r
1240 #endif /* _FSL_CLOCK_H_ */
\r
projects / freertos / blob