2 * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
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3 * Copyright 2016-2019 NXP
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4 * All rights reserved.
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6 * SPDX-License-Identifier: BSD-3-Clause
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9 #include "fsl_common.h"
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10 #define SDK_MEM_MAGIC_NUMBER 12345U
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12 typedef struct _mem_align_control_block
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14 uint16_t identifier; /*!< Identifier for the memory control block. */
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15 uint16_t offset; /*!< offset from aligned address to real address */
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18 /* Component ID definition, used by tools. */
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19 #ifndef FSL_COMPONENT_ID
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20 #define FSL_COMPONENT_ID "platform.drivers.common"
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23 #ifndef __GIC_PRIO_BITS
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24 #if defined(ENABLE_RAM_VECTOR_TABLE)
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25 uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
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27 /* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
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28 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
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29 extern uint32_t Image$$VECTOR_ROM$$Base[];
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30 extern uint32_t Image$$VECTOR_RAM$$Base[];
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31 extern uint32_t Image$$RW_m_data$$Base[];
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33 #define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
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34 #define __VECTOR_RAM Image$$VECTOR_RAM$$Base
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35 #define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
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36 #elif defined(__ICCARM__)
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37 extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
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38 extern uint32_t __VECTOR_TABLE[];
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39 extern uint32_t __VECTOR_RAM[];
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40 #elif defined(__GNUC__)
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41 extern uint32_t __VECTOR_TABLE[];
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42 extern uint32_t __VECTOR_RAM[];
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43 extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
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44 uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
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45 #endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */
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48 uint32_t irqMaskValue;
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50 irqMaskValue = DisableGlobalIRQ();
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51 if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
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53 /* Copy the vector table from ROM to RAM */
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54 for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
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56 __VECTOR_RAM[n] = __VECTOR_TABLE[n];
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58 /* Point the VTOR to the position of vector table */
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59 SCB->VTOR = (uint32_t)__VECTOR_RAM;
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62 ret = __VECTOR_RAM[irq + 16];
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63 /* make sure the __VECTOR_RAM is noncachable */
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64 __VECTOR_RAM[irq + 16] = irqHandler;
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66 EnableGlobalIRQ(irqMaskValue);
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68 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
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69 exception return operation might vector to incorrect interrupt */
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70 #if defined __CORTEX_M && (__CORTEX_M == 4U)
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76 #endif /* ENABLE_RAM_VECTOR_TABLE. */
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77 #endif /* __GIC_PRIO_BITS. */
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79 #if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
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80 #if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS)
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82 void EnableDeepSleepIRQ(IRQn_Type interrupt)
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84 uint32_t intNumber = (uint32_t)interrupt;
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88 while (intNumber >= 32u)
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94 SYSCON->STARTERSET[index] = 1u << intNumber;
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95 EnableIRQ(interrupt); /* also enable interrupt at NVIC */
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98 void DisableDeepSleepIRQ(IRQn_Type interrupt)
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100 uint32_t intNumber = (uint32_t)interrupt;
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102 DisableIRQ(interrupt); /* also disable interrupt at NVIC */
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103 uint32_t index = 0;
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105 while (intNumber >= 32u)
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111 SYSCON->STARTERCLR[index] = 1u << intNumber;
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113 #endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */
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114 #endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
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116 void *SDK_Malloc(size_t size, size_t alignbytes)
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118 mem_align_cb_t *p_cb = NULL;
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119 uint32_t alignedsize = SDK_SIZEALIGN(size, alignbytes) + alignbytes + sizeof(mem_align_cb_t);
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122 void *pointer_value;
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123 uint32_t unsigned_value;
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124 } p_align_addr, p_addr;
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126 p_addr.pointer_value = malloc(alignedsize);
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128 if (p_addr.pointer_value == NULL)
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133 p_align_addr.unsigned_value = SDK_SIZEALIGN(p_addr.unsigned_value + sizeof(mem_align_cb_t), alignbytes);
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135 p_cb = (mem_align_cb_t *)(p_align_addr.unsigned_value - 4U);
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136 p_cb->identifier = SDK_MEM_MAGIC_NUMBER;
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137 p_cb->offset = (uint16_t)(p_align_addr.unsigned_value - p_addr.unsigned_value);
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139 return p_align_addr.pointer_value;
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142 void SDK_Free(void *ptr)
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146 void *pointer_value;
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147 uint32_t unsigned_value;
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149 p_free.pointer_value = ptr;
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150 mem_align_cb_t *p_cb = (mem_align_cb_t *)(p_free.unsigned_value - 4U);
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152 if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER)
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157 p_free.unsigned_value = p_free.unsigned_value - p_cb->offset;
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159 free(p_free.pointer_value);
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163 * @brief Delay function bases on while loop, every loop includes three instructions.
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165 * @param count Counts of loop needed for dalay.
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168 #if defined(__CC_ARM) /* This macro is arm v5 specific */
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169 /* clang-format off */
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170 __ASM static void DelayLoop(uint32_t count)
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178 /* clang-format on */
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179 #elif defined(__ARMCC_VERSION) || defined(__ICCARM__) || defined(__GNUC__)
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180 /* Cortex-M0 has a smaller instruction set, SUBS isn't supported in thumb-16 mode reported from __GNUC__ compiler,
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181 * use SUB and CMP here for compatibility */
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182 static void DelayLoop(uint32_t count)
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184 __ASM volatile(" MOV R0, %0" : : "r"(count));
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187 #if defined(__GNUC__) && !defined(__ARMCC_VERSION)
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188 " SUB R0, R0, #1 \n"
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190 " SUBS R0, R0, #1 \n"
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196 #endif /* defined(__CC_ARM) */
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199 * @brief Delay at least for some time.
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200 * Please note that, this API uses while loop for delay, different run-time environments make the time not precise,
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201 * if precise delay count was needed, please implement a new delay function with hardware timer.
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203 * @param delay_us Delay time in unit of microsecond.
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204 * @param coreClock_Hz Core clock frequency with Hz.
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206 void SDK_DelayAtLeastUs(uint32_t delay_us, uint32_t coreClock_Hz)
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208 assert(0U != delay_us);
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209 uint64_t count = USEC_TO_COUNT(delay_us, coreClock_Hz);
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210 assert(count <= UINT32_MAX);
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212 /* Divide value may be different in various environment to ensure delay is precise.
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213 * Every loop count includes three instructions, due to Cortex-M7 sometimes executes
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214 * two instructions in one period, through test here set divide 2. Other M cores use
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215 * divide 4. By the way, divide 2 or 4 could let odd count lost precision, but it does
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216 * not matter because other instructions outside while loop is enough to fill the time.
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218 #if (__CORTEX_M == 7)
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219 count = count / 2U;
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221 count = count / 4U;
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223 DelayLoop((uint32_t)count);
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