2 * Copyright 2017, NXP
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3 * All rights reserved.
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5 * SPDX-License-Identifier: BSD-3-Clause
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7 #ifndef _FSL_POWER_H_
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8 #define _FSL_POWER_H_
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10 #include "fsl_common.h"
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11 #include "fsl_device_registers.h"
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18 /*******************************************************************************
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20 ******************************************************************************/
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22 /*! @name Driver version */
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24 /*! @brief power driver version 1.0.0. */
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25 #define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(1, 0, 0))
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28 /* Power mode configuration API parameter */
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29 typedef enum _power_mode_config
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32 kPmu_Deep_Sleep = 1U,
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33 kPmu_PowerDown = 2U,
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34 kPmu_Deep_PowerDown = 3U,
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38 * @brief Analog components power modes control during low power modes
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40 typedef enum pd_bits
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42 kPDRUNCFG_PD_DCDC = (1UL << 0),
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43 kPDRUNCFG_PD_BIAS = (1UL << 1),
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44 kPDRUNCFG_PD_BODCORE = (1UL << 2),
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45 kPDRUNCFG_PD_BODVBAT = (1UL << 3),
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46 kPDRUNCFG_PD_FRO1M = (1UL << 4),
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47 kPDRUNCFG_PD_FRO192M = (1UL << 5),
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48 kPDRUNCFG_PD_FRO32K = (1UL << 6),
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49 kPDRUNCFG_PD_XTAL32K = (1UL << 7),
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50 kPDRUNCFG_PD_XTAL32M = (1UL << 8),
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51 kPDRUNCFG_PD_PLL0 = (1UL << 9),
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52 kPDRUNCFG_PD_PLL1 = (1UL << 10),
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53 kPDRUNCFG_PD_USB0_PHY = (1UL << 11),
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54 kPDRUNCFG_PD_USB1_PHY = (1UL << 12),
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55 kPDRUNCFG_PD_COMP = (1UL << 13),
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56 kPDRUNCFG_PD_TEMPSENS = (1UL << 14),
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57 kPDRUNCFG_PD_GPADC = (1UL << 15),
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58 kPDRUNCFG_PD_LDOMEM = (1UL << 16),
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59 kPDRUNCFG_PD_LDODEEPSLEEP = (1UL << 17),
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60 kPDRUNCFG_PD_LDOUSBHS = (1UL << 18),
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61 kPDRUNCFG_PD_LDOGPADC = (1UL << 19),
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62 kPDRUNCFG_PD_LDOXO32M = (1UL << 20),
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63 kPDRUNCFG_PD_LDOFLASHNV = (1UL << 21),
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64 kPDRUNCFG_PD_RNG = (1UL << 22),
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65 kPDRUNCFG_PD_PLL0_SSCG = (1UL << 23),
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66 kPDRUNCFG_PD_ROM = (1UL << 24),
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68 This enum member has no practical meaning,it is used to avoid MISRA issue,
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69 user should not trying to use it.
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71 kPDRUNCFG_ForceUnsigned = 0x80000000U,
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74 /*@brief BOD VBAT level */
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75 typedef enum _power_bod_vbat_level
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77 kPOWER_BodVbatLevel1000mv = 0, /*!< Brown out detector VBAT level 1V */
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78 kPOWER_BodVbatLevel1100mv = 1, /*!< Brown out detector VBAT level 1.1V */
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79 kPOWER_BodVbatLevel1200mv = 2, /*!< Brown out detector VBAT level 1.2V */
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80 kPOWER_BodVbatLevel1300mv = 3, /*!< Brown out detector VBAT level 1.3V */
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81 kPOWER_BodVbatLevel1400mv = 4, /*!< Brown out detector VBAT level 1.4V */
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82 kPOWER_BodVbatLevel1500mv = 5, /*!< Brown out detector VBAT level 1.5V */
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83 kPOWER_BodVbatLevel1600mv = 6, /*!< Brown out detector VBAT level 1.6V */
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84 kPOWER_BodVbatLevel1650mv = 7, /*!< Brown out detector VBAT level 1.65V */
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85 kPOWER_BodVbatLevel1700mv = 8, /*!< Brown out detector VBAT level 1.7V */
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86 kPOWER_BodVbatLevel1750mv = 9, /*!< Brown out detector VBAT level 1.75V */
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87 kPOWER_BodVbatLevel1800mv = 10, /*!< Brown out detector VBAT level 1.8V */
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88 kPOWER_BodVbatLevel1900mv = 11, /*!< Brown out detector VBAT level 1.9V */
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89 kPOWER_BodVbatLevel2000mv = 12, /*!< Brown out detector VBAT level 2V */
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90 kPOWER_BodVbatLevel2100mv = 13, /*!< Brown out detector VBAT level 2.1V */
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91 kPOWER_BodVbatLevel2200mv = 14, /*!< Brown out detector VBAT level 2.2V */
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92 kPOWER_BodVbatLevel2300mv = 15, /*!< Brown out detector VBAT level 2.3V */
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93 kPOWER_BodVbatLevel2400mv = 16, /*!< Brown out detector VBAT level 2.4V */
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94 kPOWER_BodVbatLevel2500mv = 17, /*!< Brown out detector VBAT level 2.5V */
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95 kPOWER_BodVbatLevel2600mv = 18, /*!< Brown out detector VBAT level 2.6V */
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96 kPOWER_BodVbatLevel2700mv = 19, /*!< Brown out detector VBAT level 2.7V */
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97 kPOWER_BodVbatLevel2806mv = 20, /*!< Brown out detector VBAT level 2.806V */
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98 kPOWER_BodVbatLevel2900mv = 21, /*!< Brown out detector VBAT level 2.9V */
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99 kPOWER_BodVbatLevel3000mv = 22, /*!< Brown out detector VBAT level 3.0V */
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100 kPOWER_BodVbatLevel3100mv = 23, /*!< Brown out detector VBAT level 3.1V */
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101 kPOWER_BodVbatLevel3200mv = 24, /*!< Brown out detector VBAT level 3.2V */
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102 kPOWER_BodVbatLevel3300mv = 25, /*!< Brown out detector VBAT level 3.3V */
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103 } power_bod_vbat_level_t;
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105 /*@brief BOD Hysteresis control */
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106 typedef enum _power_bod_hyst
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108 kPOWER_BodHystLevel25mv = 0U, /*!< BOD Hysteresis control level 25mv */
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109 kPOWER_BodHystLevel50mv = 1U, /*!< BOD Hysteresis control level 50mv */
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110 kPOWER_BodHystLevel75mv = 2U, /*!< BOD Hysteresis control level 75mv */
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111 kPOWER_BodHystLevel100mv = 3U, /*!< BOD Hysteresis control level 100mv */
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112 } power_bod_hyst_t;
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114 /*@brief BOD core level */
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115 typedef enum _power_bod_core_level
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117 kPOWER_BodCoreLevel600mv = 0, /*!< Brown out detector core level 600mV */
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118 kPOWER_BodCoreLevel650mv = 1, /*!< Brown out detector core level 650mV */
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119 kPOWER_BodCoreLevel700mv = 2, /*!< Brown out detector core level 700mV */
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120 kPOWER_BodCoreLevel750mv = 3, /*!< Brown out detector core level 750mV */
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121 kPOWER_BodCoreLevel800mv = 4, /*!< Brown out detector core level 800mV */
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122 kPOWER_BodCoreLevel850mv = 5, /*!< Brown out detector core level 850mV */
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123 kPOWER_BodCoreLevel900mv = 6, /*!< Brown out detector core level 900mV */
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124 kPOWER_BodCoreLevel950mv = 7, /*!< Brown out detector core level 950mV */
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125 } power_bod_core_level_t;
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128 * @brief SRAM instances retention control during low power modes
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130 #define LOWPOWER_SRAMRETCTRL_RETEN_RAMX0 \
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131 (1UL << 0) /*!< Enable SRAMX_0 retention when entering in Low power modes */
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132 #define LOWPOWER_SRAMRETCTRL_RETEN_RAMX1 \
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133 (1UL << 1) /*!< Enable SRAMX_1 retention when entering in Low power modes */
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134 #define LOWPOWER_SRAMRETCTRL_RETEN_RAMX2 \
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135 (1UL << 2) /*!< Enable SRAMX_2 retention when entering in Low power modes */
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136 #define LOWPOWER_SRAMRETCTRL_RETEN_RAMX3 \
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137 (1UL << 3) /*!< Enable SRAMX_3 retention when entering in Low power modes */
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138 #define LOWPOWER_SRAMRETCTRL_RETEN_RAM00 \
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139 (1UL << 4) /*!< Enable SRAM0_0 retention when entering in Low power modes */
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140 #define LOWPOWER_SRAMRETCTRL_RETEN_RAM01 \
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141 (1UL << 5) /*!< Enable SRAM0_1 retention when entering in Low power modes */
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142 #define LOWPOWER_SRAMRETCTRL_RETEN_RAM10 \
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143 (1UL << 6) /*!< Enable SRAM1_0 retention when entering in Low power modes */
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144 #define LOWPOWER_SRAMRETCTRL_RETEN_RAM20 \
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145 (1UL << 7) /*!< Enable SRAM2_0 retention when entering in Low power modes */
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146 #define LOWPOWER_SRAMRETCTRL_RETEN_RAM30 \
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147 (1UL << 8) /*!< Enable SRAM3_0 retention when entering in Low power modes */
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148 #define LOWPOWER_SRAMRETCTRL_RETEN_RAM31 \
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149 (1UL << 9) /*!< Enable SRAM3_1 retention when entering in Low power modes */
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150 #define LOWPOWER_SRAMRETCTRL_RETEN_RAM40 \
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151 (1UL << 10) /*!< Enable SRAM4_0 retention when entering in Low power modes */
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152 #define LOWPOWER_SRAMRETCTRL_RETEN_RAM41 \
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153 (1UL << 11) /*!< Enable SRAM4_1 retention when entering in Low power modes */
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154 #define LOWPOWER_SRAMRETCTRL_RETEN_RAM42 \
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155 (1UL << 12) /*!< Enable SRAM4_2 retention when entering in Low power modes */
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156 #define LOWPOWER_SRAMRETCTRL_RETEN_RAM43 \
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157 (1UL << 13) /*!< Enable SRAM4_3 retention when entering in Low power modes */
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158 #define LOWPOWER_SRAMRETCTRL_RETEN_RAM_USB_HS \
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159 (1UL << 14) /*!< Enable SRAM USB HS retention when entering in Low power modes */
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160 #define LOWPOWER_SRAMRETCTRL_RETEN_RAM_PUF \
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161 (1UL << 15) /*!< Enable SRAM PUFF retention when entering in Low power modes */
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164 * @brief Low Power Modes Wake up sources
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166 #define WAKEUP_SYS (1ULL << 0) /*!< [SLEEP, DEEP SLEEP ] */ /* WWDT0_IRQ and BOD_IRQ*/
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167 #define WAKEUP_SDMA0 (1ULL << 1) /*!< [SLEEP, DEEP SLEEP ] */
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168 #define WAKEUP_GPIO_GLOBALINT0 (1ULL << 2) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */
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169 #define WAKEUP_GPIO_GLOBALINT1 (1ULL << 3) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */
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170 #define WAKEUP_GPIO_INT0_0 (1ULL << 4) /*!< [SLEEP, DEEP SLEEP ] */
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171 #define WAKEUP_GPIO_INT0_1 (1ULL << 5) /*!< [SLEEP, DEEP SLEEP ] */
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172 #define WAKEUP_GPIO_INT0_2 (1ULL << 6) /*!< [SLEEP, DEEP SLEEP ] */
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173 #define WAKEUP_GPIO_INT0_3 (1ULL << 7) /*!< [SLEEP, DEEP SLEEP ] */
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174 #define WAKEUP_UTICK (1ULL << 8) /*!< [SLEEP, ] */
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175 #define WAKEUP_MRT (1ULL << 9) /*!< [SLEEP, ] */
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176 #define WAKEUP_CTIMER0 (1ULL << 10) /*!< [SLEEP, DEEP SLEEP ] */
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177 #define WAKEUP_CTIMER1 (1ULL << 11) /*!< [SLEEP, DEEP SLEEP ] */
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178 #define WAKEUP_SCT (1ULL << 12) /*!< [SLEEP, ] */
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179 #define WAKEUP_CTIMER3 (1ULL << 13) /*!< [SLEEP, DEEP SLEEP ] */
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180 #define WAKEUP_FLEXCOMM0 (1ULL << 14) /*!< [SLEEP, DEEP SLEEP ] */
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181 #define WAKEUP_FLEXCOMM1 (1ULL << 15) /*!< [SLEEP, DEEP SLEEP ] */
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182 #define WAKEUP_FLEXCOMM2 (1ULL << 16) /*!< [SLEEP, DEEP SLEEP ] */
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183 #define WAKEUP_FLEXCOMM3 (1ULL << 17) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */
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184 #define WAKEUP_FLEXCOMM4 (1ULL << 18) /*!< [SLEEP, DEEP SLEEP ] */
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185 #define WAKEUP_FLEXCOMM5 (1ULL << 19) /*!< [SLEEP, DEEP SLEEP ] */
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186 #define WAKEUP_FLEXCOMM6 (1ULL << 20) /*!< [SLEEP, DEEP SLEEP ] */
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187 #define WAKEUP_FLEXCOMM7 (1ULL << 21) /*!< [SLEEP, DEEP SLEEP ] */
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188 #define WAKEUP_ADC (1ULL << 22) /*!< [SLEEP, ] */
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189 #define WAKEUP_ACMP_CAPT (1ULL << 24) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */
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190 // reserved (1ULL << 25)
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191 // reserved (1ULL << 26)
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192 #define WAKEUP_USB0_NEEDCLK (1ULL << 27) /*!< [SLEEP, DEEP SLEEP ] */
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193 #define WAKEUP_USB0 (1ULL << 28) /*!< [SLEEP, DEEP SLEEP ] */
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194 #define WAKEUP_RTC_LITE_ALARM_WAKEUP (1ULL << 29) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */
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195 #define WAKEUP_EZH_ARCH_B (1ULL << 30) /*!< [SLEEP, ] */
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196 #define WAKEUP_WAKEUP_MAILBOX (1ULL << 31) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */
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197 #define WAKEUP_GPIO_INT0_4 (1ULL << 32) /*!< [SLEEP, DEEP SLEEP ] */
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198 #define WAKEUP_GPIO_INT0_5 (1ULL << 33) /*!< [SLEEP, DEEP SLEEP ] */
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199 #define WAKEUP_GPIO_INT0_6 (1ULL << 34) /*!< [SLEEP, DEEP SLEEP ] */
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200 #define WAKEUP_GPIO_INT0_7 (1ULL << 35) /*!< [SLEEP, DEEP SLEEP ] */
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201 #define WAKEUP_CTIMER2 (1ULL << 36) /*!< [SLEEP, DEEP SLEEP ] */
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202 #define WAKEUP_CTIMER4 (1ULL << 37) /*!< [SLEEP, DEEP SLEEP ] */
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203 #define WAKEUP_OS_EVENT_TIMER (1ULL << 38) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */
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204 // reserved (1ULL << 39)
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205 // reserved (1ULL << 40)
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206 // reserved (1ULL << 41)
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207 #define WAKEUP_SDIO (1ULL << 42) /*!< [SLEEP, ] */
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208 // reserved (1ULL << 43)
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209 // reserved (1ULL << 44)
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210 // reserved (1ULL << 45)
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211 // reserved (1ULL << 46)
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212 #define WAKEUP_USB1 (1ULL << 47) /*!< [SLEEP, DEEP SLEEP ] */
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213 #define WAKEUP_USB1_NEEDCLK (1ULL << 48) /*!< [SLEEP, DEEP SLEEP ] */
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214 #define WAKEUP_SEC_HYPERVISOR_CALL (1ULL << 49) /*!< [SLEEP, ] */
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215 #define WAKEUP_SEC_GPIO_INT0_0 (1ULL << 50) /*!< [SLEEP, DEEP SLEEP ] */
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216 #define WAKEUP_SEC_GPIO_INT0_1 (1ULL << 51) /*!< [SLEEP, DEEP SLEEP ] */
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217 #define WAKEUP_PLU (1ULL << 52) /*!< [SLEEP, DEEP SLEEP ] */
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218 #define WAKEUP_SEC_VIO (1ULL << 53)
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219 #define WAKEUP_SHA (1ULL << 54) /*!< [SLEEP, ] */
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220 #define WAKEUP_CASPER (1ULL << 55) /*!< [SLEEP, ] */
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221 #define WAKEUP_PUFF (1ULL << 56) /*!< [SLEEP, ] */
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222 #define WAKEUP_PQ (1ULL << 57) /*!< [SLEEP, ] */
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223 #define WAKEUP_SDMA1 (1ULL << 58) /*!< [SLEEP, DEEP SLEEP ] */
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224 #define WAKEUP_LSPI_HS (1ULL << 59) /*!< [SLEEP, DEEP SLEEP ] */
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225 // reserved WAKEUP_PVTVF0_AMBER (1ULL << 60)
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226 // reserved WAKEUP_PVTVF0_RED (1ULL << 61)
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227 // reserved WAKEUP_PVTVF1_AMBER (1ULL << 62)
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228 #define WAKEUP_ALLWAKEUPIOS (1ULL << 63) /*!< [ , DEEP POWER DOWN] */
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231 * @brief Sleep Postpone
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233 #define LOWPOWER_HWWAKE_FORCED (1UL << 0) /*!< Force peripheral clocking to stay on during deep-sleep mode. */
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234 #define LOWPOWER_HWWAKE_PERIPHERALS \
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235 (1UL << 1) /*!< Wake for Flexcomms. Any Flexcomm FIFO reaching the level specified by its own TXLVL will cause \
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236 peripheral clocking to wake up temporarily while the related status is asserted */
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237 #define LOWPOWER_HWWAKE_SDMA0 \
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238 (1UL << 3) /*!< Wake for DMA0. DMA0 being busy will cause peripheral clocking to remain running until DMA \
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239 completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS */
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240 #define LOWPOWER_HWWAKE_SDMA1 \
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241 (1UL << 5) /*!< Wake for DMA1. DMA0 being busy will cause peripheral clocking to remain running until DMA \
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242 completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS */
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243 #define LOWPOWER_HWWAKE_ENABLE_FRO192M \
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244 (1UL << 31) /*!< Need to be set if FRO192M is disable - via PDCTRL0 - in Deep Sleep mode and any of \
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245 LOWPOWER_HWWAKE_PERIPHERALS, LOWPOWER_HWWAKE_SDMA0 or LOWPOWER_HWWAKE_SDMA1 is set */
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247 #define LOWPOWER_CPURETCTRL_ENA_DISABLE 0 /*!< In POWER DOWN mode, CPU Retention is disabled */
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248 #define LOWPOWER_CPURETCTRL_ENA_ENABLE 1 /*!< In POWER DOWN mode, CPU Retention is enabled */
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250 * @brief Wake up I/O sources
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252 #define LOWPOWER_WAKEUPIOSRC_PIO0_INDEX 0 /*!< Pin P1( 1) */
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253 #define LOWPOWER_WAKEUPIOSRC_PIO1_INDEX 2 /*!< Pin P0(28) */
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254 #define LOWPOWER_WAKEUPIOSRC_PIO2_INDEX 4 /*!< Pin P1(18) */
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255 #define LOWPOWER_WAKEUPIOSRC_PIO3_INDEX 6 /*!< Pin P1(30) */
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257 #define LOWPOWER_WAKEUPIOSRC_DISABLE 0 /*!< Wake up is disable */
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258 #define LOWPOWER_WAKEUPIOSRC_RISING 1 /*!< Wake up on rising edge */
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259 #define LOWPOWER_WAKEUPIOSRC_FALLING 2 /*!< Wake up on falling edge */
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260 #define LOWPOWER_WAKEUPIOSRC_RISING_FALLING 3 /*!< Wake up on both rising or falling edges */
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262 #define LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_INDEX 8 /*!< Wake-up I/O 0 pull-up/down configuration index */
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263 #define LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_INDEX 9 /*!< Wake-up I/O 1 pull-up/down configuration index */
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264 #define LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_INDEX 10 /*!< Wake-up I/O 2 pull-up/down configuration index */
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265 #define LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_INDEX 11 /*!< Wake-up I/O 3 pull-up/down configuration index */
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267 #define LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK \
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268 (1UL << LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_INDEX) /*!< Wake-up I/O 0 pull-up/down mask */
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269 #define LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK \
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270 (1UL << LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_INDEX) /*!< Wake-up I/O 1 pull-up/down mask */
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271 #define LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK \
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272 (1UL << LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_INDEX) /*!< Wake-up I/O 2 pull-up/down mask */
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273 #define LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK \
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274 (1UL << LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_INDEX) /*!< Wake-up I/O 3 pull-up/down mask */
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276 #define LOWPOWER_WAKEUPIO_PULLDOWN 0 /*!< Select pull-down */
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277 #define LOWPOWER_WAKEUPIO_PULLUP 1 /*!< Select pull-up */
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279 #define LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_INDEX \
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280 12 /*!< Wake-up I/O 0 pull-up/down disable/enable control index */
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281 #define LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_INDEX \
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282 13 /*!< Wake-up I/O 1 pull-up/down disable/enable control index */
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283 #define LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_INDEX \
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284 14 /*!< Wake-up I/O 2 pull-up/down disable/enable control index */
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285 #define LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_INDEX \
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286 15 /*!< Wake-up I/O 3 pull-up/down disable/enable control index */
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287 #define LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_MASK \
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288 (1UL << LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 0 pull-up/down disable/enable mask */
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289 #define LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_MASK \
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290 (1UL << LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 1 pull-up/down disable/enable mask */
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291 #define LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_MASK \
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292 (1UL << LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 2 pull-up/down disable/enable mask */
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293 #define LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_MASK \
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294 (1UL << LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 3 pull-up/down disable/enable mask */
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299 /*******************************************************************************
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301 ******************************************************************************/
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304 * @brief API to enable PDRUNCFG bit in the Syscon. Note that enabling the bit powers down the peripheral
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306 * @param en peripheral for which to enable the PDRUNCFG bit
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309 static inline void POWER_EnablePD(pd_bit_t en)
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312 PMC->PDRUNCFGSET0 = (uint32_t)en;
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316 * @brief API to disable PDRUNCFG bit in the Syscon. Note that disabling the bit powers up the peripheral
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318 * @param en peripheral for which to disable the PDRUNCFG bit
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321 static inline void POWER_DisablePD(pd_bit_t en)
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324 PMC->PDRUNCFGCLR0 = (uint32_t)en;
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328 * @brief set BOD VBAT level.
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330 * @param level BOD detect level
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331 * @param hyst BoD Hysteresis control
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332 * @param enBodVbatReset VBAT brown out detect reset
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334 static inline void POWER_SetBodVbatLevel(power_bod_vbat_level_t level, power_bod_hyst_t hyst, bool enBodVbatReset)
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336 PMC->BODVBAT = (PMC->BODVBAT & (~(PMC_BODVBAT_TRIGLVL_MASK | PMC_BODVBAT_HYST_MASK))) | PMC_BODVBAT_TRIGLVL(level) |
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337 PMC_BODVBAT_HYST(hyst);
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339 (PMC->RESETCTRL & (~PMC_RESETCTRL_BODVBATRESETENABLE_MASK)) | PMC_RESETCTRL_BODVBATRESETENABLE(enBodVbatReset);
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342 #if defined(PMC_BODCORE_TRIGLVL_MASK)
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344 * @brief set BOD core level.
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346 * @param level BOD detect level
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347 * @param hyst BoD Hysteresis control
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348 * @param enBodCoreReset core brown out detect reset
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350 static inline void POWER_SetBodCoreLevel(power_bod_core_level_t level, power_bod_hyst_t hyst, bool enBodCoreReset)
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352 PMC->BODCORE = (PMC->BODCORE & (~(PMC_BODCORE_TRIGLVL_MASK | PMC_BODCORE_HYST_MASK))) | PMC_BODCORE_TRIGLVL(level) |
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353 PMC_BODCORE_HYST(hyst);
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355 (PMC->RESETCTRL & (~PMC_RESETCTRL_BODCORERESETENABLE_MASK)) | PMC_RESETCTRL_BODCORERESETENABLE(enBodCoreReset);
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360 * @brief API to enable deep sleep bit in the ARM Core.
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365 static inline void POWER_EnableDeepSleep(void)
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367 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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371 * @brief API to disable deep sleep bit in the ARM Core.
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376 static inline void POWER_DisableDeepSleep(void)
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378 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
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382 * @brief Shut off the Flash and execute the _WFI(), then power up the Flash after wake-up event
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383 * This MUST BE EXECUTED outside the Flash:
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384 * either from ROM or from SRAM. The rest could stay in Flash. But, for consistency, it is
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385 * preferable to have all functions defined in this file implemented in ROM.
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389 void POWER_CycleCpuAndFlash(void);
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392 * @brief Configures and enters in DEEP-SLEEP low power mode
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393 * @param exclude_from_pd:
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394 * @param sram_retention_ctrl:
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395 * @param wakeup_interrupts:
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396 * @param hardware_wake_ctrl:
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400 * !!! IMPORTANT NOTES :
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401 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API.
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402 * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back in
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403 case of CPU retention or if POWERDOWN is not taken (for instance because an interrupt is pending).
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404 * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be
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405 restored back if POWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending).
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406 * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip
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409 void POWER_EnterDeepSleep(uint32_t exclude_from_pd,
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410 uint32_t sram_retention_ctrl,
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411 uint64_t wakeup_interrupts,
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412 uint32_t hardware_wake_ctrl);
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415 * @brief Configures and enters in POWERDOWN low power mode
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416 * @param exclude_from_pd:
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417 * @param sram_retention_ctrl:
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418 * @param wakeup_interrupts:
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419 * @param cpu_retention_ctrl: 0 = CPU retention is disable / 1 = CPU retention is enabled, all other values are
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424 * !!! IMPORTANT NOTES :
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425 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API.
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426 * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back in
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427 case of CPU retention or if POWERDOWN is not taken (for instance because an interrupt is pending).
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428 * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be
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429 restored back if POWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending).
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430 * 3 - In case of CPU retention, it is the responsability of the user to make sure that SRAM instance
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431 containing the stack used to call this function WILL BE preserved during low power (via parameter
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432 "sram_retention_ctrl")
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433 * 4 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip
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437 void POWER_EnterPowerDown(uint32_t exclude_from_pd,
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438 uint32_t sram_retention_ctrl,
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439 uint64_t wakeup_interrupts,
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440 uint32_t cpu_retention_ctrl);
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443 * @brief Configures and enters in DEEPPOWERDOWN low power mode
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444 * @param exclude_from_pd:
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445 * @param sram_retention_ctrl:
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446 * @param wakeup_interrupts:
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447 * @param wakeup_io_ctrl:
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451 * !!! IMPORTANT NOTES :
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452 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API.
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453 * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back if
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454 DEEPPOWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending).
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455 * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be
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456 restored back if DEEPPOWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending).
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457 * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip
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460 void POWER_EnterDeepPowerDown(uint32_t exclude_from_pd,
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461 uint32_t sram_retention_ctrl,
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462 uint64_t wakeup_interrupts,
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463 uint32_t wakeup_io_ctrl);
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466 * @brief Configures and enters in SLEEP low power mode
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470 void POWER_EnterSleep(void);
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473 * @brief Power Library API to choose normal regulation and set the voltage for the desired operating frequency.
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475 * @param system_freq_hz - The desired frequency (in Hertz) at which the part would like to operate,
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476 * note that the voltage and flash wait states should be set before changing frequency
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479 void POWER_SetVoltageForFreq(uint32_t system_freq_hz);
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482 * @brief Power Library API to return the library version.
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485 * @return version number of the power library
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487 uint32_t POWER_GetLibVersion(void);
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490 * @brief Sets board-specific trim values for 16MHz XTAL
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491 * @param pi32_32MfXtalIecLoadpF_x100 Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120
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492 * @param pi32_32MfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF
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494 * @param pi32_32MfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF
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497 * @note Following default Values can be used:
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498 * pi32_32MfXtalIecLoadpF_x100 Load capacitance, pF x 100 : 600
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499 * pi32_32MfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100 : 20
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500 * pi32_32MfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100 : 40
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502 extern void POWER_Xtal16mhzCapabankTrim(int32_t pi32_16MfXtalIecLoadpF_x100,
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503 int32_t pi32_16MfXtalPPcbParCappF_x100,
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504 int32_t pi32_16MfXtalNPcbParCappF_x100);
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506 * @brief Sets board-specific trim values for 32kHz XTAL
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507 * @param pi32_32kfXtalIecLoadpF_x100 Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120
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508 * @param pi32_32kfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF
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510 * @param pi32_32kfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF
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514 * @note Following default Values can be used:
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515 * pi32_32kfXtalIecLoadpF_x100 Load capacitance, pF x 100 : 600
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516 * pi32_32kfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100 : 40
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517 * pi32_32kfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100 : 40
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519 extern void POWER_Xtal32khzCapabankTrim(int32_t pi32_32kfXtalIecLoadpF_x100,
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520 int32_t pi32_32kfXtalPPcbParCappF_x100,
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521 int32_t pi32_32kfXtalNPcbParCappF_x100);
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523 * @brief Enables and sets LDO for 16MHz XTAL
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527 extern void POWER_SetXtal16mhzLdo(void);
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530 * @brief Set up 16-MHz XTAL Trimmings
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531 * @param amp Amplitude
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532 * @param gm Transconductance
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535 extern void POWER_SetXtal16mhzTrim(uint32_t amp, uint32_t gm);
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544 #endif /* _FSL_POWER_H_ */
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