1 //*****************************************************************************
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2 // boot_multicore_slave.c
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4 // Provides functions to boot slave core in LPC55xx multicore system
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8 //*****************************************************************************
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10 // Copyright(C) NXP Semiconductors, 2019
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11 // All rights reserved.
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13 // Software that is described herein is for illustrative purposes only
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14 // which provides customers with programming information regarding the
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15 // LPC products. This software is supplied "AS IS" without any warranties of
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16 // any kind, and NXP Semiconductors and its licensor disclaim any and
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17 // all warranties, express or implied, including all implied warranties of
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18 // merchantability, fitness for a particular purpose and non-infringement of
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19 // intellectual property rights. NXP Semiconductors assumes no responsibility
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20 // or liability for the use of the software, conveys no license or rights under any
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21 // patent, copyright, mask work right, or any other intellectual property rights in
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22 // or to any products. NXP Semiconductors reserves the right to make changes
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23 // in the software without notification. NXP Semiconductors also makes no
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24 // representation or warranty that such application will be suitable for the
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25 // specified use without further testing or modification.
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27 // Permission to use, copy, modify, and distribute this software and its
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28 // documentation is hereby granted, under NXP Semiconductors' and its
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29 // licensor's relevant copyrights in the software, without fee, provided that it
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30 // is used in conjunction with NXP Semiconductors microcontrollers. This
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31 // copyright, permission, and disclaimer notice must appear in all copies of
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33 //*****************************************************************************
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35 #if defined (__MULTICORE_MASTER)
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39 // ==================================================================
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40 // Define registers related to multicore CPU Control and setup
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41 // ==================================================================
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42 #define SYSCON_BASE ((uint32_t) 0x50000000)
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43 #define CPUCTRL (((volatile uint32_t *) (SYSCON_BASE + 0x800)))
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44 #define CPBOOT (((volatile uint32_t *) (SYSCON_BASE + 0x804)))
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45 #define CPSTACK (((volatile uint32_t *) (SYSCON_BASE + 0x808)))
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46 #define CPSTAT (((volatile uint32_t *) (SYSCON_BASE + 0x80C)))
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47 #define CPUCTRL_KEY ((uint32_t)(0x0000C0C4 << 16))
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48 #define CORE1_CLK_ENA (1<<3)
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49 #define CORE1_RESET_ENA (1<<5)
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52 // ==================================================================
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53 // Function to boot the slave (core 1)
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54 // ==================================================================
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55 void slave_core1_boot(uint32_t *coentry, uint32_t *costackptr) {
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57 volatile uint32_t *u32REG, u32Val;
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59 // Load the slave's stack pointer value
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60 *CPSTACK = (uint32_t) costackptr;
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61 // Load address of the slave code in memory (for slave's VTOR)
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62 *CPBOOT = (uint32_t) coentry;
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64 // Read CPU control register and update to start slave execution
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65 u32REG = (uint32_t *) CPUCTRL;
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67 // Enable slave clock and reset
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68 u32Val |= (CPUCTRL_KEY | ((CORE1_CLK_ENA | CORE1_RESET_ENA) & 0x7F));
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70 // Clear slave reset
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71 u32Val &= ~CORE1_RESET_ENA;
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73 // Slave is now executing
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76 // ==================================================================
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77 // Address of slave code in memory - provided by linker script
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78 extern uint8_t __core_m33slave_START__;
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79 // ==================================================================
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81 // ==================================================================
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82 // Top level function to boot the slave core
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83 // ==================================================================
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84 void boot_multicore_slave(void) {
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86 // Get the address of the slave code in memory
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87 uint32_t *slavevectortable_ptr = (uint32_t *)&__core_m33slave_START__;
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89 // Get initial address for slave's stack pointer
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90 volatile unsigned int spaddr;
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91 spaddr = *slavevectortable_ptr;
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93 // Boot the slave - passing address of code and stack pointer
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94 slave_core1_boot(slavevectortable_ptr, (uint32_t *)spaddr);
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97 #endif //defined (__MULTICORE_MASTER)
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