1 //*****************************************************************************
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2 // boot_multicore_slave.c
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4 // Provides simple functions to boot slave core in LPC55xx multicore system
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8 //*****************************************************************************
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10 // Copyright 2016-2019 NXP
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11 // All rights reserved.
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13 // SPDX-License-Identifier: BSD-3-Clause
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14 //*****************************************************************************
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16 #if defined(__MULTICORE_MASTER)
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20 //#define SYSCON_BASE ((uint32_t) 0x40000000)
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21 #define SYSCON_BASE ((uint32_t)0x50000000)
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23 #define CPBOOT (((volatile uint32_t *)(SYSCON_BASE + 0x804)))
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24 #define CPUCTRL (((volatile uint32_t *)(SYSCON_BASE + 0x800)))
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25 #define CPUCFG (((volatile uint32_t *)(SYSCON_BASE + 0xFD4)))
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27 #define CPUCTRL_KEY ((uint32_t)(0x0000C0C4 << 16))
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28 #define CORE1_CLK_ENA (1 << 3)
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29 #define CORE1_RESET_ENA (1 << 5)
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30 #define CORE1_ENABLE (1 << 2)
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32 extern uint8_t __core_m33slave_START__;
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34 void boot_multicore_slave(void)
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36 volatile uint32_t *u32REG, u32Val;
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38 unsigned int *slavevectortable_ptr = (unsigned int *)&__core_m33slave_START__;
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40 // Enable CPU1 in SYSCON->CPUCFG
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41 *CPUCFG |= CORE1_ENABLE;
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43 // Set CPU1 boot address in SYSCON->CPBoot
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44 *CPBOOT = (uint32_t)slavevectortable_ptr;
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46 // Read SYSCON->CPUCTRL and set key value in bits 31:16
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47 u32REG = (uint32_t *)CPUCTRL;
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48 u32Val = *u32REG | CPUCTRL_KEY;
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50 // Enable slave clock and reset in SYSCON->CPUCTRL
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51 *u32REG = u32Val | CORE1_CLK_ENA | CORE1_RESET_ENA;
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53 // Clear slave reset in SYSCON->CPUCTRL
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54 *u32REG = (u32Val | CORE1_CLK_ENA) & (~CORE1_RESET_ENA);
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56 #endif // defined (__MULTICORE_MASTER)
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