2 ******************************************************************************
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3 * @file system_stm32l4xx.c
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4 * @author MCD Application Team
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5 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
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7 * This file provides two functions and one global variable to be called from
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9 * - SystemInit(): This function is called at startup just after reset and
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10 * before branch to main program. This call is made inside
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11 * the "startup_stm32l4xx.s" file.
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13 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
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14 * by the user application to setup the SysTick
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15 * timer or configure other parameters.
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17 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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18 * be called whenever the core clock is changed
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19 * during program execution.
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21 * After each device reset the MSI (4 MHz) is used as system clock source.
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22 * Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to
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23 * configure the system clock before to branch to main program.
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25 * This file configures the system clock as follows:
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26 *=============================================================================
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27 *-----------------------------------------------------------------------------
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28 * System Clock source | MSI
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29 *-----------------------------------------------------------------------------
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30 * SYSCLK(Hz) | 4000000
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31 *-----------------------------------------------------------------------------
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32 * HCLK(Hz) | 4000000
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33 *-----------------------------------------------------------------------------
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35 *-----------------------------------------------------------------------------
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36 * APB1 Prescaler | 1
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37 *-----------------------------------------------------------------------------
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38 * APB2 Prescaler | 1
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39 *-----------------------------------------------------------------------------
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41 *-----------------------------------------------------------------------------
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43 *-----------------------------------------------------------------------------
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45 *-----------------------------------------------------------------------------
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47 *-----------------------------------------------------------------------------
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49 *-----------------------------------------------------------------------------
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51 *-----------------------------------------------------------------------------
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53 *-----------------------------------------------------------------------------
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55 *-----------------------------------------------------------------------------
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57 *-----------------------------------------------------------------------------
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59 *-----------------------------------------------------------------------------
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61 *-----------------------------------------------------------------------------
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62 * Require 48MHz for USB OTG FS, | Disabled
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63 * SDIO and RNG clock |
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64 *-----------------------------------------------------------------------------
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65 *=============================================================================
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66 ******************************************************************************
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69 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
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70 * All rights reserved.</center></h2>
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72 * This software component is licensed by ST under BSD 3-Clause license,
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73 * the "License"; You may not use this file except in compliance with the
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74 * License. You may obtain a copy of the License at:
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75 * opensource.org/licenses/BSD-3-Clause
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77 ******************************************************************************
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80 /** @addtogroup CMSIS
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84 /** @addtogroup stm32l4xx_system
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88 /** @addtogroup STM32L4xx_System_Private_Includes
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92 #include "stm32l4xx.h"
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94 #if !defined (HSE_VALUE)
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95 #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */
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96 #endif /* HSE_VALUE */
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98 #if !defined (MSI_VALUE)
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99 #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/
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100 #endif /* MSI_VALUE */
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102 #if !defined (HSI_VALUE)
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103 #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
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104 #endif /* HSI_VALUE */
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110 /** @addtogroup STM32L4xx_System_Private_TypesDefinitions
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118 /** @addtogroup STM32L4xx_System_Private_Defines
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122 /************************* Miscellaneous Configuration ************************/
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123 /*!< Uncomment the following line if you need to relocate your vector Table in
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125 /* #define VECT_TAB_SRAM */
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126 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
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127 This value must be a multiple of 0x200. */
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128 /******************************************************************************/
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133 /** @addtogroup STM32L4xx_System_Private_Macros
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141 /** @addtogroup STM32L4xx_System_Private_Variables
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144 /* The SystemCoreClock variable is updated in three ways:
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145 1) by calling CMSIS function SystemCoreClockUpdate()
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146 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
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147 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
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148 Note: If you use this function to configure the system clock; then there
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149 is no need to call the 2 first functions listed above, since SystemCoreClock
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150 variable is updated automatically.
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152 uint32_t SystemCoreClock = 4000000U;
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154 const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
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155 const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
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156 const uint32_t MSIRangeTable[12] = {100000U, 200000U, 400000U, 800000U, 1000000U, 2000000U, \
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157 4000000U, 8000000U, 16000000U, 24000000U, 32000000U, 48000000U};
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162 /** @addtogroup STM32L4xx_System_Private_FunctionPrototypes
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170 /** @addtogroup STM32L4xx_System_Private_Functions
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175 * @brief Setup the microcontroller system.
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180 void SystemInit(void)
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182 /* FPU settings ------------------------------------------------------------*/
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183 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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184 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
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187 /* Reset the RCC clock configuration to the default reset state ------------*/
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188 /* Set MSION bit */
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189 RCC->CR |= RCC_CR_MSION;
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191 /* Reset CFGR register */
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192 RCC->CFGR = 0x00000000U;
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194 /* Reset HSEON, CSSON , HSION, and PLLON bits */
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195 RCC->CR &= 0xEAF6FFFFU;
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197 /* Reset PLLCFGR register */
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198 RCC->PLLCFGR = 0x00001000U;
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200 /* Reset HSEBYP bit */
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201 RCC->CR &= 0xFFFBFFFFU;
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203 /* Disable all interrupts */
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204 RCC->CIER = 0x00000000U;
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206 /* Configure the Vector Table location add offset address ------------------*/
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207 #ifdef VECT_TAB_SRAM
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208 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
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210 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
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215 * @brief Update SystemCoreClock variable according to Clock Register Values.
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216 * The SystemCoreClock variable contains the core clock (HCLK), it can
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217 * be used by the user application to setup the SysTick timer or configure
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218 * other parameters.
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220 * @note Each time the core clock (HCLK) changes, this function must be called
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221 * to update SystemCoreClock variable value. Otherwise, any configuration
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222 * based on this variable will be incorrect.
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224 * @note - The system frequency computed by this function is not the real
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225 * frequency in the chip. It is calculated based on the predefined
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226 * constant and the selected clock source:
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228 * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
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230 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
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232 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
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234 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
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235 * or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
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237 * (*) MSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
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238 * 4 MHz) but the real value may vary depending on the variations
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239 * in voltage and temperature.
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241 * (**) HSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
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242 * 16 MHz) but the real value may vary depending on the variations
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243 * in voltage and temperature.
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245 * (***) HSE_VALUE is a constant defined in stm32l4xx_hal.h file (default value
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246 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
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247 * frequency of the crystal used. Otherwise, this function may
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248 * have wrong result.
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250 * - The result of this function could be not correct when using fractional
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251 * value for HSE crystal.
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256 void SystemCoreClockUpdate(void)
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258 uint32_t tmp = 0U, msirange = 0U, pllvco = 0U, pllr = 2U, pllsource = 0U, pllm = 2U;
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260 /* Get MSI Range frequency--------------------------------------------------*/
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261 if((RCC->CR & RCC_CR_MSIRGSEL) == RESET)
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262 { /* MSISRANGE from RCC_CSR applies */
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263 msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U;
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266 { /* MSIRANGE from RCC_CR applies */
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267 msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U;
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269 /*MSI frequency range in HZ*/
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270 msirange = MSIRangeTable[msirange];
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272 /* Get SYSCLK source -------------------------------------------------------*/
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273 switch (RCC->CFGR & RCC_CFGR_SWS)
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275 case 0x00: /* MSI used as system clock source */
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276 SystemCoreClock = msirange;
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279 case 0x04: /* HSI used as system clock source */
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280 SystemCoreClock = HSI_VALUE;
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283 case 0x08: /* HSE used as system clock source */
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284 SystemCoreClock = HSE_VALUE;
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287 case 0x0C: /* PLL used as system clock source */
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288 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
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289 SYSCLK = PLL_VCO / PLLR
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291 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
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292 pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4U) + 1U ;
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296 case 0x02: /* HSI used as PLL clock source */
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297 pllvco = (HSI_VALUE / pllm);
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300 case 0x03: /* HSE used as PLL clock source */
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301 pllvco = (HSE_VALUE / pllm);
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304 default: /* MSI used as PLL clock source */
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305 pllvco = (msirange / pllm);
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308 pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8U);
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309 pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25U) + 1U) * 2U;
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310 SystemCoreClock = pllvco/pllr;
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314 SystemCoreClock = msirange;
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317 /* Compute HCLK clock frequency --------------------------------------------*/
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318 /* Get HCLK prescaler */
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319 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
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320 /* HCLK clock frequency */
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321 SystemCoreClock >>= tmp;
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337 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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